1. General description
The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin
compatible with the HEF4040B series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to
Q11). The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle flip-flop.
2. Features
■Multiple package options
■Complies with JEDEC standard no. 7A
■ESD protection:
◆HBM JESD22-A114-C exceeds 2000 V
◆MM JESD22-A115-A exceeds 200 V
■Specified from −40 °Cto+85°C and from −40 °C to +125 °C
3. Applications
■Frequency dividing circuits
■Time delay circuits
■Control counters
4. Quick reference data
74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 03 — 14 September 2005 Product data sheet
Table 1: Quick reference data
GND = 0 V; T
amb
=25
°
C; t
r
=t
f
= 6 ns.
Symbol Parameter Conditions Min Typ Max Unit
Type 74HC4040
tPHL, tPLH propagation delay
CP to Q0 CL= 15 pF; VCC = 5 V - 14 - ns
Qn to Qn+1 CL= 15 pF; VCC =5V - 8 - ns
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 2 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
[1] CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
∑(CL×VCC2×fo) = sum of outputs;
CL= output load capacitance in pF;
VCC = supply voltage in V.
5. Ordering information
fmax maximum operating
frequency CL= 15 pF; VCC = 5 V - 90 - MHz
Ciinput capacitance - 3.5 - pF
CPD power dissipation
capacitance VI= GND to VCC -20-pF
Type 74HCT4040
tPHL, tPLH propagation delay
CP to Q0 CL= 15 pF; VCC = 5 V - 16 - ns
Qn to Qn+1 CL= 15 pF; VCC =5V - 8 - ns
fmax maximum operating
frequency CL= 15 pF; VCC = 5 V - 79 - MHz
Ciinput capacitance - 3.5 - pF
CPD power dissipation
capacitance VI= GND to VCC −1.5 V - 20 - pF
Table 1: Quick reference data
…continued
GND = 0 V; T
amb
=25
°
C; t
r
=t
f
= 6 ns.
Symbol Parameter Conditions Min Typ Max Unit
Table 2: Ordering information
Type number Package
Temperature range Name Description Version
74HC4040N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil);
long body SOT38-1
74HC4040D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body
width 3.9 mm SOT109-1
74HC4040DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm SOT338-1
74HC4040PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HC4040BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
74HCT4040N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil);
long body SOT38-1
74HCT4040D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body
width 3.9 mm SOT109-1
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 3 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
6. Functional diagram
74HCT4040DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm SOT338-1
74HCT4040PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT4040BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
Table 2: Ordering information
…continued
Type number Package
Temperature range Name Description Version
Fig 1. Functional diagram
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aad589
12-STAGE COUNTER
9
Q0
7
Q1
6
Q2
5
Q3
3
Q4
2
Q5
4
Q6
13
Q7
12
Q8
14
Q9
15
Q10
1
Q11
10
11 T
CD
MR
CP
001aad585
Q0 9
11 MR
10 CP
Q1 7
Q2 6
Q3 5
Q4 3
Q5 2
Q6 4
Q7 13
Q8 12
Q9 14
Q10 15
Q11 1
001aad586
09
11 CT = 0
+
10
CTR12
CT
7
6
5
3
2
4
13
12
14
15
11 1
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 4 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
7. Pinning information
7.1 Pinning
Fig 4. Logic diagram
001aad588
CP
MR
FF
1
Q
T
RD
Q0
Q
FF
2
Q
T
RD
Q1
Q
FF
7
Q
T
RD
Q6
Q
FF
8
Q
T
RD
Q7
Q
FF
9
Q
T
RD
Q8
Q
FF
10
Q
T
RD
Q9
Q
FF
11
Q
T
RD
Q10
Q
FF
12
Q
T
RD
Q11
Q
FF
3
Q
T
RD
Q2
Q
FF
4
Q
T
RD
Q3
Q
FF
5
Q
T
RD
Q4
Q
FF
6
Q
T
RD
Q5
Q
(1) The substrate is attached to this pad
using conductive die attach material. It
can not be used as supply pin or input
Fig 5. Pin configuration DIP16, SO16,
SSOP16 and TSSOP16 Fig 6. Pin configuration DHVQFN16
4040
Q11 VCC
Q5 Q10
Q4 Q9
Q6 Q7
Q3 Q8
Q2 MR
Q1 CP
GND Q0
001aad583
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aad584
4040
Q1 CP
Q2 MR
Q3 Q8
Q6 Q7
Q4 Q9
Q5 Q10
GND
Q0
Q11
VCC
Transparent top view
7 10
6 11
5 12
4 13
3 14
2 15
8
9
1
16
terminal 1
index area
GND(1)
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 5 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
7.2 Pin description
8. Functional description
8.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑= LOW-to-HIGH clock transition;
↓= HIGH-to-LOW clock transition.
Table 3: Pin description
Symbol Pin Description
Q11 1 output 11
Q5 2 output 5
Q4 3 output 4
Q6 4 output 6
Q3 5 output 3
Q2 6 output 2
Q1 7 output 1
GND 8 ground (0 V)
Q0 9 output 0
CP 10 clock input (HIGH-to-LOW, edge-triggered)
MR 11 master reset input (active HIGH)
Q8 12 output 8
Q7 13 output 7
Q9 14 output 9
Q10 15 output 10
VCC 16 positive supply voltage
Table 4: Function table
Input Output
CP MR Q0 to Q11
↑L no change
↓L count
XHL
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Product data sheet Rev. 03 — 14 September 2005 6 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
8.2 Timing diagram
9. Limiting values
[1] For DIP16 packages: above 70 °C, Ptot derates linearly with 12 mW/K.
For SO16, SSOP16, TSSOP16 and DHVQFN16 packages, above 70 °C, Ptot derates linearly with 8 mW/K.
Fig 7. Timing diagram
001aad587
1 2 4 8 16 32 64 128 256 512 1024 2048 4096
CP input
MR input
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
IIK input diode current VI<−0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output diode current VI<−0.5 V or VI> VCC + 0.5 V - ±20 mA
IOoutput source or sink current −0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC quiescent supply current - ±50 mA
IGND ground current - ±50 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation Tamb = −40 °C to +125 °C[1]
DIP16 package - 750 mW
SO16, SSOP16, TSSOP16 and
DHVQFN16 packages - 500 mW
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Product data sheet Rev. 03 — 14 September 2005 7 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
10. Recommended operating conditions
11. Static characteristics
Table 6: Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
type 74HC4040
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature see Section 11 and 12 per device −40 - +125 °C
tr, tfinput rise and fall times except for Schmitt-trigger inputs
VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0 V - - 400 ns
type 74HCT4040
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature see Section 11 and 12 per device −40 - +125 °C
tr, tfinput rise and fall times except for Schmitt-trigger inputs
VCC = 2.0V ---ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0V ---ns
Table 7: Static characteristics for 74HC4040
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 °C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 2.0 V 1.9 2.0 - V
IO=−20 µA; VCC = 4.5 V 4.4 4.5 - V
IO=−20 µA; VCC = 6.0 V 5.9 6.0 - V
IO=−4.0 mA; VCC = 4.5 V 3.98 4.32 - V
IO=−5.2 mA; VCC = 6.0 V 5.48 5.81 - V
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 8 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 2.0 V - 0 0.1 V
IO= 20 µA; VCC = 4.5 V - 0 0.1 V
IO= 20 µA; VCC = 6.0 V - 0 0.1 V
IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 V
ILl input leakage current VI= VCC or GND; VCC = 6.0 V - - 0.1 µA
ICC quiescent supply current VI= VCC or GND; IO= 0 A;
VCC = 6.0 V - - 8.0 µA
CIinput capacitance - 3.5 - pF
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 2.0 V 1.9 - - V
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−20 µA; VCC = 6.0 V 5.9 - - V
IO=−4.0 mA; VCC = 4.5 V 3.84 - - V
IO=−5.2 mA; VCC = 6.0 V; 5.34 - - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 2.0 V - - 0.1 V
IO= 20 µA; VCC = 4.5 V - - 0.1 V
IO= 20 µA; VCC = 6.0 V - - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - - 0.33 V
IO= 5.2 mA; VCC = 6.0 V - - 0.33 V
ILl input leakage current VI= VCC or GND; VCC = 6.0 V - - 1.0 µA
ICC quiescent supply current VI= VCC or GND; IO= 0 A;
VCC = 6.0 V - - 80.0 µA
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
Table 7: Static characteristics for 74HC4040
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 9 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 2.0 V 1.9 - - V
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−20 µA; VCC = 6.0 V 5.9 - - V
IO=−4.0 mA; VCC = 4.5 V 3.7 - - V
IO=−5.2 mA; VCC = 6.0 V; 5.2 - - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 2.0 V - - 0.1 V
IO= 20 µA; VCC = 4.5 V - - 0.1 V
IO= 20 µA; VCC = 6.0 V - - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - - 0.4 V
IO= 5.2 mA; VCC = 6.0 V - - 0.4 V
ILl input leakage current VI= VCC or GND; VCC = 6.0 V - - 1.0 µA
ICC quiescent supply current VI= VCC or GND; IO= 0 A;
VCC = 6.0 V - - 160.0 µA
Table 7: Static characteristics for 74HC4040
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 8: Static characteristics for 74HCT4040
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 °C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 4.5 V 4.4 4.5 - V
IO=−4.0 mA; VCC = 4.5 V 3.98 4.32 - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 4.5 V - 0 0.1 V
IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 V
ILl input leakage current VI= VCC or GND; VCC = 5.5 V - - 0.1 µA
ICC quiescent supply current VI= VCC or GND; IO= 0 A;
VCC = 5.5 V - - 8.0 µA
∆ICC additional quiescent supply
current VI= VCC − 2.1 V; VCC = 4.5 V
to 5.5 V; IO = 0 A
CP - 85 306 µA
MR - 110 396 µA
CIinput capacitance - 3.5 - pF
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 10 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−4.0 mA; VCC = 4.5 V 3.84 - - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 4.5 V - - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - - 0.33 V
ILl input leakage current VI= VCC or GND; VCC = 5.5 V - - 1.0 µA
ICC quiescent supply current VI= VCC or GND; IO= 0 A;
VCC = 5.5 V - - 80.0 µA
∆ICC additional quiescent supply
current VI= VCC − 2.1 V; VCC = 4.5 V
to 5.5 V; IO = 0 A
CP - - 383 µA
MR - - 495 µA
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−4.0 mA; VCC = 4.5 V 3.7 - - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 4.5 V - - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - - 0.4 V
ILl input leakage current VI= VCC or GND; VCC = 5.5 V - - 1.0 µA
ICC quiescent supply current VI= VCC or GND; IO= 0 A;
VCC = 5.5 V - - 160.0 µA
∆ICC additional quiescent supply
current VI= VCC −2.1 V; VCC = 4.5 V
to 5.5 V; IO=0A
CP - - 417 µA
MR - - 539 µA
Table 8: Static characteristics for 74HCT4040
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 11 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
12. Dynamic characteristics
Table 9: Dynamic characteristics for type 74HC4040
GND = 0 V; t
r
= t
f
= 6 ns. For test circuit see Figure 9.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 °C
tPHL, tPLH propagation delay CP to Q0 see Figure 8
VCC = 2.0 V; CL= 50 pF - 47 150 ns
VCC = 4.5 V; CL= 50 pF - 17 30 ns
VCC = 5.0 V; CL=15pF - 14 - ns
VCC = 6.0 V; CL= 50 pF - 14 26 ns
propagation delay Qn to Qn+1 see Figure 8
VCC = 2.0 V; CL= 50 pF - 28 100 ns
VCC = 4.5 V; CL= 50 pF - 10 20 ns
VCC = 5.0 V; CL=15pF - 8 - ns
VCC = 6.0 V; CL=50pF - 8 17 ns
tPHL propagation delay MR to Qn see Figure 8
VCC =2.0 V; CL= 50 pF - 61 185 ns
VCC = 4.5 V; CL= 50 pF - 22 37 ns
VCC = 6.0 V; CL= 50 pF - 18 31 ns
tTHL, tTLH output transition time see Figure 8
VCC = 2.0 V; CL= 50 pF - 19 75 ns
VCC = 4.5 V; CL=50pF - 7 15 ns
VCC = 6.0 V; CL=50pF - 6 13 ns
tWclock pulse width HIGH or LOW see Figure 8
VCC = 2.0 V; CL=50pF 80 14 - ns
VCC = 4.5 V; CL=50pF 16 5 - ns
VCC = 6.0 V; CL=50pF 14 4 - ns
master reset pulse width; HIGH see Figure 8
VCC = 2.0 V; CL=50pF 80 22 - ns
VCC = 4.5 V; CL=50pF 16 8 - ns
VCC = 6.0 V; CL=50pF 14 6 - ns
trec recovery time MR to CP see Figure 8
VCC = 2.0 V; CL=50pF 50 8 - ns
VCC = 4.5 V; CL=50pF 10 3 - ns
VCC = 6.0 V; CL=50pF 9 2 - ns
fmax maximum operating frequency see Figure 8
VCC = 2.0 V; CL= 50 pF 6.0 27 - MHz
VCC = 4.5 V; CL=50pF 30 82 - MHz
VCC = 5.0 V; CL= 15 pF - 90 - MHz
VCC = 6.0 V; CL=50pF 35 98 - MHz
CPD power dissipation capacitance - 20 - pF
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 12 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
Tamb = −40 °C to +85 °C
tPHL, tPLH propagation delay CP to Q0 see Figure 8
VCC = 2.0 V; CL= 50 pF - - 190 ns
VCC = 4.5 V; CL=50pF - - 38 ns
VCC = 6.0 V; CL=50pF - - 33 ns
propagation delay Qn to Qn+1 see Figure 8
VCC = 2.0 V; CL= 50 pF - - 125 ns
VCC = 4.5 V; CL=50pF - - 25 ns
VCC = 6.0 V; CL=50pF - - 21 ns
tPHL propagation delay MR to Qn see Figure 8
VCC = 2.0 V; CL= 50 pF - - 230 ns
VCC = 4.5 V; CL=50pF - - 46 ns
VCC = 6.0 V; CL=50pF - - 39 ns
tTHL, tTLH output transition time see Figure 8
VCC = 2.0 V; CL=50pF - - 95 ns
VCC = 4.5 V; CL=50pF - - 19 ns
VCC = 6.0 V; CL=50pF - - 16 ns
tWclock pulse width HIGH or LOW see Figure 8
VCC = 2.0 V; CL= 50 pF 100 - - ns
VCC = 4.5 V; CL=50pF 20 - - ns
VCC = 6.0 V; CL=50pF 17 - - ns
master reset pulse width; HIGH see Figure 8
VCC = 2.0 V; CL= 50 pF 100 - - ns
VCC = 4.5 V; CL=50pF 20 - - ns
VCC = 6.0 V; CL=50pF 17 - - ns
trec recovery time MR to CP see Figure 8
VCC = 2.0 V; CL=50pF 65 - - ns
VCC = 4.5 V; CL=50pF 13 - - ns
VCC = 6.0 V; CL=50pF 11 - - ns
fmax maximum operating frequency see Figure 8
VCC = 2.0 V; CL= 50 pF 4.8 - - MHz
VCC = 4.5 V; CL=50pF 24 - - MHz
VCC = 6.0 V; CL=50pF 28 - - MHz
Table 9: Dynamic characteristics for type 74HC4040
…continued
GND = 0 V; t
r
= t
f
= 6 ns. For test circuit see Figure 9.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 13 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
[1] CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
∑(CL×VCC2×fo) = sum of outputs;
CL= output load capacitance in pF;
VCC = supply voltage in V.
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay CP to Q0 see Figure 8
VCC = 2.0 V; CL= 50 pF - - 225 ns
VCC = 4.5 V; CL=50pF - - 45 ns
VCC = 6.0 V; CL=50pF - - 38 ns
propagation delay Qn to Qn+1 see Figure 8
VCC = 2.0 V; CL= 50 pF - - 150 ns
VCC = 4.5 V; CL=50pF - - 30 ns
VCC = 6.0 V; CL=50pF - - 26 ns
tPHL propagation delay MR to Qn see Figure 8
VCC = 2.0 V; CL= 50 pF - - 280 ns
VCC = 4.5 V; CL=50pF - - 56 ns
VCC = 6.0 V; CL=50pF - - 48 ns
tTHL, tTLH output transition time see Figure 8
VCC = 2.0 V; CL= 50 pF - - 110 ns
VCC = 4.5 V; CL=50pF - - 22 ns
VCC = 6.0 V; CL=50pF - - 19 ns
tWclock pulse width HIGH or LOW see Figure 8
VCC = 2.0 V; CL= 50 pF 120 - - ns
VCC = 4.5 V; CL=50pF 24 - - ns
VCC = 6.0 V; CL=50pF 20 - - ns
master reset pulse width; HIGH see Figure 8
VCC = 2.0 V; CL= 50 pF 120 - - ns
VCC = 4.5 V; CL=50pF 24 - - ns
VCC = 6.0 V; CL=50pF 20 - - ns
trec recovery time MR to CP see Figure 8
VCC = 2.0 V; CL=50pF 75 - - ns
VCC = 4.5 V; CL=50pF 15 - - ns
VCC = 6.0 V; CL=50pF 13 - - ns
fmax maximum operating frequency see Figure 8
VCC = 2.0 V; CL= 50 pF 4.0 - - MHz
VCC = 4.5 V; CL=50pF 20 - - MHz
VCC = 6.0 V; CL=50pF 24 - - MHz
Table 9: Dynamic characteristics for type 74HC4040
…continued
GND = 0 V; t
r
= t
f
= 6 ns. For test circuit see Figure 9.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 14 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
Table 10: Dynamic characteristics for type 74HCT4040
GND = 0 V; t
r
= t
f
= 6 ns. For test circuit see Figure 9.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 °C
tPHL, tPLH propagation delay CP to Q0 see Figure 8
VCC = 4.5 V; CL= 50 pF - 19 40 ns
VCC = 5.0 V; CL= 15 pF - 16 - ns
propagation delay Qn to Qn+1 see Figure 8
VCC = 4.5 V; CL= 50 pF - 10 20 ns
VCC = 5.0 V; CL= 15 pF - 8 - ns
tPHL propagation delay MR to Qn VCC = 4.5 V; CL=50pF;
see Figure 8;-2345ns
tTHL, tTLH output transition time VCC = 4.5 V; CL=50pF;
see Figure 8;- 7 15 ns
tWclock pulse width HIGH or LOW VCC = 4.5 V; CL=50pF;
see Figure 8;16 7 - ns
master reset pulse width; HIGH VCC = 4.5 V; CL=50pF;
see Figure 8;16 6 - ns
trec recovery time MR to CP VCC = 4.5 V; CL=50pF;
see Figure 8;10 2 - ns
fmax maximum operating frequency see Figure 8
VCC = 4.5 V; CL=50pF 30 72 - MHz
VCC = 5.0 V; CL= 15 pF - 79 - MHz
CPD power dissipation capacitance
per package [1] -20-pF
Tamb = −40 °C to +85 °C
tPHL, tPLH propagation delay CP to Q0 VCC = 4.5 V; CL=50pF;
see Figure 8;--50ns
propagation delay Qn to Qn+1 VCC = 4.5 V; CL=50pF;
see Figure 8;--25ns
tPHL propagation delay MR to Qn VCC = 4.5 V; CL=50pF;
see Figure 8;--56ns
tTHL, tTLH output transition time VCC = 4.5 V; CL=50pF;
see Figure 8;--19ns
tWclock pulse width HIGH or LOW VCC = 4.5 V; CL=50pF;
see Figure 8;20 - - ns
master reset pulse width; HIGH VCC = 4.5 V; CL=50pF;
see Figure 8;20 - - ns
trec recovery time MR to CP VCC = 4.5 V; CL=50pF;
see Figure 8;13 - - ns
fmax maximum operating frequency VCC = 4.5 V; CL=50pF;
see Figure 8;24 - - MHz
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay CP to Q0 VCC = 4.5 V; CL=50pF;
see Figure 8;--60ns
propagation delay Qn to Qn+1 VCC = 4.5 V; CL=50pF;
see Figure 8 --30ns
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 15 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
[1] CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
∑(CL×VCC2×fo) = sum of outputs;
CL= output load capacitance in pF;
VCC = supply voltage in V.
13. Waveforms
tPHL propagation delay MR to Qn VCC = 4.5 V; CL=50pF;
see Figure 8 --68ns
tTHL, tTLH output transition time VCC = 4.5 V; CL=50pF;
see Figure 8 --22ns
tWclock pulse width HIGH or LOW VCC = 4.5 V; CL=50pF;
see Figure 8 24 - - ns
master reset pulse width; HIGH VCC = 4.5 V; CL=50pF;
see Figure 8 24 - - ns
trec recovery time MR to CP VCC = 4.5 V; CL=50pF;
see Figure 8 15 - - ns
fmax maximum operating frequency VCC = 4.5 V; CL=50pF;
see Figure 8 20 - - MHz
Table 10: Dynamic characteristics for type 74HCT4040
…continued
GND = 0 V; t
r
= t
f
= 6 ns. For test circuit see Figure 9.
Symbol Parameter Conditions Min Typ Max Unit
74HC4040: VM= 50 %; VI= GND to VCC.
74HCT4040: VM= 1.3 V; VI= GND to 3 V.
Fig 8. Clock (CP) to output (Qn) propagation delays, clock pulse width, output transition
times, maximum clock pulse frequency, master reset (MR) pulse width, master
reset to output (Qn) propagation delays and master reset to clock (CP) removal
time.
MR input
CP input
Q0 or Qn
output
tW
tPHL
1/fmax
trem
VM
VI
VI
VM
001aad590
tPLH tW
tTLH tTHL
tPHL
VM
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 16 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance (See Section 12 for the value).
RT = termination resistance should be equal to output impedance ZO of the pulse generator.
Fig 9. Test circuit
mna101
VCC
VIVO
RTCL
PULSE
GENERATOR DUT
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 17 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
14. Package outline
Fig 10. Package outline SOT38-1 (DIP16)
UNIT A
max. 1 2 b1cEe M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT38-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
ME
e1
1.40
1.14
0.055
0.045
0.53
0.38 0.32
0.23 21.8
21.4
0.86
0.84
6.48
6.20
0.26
0.24
3.9
3.4
0.15
0.13
0.2542.54 7.62
0.3
8.25
7.80
0.32
0.31
9.5
8.3
0.37
0.33
2.2
0.087
4.7 0.51 3.7
0.15 0.021
0.015 0.013
0.009 0.010.10.020.19
050G09 MO-001 SC-503-16
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
16
1
9
8
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
(1) (1)
D(1)
Z
DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 18 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
Fig 11. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 19 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
Fig 12. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 20 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
Fig 13. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 21 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
Fig 14. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 22 of 24
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
15. Revision history
Table 11: Revision history
Document ID Release date Data sheet
status Change
notice Doc.
number Supersedes
74HC_HCT4040_3 20050914 Product data
sheet - - 74HC_HCT4040_CNV_2
Modifications: •The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors
•Reference to family specifications is replaced by the actual information: Section 5 “Ordering
information”,Section 7 “Pinning information”,Section 9 “Limiting values”,Section 10
“Recommended operating conditions”,Section 11 “Static characteristics”,Figure 9 “Test
circuit”
•Section 14 “Package outline” (DHVQFN16) added
74HC_HCT4040_CNV_2 19901231 Product
specification -- -
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
74HC_HCT4040_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 14 September 2005 23 of 24
16. Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
19. Trademarks
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
20. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
Level Data sheet status[1] Product status[2] [3] Definition
I Objective data Development This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 14 September 2005
Document number: 74HC_HCT4040_3
Published in The Netherlands
Philips Semiconductors 74HC4040; 74HCT4040
12-stage binary ripple counter
21. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1
5 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Functional description . . . . . . . . . . . . . . . . . . . 5
8.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8.2 Timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
10 Recommended operating conditions. . . . . . . . 7
11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 11
13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
16 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 23
17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
18 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
20 Contact information . . . . . . . . . . . . . . . . . . . . 23
