 
   
SCLS065D – NOVEMBER 1988 – REVISED DECEMBER 2002
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DOperating Voltage Range of 4.5 V to 5.5 V
DOutputs Can Drive Up To 10 LSTTL Loads
DLow Power Consumption, 20-µA Max ICC
DTypical tpd = 10 ns
D±4-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
DInputs Are TTL-Voltage Compatible
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Y
1A
1B
2Y
2A
2B
GND
VCC
4Y
4B
4A
3Y
3B
3A
SN54HCT02 ...J OR W PACKAGE
SN74HCT02 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4B
NC
4A
NC
3Y
1B
NC
2Y
NC
2A
1A
1Y
NC
3A
3B V
4Y
2B
GND
NC
SN54HCT02 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
description/ordering information
These devices contain four independent 2-input NOR gates. They perform the Boolean function Y = A B or
Y = A + B in positive logic.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N Tube SN74HCT02N SN74HCT02N
SOIC D
Tube SN74HCT02D
HCT02
40°Cto85°C
SOIC – D Tape and reel SN74HCT02DR HCT02
–40°C to 85°CSOP – NS Tape and reel SN74HCT02NSR HCT02
SSOP – DB Tape and reel SN74HCT02DBR HT02
TSSOP – PW Tape and reel SN74HCT02PWR HT02
CDIP – J Tube SNJ54HCT02J SNJ54HCT02J
–55°C to 125°CCFP – W Tube SNJ54HCT02W SNJ54HCT02W
55 C
to
125 C
LCCC – FK Tube SNJ54HCT02FK SNJ54HCT02FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B
OUTPUT
Y
H X L
XHL
L L H
Copyright 2002, Texas Instruments Incorporated
      
         
        
        

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
 
   
SCLS065D NOVEMBER 1988 REVISED DECEMBER 2002
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram, each gate (positive logic)
A
BY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only , an d
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT02 SN74HCT02
UNIT
MIN NOM MAX MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
t/vInput transition rise/fall time 500 500 ns
TAOperating free-air temperature 55 125 40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
        
       
         
      
 
   
SCLS065D NOVEMBER 1988 REVISED DECEMBER 2002
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C SN54HCT02 SN74HCT02
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT
V
VVorV
IOH = 20 µA
45V
4.4 4.499 4.4 4.4
V
VOH VI = VIH or VIL IOH = 4 mA 4.5 V 3.98 4.3 3.7 3.84 V
V
VVorV
IOL = 20 µA
45V
0.001 0.1 0.1 0.1
V
VOL VI = VIH or VIL IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 V
IIVI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 5.5 V 2 40 20 µA
ICCOne input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA
Ci4.5 V
to 5.5 V 3 10 10 10 pF
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
TA = 25°C SN54HCT02 SN74HCT02
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT
t
AorB
Y
4.5 V 11 20 30 25
ns
tpd A or B Y5.5 V 10 18 27 22 ns
tt
Y
4.5 V 9 15 22 19
ns
ttY5.5 V 8 14 20 17 ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 20 pF
        
       
         
      
 
   
SCLS065D NOVEMBER 1988 REVISED DECEMBER 2002
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
1.3 V1.3 V 0.3 V0.3 V 2.7 V 2.7 V 3 V
0 V
trtf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V1.3 V 10%10% 90% 90%
3 V
VOH
VOL
0 V
trtf
Input
In-Phase
Output
1.3 V
tPLH tPHL
1.3 V 1.3 V
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
Test
Point
From Output
Under Test
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
CL = 50 pF
(see Note A)
Figure 1. Load Circuit and Voltage Waveforms
MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
BB AC AD
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
Gauge Plane
0.015 (0,38)
0.430 (10,92) MAX
20
1.060
(26,92)
0.940
(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775
(19,69)
(18,92)
0.745
A MIN
DIM
A MAX
PINS **
(23,37)
(21,59)
Seating Plane
14/18 PIN ONLY
20 pin vendor option 4040049/E 12/2002
9
8
0.070 (1,78)
A
0.045 (1,14) 0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
M
0.010 (0,25)
0.100 (2,54)
16 PINS SHOWN
MS-100
VARIATION AA
C
D
D
D
0.030 (0,76)
0.045 (1,14)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN (4,80)
0.189 0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1 4
8 5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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