M470T2953BS3-CD5/CC - Samsung Electronics

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

DDR2 Unbuffered SODIMM

200pin Unbuffered SODIMM based on 512Mb B-die

64bit Non-ECC

* Samsung Electronics reserves the right to change products or specification without notice.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

DDR2 Unbuffered SODIMM Ordering Information

Note: “Z” and “Y” of Part number(11th digit) stand for Lead-free products.

Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.

Part Number Density Organization Component Composition Number of

Rank Height

M470T3354BG(Z)3-CD5/CC 256MB 32Mx64 32Mx16(K4T51163QB)*4 1 30mm

M470T3354BG(Z)0-CD5/CC 256MB 32Mx64 32Mx16(K4T51163QB)*4 1 30mm

M470T3354BZ3-LD5/CC 256MB 32Mx64 32Mx16(K4T51163QB)*4 1 30mm

M470T3354BZ0-LD5/CC 256MB 32Mx64 32Mx16(K4T51163QB)*4 1 30mm

M470T6554BG(Z)3-CD5/CC 512MB 64Mx64 32Mx16(K4T51163QB)*8 2 30mm

M470T6554BG(Z)0-CD5/CC 512MB 64Mx64 32Mx16(K4T51163QB)*8 2 30mm

M470T6554BZ3-LD5/CC 512MB 64Mx64 32Mx16(K4T51163QB)*8 2 30mm

M470T6554BZ0-LD5/CC 512MB 64Mx64 32Mx16(K4T51163QB)*8 2 30mm

M470T2953BS(Y)3-CD5/CC 1GB 128Mx64 64Mx8(K4T51083QB)*16 2 30mm

M470T2953BS(Y)0-CD5/CC 1GB 128Mx64 64Mx8(K4T51083QB)*16 2 30mm

M470T2953BY3-LD5/CC 1GB 128Mx64 64Mx8(K4T51083QB)*16 2 30mm

M470T2953BY0-LD5/CC 1GB 128Mx64 64Mx8(K4T51083QB)*16 2 30mm

Features

• Performance range

• JEDEC standard 1.8V ± 0.1V Power Supply

•V

DDQ = 1.8V ± 0.1V

• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin

• 4 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5

• Programmable Additive Latency: 0, 1 , 2 , 3 and 4

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C

- support High Temperature Self-Refresh rate enable feature

• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16

• All of Lead-free products are compliant for RoHS

Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.

D5(DDR2-533) CC(DDR2-400) Unit

Speed@CL3 400 400 Mbps

Speed@CL4 533 400 Mbps

CL-tRCD-tRP 4-4-4 3-3-3 CK

Address Configuration

Organization Row Address Column Address Bank Address Auto Precharge

64Mx8(512Mb) based Module A0-A13 A0-A9 BA0-BA1 A10

32Mx16(512Mb) based Module A0-A12 A0-A9 BA0-BA1 A10

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Pin Configurations (Front side/Back side)

Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules.

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1VREF 2VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46

3VSS 4DQ453

VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47

5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS

7DQ18 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52

9VSS 10 DM0 59 VSS 60 VSS 109 WE 110 S0 159 DQ49 160 DQ53

11 DQS012 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS

13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODT0 163 NC, TEST 164 CK1

15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/ S1 116 A13 165 VSS 166 CK1

17 DQ2 18 VSS 67 DM3 68 DQS3117 VDD 118 VDD 167 DQS6168 VSS

19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6

21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS

23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54

25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55

27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS

29 DQS1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60

31 DQS1 32 CK081VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61

33 VSS 34 VSS 83 NC 84 NC 133 VSS 134 DQ38 183 VSS 184 VSS

35 DQ10 36 DQ14 85 BA2 86 NC 135 DQ34 136 DQ39 185 DM7 186 DQS7

37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7

39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS

41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62

43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63

45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS5195 SDA 196 VSS

47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0

49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1

Pin Description

Pin Name Function Pin Name Function

CK0,CK1 Clock Inputs, positive line SDA SPD Data Input/Output

CK0,CK1 Clock Inputs, negative line SA1,SA0 SPD address

CKE0,CKE1 Clock Enables DQ0~DQ63 Data Input/Output

RAS Row Address Strobe DM0~DM7 Data Masks

CAS Column Address Strobe DQS0~DQS7 Data strobes

WE Write Enable DQS0~DQS7 Data strobes complement

S0,S1 Chip Selects TEST Logic Analyzer specific test pin (No connect on So-DIMM)

A0~A9, A11~A13 Address Inputs VDD Core and I/O Power

A10/AP Address Input/Autoprecharge VSS Ground

BA0,BA1 SDRAM Bank Address VREF Input/Output Reference

ODT0,ODT1 On-die termination control VDDSPD SPD Power

SCL Serial Presence Detect(SPD) Clock Input NC Spare pins, No connect

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Input/Output Functional Description

Symbol Type Function

CK0-CK1

CK0-CK1Input

The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling

edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output timing for read operations is syn-

chronized to the input clock.

CKE0-CKE1 Input Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivating the clocks, CKE

low initiates the Power Down mode or the Self Refesh mode.

S0-S1 Input

Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When

the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0,

Rank 1 is selected by S1. Ranks are also called “Physical banks”.

RAS, CAS, WE Input When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE define the operation

to be executed by the SDRAM.

BA0~BA1 Input Selects which DDR2 SDRAM internal bank is activated.

ODT0~ODT1 Input Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM Extended Mode Register

Set (EMRS).

A0~A9,

A10/AP,

A11~A13

Input

During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK

and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross

point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge

operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank

to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction

with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of

BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.

DQ0~DQ63 In/Out Data Input/Output pins.

DM0~DM7 Input

The data write masks, associated with one data byte. In Write mode, DM operates as a byte

mask by allowing input data to be written if it is low but blocks the write operation if it is high. In

Read mode, DM lines have no effect.

DQS0~DQS7

DQS0~DQS7In/Out

The data strobes, associated with one data byte, sourced with data transfers. In Write mode,

the data strobe is sourced by the controller and is centered in the data window. In Read mode,

the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the data

window. DQS signals are complements, and timing is relative to the crosspoint of respective

DQS and DQS If the module is to be operated in single ended strobe mode, all DQS signals

must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately.

VDD,VDD

SPD,VSS

Supply Power supplies for core, I/O, Serial Presence Detect, and ground for the module.

SDA In/Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected to VDD to act

as a pull up.

SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as

a pull up.

SA0~SA1 Input Address pins used to select the Serial Presence Detect base address.

TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SO-DIMMs).

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Functional Block Diagram: 512MB, 64Mx64 Module(Populated as 2 rank of x16 DDR2 SDRAMs)

M470T6554BG(Z)3/M470T6554BG(Z)0

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS4

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

CKE0

CKE1

ODT0

ODT1

SPD

SA0

SCL

SDA

VSS DDR2 SDRAMs D0 - D7, SPD

VREF DDR2 SDRAMs D0 - D7

DDR2 SDRAMs D0 - D7, VDD and VDDQVDD

VDDSPD Serial PD

SA1

SCL

A0 - A13 DDR2 SDRAMs D0 - D7

RAS DDR2 SDRAMs D0 - D7

CAS DDR2 SDRAMs D0 - D7

WE DDR2 SDRAMs D0 - D7

BA0 - BA1 DDR2 SDRAMs D0 - D7

3Ω + 5%

Notes :

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms ± 5%.

* Wire per Clock Loading

Table/Wiring Diagrams

* Clock Wiring

Clock Input DDR2 SDRAMs

*CK0/CK0

*CK1/CK1

4 DDR2 SDRAMs

3Ω + 5%

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Functional Block Diagram: 256MB, 32Mx64 Module(Populated as 1 rank of x16 DDR2 SDRAMs)

M470T3354BG(Z)3/M470T3354BG(Z)0

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS4

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

LDQS

LDM

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDM

ODT0

CKE0

SPD

SA0

SCL

SDA

VSS DDR2 SDRAMs D0 - D3, SPD

VREF DDR2 SDRAMs D0 - D3

DDR2 SDRAMs D0 - D3, VDD and VDDQVDD

VDDSPD Serial PD

SA1

SCL

A0 - A13 DDR2 SDRAMs D0 - D3

RAS DDR2 SDRAMs D0 - D3

CAS DDR2 SDRAMs D0 - D3

WE DDR2 SDRAMs D0 - D3

BA0 - BA1 DDR2 SDRAMs D0 - D3

3Ω

Notes :

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms ± 5%.

* Wire per Clock Loading

Table/Wiring Diagrams

* Clock Wiring

Clock Input DDR2 SDRAMs

*CK0/CK0

*CK1/CK1

2 DDR2 SDRAMs

3Ω + 5%

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Functional Block Diagram: 1GB, 128Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs)

M470T2953BS(Y)3/M470T2953BS(Y)0

ODT0

CKE0

ODT1

CKE1

SPD

SA0

SCL

SDA

VSS DDR2 SDRAMs D0 - D15, SPD

VREF DDR2 SDRAMs D0 - D15

DDR2 SDRAMs D0 - D15, VDD and VDDQVDD

VDDSPD Serial PD

SA1

SCL

A0 - A13 DDR2 SDRAMs D0 - D15

RAS DDR2 SDRAMs D0 - D15

CAS DDR2 SDRAMs D0 - D15

WE DDR2 SDRAMs D0 - D15

BA0 - BA1 DDR2 SDRAMs D0 - D15

10Ω + 5%

3Ω + 5%

DQS1

DM1

CS0

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

DQS4

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS

CS1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS

1I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D12

DQS

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS

CS0O

CS1O

CS0

D1 D5

CS1

D13

CS0O

CS1O

CS0

D2 D6

CS1

D10

D14

CS0O

CS1O

CS0

D3 D7

CS1

D11

D15

CS0O

CS1O

Notes :

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.

* Wire per Clock Loading

Table/Wiring Diagrams

* Clock Wiring

Clock Input DDR2 SDRAMs

*CK0/CK0

*CK1/CK1

8 DDR2 SDRAMs

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Absolute Maximum DC Ratings

Note :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2

standard.

AC & DC Operating Conditions

Recommended DC Operating Conditions (SSTL - 1.8)

Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal

to VDD.

1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5

x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).

3. VTT of transmitting device must track VREF of receiving device.

4. AC parameters are measured with VDD, VDDQ and VDDL tied together.

Symbol Parameter Rating Units Notes

VDD Voltage on VDD pin relative to VSS - 1.0 V ~ 2.3 V V 1

VDDQ Voltage on VDDQ pin relative to VSS - 0.5 V ~ 2.3 V V 1

VDDL Voltage on VDDL pin relative to VSS - 0.5 V ~ 2.3 V V 1

VIN, VOUT Voltage on any pin relative to VSS - 0.5 V ~ 2.3 V V 1

TSTG Storage Temperature -55 to +100 °C 1, 2

Symbol Parameter Rating Units Notes

Min. Typ. Max.

VDD Supply Voltage 1.7 1.8 1.9 V

VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 4

VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 4

VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 1,2

VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 3

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Operating Temperature Condition

Note :

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2

standard.

2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.

3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self

refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

Input DC Logic Level

Input AC Logic Level

AC Input Test Conditions

Notes:

1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)

max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative

transitions.

Symbol Parameter Rating Units Notes

TOPER Operating Temperature 0 to 95 °C 1, 2, 3

Symbol Parameter Min. Max. Units Notes

VIH(DC) DC input logic high VREF + 0.125 VDDQ + 0.3 V

VIL(DC) DC input logic low - 0.3 VREF - 0.125 V

Symbol Parameter Min. Max. Units Notes

VIH(AC) AC input logic high VREF + 0.250 - V

VIL(AC) AC input logic low -V

REF - 0.250 V

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V1

VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

VDDQ

VIH(AC) min

VIH(DC) min

VREF

VIL(DC) max

VIL(AC) max

VSS

< AC Input Test Signal Waveform >

VSWING(MAX)

delta TRdelta TF

VREF - VIL(AC) max

delta TF

Falling Slew = Rising Slew = VIH(AC) min - VREF

delta TR

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

IDD Specification Parameters Definition

(IDD values are for full operating range of Voltage and Temperature)

Symbol Proposed Conditions Units Notes

IDD0

Operating one bank active-precharge current;

tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD1

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =

tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern

is same as IDD4W

IDD2P

Precharge power-down current;

All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

IDD2Q

Precharge quiet standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

IDD2N

Precharge standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD3P

Active power-down current;

All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0mA mA

Slow PDN Exit MRS(12) = 1mA mA

IDD3N

Active standby current;

All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD4W

Operating burst write current;

All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP

= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus

inputs are SWITCHING

IDD4R

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-

max(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-

ING; Data pattern is same as IDD4W

IDD5B

Burst auto refresh current;

tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD6

Self refresh current;

CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

Normal mA

Low Power mA

IDD7

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =

tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the follow-

ing page for detailed timing conditions

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)

M470T6554BG(Z)3/M470T6554BG(Z)0 : 64Mx64 512MB Module

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol CD5

(DDR533@CL=4)

LD5

(DDR533@CL=4)

CCC

(DDR400@CL=3)

LCC

(DDR400@CL=3) Unit Notes

IDD0 760 460 720 460 mA

IDD1 860 560 760 520 mA

IDD2P 64 64 64 64 mA

IDD2Q 200 200 200 200 mA

IDD2N 240 200 240 200 mA

IDD3P-F 240 120 240 120 mA

IDD3P-S 120 120 120 120 mA

IDD3N 560 260 520 260 mA

IDD4W 1,200 700 1,000 700 mA

IDD4R 1,100 700 940 700 mA

IDD5B 1,060 860 1,000 860 mA

IDD6 44 40 44 40 mA

IDD7 1,840 1,060 1,760 1,060 mA

M470T3354BG(Z)3/M470T3354BG(Z)0 : 32Mx64 256MB Module

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol CD5

(DDR533@CL=4)

LD5

(DDR533@CL=4)

CCC

(DDR400@CL=3)

LCC

(DDR400@CL=3) Unit Notes

IDD0 480 360 460 360 mA

IDD1 580 460 500 420 mA

IDD2P 32 32 32 32 mA

IDD2Q 100 100 100 100 mA

IDD2N 120 100 120 100 mA

IDD3P-F 120 60 120 60 mA

IDD3P-S 60 60 60 60 mA

IDD3N 280 160 260 160 mA

IDD4W 920 600 740 520 mA

IDD4R 820 600 680 520 mA

IDD5B 780 760 740 760 mA

IDD6 22 20 22 20 mA

IDD7 1,560 960 1,500 960 mA

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)

M470T2953BS(Y)3/M470T2953BS(Y)0 : 128Mx64 1GB Module

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol CD5

(DDR533@CL=4)

LD5

(DDR533@CL=4)

CCC

(DDR400@CL=3)

LCC

(DDR400@CL=3) Unit Notes

IDD0 1,360 760 1,280 760 mA

IDD1 1,440 920 1,320 840 mA

IDD2P 128 128 128 128 mA

IDD2Q 400 400 400 400 mA

IDD2N 480 400 480 400 mA

IDD3P-F 480 240 480 240 mA

IDD3P-S 240 240 240 240 mA

IDD3N 1,120 520 1,040 520 mA

IDD4W 2,160 1,160 1,680 1,000 mA

IDD4R 2,000 1,160 1,680 1,000 mA

IDD5B 2,120 1,720 2,000 1,720 mA

IDD6 88 80 88 80 mA

IDD7 2,760 1,960 2,680 1,960 mA

Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)

* DM is internally loaded to match DQ and DQS identically.

Parameter

Symbol

Min Max Min Max Min Max

Units

Non-ECC M470T6554BG(Z)3

M470T6554BG(Z)0

M470T3354BG(Z)3

M470T3354BG(Z)0

M470T2953BS(Y)3

M470T2953BS(Y)0

Input capacitance, CK and CK CCK -32 -24 -48

pFInput capacitance, CKE , CS, Addr, RAS, CAS, WE CI -34 -34 -42

Input/output capacitance, DQ, DM, DQS, DQS CIO - 10 - 6 - 10

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM

(0 °C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)

Refresh Parameters by Device Density

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units

Refresh to active/Refresh command time tRFC 75 105 127.5 195 tbd ns

Average periodic refresh interval tREFI

0 °C ≤ TCASE ≤ 85°C7.8 7.8 7.8 7.8 7.8 µs

85 °C < TCASE ≤ 95°C3.9 3.9 3.9 3.9 3.9 µs

Speed DDR2-533(D5) DDR2-400(CC)

UnitsBin (CL - tRCD - tRP) 4 - 4 - 4 3 - 3 - 3

Parameter min max min max

tCK, CL=3 5 8 5 8 ns

tCK, CL=4 3.75 8 5 8 ns

tCK, CL=5 - - - - ns

tRCD 15 15 ns

tRP 15 15 ns

tRC 55 55 ns

tRAS 40 70000 40 70000 ns

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the bottom)

Parameter Symbol DDR2-533 DDR2-400 Units Notes

min max min max

DQ output access time from CK/CK tAC -500 +500 -600 +600 ps

DQS output access time from CK/CK tDQSCK -450 +450 -500 +500 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP min(tCL,

tCH) xmin(tCL,

tCH) xps

Clock cycle time, CL=x tCK 3750 8000 5000 8000 ps

DQ and DM input hold time tDH 225 x275 xps

DQ and DM input setup time tDS 100 x150 xps

Control & Address input pulse width for each input tIPW 0.6 x0.6 xtCK

DQ and DM input pulse width for each input tDIPW 0.35 x0.35 xtCK

Data-out high-impedance time from CK/CK tHZ x tAC max x tAC max ps

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2* tACmin tAC max 2* tACmin tAC max ps

DQS-DQ skew for DQS and associated DQ signals tDQSQ x 300 x 350 ps

DQ hold skew factor tQHS x 400 x 450 ps

DQ/DQS output hold time from DQS tQH tHP - tQHS xtHP - tQHS xps

Write command to first DQS latching transition tDQSS WL-0.25 WL+0.25 WL-0.25 WL+0.25 tCK

DQS input high pulse width tDQSH 0.35 x0.35 x tCK

DQS input low pulse width tDQSL 0.35 x0.35 x tCK

DQS falling edge to CK setup time tDSS 0.2 x0.2 x tCK

DQS falling edge hold time from CK tDSH 0.2 x0.2 x tCK

Mode register set command cycle time tMRD 2 x 2 x tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.35 x0.35 x tCK

Address and control input hold time tIH 375 x475 xps

Address and control input setup time tIS 250 x350 xps

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Active to active command period for 1KB page size products tRRD 7.5 x7.5 xns

Active to active command period for 2KB page size products tRRD 10 x10 xns

Four Activate Window for 1KB page size products tFAW 37.5 37.5 ns

Four Activate Window for 2KB page size products tFAW 50 50 ns

CAS to CAS command delay tCCD 2 2 tCK

Write recovery time tWR 15 x15 xns

Auto precharge write recovery + precharge time tDAL tWR+tRP xtWR+tRP x tCK

Internal write to read command delay tWTR 7.5 x10 xns

Internal read to precharge command delay tRTP 7.5 7.5 ns

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 200 tCK

Exit precharge power down to any non-read command tXP 2 x 2 x tCK

Exit active power down to read command tXARD 2 x 2 x tCK

Exit active power down to read command (Slow exit, Lower

power) tXARDS 6 - AL 6 - AL tCK

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Parameter Symbol DDR2-533 DDR2-400 Units Notes

min max min max

CKE minimum pulse width (high and low pulse width) tCKE 3 3 tCK

ODT turn-on delay tAOND 2 2 2 2 tCK

ODT turn-on tAON tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns

ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+tAC(

max)+1 tAC(min)+2 2tCK+tAC

(max)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max)+

0.6 tAC(min) tAC(max)+

0.6 ns

ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+

tAC(max)+1 tAC(min)+2 2.5tCK+

tAC(max)+1 ns

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after CKE asynchronously

drops LOW tDelay tIS+tCK +tIH tIS+tCK +tIH ns

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Physical Dimensions: 32Mbx16 based 64Mx64 Module(2 Rank)

The used device is 32M x16 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51163QB

M470T6554BG(Z)3/M470T6554BG(Z)0

67.60 mm

4.00 ± 0.10

20.00

30.00

1199

11.40 47.40

6.00

SPD

3.8 mm

Max

1.1 mm

Max

63.00

16.25

2.00

67.60 mm

30.00

2200

4.20

2.70 ± 0.10

4.00 ± 0.10 1.0 ± 0.05

1.50 ± 0.10

FRONT SIDE

4.20

1.80 ± 0.10

4.00 ± 0.10 1.0 ± 0.05

2.40 ± 0.10

BACK SIDE

0.60

0.45 ± 0.03

2.55

0.20 ± 0.15

DETAIL a DETAIL b

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Physical Dimensions: 32Mbx16 based 32Mx64 Module(1 Rank)

The used device is 32M x16 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51163QB

M470T3354BG(Z)3/M470T3354BG(Z)0

2.45 mm

Max

1.1 mm

Max

67.60 mm

4.00 ± 0.10

20.00

30.00

1199

11.40 47.40

6.00

SPD

63.00

16.25

2.00

67.60 mm

30.00

2200

4.20

2.70 ± 0.10

4.00 ± 0.10 1.0 ± 0.05

1.50 ± 0.10

FRONT SIDE

4.20

1.80 ± 0.10

4.00 ± 0.10 1.0 ± 0.05

2.40 ± 0.10

BACK SIDE

0.60

0.45 ± 0.03

2.55

0.20 ± 0.15

DETAIL a DETAIL b

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Physical Dimensions: 64Mbx8 based 128Mx64 Module(2 Ranks)

M470T2953BS(Y)3/M470T2953BS(Y)0

The used device is 64M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QB

3.8 mm

1.1mm

max

67.60 mm

4.00 ± 0.10

20.00

30.00

1199

11.40 47.40

6.00

63.00

16.25

2.00

67.60 mm

30.00

2200

SPD

4.20

2.70 ± 0.10

4.00 ± 0.10 1.0 ± 0.05

1.50 ± 0.10

FRONT SIDE

4.20

1.80 ± 0.10

4.00 ± 0.10 1.0 ± 0.05

2.40 ± 0.10

BACK SIDE

0.60

0.45 ± 0.03

2.55

0.20 ± 0.15

DETAIL a DETAIL b

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

Revision History

Revision 1.0 (Jan. 2004)

- Initial Release

Revision 1.1 (Jun. 2004)

- Added lead-free part number in the ordering information

- Changed IDD2P

Revision 1.2 (Jul. 2004)

- Added current values and part number of low power product

Revision 1.3 (Feb. 2005)

- Added the detail information for mechanical dimension

Revision 1.4 (Mar. 2005)

- Changed 1GB Functional Block Diagram

Revision 1.5 (Aug. 2005)

- Changed the IDD Specification Parameters Definition