DATA SHEET CMOS INTEGRATED CIRCUIT +PD5713TK WIDE BAND SPDT SWITCH DESCRIPTION The +PD5713TK is a CMOS MMIC for wide band SPDT (Single Pole Double Throw) switch which were developed for mobile communications, wireless communications and other general-purpose RF switching application. This device can operate frequency from 0.05 to 2.5 GHz, having the low insertion loss and high isolation. This device is housed in a 6-pin lead-less minimold (1511) package. And this package is able to high-density surface mounting. FEATURES * Supply voltage : VDD = 1.8 to 3.6 V (2.8 V TYP.) * Switch control voltage : Vcont (H) = 1.8 to 3.6 V (2.8 V TYP.) : Vcont (L) = <0.2 to +0.4 V (0 V TYP.) * Low insertion loss : Lins1 = 0.6 dB TYP. @ f = 0.05 to 1.0 GHz, VDD = 2.8 V, Vcont (H) = 2.8 V, Vcont (L) = 0 V : Lins2 = 0.8 dB TYP. @ f = 1.0 to 2.0 GHz, VDD = 2.8 V, Vcont (H) = 2.8 V, Vcont (L) = 0 V : Lins3 = 0.95 dB TYP. @ f = 2.0 to 2.5 GHz, VDD = 2.8 V, Vcont (H) = 2.8 V, Vcont (L) = 0 V * High isolation : ISL1 = 32.5 dB TYP. @ f = 0.05 to 1.0 GHz, VDD = 2.8 V, Vcont (H) = 2.8 V, Vcont (L) = 0 V : ISL2 = 25 dB TYP. @ f = 1.0 to 2.0 GHz, VDD = 2.8 V, Vcont (H) = 2.8 V, Vcont (L) = 0 V : ISL3 = 22.5 dB TYP. @ f = 2.0 to 2.5 GHz, VDD = 2.8 V, Vcont (H) = 2.8 V, Vcont (L) = 0 V * Handling power : Pin (1 dB) = +21.0 dBm TYP. @ f = 1.0 GHz, VDD = 2.8 V, Vcont (H) = 2.8 V, Vcont (L) = 0 V : Pin (0.1 dB) = +17.0 dBm TYP. @ f = 1.0 GHz, VDD = 2.8 V, Vcont (H) = 2.8 V, Vcont (L) = 0 V * High-density surface mounting : 6-pin lead-less minimold package (1.5 = 1.1 = 0.55 mm) APPLICATIONS * Mobile communications * Wireless communications * Another general-purpose RF switching applications ORDERING INFORMATION Part Number Order Number +PD5713TK-E2 +PD5713TK-E2-A Package 6-pin lead-less minimold (1511) (Pb-Free) Marking C3Q Supplying Form % Embossed tape 8 mm wide % Pin 1, 6 face the perforation side of the tape % Qty 5 kpcs/reel Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: +PD5713TK-A Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Document No. PU10627EJ01V0DS (1st edition) Date Published September 2006 NS CP(K) +PD5713TK PIN CONNECTIONS AND INTERNAL BLOCK DIAGRAM (Top View) 2 3 C3Q 1 (Top View) (Bottom View) 6 1 6 6 1 5 2 5 5 2 4 3 4 4 3 Pin No. Pin Name 1 OUTPUT1 2 GND 3 OUTPUT2 4 Vcont 5 INPUT 6 VDD TRUTH TABLE Vcont INPUT