XRT91L30
I
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TABLE OF CONTENTS
NOTES:.....................................................................................................................................................II
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
XRT91L30...................................................................................................................................... 1
FEATURES
.....................................................................................................................................................2
F
IGURE
2. 64 QFP P
IN
O
UT
OF
THE
XRT91L30 (T
OP
V
IEW
)............................................................................................................ 3
ORDERING INFORMATION ....................................................................................................................3
T
ABLE
1: ........................................................................................................................................................................................ 4
PIN DESCRIPTIONS..........................................................................................................4
.....................................................................................................................................................................4
H
ARDWARE
C
ONTROL
....................................................................................................................................4
T
RANSMITTER
S
ECTION
..................................................................................................................................7
R
ECEIVER
S
ECTION
.......................................................................................................................................9
P
OWER
AND
G
ROUND
..................................................................................................................................10
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 12
1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 12
T
ABLE
2: CMU R
EFERENCE
F
REQUENCY
O
PTIONS
(D
IFFERENTIAL
OR
S
INGLE
-E
NDED
) ................................................................... 12
1.3 DATA LATENCY ............................................................................................................................................. 12
T
ABLE
3: D
ATA
INGRESS
TO
DATA
EGRESS
LATENCY
....................................................................................................................... 12
2.0 RECEIVE SECTION .............................................................................................................................13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13
F
IGURE
3. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
..................................................................................................................... 13
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 14
F
IGURE
4. R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
D
IAGRAM
.......................................................................................... 14
T
ABLE
4: R
ECEIVE
H
IGH
-
SPEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ............................................................. 14
T
ABLE
5: R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
)............................................................... 14
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
T
ABLE
6: C
LOCK
D
ATA
R
ECOVERY
UNIT
REFERENCE
CLOCK
SETTINGS
............................................................................................ 15
T
ABLE
7: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
.......................................................................................................... 15
2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 16
F
IGURE
5. I
NTERNAL
C
LOCK
AND
D
ATA
R
ECOVERY
B
YPASS
............................................................................................................ 16
2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
.............................................................................................................................................. 16
2.5 LOSS OF SIGNAL .......................................................................................................................................... 16
F
IGURE
7. LOS D
ECLARATION
CIRCUIT
........................................................................................................................................... 17
2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 17
2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 17
F
IGURE
8. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
SIPO ........................................................................................................................... 18
2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 18
F
IGURE
9. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
............................................................................................................. 18
2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 18
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 19
F
IGURE
10. R
ECEIVE
P
ARALLEL
O
UTPUT
T
IMING
............................................................................................................................ 19
T
ABLE
8: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-12/STM-4 O
PERATION
)......................................................................... 19
T
ABLE
9: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-3/STM-1 O
PERATION
)........................................................................... 19
T
ABLE
10: PECL
AND
TTL R
ECEIVE
O
UTPUTS
T
IMING
S
PECIFICATION
............................................................................................ 20
3.0 TRANSMIT SECTION ..........................................................................................................................21
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................ 21
F
IGURE
11. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
............................................................................................................. 21
3.2 TRANSMIT PARALLEL DATA INPUT TIMING ............................................................................................. 22
F
IGURE
12. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
.............................................................................................................................. 22
T
ABLE
11: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
)......................................................................... 22
T
ABLE
12: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
)........................................................................... 22
3.3 ALTERNATE TRANSMIT PARALLEL BUS CLOCK INPUT OPTION .......................................................... 23
F
IGURE
13. A
LTERNATE
T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
(P
ARALLEL
C
LOCK
I
NPUT
O
PTION
)...................................... 23
3.4 ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING ....................................................................... 23