RT8016
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DS8016-01 October 2008 www.richtek.com
Features
+2.5V to +5.5V Input Range
Adjustable Output From 0.6V to VIN
1A Output Current
95% Efficiency
No Schottky Diode Required
1.5MHz Fixed-Frequency PWM Operation
Small 6-Lead WDFN Package
RoHS Compliant and 100% Lead (Pb)-Free
Applications
Mobile Phones
Personal Information Appliances
Wireless and DSL Modems
MP3 Players
Portable Instruments
1.5MHz, 1A, High Efficiency PWM Step-Down DC/DC
Converter
General Description
The RT8016 is a high-efficiency Pulse-Width-Modulated
(PWM) step-down DC-DC converter. Capable of delivering
1A output current over a wide input voltage range from
2.5V to 5.5V, the RT8016 is ideally suited for portable
electronic devices that are powered from 1-cell Li-ion
battery or from other power sources such as cellular
phones, PDAs and hand-held devices.
Two operating modes are available including : PWM/Low-
Dropout autoswitch and shut-down modes, the Internal
synchronous rectifier with low RDS(ON) dramatically reduces
conduction loss at PWM mode. No external Schottky
diode is required in practical application.
The RT8016 enters Low-Dropout mode when normal PWM
cannot provide regulated output voltage by continuously
turning on the upper PMOS. The RT8016 enters shut-
down mode and consumes less than 0.1uA when EN pin
is pulled low. The RT8016 also offers a range of 1V to
3.3V with 0.1V per step or adjustable output voltage by
two external resistor.
The switching ripple is easily smoothed-out by small
package filtering elements due to a fixed operating
frequency of 1.5MHz. This along with small WDFN-6L 2x2
package provides small PCB area application. Other
features include soft start, lower internal reference voltage
with 2% accuracy, over temperature protection, and over
current protection.
Ordering Information
Pin Configurations
(TOP VIEW)
WDFN-6L 2x2
Note :
Richtek Pb-free and Green products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area, otherwise visit our website for detail.
RT8016-
Package Type
QW : WDFN-6L 2x2 (W-Type)
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Output Voltage
Default : Adjustable
10 : 1.0V
11 : 1.1V
:
32 : 3.2V
33 : 3.3V
GND
VIN
FB/VOUT
GND
LX
EN 5
4
1
2
3
6
7
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Typical Application Circuit
Figure 1. Fixed Voltage Regulator
Figure 2. Adjustable Voltage Regulator
⎟
⎠
⎞
⎜
⎝
⎛+= R2
R1
1 x VV REFOUT
with R2 = 300kΩ to 60kΩ so the IR2 = 2μA to 10μA,
and (R1 x C1) should be in the range between 3x10-6 and 6x10-6 for component selection.
Figure 3. Layout Guide for RT8016
Layout note:
1. The distance that CIN connects to VIN is as close as possible (Under 2mm).
2. COUT should be placed near RT8016.
Layout Guide
4.7uF
10uF
VIN LX
RT8016
EN VOUT
2.2uH
2.5V to 5.5V
VIN VOUT
CIN
L
6
4
3
2
1, 5
COUT
GND
4.7uF
10uF
VIN LX
RT8016
EN FB
2.2uH
2.5V to 5.5V
VIN VOUT
CIN
L
6
4
3
2COUT
R1
R2
C1
IR2
1, 5
GND
GND
L1
EN
VIN
GND
LX
COUT
CIN
RT8016_FIX
CIN must be placed
between VDD and
GND as close as
possible
LX should be connected
to Inductor by wide and
short trace, keep
sensitive compontents
away from this trace
Output capacitor
must be near
RT8016
1
2
34
5
6VOUT
EN
VIN
FB
GND
LX
RT8016_ADJ
CIN must be placed
between VDD and
GND as close as
possible
LX should be
connected to
Inductor by wide
and short trace,
keep sensitive
compontents away
from this trace
Output
capacitor
must be near
RT8016
L1
COUT
CIN
1
2
34
5
6
R1
R2
GND
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Function Block Diagram
Functional Pin Description
Pin No. Pin Name Pin Function
2 EN Chip Enable (Active High).
3 VIN Power Input.
4 LX Pin for Switching.
1, 5 GND Ground Pin.
6 FB/VOUT Feedback/Output Voltage Pin.
7 (Exposed Pad) NC No Internal Connection. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
COMP
RC
RS1
RS2
EN VIN
LX
FB/VOUT
UVLO &
Power Good
Detector VREF
Slope
Compensation
Current
Sense
OSC &
Shutdown
Control
Current
Limit
Detector
Driver
Control
Logic
PWM
Comparator
Error
Amplifier
GND
Current
Source
Controller
Mux
Current
Detector
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Absolute Maximum Ratings (Note 1)
Supply Input Voltage ------------------------------------------------------------------------------------------------------ 6.5V
EN, FB Pin Voltage ------------------------------------------------------------------------------------------------------- −0.3V to VIN
Power Dissipation, PD @ TA = 25°C
WDFN-6L 2x2 -------------------------------------------------------------------------------------------------------------- 0.606W
Package Thermal Resistance (Note 4)
WDFN-6L 2x2, θJA --------------------------------------------------------------------------------------------------------- 165°C/W
WDFN-6L 2x2, θJC -------------------------------------------------------------------------------------------------------- 20°C/W
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
ESD Susceptibility (Note 2)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------------ 200V
Electrical Characteristics
(VIN = 3.6V, VOUT = 2.5V, VREF = 0.6V, L = 2.2uH, CIN = 4.7uF, COUT = 10uF, TA = 25°C, IMAX = 1A unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Units
Input Voltage Range VIN 2.5 -- 5.5 V
Quiescent Current IQ I
OUT = 0mA, VFB = VREF + 5% -- 50 70 uA
Shutdown Current ISHDN EN = GND -- 0.1 1 uA
Reference Voltage VRE F For Adjustable Output Voltage 0.588 0.6 0.612 V
Adjustable Output Range VOUT (Note 6) VREF -- VIN − 0.2V V
Output Voltage
Accuracy
Fix ΔVOUT
VIN = (VOUT + ΔV) to 5.5V or
VIN > 2.5V which ever is larger.
(
Note 5
)
−3 -- +3 %
Adjustable ΔVOUT VIN = VOUT + ΔV to 5.5V (Note 5)
0A < IOUT < 1A −3 -- +3 %
FB Input C urrent IFB V
FB = VIN −50 -- 50 nA
PMOSFET RON R
DS(ON)_P IOUT = 200 mA VIN = 3.6V -- 0.28 -- Ω
VIN = 2.5V -- 0.38 --
NMOSFET RON R
DS(ON)_N IOUT = 200 mA VIN = 3.6V -- 0.25 -- Ω
VIN = 2.5V -- 0.35 --
P-Channel Current Limit ILIM_P VIN = 2.5V to 5.5 V 1.4 1.5 -- A
EN High-Level Input
Volta
g
e VEN_H 1.5 --
VIN V
To be continued
Recommended Operating Conditions (Note 3)
Supply Input Voltage ------------------------------------------------------------------------------------------------------ 2.5V to 5.5V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C
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Parameter Symbol Test Conditions Min Typ Max Units
EN Low-Level Input Voltage VEN_L -- -- 0.4 V
Under Voltage Lock Out threshold UVLO -- 1.8 -- V
Hysteresis -- 0.1 -- V
Oscillator Frequency fOSC V
IN = 3.6V, IOUT = 100mA 1.2 1.5 1.8 MHz
Thermal Shutdown Temperature TSD -- 160 -- °C
Max. Duty C ycle 100 -- -- %
LX Current Source VIN = 3.6V, VLX = 0V or VLX = 3.6V 1 -- 100 uA
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution is recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of
JEDEC 51-3 thermal measurement standard. The case point of θJC is on the expose pad for the QFN package.
Note 5. ΔV = IOUT x PRDS(ON)
Note 6. Guarantee by design.
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Typical Operating Characteristics
Output Voltage vs. Output Current
1.200
1.202
1.204
1.206
1.208
1.210
1.212
1.214
1.216
1.218
1.220
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Output Current (A)
Output Voltage (V)
VIN = 3.6V
VIN = 5V
Efficiency vs. Output Current
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Output Current (A)
Efficiency (%)
VOUT = 1.2V, COUT = 10uF, L = 2.2H
VIN = 3.6V
VIN = 5V
UVLO Threshold vs. Temperature
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
-50 -25 0 25 50 75 100 125
Temperature
Input Voltage (V)
(°C)
VOUT = 1.2V, IOUT = 0A
Rising
Falling
Output Voltage vs. Temperature
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
-50 -25 0 25 50 75 100 125
Temperature
Output Voltage (V)
(°C)
VIN = 3.6V, IOUT = 0A
EN Threshold vs. Temperature
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
-40 -15 10 35 60 85 110 135
Temperature
EN Voltage (V)
(°C)
VIN = 3.6V, VOUT = 1.2V, IOUT = 0A
Rising
Falling
EN Threshold vs. Input Voltage
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
2.52.83.13.43.7 4 4.34.64.95.25.5
Input Voltage (V)
EN Voltage (V)
VOUT = 1.2V, IOUT = 0A
Rising
Falling
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Output Ripple Voltage
Time (500ns/Div)
VIN = 5V, VOUT = 1.2V, IOUT = 1A
VOUT
(10mV/Div)
VLX
(5V/Div)
Output Ripple Voltage
Time (500ns/Div)
VIN = 3.6V, VOUT = 1.2V, IOUT = 1A
VOUT
(10mV/Div)
VLX
(5V/Div)
Current Limit vs. Temperature
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
-40 -15 10 35 60 85 110 135
Temperature
Output Current (A)
VIN = 3.6V
(°C)
VIN = 5V
VIN = 3.3V
VOUT = 1.2V
Current Limit vs. Input Voltage
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
Input Voltage (V)
Output Current (A)
VOUT = 1.2V
Frequency vs. Temperature
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
-40 -15 10 35 60 85 110 135
Temperature
Frequency (MHz)
VIN = 3.6V, VOUT = 1.2V, IOUT = 300mA
(°C)
Frequency vs. Input Voltage
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
Input Voltage (V)
Frequency (MHz)
VIN = 3.6V, VOUT = 1.2V, IOUT = 300mA
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Load Transient Response
Time (50us/Div)
VIN = 3.6V, VOUT = 1.2V
IOUT = 50mA to 0.5A
VOUT
(50mV/Div)
IOUT
(500mA/Div)
Load Transient Response
Time (50us/Div)
VIN = 3.6V, VOUT = 1.2V
IOUT = 50mA to 1A
VOUT
(50mV/Div)
IOUT
(500mA/Div)
Power Off from EN
Time (100us/Div)
VIN = 3.6V, VOUT = 1.2V, IOUT = 1A
VOUT
(1V/Div)
VEN
(2V/Div)
IIN
(500mA/Div)
Power On from VIN
Time (250us/Div)
VEN = 3.6V, VOUT = 1.2V, IOUT = 1A
VOUT
(1V/Div)
VIN
(2V/Div)
IIN
(500mA/Div)
Power On from EN
Time (100us/Div)
VIN = 3.6V, VOUT = 1.2V, IOUT = 1A
VOUT
(1V/Div)
VEN
(2V/Div)
IIN
(500mA/Div)
Power On from EN
Time (100us/Div)
VIN = 3.6V, VOUT = 1.2V, IOUT = 10mA
VOUT
(1V/Div)
VEN
(2V/Div)
IIN
(500mA/Div)
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Load Transient Response
Time (50us/Div)
VIN = 5V, VOUT = 1.2V
IOUT = 50mA to 0.5A
VOUT
(50mV/Div)
IOUT
(500mA/Div)
Load Transient Response
Time (50us/Div)
VIN = 5V, VOUT = 1.2V
IOUT = 50mA to 1A
VOUT
(50mV/Div)
IOUT
(500mA/Div)
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⎥
⎦
⎤
⎢
⎣
⎡+≤
OUT
LOUT 8fC
1
ESR ΔIΔV
Applications Information
The basic RT8016 application circuit is shown in Typical
Application Circuit. External component selection is
determined by the maximum load current and begins with
the selection of the inductor value and operating frequency
followed by CIN and COUT.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN and decreases
with higher inductance.
Having a lower ripple current reduces the ESR losses in
the output capacitors and the output voltage ripple. Highest
efficiency operation is achieved at low frequency with small
ripple current. This, however, requires a large inductor.
A reasonable starting point for selecting the ripple current
is ΔIL = 0.4(IMAX). The largest ripple current occurs at the
highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation :
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or mollypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which means that
inductance collapses abruptly when the peak design
⎥
⎦
⎤
⎢
⎣
⎡−×
⎥
⎦
⎤
⎢
⎣
⎡
×
=
IN
OUTOUT
LV
V
1
Lf
V
ΔI
⎥
⎦
⎤
⎢
⎣
⎡−×
⎥
⎦
⎤
⎢
⎣
⎡
Δ×
=
IN(MAX)
OUT
L(MAX)
OUT
V
V
1
If
V
L
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage ripple.
Do not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials
are small and don't radiate energy but generally cost more
than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and
any radiated field/EMI requirements.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the top MOSFET. To
prevent large ripple voltage, a low ESR input capacitor
sized for the maximum RMS current should be used. RMS
current is given by :
1
V
V
V
V
II
OUT
IN
IN
OUT
OUT(MAX)RMS −=
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple current
ratings from capacitor manufacturers are often based on
only 2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be paralleled to meet size or height requirements in the
design.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients, as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
The output ripple, ΔVOUT, is determined by :
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The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capacitors
have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.
Output Voltage Programming
The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 4.
)
R2
R1
(1VV REFOUT +=
Figure 4. Setting the Output Voltage
where VREF is the internal reference voltage (0.6V typ.)
For adjustable voltage mode, the output voltage is set by
an external resistive divider according to the following
equation :
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as :
Efficiency = 100% − (L1+ L2+ L3+ ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. Although all dissipative elements in the
circuit produce losses, two main sources usually account
for most of the losses : VIN quiescent current and I2R
losses.
The VIN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve
at very low load currents can be misleading since the
actual power lost is of no consequence.
1. The VIN quiescent current appears due to two factors
including : the DC bias current as given in the electrical
characteristics and the internal main switch and
synchronous switch gate charge currents. The gate charge
current results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of charge
ΔQ moves from VIN to ground.
The resulting ΔQ/Δt is the current out of VIN that is typically
larger than the DC bias current. In continuous mode,
IGATECHG = f(QT+QB)
where QT and QB are the gate charges of the internal top
and bottom switches. Both the DC bias and gate charge
losses are proportional to VIN and thus their effects will
be more pronounced at higher supply voltages.
RT8016
GND
FB
R1
R2
VOUT
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Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD (ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8016.
` For the main current paths as indicated in bold lines in
Figure 6, keep their traces short and wide.
` Put the input capacitor as close as possible to the device
pins (VIN and GND).
` LX node is with high frequency voltage swing and should
be kept small area. Keep analog components away from
LX node to prevent stray capacitive noise pick-up.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT8016.
2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main switch
and the synchronous switch. Thus, the series resistance
looking into the LX pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows :
RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1−DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses, simply add RSW to RL
and multiply the result by the square of the average output
current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
PD(MAX) = ( TJ(MAX) - TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8016 DC/DC converter, where TJ(MAX) is the maximum
junction temperature of the die and TA is the maximum
ambient temperature. The junction to ambient thermal
resistance θJA is layout dependent. For WDFN-6L 2x2
packages, the thermal resistance θJA is 165°C/W on the
standard JEDEC 51-7 four layers thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by following formula :
PD(MAX) = (125°C − 25°C) / 165°C/W = 0.606W for
WDFN-6L 2x2 packages
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA.
For RT8016 packages, the Figure 5 of derating curves
allows the designer to see the effect of rising ambient
temperature on the maximum power allowed.
Figure 5. Derating Curves for RT8016 Package
0
100
200
300
400
500
600
700
0 20 40 60 80 100 120 140
Ambient Temperature (°C)
Maximum Power Dissipation (mW)
Single Layer PCB
WDFN-6L 2x2
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` Connect all analog grounds to a command node and
then connect the command node to the power ground
behind the output capacitors.
` An example of 2-layer PCB layout is shown in Figure 7
to Figure 8 for reference.
Figure 6. EVB Schematic
Figure 7. Top Layer
Figure 8. Bottom Layer
Table 1. Recommended Inductors
Table 2. Recommended Capacitors for CIN and COUT
Supplier Inductance
(uH) Current Rating (mA) DCR
(mΩ)
Dimensions
(mm) Series
TAIYO YUDEN 2.2 1480 60 3.00 x 3.00 x 1.50 NR 3015
GOTREND 2.2 1500 58 3.85 x 3.85 x 1.80 GTSD32
Sumida 2.2 1500 75 4.50 x 3.20 x 1.55 CDRH2D14
Sumida 4.7 1000 135 4.50 x 3.20 x 1.55 CDRH2D14
TAIYO YUDEN 4.7 1020 120 3.00 x 3.00 x 1.50 NR 3015
GOTREND 4.7 1100 146 3.85 x 3.85 x 1.80 GTSD32
Supplier Capacitance
(uF) Package Part Number
TDK 4.7 603 C1608JB0J475M
MURATA 4.7 603 GRM188R60J475KE19
TAIYO YUDEN 4.7 603 JMK107BJ475RA
TAIYO YUDEN 10 603 JMK107BJ106MA
TDK 10 805 C2012JB0J106M
MURATA 10 805 GRM219R60J106ME19
MURATA 10 805 GRM219R60J106KE19
TAIYO YUDEN 10 805 JMK212BJ106RD
LX
GND
RT8016
EN
FB/VOUT
L1
C3
VIN VOUT
C1
R1
R2
VIN
VIN
3
21, 5
4
6
C2
R3
RT8016
14
DS8016-01 October 2008www.richtek.com
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Outline Dimension
Dimensions In Millimeters Dimensions In Inches
Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250
0.007 0.010
b 0.200 0.350 0.008 0.014
D 1.950 2.050 0.077 0.081
D2 1.000 1.450 0.039 0.057
E 1.950 2.050 0.077 0.081
E2 0.500 0.850 0.020 0.033
e 0.650 0.026
L 0.300 0.400
0.012 0.016
W-Type 6L DFN 2x2 Package
D
1
E
A3
A
A1
eb
L
D2
E2
SEE DETAIL A
11
2
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID and Tie Bar Mark Options
