DAC714 DA C71 4 DAC 714 SBAS032A - JULY 1997 - REVISED NOVEMBER 2005 16-Bit DIGITAL-TO-ANALOG CONVERTER With Serial Data Interface FEATURES: DESCRIPTION SERIAL DIGITAL INTERFACE The DAC714 is a complete monolithic digital-toanalog (D/A) converter including a +10V temperature compensated reference, current-to-voltage amplifier, a high-speed synchronous serial interface, a serial output which allows cascading multiple converters, and an asynchronous clear function which immediately sets the output voltage to midscale. VOLTAGE OUTPUT: 10V, 5V, 0 to +10V 1 LSB INTEGRAL LINEARITY 16-BIT MONOTONIC OVER TEMPERATURE PRECISION INTERNAL REFERENCE The output voltage range is 10V, 5V, or 0 to +10V while operating from 12V or 15V supplies. The gain and bipolar offset adjustments are designed so that they can be set via external potentiometers or external D/A converters. The output amplifier is protected against short circuit to ground. LOW NOISE: 120nV/Hz Including Reference 16-LEAD PLASTIC AND CERAMIC SKINNY DIP AND PLASTIC SO PACKAGES The 16-pin DAC714 is available in a plastic 0.3" DIP, ceramic 0.3" CERDIP, and wide-body plastic SO package. The DAC714P, U, HB, and HC are specified over the -40C to +85C temperature range while the DAC714HL is specified over the 0C to +70C range. A0 Input Shift Register A1 SDI SDO 16 RFB2 CLK D/A Latch CLR 16 Reference Circuit Gain Adjust 16-Bit D/A Converter VOUT VREF OUT +10V RBPO Offset Adjust Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright (c) 1997-2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) +VCC to Common .................................................................... 0V to +17V -VCC to Common .................................................................... 0V to -17V +VCC to -VCC ....................................................................................... 34V ACOM to DCOM ............................................................................... 0.5V Digital Inputs to Common ............................................. -1V to (VCC -0.7V) External Voltage Applied to BPO and Range Resistors .................... VCC VREF OUT .......................................................... Indefinite Short to Common VOUT ............................................................... Indefinite Short to Common SDO ............................................................... Indefinite Short to Common Power Dissipation .......................................................................... 750mW Storage Temperature ...................................................... -60C to +150C Lead Temperature (soldering, 10s) ............................................... +300C NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PIN CONFIGURATION PIN DESCRIPTIONS Top View SO/DIP CLK 1 16 CLR A0 2 15 -VCC A1 3 14 Gain Adjust SDI 4 13 Offset Adjust DAC714 2 SDO 5 12 VREF OUT DCOM 6 11 RBPO +VCC 7 10 RFB2 ACOM 8 9 VOUT PIN LABEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK A0 A1 SDI SDO DCOM +VCC ACOM VOUT RFB2 RBPO VREF OUT Offset Adjust Gain Adjust -VCC CLR DESCRIPTION Serial Data Clock Enable for Input Register (Active Low) Enable for D/A Latch (Active Low) Serial Data Input Serial Data Output Digital Ground Positive Power Supply Analog Ground D/A Output 10V Range Feedback Output Bipolar Offset Voltage Reference Output Offset Adjust Gain Adjust Negative Power Supply Clear DAC714 www.ti.com SBAS032A ELECTRICAL CHARACTERISTICS At TA = +25C, +VCC = +12V and +15V, -VCC = -12V, and -15V, unless otherwise noted. DAC714P, U PARAMETER MIN TYP DAC714HB MAX MIN TYP DAC714HC MAX MIN TYP DAC714HL MAX MIN TYP MAX UNITS 1 2 1 1 LSB LSB LSB LSB Bits Bits % % % of FSR(2) % of FSR %FSR/%VCC ppm FSR/%VCC TRANSFER CHARACTERISTICS ACCURACY Linearity Error TMIN to TMAX Differential Linearity Error TMIN to TMAX Monotonicity Monotonicity Over Spec Temp Range Gain Error(3) TMIN to TMAX Unipolar/Bipolar Zero Error(3) TMIN to TMAX Power Supply Sensitivity of Gain 4 8 4 8 14 13 REFERENCE VOLTAGE Voltage TMIN to TMAX Output Resistance Source Current Short Circuit to ACOM Duration 15 14 6 4 10 10 6 4 10 0.1 0.25 0.1 0.2 0.003 30 10 6 4 10 0.005 0.03 3.0 87 2 15 120 10 5 0.1 Indefinite +9.975 +9.960 1 6 4 10 +10.000 0.005 0.03 3.0 87 2 15 120 0.1 Indefinite +10.025 +10.040 2 10 +9.975 +9.960 V mA 0.1 Indefinite +10.000 +10.025 +10.040 1 2 +9.975 +9.960 +10.000 +10.025 +10.040 1 2 Indefinite Indefinite Indefinite Indefinite 16 16 16 16 s s V/s % % % dB nV-s nV-s nV/Hz 10 5 1 2 10 10 5 0.1 Indefinite +10.025 +10.040 0.1 0.25 0.1 0.2 0.003 30 0.005 0.03 3.0 87 2 15 120 10 5 +10.000 16 16 0.1 0.25 0.1 0.2 0.003 30 0.005 0.03 3.0 87 2 15 120 +9.975 +9.960 1 2 1 2 16 15 0.1 0.25 0.1 0.2 0.003 30 DYNAMIC PERFORMANCE Settling Time (to 0.003%FSR, 5k || 500pF Load)(4) 20V Output Step 1LSB Output Step(5) Output Slew Rate Total Harmonic Distortion 0dB, 1001Hz, fS = 100kHz -20dB, 1001Hz, fS = 100kHz -60dB, 1001Hz, fS = 100kHz SINAD: 1001Hz, fS = 100kHz Digital Feedthrough(5) Digital-to-Analog Glitch Impulse(5) Output Noise Voltage (includes reference) ANALOG OUTPUT Output Voltage Range +VCC, -VCC = 11.4V Output Current Output Impedance Short Circuit to ACOM Duration 2 4 2 4 V V mA INTERFACE RESOLUTION DIGITAL INPUTS Serial Data Input Code Logic Levels(1) VIH VIL +2.0 (VCC -1.4) +2.0 0 +0.8 0 Binary Two's Complement (VCC -1.4) +2.0 +0.8 0 Bits (VCC -1.4) +2.0 (VCC -1.4) +0.8 0 +0.8 V V IIH (VI = +2.7V) 10 10 10 10 A IIL (VI = +0.4V) 10 10 10 10 A +0.4 +5 V V +15 -15 +16.5 -16.5 V V 13 22 16 26 625 mA mA mW +70 +150 C C C/W DIGITAL OUTPUT Serial Data VOL (ISINK = 1.6mA) VOH (ISOURCE = 500A), TMIN to TMAX POWER SUPPLY REQUIREMENTS Voltage +VCC -VCC Current (No Load, 15V Supplies)(6) +VCC -VCC Power Dissipation(7) TEMPERATURE RANGES Specification All Grades Storage Thermal Coefficient, JA 0 +2.4 +11.4 -11.4 +0.4 +5 0 +2.4 +15 -15 +16.5 -16.5 +11.4 -11.4 13 22 16 26 625 -40 -60 +85 +150 75 +0.4 +5 0 +2.4 +15 -15 +16.5 -16.5 +11.4 -11.4 13 22 16 26 625 -40 -60 +85 +150 75 +0.4 +5 0 +2.4 +15 -15 +16.5 -16.5 +11.4 -11.4 13 22 16 26 625 -40 -60 +85 +150 75 0 -60 75 NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for 10V output, FSR = 20V. (3) Errors externally adjustable to zero. (4) Maximum represents the 3 limit. Not 100% tested for this parameter. (5) For the worst-case Binary Two's Complement code changes: FFFF H to 0000H and 0000H to FFFFH. (6) During power supply turn on, the transient supply current may approach 3x the maximum quiescent specification. (7) Typical (i.e. rated) supply voltages times maximum currents. DAC714 SBAS032A www.ti.com 3 TIMING SPECIFICATIONS TRUTH TABLE TA = -40C to +85C, +VCC = +12V or +15V, -VCC = -12V or -15V. SYMBOL PARAMETER MIN tCLK tCL tCH tA0S tA1S tAOH tA1H tDS tDH tDSOP tCP Data Clock Period Clock LOW Clock HIGH Setup Time for A0 Setup Time for A1 Hold Time for A0 Hold Time for A1 Setup Time for DATA Hold Time for DATA Output Propagation Delay Clear Pulsewidth 100 50 50 50 50 0 0 50 10 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns 140 200 A0 A1 CLK CLR DESCRIPTION 0 1 1 0 101 1 Shift Serial Data into SDI 101 1 1 Load D/A Latch 1 101 1 No Change 0 0 101 1 Two Wire Operation(1) X X 1 1 No Change X X X 0 Reset D/A Latch NOTES: X = Don't Care. (1) All digital input changes will appear at the output. TIMING DIAGRAMS Serial Data In tCLK tCH tCL CLK tA 0H tA 0S A0 tDS Serial Data Input MSB First tDH D15 SDI D14 D0 tA 1S Latch Data In D/A Latch tA 1H A1 Serial Data Out tCLK tCH tCL CLK tA tA 0S 0H A0 Serial Data Out D15 SDO D14 D0 tDSOP tDSOP Clear tCP CLR 4 DAC714 www.ti.com SBAS032A TYPICAL CHARACTERISTICS POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY LOGIC vs V LEVEL 1k 2.0 -VCC 100 I Digital Input (A) [Change in FSR] / [Change in Supply Voltage] (ppm of FSR/ %) At TA = +25C, VCC = 15V, unless otherwise noted. +VCC 10 1 100 1k 10k 100k A0, A1 CLR 0 SDI -1.0 -2.0 -0.85 0.1 10 1.0 1M 0 0.85 1.7 2.55 3.4 4.25 5.1 5.95 6.8 V Digital Input Frequency (Hz) SETTLING TIME, +10V TO -10V FULL SCALE OUTPUT SWING Around -10V (V) VOUT (V) 10 0 2000 +5V 1500 0V A1 (V) 2500 1000 500 0 -500 -1000 -1500 -2000 -10 -2500 Time (1s/div) Time (10s/div) VOUT SPECTRAL NOISE DENSITY SETTLING TIME, -10V TO +10V 1000 +5V 1500 0V A1 2000 1000 100 nV/Hz Around +10V (V) 2500 500 0 -500 10 -1000 -1500 -2000 1 -2500 1 Time (1s/div) 10 100 1k 10k 100k 1M 10M Frequency (Hz) DAC714 SBAS032A www.ti.com 5 DISCUSSION OF SPECIFICATIONS LINEARITY ERROR Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points of the transfer characteristic. DIFFERENTIAL LINEARITY ERROR Differential linearity error (DLE) is the deviation from 1LSB of an output change from one adjacent state to the next. A DLE specification of 1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word. If the DLE is more positive than -1LSB, the D/A is said to be monotonic. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. Monotonicity of the C and L grades is assured over the specification temperature range to 16 bits. SETTLING TIME Settling time is the total time (including slew time) for the D/A output to settle to within an error band around its final value after a change in input. Settling times are specified to within 0.003% of Full Scale Range (FSR) for an output step change of 20V and 1LSB. The 1LSB change is measured at the Major Carry (FFFFH to 0000H, and 0000H to FFFFH: BTC codes), the input transition at which worst-case settling time occurs. TOTAL HARMONIC DISTORTION Total harmonic distortion is defined as the ratio of the square root of the sum of the squares of the values of the harmonics to the value of the fundamental frequency. It is expressed in % of the fundamental frequency amplitude at sampling rate fS. SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) SINAD includes all the harmonic and outstanding spurious components in the definition of output noise power in addition to quantizing and internal random noise power. SINAD is expressed in dB at a specified input frequency and sampling rate, fS. DIGITAL-TO-ANALOG GLITCH IMPULSE The amount of charge injected into the analog output from the digital inputs when the inputs change state. It is measured at half scale at the input codes where as many as possible switches change state--from 0000H to FFFFH. 6 DIGITAL FEEDTHROUGH When the A/D is not selected, high frequency logic activity on the digital inputs is coupled through the device and shows up as output noise. This noise is digital feedthrough. OPERATION The DAC714 is a monolithic integrated-circuit 16-bit D/A converter complete with 16-bit D/A switches and ladder network, voltage reference, output amplifier and a serial interface. INTERFACE LOGIC The DAC714 has double-buffered data latches. The input data latch holds a 16-bit data word before loading it into the second latch, the D/A latch. This double-buffered organization permits simultaneous update of several D/A converters. All digital control inputs are active low. Refer to the block diagram shown in Figure 1. All latches are level-triggered. Data present when the enable inputs are logic "0" will enter the latch. When the enable inputs return to logic "1", the data is latched. The CLR input resets both the input latch and the D/A latch to 0000H (midscale). LOGIC INPUT COMPATIBILITY The DAC714 digital inputs are TTL compatible (1.4V switching level), low leakage, and high impedance. Thus, the inputs are suitable for being driven by any type of 5V logic family, such as CMOS. An equivalent circuit for the digital inputs is shown in Figure 2. The inputs will float to logic "0" if left unconnected. It is recommended that any unused inputs be connected to DCOM to improve noise immunity. Digital inputs remain high impedance when power is off. INPUT CODING The DAC714 is designed to accept binary two's complement (BTC) input codes with the MSB first which are compatible with bipolar analog output operation. For this configuration, a digital input of 7FFFH produces a plus full scale output, 8000H produces a minus full scale output, and 0000H produces bipolar zero output. INTERNAL REFERENCE The DAC714 contains a +10V reference. The reference output may be used to drive external loads, sourcing up to 2mA. The load current should be constant; otherwise, the gain and bipolar offset of the converter will vary. DAC714 www.ti.com SBAS032A Gain Adjust VREF OUT +VCC - VCC 14 12 7 15 180 15k +10V Reference 10 RFB2 11 RBPO 13 Offset Adjust 9 VOUT 250 10k +2.5V 9750 10k -VCC D/A Switches CLK 1 A1 3 CLR 16 A0 2 SDI 4 SDO 5 DAC Latch 16 Shift Register 8 6 ACOM DCOM FIGURE 1. DAC714 Block Diagram. +VCC ESD Protection Circuit Range of Gain Adjust 0.3% + Full Scale 6.8V Analog Output 1k Digital Input 5pF -VCC FIGURE 2. Equivalent Circuit of Digital Inputs. OUTPUT VOLTAGE SWING The output amplifier of the DAC714 is designed to achieve a 10V output range while operating on 11.4V or higher power supplies. All Bits Logic 0 Range of Offset Adjust Offset Adj. Translates the Line 0.3% Full Scale Range Bipolar Offset Gain Adjust Rotates the Line MSB on All Others Off All Bits Logic 1 - Full Scale Digital Input FIGURE 3. Relationship of Offset and Gain Adjustments. GAIN AND OFFSET ADJUSTMENTS Figure 3 illustrates the relationship of offset and gain adjustments for a bipolar connected D/A converter. Offset should be adjusted first to avoid interaction of adjustments. See Table I for calibration values and codes. These adjustments have a minimum range of 0.3%. Offset Adjustment Apply the digital input code, 8000H, that produces the maximum negative output voltage and adjust the offset potentiometer or the offset adjust D/A converter for -10V (or 0V unipolar). DAC714 SBAS032A www.ti.com 7 DAC714 CALIBRATION VALUES DIGITAL INPUT CODE ANALOG OUTPUT (V) BINARY TWO'S BIPOLAR UNIPOLAR COMPLEMENT, BTC 20V RANGE 10V RANGE DESCRIPTION 7FFFH | 4000H | 0001H +9.999695 +9.999847 + Full Scale -1LSB +5.000000 +7.500000 3/4 Scale +0.000305 +5.000153 BPZ + 1LSB 0000H 0.000000 +5.000000 Bipolar Zero (BPZ) FFFFH | C000H | 8000H -0.000305 +4.999847 BPZ - 1LSB -5.000000 +2.500000 1/4 Scale -10.00000 0.000000 Minus Full Scale 1 16 2 -VCC 15 3 14 4 -12V to -15V 13 DAC714 5 12 6 DCOM 11 7 +VCC 10 8 ACOM 9 + 1F +12V to +15V 1F + TABLE I. Digital Input and Analog Output Voltage Calibration Values. FIGURE 4. Power Supply Connections. Gain Adjustment Apply the digital input that gives the maximum positive voltage output. Adjust the gain potentiometer or the gain adjust D/A converter for this positive full scale voltage. INSTALLATION GENERAL CONSIDERATIONS Due to the high accuracy of the DAC714 system design, problems such as grounding and contact resistance become very important. A 16-bit converter with a 20V full-scale range has a 1LSB value of 305V. With a load current of 5mA, series wiring and connector resistance of only 60m will cause a voltage drop of 300V. To understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copper-clad printed circuit board is 1/2 m per square. For a 5mA load, a 10 milliinch wide printed circuit conductor 60 milliinches long will result in a voltage drop of 150V. The analog output of DAC714 has an LSB size of 305V (-96dB) in the bipolar mode. The rms noise floor of the D/A should remain below this level in the frequency range of interest. The DAC714's output noise spectral density (which includes the noise contributed by the internal reference,) is shown in the Typical Characteristic section. Wiring to high-resolution D/A converters should be routed to provide optimum isolation from sources of RFI and EMI. The key to elimination of RF radiation or pickup is small loop area. Signal leads and their return conductors should be kept close together such that they present a small capture cross-section for any external field. Wire-wrap construction is not recommended. POWER SUPPLY AND REFERENCE CONNECTIONS Power supply decoupling capacitors should be added as shown in Figure 4. Best performance occurs using a 1 to 10F tantalum capacitor at -VCC. Applications with less 8 critical settling time may be able to use 0.01F at -VCC as well as at +VCC. The capacitors should be located close to the package. The DAC714 has separate ANALOG COMMON and DIGITAL COMMON pins. The current through DCOM is mostly switching transients and are up to 1mA peak in amplitude. The current through ACOM is typically 5A for all codes. Use separate analog and digital ground planes with a single interconnection point to minimize ground loops. The analog pins are located adjacent to each other to help isolate analog from digital signals. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. A solid analog ground plane around the D/A package, as well as under it in the vicinity of the analog and power supply pins, will isolate the D/A from switching currents. It is recommended that DCOM and ACOM be connected directly to the ground planes under the package. If several DAC714s are used or if DAC714 shares supplies with other components, connecting the ACOM and DCOM lines to together once at the power supplies rather than at each chip may give better results. LOAD CONNECTIONS Since the reference point for VOUT and VREF OUT is the ACOM pin, it is important to connect the D/A converter load directly to the ACOM pin. Refer to Figure 5. Lead and contact resistances are represented by R1 through R3. As long as the load resistance RL is constant, R1 simply introduces a gain error and can be removed by gain adjustment of the D/A or system-wide gain calibration. R2 is part of RL if the output voltage is sensed at ACOM. In some applications it is impractical to return the load to the ACOM pin of the D/A converter. Sensing the output voltage at the SYSTEM GROUND point is reasonable, because there is no change in DAC714 ACOM current, provided that R3 is a low-resistance ground plane or conductor. In this case you may wish to connect DCOM to SYSTEM GROUND as well. DAC714 www.ti.com SBAS032A GAIN AND OFFSET ADJUST Connections Using Potentiometers GAIN and OFFSET adjust pins provide for trim using external potentiometers. 15-turn potentiometers provide sufficient resolution. Range of adjustment of these trims is at least 0.3% of Full Scale Range. Refer to Figure 6. Using D/A Converters The GAIN ADJUST and OFFSET ADJUST circuits of the DAC714 have been arranged so that these points may be easily driven by external D/A converters. Refer to Figure 7. 12-bit D/A converters provide an OFFSET adjust resolution and a GAIN adjust resolution of 30V to 50V per LSB step. Nominal values of GAIN and OFFSET occur when the D/A converters outputs are at approximately half scale, +5V. OUTPUT VOLTAGE RANGE CONNECTIONS The DAC714 output amplifier is connected internally to provide a 20V output range. For other ranges and configurations, see Figures 6 and 7. DIGITAL INTERFACE SERIAL INTERFACE The DAC714 has a serial interface with two data buffers which can be used for either synchronous or asynchronous updating of multiple D/A converters. A0 is the enable control for the input shift register. A1 is the enable for the D/A Latch. CLK is used to strobe data into the latches enabled by A0 and A1. A CLR function is also provided and when enabled it sets the shift register and the D/A Latch to 0000H (output voltage is midscale). Multiple DAC714s can be connected to the same CLK and data lines in two ways. The output of the serial shift register is available as SDO so that any number of DAC714s can be cascaded on the same input bit stream as shown in Figures 8 and 9. This configuration allows all D/A converters to be updated simultaneously and requires a minimum number of control signals. These configurations do require 16N CLK cycles to load any given D/A converter, where N is the number of D/A converters. The DAC714 can also be connected in parallel as shown in Figure 10. This configuration allows any D/A converter in the system to be updated in a maximum of 16 CLK cycles. VREF RBPO DAC714 10k SDI RFB2 A0 A1 VREF 10k 10k CLR VOUT R1 Bus Interface RL DCOM Sense Output ACOM R2 R3 Alternate Ground Sense Connection To +VCC 0.01F(1) 0.01F System Ground Analog Power Supply To -VCC NOTE: (1) Locate close to DAC714 package. FIGURE 5. System Ground Considerations for High-Resolution D/A Converters. DAC714 SBAS032A www.ti.com 9 Internal +10V Reference VREF OUT 12 P1 1k 180 R1 100 Gain Adjust 14 Offset Adjust R2 2M 10k to 100k 13 15k 10k 9.75k RFB2 9 IDAC 0-2mA -VCC R3 27k 10 10k 8 +VCC VOUT For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R3 are standard 1% values. Range of adjustment at least 0.3% FSR. ACOM FIGURE 6a. Manual Offset and Gain Adjust Circuits; Unipolar Mode (0V to +10V output range). Internal +10V Reference VREF OUT 12 Bipolar Offset 11 P1 1k 180 P2 1k 250 R1 100 Gain Adjust Offset Adjust 15k 14 13 10k 9.75k 10 10k RFB2 9 IDAC 0-2mA 8 R2 100 ACOM R3 27k R4 10k VOUT For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R4 are standard 1% values. Range of adjustment at least 0.3% FSR. FIGURE 6b. Manual Offset and Gain Adjust Circuits; Bipolar Mode (-5V to +5V output range). 10 DAC714 www.ti.com SBAS032A Internal +10V Reference VREF OUT 12 Bipolar Offset 180 R2 1.3k R1 200 250 10k +10V 11 10k Gain Adjust -10V 14 Offset Adjust 5k 13 15k 9.75k 10k RFB2 10 Suggested Op Amps OPA177GP, GS or OPA604AP, AU R4 24.3k R3 11.8k 10k RFB VREF A 0 to +10V IDAC 0-2mA Suggested Op Amps OPA177GP, GS: Single or OPA2604AP, AU: Dual 9 10V VOUT 0 to +10V RFB VREF B DAC714 For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R4 tolerance: 1%. Range of adjustment at least 0.3% FSR. Suggested D/As CMOS DAC7800: Dual: Serial Input, 12-bit Resolution DAC7801: Dual: 8-bit Port Input, 12-bit Resolution DAC7802: Dual: 12-bit Port Input, 12-bit Resolution DAC7528: Dual: 8-bit Port Input, 8-bit Resolution DAC7545: Dual: 12-bit Port Input, 12-bit Resolution DAC8043: Single: Serial Input, 12-bit Resolution BIPOLAR (complete) DAC813 (Use 11-bit resolution for 0V to +10V output. No op amps required). FIGURE 7. Gain and Offset Adjustment in the Bipolar Mode Using D/A Converters (-10V to +10V output range). DAC714 SBAS032A www.ti.com 11 4 Data 2 Data Latch 3 Update 1 CLK +5V 16 4 2 3 1 +5V 16 4 2 3 1 +5V 16 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 To other DACs FIGURE 8a. Cascaded Serial Bus Connection with Synchronous Update. DAC3 DAC2 DAC1 Clock(1) Data F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 Data Latch Update FIGURE 8b. Timing Diagram For Figure 8a. 12 DAC714 www.ti.com SBAS032A 4 Data 2 Data Latch 3 Update 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 +5V 4 2 3 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 +5V 4 2 3 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 To other DACs +5V FIGURE 9a. Cascaded Serial Bus Connection with Asynchronous Update. DAC3 DAC2 DAC1 Data Latch(1) Data F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 Update FIGURE 9b. Timing Diagram For Figure 9a. DAC714 SBAS032A www.ti.com 13 Data Data Latch 1 Update 4 2 3 1 CLK 16 CLR 4 Data Latch 2 2 3 1 16 4 Data Latch 3 2 3 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 FIGURE 10a. Parallel Bus Connection. DAC1 DAC2 DAC3 Clock(1) Data F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 Data Latch 1 Data Latch 2 Data Latch 3 Update FIGURE 10b. Timing Diagram For Figure 10a. 14 DAC714 www.ti.com SBAS032A PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) DAC714HB OBSOLETE CDIP SB JD 16 TBD Call TI Call TI DAC714HC OBSOLETE CDIP SB JD 16 TBD Call TI Call TI DAC714HL OBSOLETE CDIP SB JD 16 Call TI Call TI DAC714P NRND PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC714PG4 NRND PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC714U ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC714U/1K ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC714U/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC714UG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TBD Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC714U/1K Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC714U/1K SOIC DW 16 1000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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