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FEATURES:
● SERIAL DIGITAL INTERFACE
● VOLTAGE OUTPUT: ±10V, ±5V, 0 to +10V
● ±1 LSB INTEGRAL LINEARITY
●
16-BIT MONOTONIC OVER TEMPERATURE
● PRECISION INTERNAL REFERENCE
● LOW NOISE: 120nV/√Hz Including Reference
● 16-LEAD PLASTIC AND CERAMIC SKINNY
DIP AND PLASTIC SO PACKAGES
16-Bit DIGITAL-TO-ANALOG CONVERTER
With Serial Data Interface
DESCRIPTION
The DAC714 is a complete monolithic digital-to-
analog (D/A) converter including a +10V temperature com-
pensated reference, current-to-voltage amplifier, a high-speed
synchronous serial interface, a serial output which allows
cascading multiple converters, and an asynchronous clear
function which immediately sets the output voltage to midscale.
The output voltage range is ±10V, ±5V, or 0 to +10V while
operating from ±12V or ±15V supplies. The gain and bipolar
offset adjustments are designed so that they can be set via
external potentiometers or external D/A converters. The
output amplifier is protected against short circuit to ground.
The 16-pin DAC714 is available in a plastic 0.3" DIP, ceramic
0.3" CERDIP, and wide-body plastic SO package. The
DAC714P, U, HB, and HC are specified over the –40°C to
+85°C temperature range while the DAC714HL is specified
over the 0°C to +70°C range.
VOUT
VREF OUT
+10V
Reference
Circuit 16-Bit D/A Converter
D/A Latch
SDO
RFB2
16
Input Shift Register
16
A1
SDI
CLK
CLR
A0
Offset AdjustGain
Adjust RBPO
DAC714
SBAS032A – JULY 1997 – REVISED NOVEMBER 2005
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997-2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
DAC714
DAC714
DAC714
2SBAS032A
www.ti.com
PIN CONFIGURATION
Top View
CLK
A
0
A
1
SDI
SDO
DCOM
+V
CC
ACOM
DAC714
CLR
–V
CC
Gain Adjust
Offset Adjust
V
REF OUT
R
BPO
R
FB2
V
OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PIN DESCRIPTIONS
PIN LABEL DESCRIPTION
1 CLK Serial Data Clock
2A
0Enable for Input Register (Active Low)
3A
1Enable for D/A Latch (Active Low)
4 SDI Serial Data Input
5 SDO Serial Data Output
6 DCOM Digital Ground
7+V
CC Positive Power Supply
8 ACOM Analog Ground
9V
OUT D/A Output
10 RFB2 ±10V Range Feedback Output
11 RBPO Bipolar Offset
12 VREF OUT Voltage Reference Output
13 Offset Adjust Offset Adjust
14 Gain Adjust Gain Adjust
15 –VCC Negative Power Supply
16 CLR Clear
SO/DIP
+VCC to Common .................................................................... 0V to +17V
–VCC to Common .................................................................... 0V to –17V
+VCC to –VCC ....................................................................................... 34V
ACOM to DCOM ............................................................................... ±0.5V
Digital Inputs to Common............................................. –1V to (VCC –0.7V)
External Voltage Applied to BPO and Range Resistors .................... ±VCC
VREF OUT ..........................................................Indefinite Short to Common
VOUT ............................................................... Indefinite Short to Common
SDO ............................................................... Indefinite Short to Common
Power Dissipation .......................................................................... 750mW
Storage Temperature...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under
Absolute Maximum Ratings
may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
PACKAGE/ORDERING INFORMATION
DAC714 3
SBAS032A www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C, +VCC = +12V and +15V, –VCC = –12V, and –15V, unless otherwise noted.
Binary Two’s Complement
DAC714P, U DAC714HB DAC714HC DAC714HL
PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error ±4±2±1±1 LSB
TMIN to TMAX ±8±4±2±2 LSB
Differential Linearity Error ±4±2±1±1 LSB
TMIN to TMAX ±8±4±2±1 LSB
Monotonicity 14 15 16 16 Bits
Monotonicity Over Spec Temp Range 13 14 15 16 Bits
Gain Error(3) ±0.1 ±0.1 ±0.1 ±0.1 %
TMIN to TMAX ±0.25 ±0.25 ±0.25 ±0.25 %
Unipolar/Bipolar Zero Error(3) ±0.1 ±0.1 ±0.1 ±0.1 % of FSR(2)
TMIN to TMAX ±0.2 ±0.2 ±0.2 ±0.2 % of FSR
Power Supply Sensitivity of Gain ±0.003 ±0.003 ±0.003 ±0.003 %FSR/%VCC
±30 ±30 ±30 ±30 ppm FSR/%VCC
DYNAMIC PERFORMANCE
Settling Time
(to ±0.003%FSR, 5kΩ || 500pF Load)(4)
20V Output Step 6 10 6 10 6 10 6 10 µs
1LSB Output Step(5) 4444µs
Output Slew Rate 10 10 10 10 V/µs
Total Harmonic Distortion
0dB, 1001Hz, fS = 100kHz 0.005 0.005 0.005 0.005 %
–20dB, 1001Hz, fS = 100kHz 0.03 0.03 0.03 0.03 %
–60dB, 1001Hz, fS = 100kHz 3.0 3.0 3.0 3.0 %
SINAD: 1001Hz, fS = 100kHz 87 87 87 87 dB
Digital Feedthrough(5) 2222nV–s
Digital-to-Analog Glitch Impulse(5) 15 15 15 15 nV–s
Output Noise Voltage (includes reference)
120 120 120 120 nV/√Hz
ANALOG OUTPUT
Output Voltage Range
+VCC, –VCC = ±11.4V ±10 ±10 ±10 ±10 V
Output Current ±5±5±5±5mA
Output Impedance 0.1 0.1 0.1 0.1 Ω
Short Circuit to ACOM Duration Indefinite Indefinite Indefinite Indefinite
REFERENCE VOLTAGE
Voltage +9.975 +10.000 +10.025 +9.975 +10.000 +10.025 +9.975 +10.000 +10.025 +9.975 +10.000 +10.025 V
TMIN to TMAX +9.960 +10.040 +9.960 +10.040 +9.960 +10.040 +9.960 +10.040 V
Output Resistance 1111Ω
Source Current 2222 mA
Short Circuit to ACOM Duration Indefinite Indefinite Indefinite Indefinite
INTERFACE
RESOLUTION 16 16 16 16 Bits
DIGITAL INPUTS
Serial Data Input Code
Logic Levels(1)
VIH +2.0
(VCC –1.4)
+2.0
(VCC –1.4)
+2.0
(VCC –1.4)
+2.0
(VCC –1.4)
V
VIL 0 +0.8 0 +0.8 0 +0.8 0 +0.8 V
IIH (VI = +2.7V) ±10 ±10 ±10 ±10 µA
IIL (VI = +0.4V) ±10 ±10 ±10 ±10 µA
DIGITAL OUTPUT
Serial Data
VOL (ISINK = 1.6mA) 0 +0.4 0 +0.4 0 +0.4 0 +0.4 V
VOH (ISOURCE = 500µA), TMIN to TMAX +2.4 +5 +2.4 +5 +2.4 +5 +2.4 +5 V
POWER SUPPLY REQUIREMENTS
Voltage
+VCC +11.4 +15 +16.5 +11.4 +15 +16.5 +11.4 +15 +16.5 +11.4 +15 +16.5 V
–VCC –11.4 –15 –16.5 –11.4 –15 –16.5 –11.4 –15 –16.5 –11.4 –15 –16.5 V
Current (No Load, ±15V Supplies)(6)
+VCC 13 16 13 16 13 16 13 16 mA
–VCC 22 26 22 26 22 26 22 26 mA
Power Dissipation(7) 625 625 625 625 mW
TEMPERATURE RANGES
Specification
All Grades –40 +85 –40 +85 –40 +85 0 +70 °C
Storage –60 +150 –60 +150 –60 +150 –60 +150 °C
Thermal Coefficient,
θ
JA 75 75 75 75 °C/W
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for ±10V output, FSR = 20V. (3) Errors
externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst-case Binary Two’s Complement code changes: FFFF
H
to 0000
H
and 0000
H
to FFFF
H
. (6) During power supply turn on, the transient supply current may approach 3x the maximum quiescent specification. (7) Typical (i.e. rated) supply voltages times maximum currents.
DAC714
4SBAS032A
www.ti.com
CLK
A
0
SDI
Serial Data Input
MSB First
Latch Data
In D/A Latch A
1
t
A0H
D
0
D
14
D
15
t
A1S
t
A1H
t
DH
t
DS
t
A0S
t
CLK
t
CH
t
CL
CLK
A
0
SDO
Serial Data
Out
t
A0S
t
A0H
D
0
D
14
Clear
D
15
t
CLK
t
CH
t
CL
CLR
t
DSOP
t
CP
t
DSOP
TIMING SPECIFICATIONS
TA = –40°C to +85°C, +VCC = +12V or +15V, –VCC = –12V or –15V.
SYMBOL PARAMETER MIN MAX UNITS
tCLK Data Clock Period 100 ns
tCL Clock LOW 50 ns
tCH Clock HIGH 50 ns
tA0S Setup Time for A050 ns
tA1S Setup Time for A150 ns
tAOH Hold Time for A00ns
tA1H Hold Time for A10ns
tDS Setup Time for DATA 50 ns
tDH Hold Time for DATA 10 ns
tDSOP Output Propagation Delay 140 ns
tCP Clear Pulsewidth 200 ns
A0A1CLK CLR DESCRIPTION
011 → 0 → 1 1 Shift Serial Data into SDI
101 → 0 → 1 1 Load D/A Latch
111 → 0 → 1 1 No Change
001 → 0 → 1 1 Two Wire Operation(1)
X X 1 1 No Change
X X X 0 Reset D/A Latch
NOTES: X = Don’t Care. (1) All digital input changes will appear at the
output.
TRUTH TABLE
TIMING DIAGRAMS
Serial Data In
Serial Data Out
DAC714 5
SBAS032A www.ti.com
Time (10µs/div)
± FULL SCALE OUTPUT SWING
V (V)
OUT
0
10
–10
Frequency (Hz)
[Change in FSR] / [Change in Supply Voltage]
1k
10 100 1k 10k 100k 1M
POWER SUPPLY REJECTION vs
POWER SUPPLY RIPPLE FREQUENCY
(ppm of FSR/ %)
100
10
1
0.1
–VCC
+VCC
TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = ±15V, unless otherwise noted.
A
1
(V)
SETTLING TIME, +10V TO –10V
Time (1µs/div)
2500
2000
1500
1000
500
0
–500
–1000
–1500
–2000
–2500
∆ Around –10V (µV)
+5V
0V
A1
SETTLING TIME, –10V TO +10V
Time (1µs/div)
2500
2000
1500
1000
500
0
–500
–1000
–1500
–2000
–2500
∆ Around +10V (µV)
+5V
0V
1000
100
10
11 10 100 1k 10k 100k 1M 10M
Frequency (Hz)
nV/√Hz
V
OUT
SPECTRAL NOISE DENSITY
2.0
–0.85 0 2.55 4.25 5.95 6.8
LOGIC vs V LEVEL
1.0
0
–1.0
–2.0 0.85 1.7 3.4 5.1
SDI
A
0
, A
1
CLR
V Digital Input
I Digital Input (µA)
DAC714
6SBAS032A
www.ti.com
DISCUSSION OF
SPECIFICATIONS
LINEARITY ERROR
Linearity error is defined as the deviation of the analog
output from a straight line drawn between the end points of
the transfer characteristic.
DIFFERENTIAL LINEARITY ERROR
Differential linearity error (DLE) is the deviation from
1LSB of an output change from one adjacent state to the
next. A DLE specification of ±1/2LSB means that the output
step size can range from 1/2LSB to 3/2LSB when the digital
input code changes from one code word to the adjacent code
word. If the DLE is more positive than –1LSB, the D/A is
said to be monotonic.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital input values.
Monotonicity of the C and L grades is assured over the
specification temperature range to 16 bits.
SETTLING TIME
Settling time is the total time (including slew time) for the
D/A output to settle to within an error band around its final
value after a change in input. Settling times are specified to
within ±0.003% of Full Scale Range (FSR) for an output
step change of 20V and 1LSB. The 1LSB change is mea-
sured at the Major Carry (FFFFH to 0000H, and 0000H to
FFFFH: BTC codes), the input transition at which worst-case
settling time occurs.
TOTAL HARMONIC DISTORTION
Total harmonic distortion is defined as the ratio of the
square root of the sum of the squares of the values of the
harmonics to the value of the fundamental frequency. It is
expressed in % of the fundamental frequency amplitude at
sampling rate fS.
SIGNAL-TO-NOISE
AND DISTORTION RATIO (SINAD)
SINAD includes all the harmonic and outstanding spurious
components in the definition of output noise power in
addition to quantizing and internal random noise power.
SINAD is expressed in dB at a specified input frequency and
sampling rate, fS.
DIGITAL-TO-ANALOG GLITCH IMPULSE
The amount of charge injected into the analog output from
the digital inputs when the inputs change state. It is mea-
sured at half scale at the input codes where as many as
possible switches change state—from 0000H to FFFFH.
DIGITAL FEEDTHROUGH
When the A/D is not selected, high frequency logic activity
on the digital inputs is coupled through the device and shows
up as output noise. This noise is digital feedthrough.
OPERATION
The DAC714 is a monolithic integrated-circuit 16-bit D/A
converter complete with 16-bit D/A switches and ladder
network, voltage reference, output amplifier and a serial
interface.
INTERFACE LOGIC
The DAC714 has double-buffered data latches. The input
data latch holds a 16-bit data word before loading it into the
second latch, the D/A latch. This double-buffered organiza-
tion permits simultaneous update of several D/A converters.
All digital control inputs are active low. Refer to the block
diagram shown in Figure 1.
All latches are level-triggered. Data present when the enable
inputs are logic “0” will enter the latch. When the enable
inputs return to logic “1”, the data is latched.
The CLR input resets both the input latch and the D/A latch
to 0000H (midscale).
LOGIC INPUT COMPATIBILITY
The DAC714 digital inputs are TTL compatible (1.4V switch-
ing level), low leakage, and high impedance. Thus, the
inputs are suitable for being driven by any type of 5V logic
family, such as CMOS. An equivalent circuit for the digital
inputs is shown in Figure 2.
The inputs will float to logic “0” if left unconnected. It is
recommended that any unused inputs be connected to DCOM
to improve noise immunity.
Digital inputs remain high impedance when power is off.
INPUT CODING
The DAC714 is designed to accept binary two’s comple-
ment (BTC) input codes with the MSB first which are
compatible with bipolar analog output operation. For this
configuration, a digital input of 7FFFH produces a plus full
scale output, 8000H produces a minus full scale output, and
0000H produces bipolar zero output.
INTERNAL REFERENCE
The DAC714 contains a +10V reference. The reference
output may be used to drive external loads, sourcing up to
2mA. The load current should be constant; otherwise, the
gain and bipolar offset of the converter will vary.
DAC714 7
SBAS032A www.ti.com
FIGURE 1. DAC714 Block Diagram.
OUTPUT VOLTAGE SWING
The output amplifier of the DAC714 is designed to achieve
a ±10V output range while operating on ±11.4V or higher
power supplies.
GAIN AND OFFSET ADJUSTMENTS
Figure 3 illustrates the relationship of offset and gain adjust-
ments for a bipolar connected D/A converter. Offset should
be adjusted first to avoid interaction of adjustments. See
Table I for calibration values and codes. These adjustments
have a minimum range of ±0.3%.
FIGURE 3. Relationship of Offset and Gain Adjustments.
Offset Adjustment
Apply the digital input code, 8000H, that produces the maxi-
mum negative output voltage and adjust the offset potentiometer
or the offset adjust D/A converter for –10V (or 0V unipolar).
Shift Register
DAC Latch
14 12
+10V
Reference
8 6
7
DCOM
+VCC
ACOM
VREF OUT
Gain Adjust
4SDI
5SDO
16
2A0
3A1
1
16
CLK
CLR
15
– VCC
Offset
Adjust
13
RBPO
11
RFB2
10
9VOUT
D/A Switches
–VCC
+2.5V
15kΩ
180Ω
9750Ω
250Ω
10kΩ
10kΩ
FIGURE 2. Equivalent Circuit of Digital Inputs.
1kΩ
ESD Protection Circuit
6.8V 5pF
Digital
Input
–VCC
+VCC
+ Full Scale
All Bits
Logic 0
Range of
Offset Adjust
Offset Adj.
Translates
the Line Digital Input
All Bits
Logic 1
Analog Output
Full Scale
Range Gain Adjust
Rotates the Line
– Full Scale
MSB on All
Others Off
Bipolar
Offset
Range of
Gain Adjust
≈±0.3%
≈±0.3%
DAC714
8SBAS032A
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DAC714 CALIBRATION VALUES
DIGITAL INPUT CODE ANALOG OUTPUT (V)
BINARY TWO’S BIPOLAR UNIPOLAR
COMPLEMENT, BTC 20V RANGE 10V RANGE DESCRIPTION
7FFFH+9.999695 +9.999847 + Full Scale –1LSB
|
4000H+5.000000 +7.500000 3/4 Scale
|
0001H+0.000305 +5.000153 BPZ + 1LSB
0000H0.000000 +5.000000 Bipolar Zero (BPZ)
FFFFH–0.000305 +4.999847 BPZ – 1LSB
|
C000H–5.000000 +2.500000 1/4 Scale
|
8000H–10.00000 0.000000 Minus Full Scale
critical settling time may be able to use 0.01µF at –VCC
as well as at +VCC. The capacitors should be located
close to the package.
The DAC714 has separate ANALOG COMMON and DIGI-
TAL COMMON pins. The current through DCOM is mostly
switching transients and are up to 1mA peak in amplitude.
The current through ACOM is typically 5µA for all codes.
Use separate analog and digital ground planes with a single
interconnection point to minimize ground loops. The analog
pins are located adjacent to each other to help isolate analog
from digital signals. Analog signals should be routed as far
as possible from digital signals and should cross them at
right angles. A solid analog ground plane around the D/A
package, as well as under it in the vicinity of the analog and
power supply pins, will isolate the D/A from switching
currents. It is recommended that DCOM and ACOM be
connected directly to the ground planes under the package.
If several DAC714s are used or if DAC714 shares supplies
with other components, connecting the ACOM and DCOM
lines to together once at the power supplies rather than at
each chip may give better results.
LOAD CONNECTIONS
Since the reference point for VOUT and VREF OUT is the
ACOM pin, it is important to connect the D/A converter load
directly to the ACOM pin. Refer to Figure 5.
Lead and contact resistances are represented by R1 through
R3. As long as the load resistance RL is constant, R1 simply
introduces a gain error and can be removed by gain adjust-
ment of the D/A or system-wide gain calibration. R2 is part
of RL if the output voltage is sensed at ACOM.
In some applications it is impractical to return the load to the
ACOM pin of the D/A converter. Sensing the output voltage
at the SYSTEM GROUND point is reasonable, because there
is no change in DAC714 ACOM current, provided that R3 is
a low-resistance ground plane or conductor. In this case you
may wish to connect DCOM to SYSTEM GROUND as well.
FIGURE 4. Power Supply Connections.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1µF
1µF
DAC714
DCOM
+V
CC
ACOM
−V
CC
+12V to +15V
−12V to −15V
+
+
TABLE I. Digital Input and Analog Output Voltage Calibra-
tion Values.
Gain Adjustment
Apply the digital input that gives the maximum positive
voltage output. Adjust the gain potentiometer or the gain
adjust D/A converter for this positive full scale voltage.
INSTALLATION
GENERAL CONSIDERATIONS
Due to the high accuracy of the DAC714 system design,
problems such as grounding and contact resistance become
very important. A 16-bit converter with a 20V full-scale
range has a 1LSB value of 305µV. With a load current of
5mA, series wiring and connector resistance of only 60mΩ
will cause a voltage drop of 300µV. To understand what this
means in terms of a system layout, the resistivity of a typical
1 ounce copper-clad printed circuit board is 1/2 mΩ per
square. For a 5mA load, a 10 milliinch wide printed circuit
conductor 60 milliinches long will result in a voltage drop of
150µV.
The analog output of DAC714 has an LSB size of 305µV
(–96dB) in the bipolar mode. The rms noise floor of the D/A
should remain below this level in the frequency range of
interest. The DAC714’s output noise spectral density (which
includes the noise contributed by the internal reference,) is
shown in the Typical Characteristic section.
Wiring to high-resolution D/A converters should be routed
to provide optimum isolation from sources of RFI and EMI.
The key to elimination of RF radiation or pickup is small
loop area. Signal leads and their return conductors should be
kept close together such that they present a small capture
cross-section for any external field. Wire-wrap construction
is not recommended.
POWER SUPPLY AND
REFERENCE CONNECTIONS
Power supply decoupling capacitors should be added as
shown in Figure 4. Best performance occurs using a 1 to
10µF tantalum capacitor at –VCC. Applications with less
DAC714 9
SBAS032A www.ti.com
DIGITAL INTERFACE
SERIAL INTERFACE
The DAC714 has a serial interface with two data buffers
which can be used for either synchronous or asynchronous
updating of multiple D/A converters. A0 is the enable control
for the input shift register. A1 is the enable for the D/A Latch.
CLK is used to strobe data into the latches enabled by A0 and
A1. A CLR function is also provided and when enabled it sets
the shift register and the D/A Latch to 0000H (output voltage
is midscale).
Multiple DAC714s can be connected to the same CLK and
data lines in two ways. The output of the serial shift register
is available as SDO so that any number of DAC714s can be
cascaded on the same input bit stream as shown in Figures
8 and 9. This configuration allows all D/A converters to be
updated simultaneously and requires a minimum number of
control signals. These configurations do require 16N CLK
cycles to load any given D/A converter, where N is the
number of D/A converters.
The DAC714 can also be connected in parallel as shown in
Figure 10. This configuration allows any D/A converter in
the system to be updated in a maximum of 16 CLK cycles.
GAIN AND OFFSET ADJUST
Connections Using Potentiometers
GAIN and OFFSET adjust pins provide for trim using
external potentiometers. 15-turn potentiometers provide suf-
ficient resolution. Range of adjustment of these trims is at
least ±0.3% of Full Scale Range. Refer to Figure 6.
Using D/A Converters
The GAIN ADJUST and OFFSET ADJUST circuits of
the DAC714 have been arranged so that these points may
be easily driven by external D/A converters. Refer to
Figure 7. 12-bit D/A converters provide an OFFSET
adjust resolution and a GAIN adjust resolution of 30µV
to 50µV per LSB step.
Nominal values of GAIN and OFFSET occur when the D/A
converters outputs are at approximately half scale, +5V.
OUTPUT VOLTAGE RANGE CONNECTIONS
The DAC714 output amplifier is connected internally to
provide a 20V output range. For other ranges and configu-
rations, see Figures 6 and 7.
FIGURE 5. System Ground Considerations for High-Resolution D/A Converters.
R
1
Sense
Output
R
L
R
2
R
3
Alternate Ground
Sense Connection
System Ground
ACOMDCOM
Bus
Interface
DAC714
Analog
Power
Supply
0.01µF
(1)
0.01µF
To +V
CC
To –V
CC
NOTE: (1) Locate close to DAC714 package.
V
OUT
10kΩ10kΩ
V
REF
V
REF
R
BPO
SDI
A
0
A
1
CLR
10kΩR
FB2
DAC714
10 SBAS032A
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FIGURE 6a. Manual Offset and Gain Adjust Circuits; Unipolar Mode (0V to +10V output range).
FIGURE 6b. Manual Offset and Gain Adjust Circuits; Bipolar Mode (–5V to +5V output range).
10kΩ
9
13
14
9.75kΩ
IDAC
0-2mA
15kΩ
R
3
27kΩR
4
10kΩ
P
1
1kΩP
2
1kΩ
12
11
180Ω250Ω
Internal
+10V Reference V
REF OUT
Gain Adjust
Bipolar Offset
Offset Adjust
8ACOM
10kΩ10
R
FB2
For no external adjustments, pins 13 and 14 are not
connected. External resistors R
1
- R
4
are standard ±1%
values. Range of adjustment at least ±0.3% FSR.
V
OUT
R
1
100ΩR
2
100Ω
10kΩ
10kΩ
R2
2MΩ
9
13
10
14
9.75kΩ
IDAC
0-2mA
15kΩ
R3
27kΩ
R1
100Ω+VCC
–VCC
VOUT
P1
1kΩ
12
180Ω
10kΩ to 100kΩ
Internal
+10V Reference VREF OUT
Gain Adjust
Offset Adjust
8ACOM
RFB2
For no external adjustments, pins 13 and 14 are not
connected. External resistors R1 - R3 are standard ±1%
values. Range of adjustment at least ±0.3% FSR.
DAC714 11
SBAS032A www.ti.com
FIGURE 7. Gain and Offset Adjustment in the Bipolar Mode Using D/A Converters (–10V to +10V output range).
10kΩ
9
13
10
14
11
±10V VOUT
DAC714
9.75kΩ
IDAC
0-2mA
15kΩR3
11.8kΩ
0 to +10V
R4
24.3kΩ
180Ω250Ω
Internal
+10V Reference VREF OUT
Gain Adjust
Offset Adjust
R1
200ΩR2
1.3kΩ
RFB VREF A
12
Suggested Op Amps
OPA177GP, GS or
OPA604AP, AU
RFB VREF B
0 to +10V
Suggested Op Amps
OPA177GP, GS: Single or
OPA2604AP, AU: Dual
5kΩ
10kΩ
+10V 10kΩ
–10V
Suggested D/As
CMOS
DAC7800: Dual: Serial Input, 12-bit Resolution
DAC7801: Dual: 8-bit Port Input, 12-bit Resolution
DAC7802: Dual: 12-bit Port Input, 12-bit Resolution
DAC7528: Dual: 8-bit Port Input, 8-bit Resolution
DAC7545: Dual: 12-bit Port Input, 12-bit Resolution
DAC8043: Single: Serial Input, 12-bit Resolution
BIPOLAR (complete)
DAC813 (Use 11-bit resolution for 0V to +10V output. No op amps required).
10kΩRFB2
Bipolar Offset
For no external adjustments, pins 13 and 14 are not
connected. External resistors R1 - R4 tolerance: ±1%.
Range of adjustment at least ±0.3% FSR.
DAC714
12 SBAS032A
www.ti.com
FIGURE 8a. Cascaded Serial Bus Connection with Synchronous Update.
FIGURE 8b. Timing Diagram For Figure 8a.
SDI
A0
A1
CLK
CLR
DAC714
SDO
Data
Data Latch
Update
CLK
4
2
3
1
16
+5V
SDI
A0
A1
CLK
CLR
DAC714
SDO
4
2
3
1
16
+5V
SDI
A0
A1
CLK
CLR
DAC714
SDO
4
2
3
1
16
+5V
5
5
5
To other DACs
FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210
Clock(1)
Data
Data Latch
Update
DAC3 DAC2 DAC1
DAC714 13
SBAS032A www.ti.com
FIGURE 9a. Cascaded Serial Bus Connection with Asynchronous Update.
FIGURE 9b. Timing Diagram For Figure 9a.
SDI
A0
A1
CLK
CLR
DAC714
SDO
Data
Data Latch
Update
4
2
3
1
16
+5V
SDI
A0
A1
CLK
CLR
DAC714
SDO
4
2
3
1
16
+5V
SDI
A0
A1
CLK
CLR
DAC714
SDO
4
2
3
1
16
+5V
5
5
5
To other DACs
FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210
Update
DAC3 DAC2 DAC1
Data Latch
(1)
Data
DAC714
14 SBAS032A
www.ti.com
FIGURE 10a. Parallel Bus Connection.
FIGURE 10b. Timing Diagram For Figure 10a.
SDI
A0
A1
CLK
CLR
DAC714
SDO
Data
Data Latch 1
Data Latch 2
Data Latch 3
Update
CLK
4
2
3
1
16
SDI
A0
A1
CLK
CLR
DAC714
SDO
4
2
3
1
16
SDI
A0
A1
CLK
CLR
DAC714
SDO
4
2
3
1
16
5
5
5
CLR
FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210
Clock(1)
Data
Data Latch 1
Data Latch 2
Data Latch 3
Update
DAC1 DAC2 DAC3
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC714HB OBSOLETE CDIP SB JD 16 TBD Call TI Call TI
DAC714HC OBSOLETE CDIP SB JD 16 TBD Call TI Call TI
DAC714HL OBSOLETE CDIP SB JD 16 TBD Call TI Call TI
DAC714P NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC714PG4 NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC714U ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC714U/1K ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC714U/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC714UG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC714U/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC714U/1K SOIC DW 16 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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