AE0.3E
FUJITSU SEMICONDUCTOR
DATA SHEET
1
This d ocumen t conta ins infor mati on on pr oduct und er devel opme nt at Fujits u. Th e infor mation is int ended to he lp yo u evalu ate this pr oduct. Fujitsu reserves the
right to change this proposed product without notice.
FLASH MEMORY
CMOS
32 M (4M ×
××
× 8/2M ×
××
× 16) BIT
MirrorFlashTM
MBM29PL32TM/BM 90/10
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nDESCRIPTION
The MBM29PL32TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes by 8 bits or 2M words
by 16 bits. The MBM29PL32TM/BM is offered in 48-pin TSOP(I) and 48-ball FBGA. The device is designed to
be programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for
write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
The standard MBM29PL32TM/BM offers access times of 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
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nPRODUCT LINE UP
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nPACKAGE
Part No. MBM29PL32TM/BM
90 10
VCC 3.0V to 3.6V 3.0V to 3.6V
Max. Address Access Time 90 ns 100 ns
Max. C E Access Time 90 ns 100 ns
Max. Page Read Access Time 25 ns 30 ns
(FPT-48P-M19)
(BGA-48P-M20)
Marking Side
48-ball plastic FBGA
48-pin plastic TSOP(I)
2 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
The MBM29PL32TM/BM supports command set compatible with JEDEC single-power-supply EEPROMS
standard. Commands are written into the command register. The register contents serv e as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the de vices is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29PL32TM/BM is programmed by ex ecuting the program command sequence. This will invoke the
Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse
widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.1
seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded
Erase AlgorithmTM which is an internal algorithm that automatically preprograms the arra y if it is not already
programmed before executing the erase operation. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
Each sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided f or the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of
DQ7, by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the
devices internally return to the read mode.
Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The devices electrically erase all bits within a sector
simultaneously via hot-hole assisted erase. The words are programmed one word at a time using the EPROM
programming mechanism of hot electron injection.
Advance Info. ( AE0.3E ) 3
MBM29PL32TM/BM 90/10
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nFEATURES
• 0.23 µ
µµ
µm Process Technology
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Industry-standard pinouts
48-pin TSOP (I) (Package suffix: TN - Normal Bend Type)
48-ball FBGA (P ackage suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance Page mode
Fast 8 bytes / 4 words access cap ablilty
• Sector erase architecture
Eight 8K byte and sixty-three 64K byte sectors
Eight 4K word and sixty-three 32K w ord sectors
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
•HiddenROM
TM (Hi-ROM)
256 bytes / 128 words of Hi-ROM, accessible through a “Hi-ROM Entry” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•WP
/ACC input pin
At VIL, allows protection of outermost two 8K bytes / 4K words sectors, regardless of sector protection/
unprotection status
At VACC, increases program performance
• Embedded EraseTM Algo rithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
•Data
Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
• Program Suspend/Resume
Suspends the program operation to allow a read in another address
•Low V
CC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector Group Protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector protect command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin
This feature allows code changes in previously locked sectors
• In accordance with CFI (Common Flash Memory Interface)
Embedd e d Era seTM and Embedde d ProgramTM are trademarks of Advanced Mic ro Devices, Inc.
MirrorFlashTM an d H iddenRO MTM are trademarks of Fujitsu Limited.
4 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
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nPIN ASSIGNMENTS
(Continued)
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
N.C.
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48 pin TSOP(I)
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
(Marking Side)
FPT-48P-M19
(Top View)
C7 D7 E7 F7 G7 H7
BYTE J7 K7
C6 D6 E6 F6 G6 H6 J6 K6
A
9
A
8
A
10
A
11
DQ
7
DQ
14
DQ
13
DQ
6
C5 D5 E5 F5 G5 H5 J5 K5
WE RESET N.C. A
19
DQ
5
DQ
12
V
CC
DQ
4
C4 D4 E4 F4 G4 H4 J4 K4
RY/BY WP/
ACC A
18
A
20
DQ
2
DQ
10
DQ
11
DQ
3
C3 D3 E3 F3 G3 H3 J3 K3
A
7
A
17
A
6
A
5
DQ
0
DQ
8
DQ
9
DQ
1
C2 D2 E2 F2 G2 H2 J2 K2
A
3
A
4
A
2
A
1
A
0
CE OE V
SS
A
13
A
12
A
14
A
15
A
16
DQ
15
/
A
-1
V
SS
48 ball FBGA
(Top View)
Marking Side
BGA-48P-M20
Advance Info. ( AE0.3E ) 5
MBM29PL32TM/BM 90/10
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nPIN DESCRIPTIONS
Table1 MBM29PL32TM/BM Pin Configuration
Pin Function
A20 to A0, A-1 Address Inpu ts
DQ15 to DQ0Data Inputs/Outputs
CE Chip Enable
OE Output Ena ble
WE Write Enable
WP/ACC Hardware Write Protection/Program Acceleration
RESET Hardware Reset Pin/Temporary Sector Group Unprotection
BYTE Select Byte or Word mode
RY/BY R eady /B us y Ou tput
VCC Device Power Supply
VSS Device Ground
N.C. No Internal Connection
6 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
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nBLO C K DIAGR AM
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nLOGIC SYMBOL
VSS
VCC
WE
CE
A1, A0
OE
Erase Voltage
Generator
DQ15 to D Q 0
State
Control
Command
Register Program Voltage
Generator
Address
Latch X-Decoder
Y-Decoder
Cell Matrix
Y-Gating
Chip Enable
Output Enable
Logic Data Latch
STB
STB
RESET
WP/ACC
Timer for
Program/Erase
Input/Output
Buffers
A20 to A2
BYTE
21 A20 to A0
WE
OE
CE
DQ 15 to DQ 0
WP/ACC
RESET
16 or 8
BYTE RY/BY
A-1
Advance Info. ( AE0.3E ) 7
MBM29PL32TM/BM 90/10
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nDEVICE BUS OPERATION
(Continued)
Legend: L = VIL, H = V IH, X = VIL or VIH. See DC Characteristics f or voltage levels.
Hi-Z = High-Z, VID = 11.5 to 12.5V
Notes: *1.Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 3.
*2.Refer to Sector Group Protection.
*3.Protects the outermost two 4K words sectors
*4.DIN or DOUT as required by command sequence, data pulling, or sector protect algorithm
*5.If WP/ACC = VIL, the outermost two sectors remain protected.
If WP/ACC = VIH, the outermost two sectors will be protected or unprotected as determined by the
method specified in "Sector Group Protection" in page 23.
Table 2.1 MBM29PL32TM/BM User Bus Operations (Word Mode : BYTE = VIH)
Operation CE OE WE A0A1A2A3A6A9DQ0 to
DQ15 RESET WP/
ACC
Standby HXXXXXXXX Hi-Z H X
Autoselect Manufacture Code *1 LLHLLLLLV
ID Code H X
Autoselect Device Code *1 LLHHLLLLV
ID Code H X
Read L L H A0A1A2A3A6A9DOUT HX
Output Disable LHHXXXXXX Hi-Z H X
Write (Program/Erase) L H L A0A1A2A3A6A9*4 H *5
Enable Sector Group Protection *2 LHLLHLLLX *4 V
ID H
Temporary Sector Group
Unprotection XXXXXXXXX *4 V
ID H
Reset (Hardware) XXXXXXXXX Hi-Z L X
Sector Write Pr otection *3 XXXXXXXXX X H L
8 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
(Contin ued )
Legend: L = VIL, H = V IH, X = VIL or VIH. See DC Characteristics f or voltage levels.
Hi-Z = High-Z, VID = 11.5 to 12.5V
Notes: *1.Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 3.
*2.Refer to Sector Group Protection.
*3.Protects the outermost two 8K bytes sectors
*4.DIN or DOUT as required by command sequence, data pulling, or sector protect algorithm
*5.If WP/ACC = VIL, the outermost two sectors remain protected.
If WP/ACC = VIH, the outermost two sectors will be protected or unprotected as determined by the
method specified in "Sector Group Protection" in page 23.
Table 2.2 MBM29PL32TM/BM User Bus Operations (Byte Mode :
BYTE = VIL)
Operation CE OE WE DQ15/
A-1 A0A1A2A3A6A9DQ0 to
DQ7RESET WP/
ACC
Standby H X X X X X X X X X Hi-Z H X
Autoselect Manufacture Code *1 LLH L LLLLLV
ID Code H X
Autoselect Device Code *1 LLH L HLLLLV
ID Code H X
Read L L H A-1 A0A1A2A3A6A9DOUT HX
Output Disable L H H X X X X X X X Hi-Z H X
Write (Program/Erase) L H L A-1 A0A1A2A3A6A9*4 H *5
Enable Sector Gr ou p Prot ection *2 LHLLLHLLLX*4 V
ID H
Temporary Sector Group
Unprotection XXX X XXXXXX *4 V
ID H
Reset (Hardware) XXX X XXXXXXHi-Z L X
Sector Write Protection *3 XXX X XXXXXX X H L
Advance Info. ( AE0.3E ) 9
MBM29PL32TM/BM 90/10
Table 3 MBM29PL32TM/BM Standard Command Definitions (Note*1)
Command
Sequence
Bus
Write
Cycle
s
Req'd
First Bus
Write Cycle Second Bus
Write Cycle Third Bus
Write Cycle Fourth Bus
Read/Write
Cycle Fifth Bus
Write Cycle Sixth Bus
Write Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset *2 Word/
Byte 1 XXXh F0h — — — — — — — — — —
Reset *2 Word 3555h AAh 2AAh 55h 555h F0h — — — — — —
Byte AAAh 555h AAAh
Autoselect(Device ID) Word 4555h AAh 2AAh 55h 555h 90h 00h 04h — — — —
Byte AAAh 555h AAAh
Program Word 4555h AAh 2AAh 55h 555h A0h PA PD — — — —
Byte AAAh 555h AAAh
Chip Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
Byte AAAh 555h AAAh AAAh 555h AAAh
Sector Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h
Byte AAAh 555h AAAh AAAh 555h
Program/Erase Suspend *3 1 BAh B0h — — — — — — — — — —
Program/Erase Resume *3 1BAh30h— — ———— ————
Set to Fast Mode *4 Word 3555h AAh 2AAh 55h 555h 20h—— ————
Byte AAAh 555h AAAh
Fast Program *4 Word/
Byte 2 XXXh A0h PA PD — — — — — — — —
Reset from Fast Mode *5 Word/
Byte 2 XXXh 90h XXXh 00h*12 ———— ————
Write to Buffer Word 20 555h AAh 2AAh 55h SA 25h SA 0Fh PA PD WBL PD
Byte AAAh 555h
Program Buffer to F lash (Co nfirm) 1 SA 29h — — — — — — — — — —
Write to Buffer Abort
Reset*6
Word 3555h AAh 2AAh 55h XXXh F0h — — — — — —
Byte AAAh 555h
Extended Sector Group
Protection *7,*8
Word 4XXXh 60h SGA 60h SGA 40h SGA SD ————
Byte
Query *9 Word 155h 98h— — ———— ————
Byte AAh
Hi-ROM Entry *10 Word 3555h AAh 2AAh 55h 555h 88h—— ————
Byte AAAh 555h AAAh
Hi-ROM Program *10,*11 Word 4555h AAh 2AAh 55h 555h A0h PA PD — — — —
Byte AAAh 555h AAAh
Hi-ROM Exit *11 Word 4555h AAh 2AAh 55h 555h 90h XXXh 00h — — — —
Byte AAAh 555h AAAh
10 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Legend: Addres s bi t s A20 to A11 = X = “H” or “L” for all address commands except for Program Address (PA),
Sector Address (SA) and Sector Group Address (SGA).
Bus operations are defined in Tables 2.
RA = Address of the memory location to be read.
P A = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the write pulse.
SA = Address of the sector to be programmed / erased. The combination of A20, A19, A18, A17, A16
and A15 will uniquely select any sector. See Table 5.
SGA = Sector Group Address to be protected. See Table 6.
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write plus.
WBL = Write Buffer Location
HRA = Address of the HiddenROM area ;
29PL32TM (Top Boot Type) Word Mode : 1FFF7Fh to 1FFFFFh
Byte Mode : 3FFEFFh to 3FFFFFh
29P L32BM (Bottom Boot Type)Word Mode : 000000h to 00007Fh
Byte Mode : 000000h to 0000FFh
Notes: *1.The command combinations not described in Table 3 are illegal.
*2.Both of these reset commands are equivalent except for "Write to Buffer Abort" reset.
*3.The Erase Suspend and Erase Resume command are valid only during a sector erase operation.
*4.The Set to Fast Mode command is required prior to the Fast Program command.
*5.The Reset from Fast Mode command is required to return to the read mode when the device is in
fast mode.
*6.Reset to the read mode. The Write to Buffer Abert Reset command is required after the Write to
Buffer operation was aborted.
*7.This command is valid while RESET = VID.
*8.Sector Group Address (SGA) with A6 = 0, A3 = 0, A2 = 0, A1 = 1, and A0 = 0
*9.The valid address are A6 to A0.
*10.The HiddenROM Entry command is required prior to the HiddenROM programming.
*11.This command is valid during HiddenROM mode.
*12.The data “F0h” is also acceptable.
Advance Info. ( AE0.3E ) 11
MBM29PL32TM/BM 90/10
Notes: *1. A-1 is for Byte mode.
*2.At Word mode, a read cycle at address 01h ( at Byte mode, 02h ) outputs device code. When 227Eh
( at Byte mode, 7Eh ) is output, it indicates that reading two additional codes, called Extended Device
Codes, will be required. Therefore the system may continue reading out these Extended Device
Codes at the address of 0Eh ( at Byte mode, 1Ch ), as well as at 0Fh ( at Byte mode, 1Eh ).
*3. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group
addresses.
Table 4 Sector Group Protection Verify Autoselect Codes
Type A20 to A12 A6A3A2A1A0A-1*1 Code (HEX )
Manufacturer’s Code X VIL VIL VIL VIL VIL VIL 04h
Device Code
Word
XV
IL VIL VIL VIL VIH X 227Eh
Byte
VIL 7Eh
Extended
Device
Code *2
MBM29PL32TM
Word
XV
IL VIH VIH VIH VIL X
221Ah
Byte
VIL
1Ah
Word
XV
IL VIH VIH VIH VIH X
2201h
Byte
VIL
01h
MBM29PL32BM
Word
XV
IL VIH VIH VIH VIL X
221Ah
Byte
VIL
1Ah
Word
XV
IL VIH VIH VIH VIH X
2200h
Byte
VIL
00h
Sector Group Protection Sector Group
Addresses VIL VIL VIL VIH VIL VIL *3
12 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Table 5.1 Sector Address Table (MBM29PL32TM)
(Continued)
Sec-
tor
Se ctor Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA0 0 0 0 0 0 0 X X X 64/32 000000h to 00FFFFh 000000h to 007FFFh
SA1 0 0 0 0 0 1 X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh
SA2 0 0 0 0 1 0 X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh
SA3 0 0 0 0 1 1 X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh
SA4 0 0 0 1 0 0 X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh
SA5 0 0 0 1 0 1 X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh
SA6 0 0 0 1 1 0 X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh
SA7 0 0 0 1 1 1 X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh
SA8 0 0 1 0 0 0 X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh
SA9 0 0 1 0 0 1 X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh
SA10 0 0 1 0 1 0 X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh
SA11 0 0 1 0 1 1 X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh
SA12 0 0 1 1 0 0 X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh
SA13 0 0 1 1 0 1 X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh
SA14 0 0 1 1 1 0 X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh
SA15 0 0 1 1 1 1 X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh
SA16 0 1 0 0 0 0 X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh
SA17 0 1 0 0 0 1 X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh
SA18 0 1 0 0 1 0 X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh
SA19 0 1 0 0 1 1 X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh
SA20 0 1 0 1 0 0 X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh
SA21 0 1 0 1 0 1 X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh
SA22 0 1 0 1 1 0 X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh
SA23 0 1 0 1 1 1 X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh
SA24 0 1 1 0 0 0 X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh
SA25 0 1 1 0 0 1 X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh
SA26 0 1 1 0 1 0 X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA27 0 1 1 0 1 1 X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA28 0 1 1 1 0 0 X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA29 0 1 1 1 0 1 X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA30 0 1 1 1 1 0 X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA31 0 1 1 1 1 1 X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
Advance Info. ( AE0.3E ) 13
MBM29PL32TM/BM 90/10
(Continued)
(Continued)
Sec-
tor
Se ctor Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA32 1 0 0 0 0 0 X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh
SA33 1 0 0 0 0 1 X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh
SA34 1 0 0 0 1 0 X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh
SA35 1 0 0 0 1 1 X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh
SA36 1 0 0 1 0 0 X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh
SA37 1 0 0 1 0 1 X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh
SA38 1 0 0 1 1 0 X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh
SA39 1 0 0 1 1 1 X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh
SA40 1 0 1 0 0 0 X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh
SA41 1 0 1 0 0 1 X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh
SA42 1 0 1 0 1 0 X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh
SA43 1 0 1 0 1 1 X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh
SA44 1 0 1 1 0 0 X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh
SA45 1 0 1 1 0 1 X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh
SA46 1 0 1 1 1 0 X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh
SA47 1 0 1 1 1 1 X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh
SA48 1 1 0 0 0 0 X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh
SA49 1 1 0 0 0 1 X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh
SA50 1 1 0 0 1 0 X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh
SA51 1 1 0 0 1 1 X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh
SA52 1 1 0 1 0 0 X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh
SA53 1 1 0 1 0 1 X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh
SA54 1 1 0 1 1 0 X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh
SA55 1 1 0 1 1 1 X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh
SA56 1 1 1 0 0 0 X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh
SA57 1 1 1 0 0 1 X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh
SA58 1 1 1 0 1 0 X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA59 1 1 1 0 1 1 X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA60 1 1 1 1 0 0 X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA61 1 1 1 1 0 1 X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA62 1 1 1 1 1 0 X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA63 1 1 1 1 1 1 0 0 0 8/4 3F0000h to 3F1FFFh 1F8000h to 1F8FFFh
SA64 1 1 1 1 1 1 0 0 1 8/4 3F2000h to 3F3FFFh 1F9000h to 1F9FFFh
14 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
(Continued)
Note : The address range is A20 : A-1 if in Byte mode (BYTE = VIL) .
The address range is A20 : A0 if in Word mode (BYTE = VIH) .
Sec-
tor
Se ctor Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA65 1 1 1 1 1 1 0 1 0 8/4 3F4000h to 3F5FFFh 1FA000h to 1FAFFFh
SA66 1 1 1 1 1 1 0 1 1 8/4 3F6000h to 3F7FFFh 1FB000h to 1FBFFFh
SA67 1 1 1 1 1 1 1 0 0 8/4 3F8000h to 3F9FFFh 1FC000h to 1FCFFFh
SA68 1 1 1 1 1 1 1 0 1 8/4 3FA000h to 3FBFFFh 1FD000h to 1FDFFFh
SA69 1 1 1 1 1 1 1 1 0 8/4 3FC000h to 3FDFFFh 1FE000h to 1FEFFFh
SA70 1 1 1 1 1 1 1 1 1 8/4 3FE000h to 3FFFFFh 1FF000h to 1FFFFFh
Advance Info. ( AE0.3E ) 15
MBM29PL32TM/BM 90/10
Table 5.2 Sector Address Table (MBM29PL32BM)
(Continued)
Sec-
tor
Se ctor Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA70 1 1 1 1 1 1 X X X 64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
SA69 1 1 1 1 1 0 X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA68 1 1 1 1 0 1 X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA67 1 1 1 1 0 0 X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA66 1 1 1 0 1 1 X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA65 1 1 1 0 1 0 X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA64 1 1 1 0 0 1 X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh
SA63 1 1 1 0 0 0 X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh
SA62 1 1 0 1 1 1 X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh
SA61 1 1 0 1 1 0 X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh
SA60 1 1 0 1 0 1 X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh
SA59 1 1 0 1 0 0 X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh
SA58 1 1 0 0 1 1 X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh
SA57 1 1 0 0 1 0 X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh
SA56 1 1 0 0 0 1 X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh
SA55 1 1 0 0 0 0 X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh
SA54 1 0 1 1 1 1 X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh
SA53 1 0 1 1 1 0 X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh
SA52 1 0 1 1 0 1 X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh
SA51 1 0 1 1 0 0 X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh
SA50 1 0 1 0 1 1 X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh
SA49 1 0 1 0 1 0 X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh
SA48 1 0 1 0 0 1 X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh
SA47 1 0 1 0 0 0 X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh
SA46 1 0 0 1 1 1 X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh
SA45 1 0 0 1 1 0 X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh
SA44 1 0 0 1 0 1 X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh
SA43 1 0 0 1 0 0 X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh
SA42 1 0 0 0 1 1 X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh
SA41 1 0 0 0 1 0 X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh
SA40 1 0 0 0 0 1 X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh
SA39 1 0 0 0 0 0 X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh
SA38 0 1 1 1 1 1 X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
16 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
(Continued)
(Continued)
Sec-
tor
Se ctor Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA37 0 1 1 1 1 0 X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA36 0 1 1 1 0 1 X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA35 0 1 1 1 0 0 X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA34 0 1 1 0 1 1 X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA33 0 1 1 0 1 0 X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA32 0 1 1 0 0 1 X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh
SA31 0 1 1 0 0 0 X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh
SA30 0 1 0 1 1 1 X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh
SA29 0 1 0 1 1 0 X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh
SA28 0 1 0 1 0 1 X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh
SA27 0 1 0 1 0 0 X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh
SA26 0 1 0 0 1 1 X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh
SA25 0 1 0 0 1 0 X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh
SA24 0 1 0 0 0 1 X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh
SA23 0 1 0 0 0 0 X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh
SA22 0 0 1 1 1 1 X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh
SA21 0 0 1 1 1 0 X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh
SA20 0 0 1 1 0 1 X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh
SA19 0 0 1 1 0 0 X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh
SA18 0 0 1 0 1 1 X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh
SA17 0 0 1 0 1 0 X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh
SA16 0 0 1 0 0 1 X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh
SA15 0 0 1 0 0 0 X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh
SA14 0 0 0 1 1 1 X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh
SA13 0 0 0 1 1 0 X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh
SA12 0 0 0 1 0 1 X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh
SA11 0 0 0 1 0 0 X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh
SA10 0 0 0 0 1 1 X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh
SA9 0 0 0 0 1 0 X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh
SA8 0 0 0 0 0 1 X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh
SA7 0 0 0 0 0 0 1 1 1 8/4 00E000h to 00FFFFh 007000h to 007FFFh
SA6 0 0 0 0 0 0 1 1 0 8/4 00C000h to 00DFFFh 006000h to 006FFFh
SA5 0 0 0 0 0 0 1 0 1 8/4 00A000h to 00BFFFh 005000h to 005FFFh
Advance Info. ( AE0.3E ) 17
MBM29PL32TM/BM 90/10
(Continued)
Note : The address range is A20 : A-1 if in Byte mode (BYTE = VIL) .
The address range is A20 : A0 if in Word mode (BYTE = VIH) .
Sec-
tor
Se ctor Address Sector
Size
(Kbytes/
Kwords)
(×
××
×8)
Address Range (×
××
×16)
Address Range
A20 A19 A18 A17 A16 A15 A14 A13 A12
SA4 0 0 0 0 0 0 1 0 0 8/4 008000h to 009FFFh 004000h to 004FFFh
SA3 0 0 0 0 0 0 0 1 1 8/4 006000h to 007FFFh 003000h to 003FFFh
SA2 0 0 0 0 0 0 0 1 0 8/4 004000h to 005FFFh 002000h to 002FFFh
SA1 0 0 0 0 0 0 0 0 1 8/4 002000h to 003FFFh 001000h to 001FFFh
SA0 0 0 0 0 0 0 0 0 0 8/4 000000h to 001FFFh 000000h to 000FFFh
18 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Table 6.1 Sector Group Address Table (MBM29PL32TM)
Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 0000XXXXX SA0 to SA3
SGA1 0001XXXXX SA4 to SA7
SGA2 0010XXXXX SA8 to SA11
SGA3 0011XXXXX SA12 to SA15
SGA4 0100XXXXX SA16 to SA19
SGA5 0101XXXXX SA20 to SA23
SGA6 0110XXXXX SA24 to SA27
SGA7 0111XXXXX SA28 to SA31
SGA8 1000XXXXX SA32 to SA35
SGA9 1001XXXXX SA36 to SA39
SGA10 1010XXXXX SA40 to SA43
SGA11 1011XXXXX SA44 to SA47
SGA12 1100XXXXX SA48 to SA51
SGA13 1101XXXXX SA52 to SA55
SGA14 1110XXXXX SA56 to SA59
SGA15 1 1 1 1
00
XXX SA60 to SA6201
10
SGA16 111111000 SA63
SGA17 111111001 SA64
SGA18 111111010 SA65
SGA19 111111011 SA66
SGA20 111111100 SA67
SGA21 111111101 SA68
SGA22 111111110 SA69
SGA23 111111111 SA70
Advance Info. ( AE0.3E ) 19
MBM29PL32TM/BM 90/10
Table 6.2 Sector Group Address Table (MBM29PL32BM)
Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 000000000 SA0
SGA1 000000001 SA1
SGA2 000000010 SA2
SGA3 000000011 SA3
SGA4 000000100 SA4
SGA5 000000101 SA5
SGA6 000000110 SA6
SGA7 000000111 SA7
SGA8 0000
01
X X X SA8 to SA1010
11
SGA9 0001XXXXX SA11 to SA14
SGA10 0010XXXXX SA15 to SA18
SGA11 0011XXXXX SA19 to SA22
SGA12 0100XXXXX SA23 to SA26
SGA13 0101XXXXX SA27 to SA30
SGA14 0110XXXXX SA31 to SA34
SGA15 0111XXXXX SA35 to SA38
SGA16 1000XXXXX SA39 to SA42
SGA17 1001XXXXX SA43 to SA46
SGA18 1010XXXXX SA47 to SA50
SGA19 1011XXXXX SA51 to SA54
SGA20 1100XXXXX SA55 to SA58
SGA21 1101XXXXX SA59 to SA62
SGA22 1110XXXXX SA63 to SA66
SGA23 1111XXXXX SA67 to SA70
20 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Table 7 Common Flash Memory Interface Code
(Continued)
A0 to A6DQ0 to DQ15 Description
10h
11h
12h
0051h
0052h
0059h
Query-unique ASCII string “QRY”
13h
14h 0002h
0000h Primary OEM Co mmand Set
(02h = Fujitsu standard)
15h
16h 0040h
0000h Address for Primary Extended Table
17h
18h 0000h
0000h Alternate OEM Command Set
(00h = not applicable)
19h
1Ah 0000h
0000h Address for Alternate OEM Extended Table
(00h = not applicable)
1Bh 0027h VCC Min. (write/erase)
DQ7-DQ4: 1V/bit,
DQ3-DQ0: 100 mV/bit
1Ch 0036h VCC Max. (write/erase)
DQ7-DQ4: 1V/bit,
DQ3-DQ0: 100 mV/bit
1Dh 0000h VPP Min. voltage (00h = no Vpp pin)
1Eh 0000h VPP Max. voltage (00h =no Vpp pin)
1Fh 0007h Typical timeout per single write 2N µS
20h 0007h Typical timeout for Min. size buffer write 2N µS
21h 000Ah Typical timeout per individual sector erase 2N mS
22h 0000h Typical timeout for full chip erase 2N mS
23h 0001h Max. timeout for write 2N times typical
24h 0005h Max. timeout for buffer write 2N times typical
25h 0004h Max. timeout per individual sector erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical
27h 0016h Device Size = 2N by te
28h
29h 0002h
0000h Flash Device Interface description
2Ah
2Bh 0005h
0000h Max. number of byte in
multi-byte write = 2N
2Ch 0002h Number of Erase Block Regions within device (01h = uniform)
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
31h
32h
33h
34h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
Advance Info. ( AE0.3E ) 21
MBM29PL32TM/BM 90/10
(Continued)
A0 to A6DQ0 to DQ15 Description
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h 0031h Major version number, ASCII
44h 0033h Minor version number, ASCII
45h 0008h Address Sensitiv e Unlock
Required
46h 0002h Erase Suspend
(02h = To Read & Write)
47h 0004h Number of sectors in per group
48h 0001h Sector Temporary Unprotection
(01h = Supp orted)
49h 0004h Sector Protection Algorithm
4Ah 0000h Dual Operation
(00h = Not Supported)
4Bh 0000h Burst Mode Type
(00h = Not Supported)
4Ch 0001h Page Mode Type
(01h = 4-Word Page Supported)
4Dh 00B5h VACC (Acceleration) Supply Minimum
DQ7-DQ4: 1V/bit,
DQ3-DQ0: 100mV/bit
4Eh 00C5h VACC (Acceleration) Supply Maximum
DQ7-DQ4: 1V/bit,
DQ3-DQ0: 100mV/bit
4Fh 00XXh Write Protect
(02h = MBM29PL32BM
03h = MBM29PL32TM
04h = Uniform sectors bottom Write Protect)
50h 01h Program Suspend
(01h = Supp orted)
22 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
n
nn
nFUNCTIONAL DESCRIPTION
Standby Mode
There are two wa ys to implement the standby mode on the device, one using both the CE and RESET pins,
and the other via the RESET pin only.
When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC ±0.3 V. Under
this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active
current (ICC2) is required even when CE = "H”. The device can be read with standard access time (tCE) from
either of these standby modes.
When using the RESET pin only, CMOS standby mode is achiev ed with RESET input held at VSS ±0.3 V (CE
= “H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set
high, the device requires tRH as a wake-up time for output to be valid for read access.
During standby mode, the output is in the high impedance state, regardless of OE input.
Automatic Sleep Mode
A utomatic sleep mode works to restrain power consumption during read-out of de vice data. It can be useful
in applications such as handy terminal, which requires low power consumption.
To activate this mode, the device automatically switch themselves to low power mode when the device
addresses remain stable after 30 ns from data valid. It is not necessary to control CE, WE, and OE in this
mode. The current consumed is typically 1 µA (CMOS Level).
Since the data are latched during this mode, the data are continuously read out. When the addresses are
changed, the mode is automatically canceled and the device read-out the data f or changed addresses.
Autoselect
The Autoselect mode allows reading out of a binary code and identifies its manufacturer and type.It is intended
for use by programming equipment for the purpose of automatically matching the device to be programmed
with its corresponding programming algorithm.
To activate this mode, the programming equipment must force VID on address pin A9. Two identifier bytes
may then be sequenced from the devices outputs by toggling A0. All addresses can be either High or Low
except A6, A3,A2,A1 and A0. See Table 2.
The manufacturer and device codes may also be read via the command register, f or instances when the
device is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in Table 3.Refer to Autoselect Command section.
In W ord mode, a read cycle from address 00h returns the manuf acturer’ s code (Fujitsu = 04h) . A read cycle
at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, calle d
Extend ed Device Codes will be r equired. Therefor e the system may continue readi ng out these E xtended
Device Codes at add resses of 0Eh and 0Fh. Notic e that th e above applies to Word mode. The addr esses
and codes differ from those of Byte mode. Refer to Tab le 4.
Read Mode
The device has two con trol functions r equired to obtai n data at the outputs. CE is the power control an d
used for a device selection. OE is the output control and used to gate data to the output pins.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enab le
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable f or at least tACC-tOE time.) When reading out a data without changing addresses
after power-up, input hardware reset or to change CE pin from “H” or “L”.
Advance Info. ( AE0.3E ) 23
MBM29PL32TM/BM 90/10
Page Mode Read
The device is capable of fast read access f or random locations within limited address location called P age .
The P age size of the device is 8 bytes / 4 words, within the appropriate P age being selected by the higher
address bits A20 to A2 and the address bits A1 to A0 in Word mode ( A1 to A-1 in Byte mode) determining the
specific word within that page. this is an asynchronous operation with the microprocessor supplying the
specific word location.
The initial page access is equal to the random access (tACC) and subsequent Page read access (as long as
the locations specified by the microprocessor fall within that Page) is equivalent to the page address access
time(tPACC). Here again, CE selects the device and OE is the output control and should be used to gate data
to the output pins if the device is selected. Fast Page mode, accesses are obtained by keeping A20 to A2
constant and changing A1 and A0 in Word mode ( A1 to A-1 in Byte mode ) to select the specific word within
that Page.
Output Disable
With th e OE input at logic high level (VIH), output from the de vices are disabled. This may cause the output
pins to be in a high impedance state.
Write
Device erasure and programming are accomplished via the command register . The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the device function.
The command register itself does not occupy any addressable memory location. The register is a latch used
to store the commands, along with the address and data inf ormation needed to ex ecute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched
on the falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or
CE, whichever starts first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The device features hardware sector group protection. This feature will disable both program and erase
operation s in any c omb ina tio n o f th irty two s ec tor grou ps of me mory.See Table 6. The us er‘s s ide c an us e
the sector group protection using programming equipment. The device is shipped with all sector groups that
are unprotected.
To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL
and A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A 16, A15, A 14, A13, and A12)
should be set to the sector to be protected. Table 5 defines the sector address for each of the se v enty-one
(71) individual sectors, and T able 6 defines the sector group address for each of the twenty-four (24) individual
group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is
terminated with the rising edge of the same. Sector group addresses must be held constant during the WE
pulse. See Figures 18 and 26 for sector group protection timing diagram and algorithm.
To verify programming of the protection circuitry, the programming equipment must f orce VID on address pin
A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15,
A14, A 13, and A12) while (A6, A3, A 2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ0
for a protected sector . Otherwise the de vice will produce “0” for unprotected sectors. In this mode, the lower
order addresses, e xcept f or A0, A 1, A2, A3, and A6 can be either High or Low. Address locations with A1 = VIL
are reserved for Autoselect manufacturer and device codes. A-1 requires applying to VIL on Byte mode.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
P erf orming a read operation at the address location XX02h, where the higher order addresses(A20, A19, A18,
A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a
protected sector group. See Table 4 for Autoselect codes.
24 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Temporary Sector Group Unprotection
This feature allows temporary unprotection of pre viously protected sector groups of the devices in order to
change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage
(VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the
sector group addresses. Once the VID is taken awa y from the RESET pin, all the previously protected sector
groups will be protected again. Refer to Figures 19 and 27.
Hardware Reset
The devices ma y be reset by driving the RESET pin to VIL from VIH. The RESET pin has a pulse requirement
and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation
in the process of being executed will be terminated and the internal state machine will be reset to the read
mode “ tREADY” after the RESET pin i s dri ven low. Fur t her m ore, once the RESE T p in go es hi gh , th e devices
require an additional “tRH” bef ore it will allow read access. When the RESET pin is low, the devices will be in
the sta ndby mode for the duration of th e pul se an d all th e data outpu t pins wil l be tri- stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted.
Write Protect (WP)
The Write Protection function provides a hardware method of protecting certain outermost 8K bytes / 4K
words sectors without using VID. This function is one of two provided by the WP/ACC pin.
If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the
outermost 8K b ytes / 4K words sectors independently of whether this sector was protected or unprotected
using the method described in “Sector Group Protection" above.
If the system asserts VIH on the WP/ACC pin, the device reverts of whether the outermost 8K bytes / 4K
words sectors were last set to be protected to the unprotected status. Sector protection or unprotection for
this sector depends on whether this was last protected or unprotected using the method described in “Sector
protection/unprotection”.
Accelerated Program Operation
The device offers accelerated program operation which enables programming in high speed. If the system
asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required
for program operation will reduce to about 60%. This function is primarily intended to allow high speed
programing, so caution is needed as the sector group becomes temporarily unprotected.
The system would use a fast program command sequence when programming during acceleration mode.
Set command to fast mode and reset command from f ast mode are not necessary. When the device enters
the acceleration mode, the device is automatically set to fast mode. Therefore , the present sequence could
be used for programming and detection of completion during acceleration mode.
Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remov e VACC from the
WP/ACC pin while programming. See Figure 21
Advance Info. ( AE0.3E ) 25
MBM29PL32TM/BM 90/10
n
nn
nCOMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register .
T able 3 shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume
(30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend
(B0h) and Program Resume (30h) commands are valid only while the Program operation is in
progress.Moreover Reset commands are functionally equivalent, resetting the device to the read mode.
Please note that commands must be asserted to DQ7 to DQ0 and DQ15 to DQ8 bits are ignored.
Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read mode, the Reset
operation is initiated by writing the Reset command sequence into the command register. The devices remain
enabled for reads until the command register contents are altered.
The devices will automatically be in the reset state after power-up . In this case, a command sequence is not
required in order to read data.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However applying high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command
register.
The Autoselect command sequence is initiated first by writing two unlock cycles. This is follow ed by a third
write cycle that contains the address and the Autoselect command. Then the manufacture and device codes
can be read from the address, and an actual data of memory cell can be read from the another address.
Following the command write, a read cycle from address 00h retur ns the manufactures’s code (Fujitsu =
04h). A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional
codes, called Extended Device Codes will be required. Therefore the system may continue reading out these
Extended Device Codes at address of 0Eh as well as at 0Fh. Notice that abov e applies to Word mode. The
addresses and codes differ from those of Byte mode. Refer to Table 4.
To terminate the operation, it is necessary to write the Reset command into the register. To execute the
Autoselect command during the operation, Reset command must be written before the Autoselect command.
26 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Programming
The devices are programmed on a word-by-word (or byte-by-byte ) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and
data write cycles. Addresses are latched on the falling edge of CE or WE, whichev er happens later and the
data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE
(whichever happens first) starts programming. Upon executing the Embedded Program Algorithm command
sequence, the system is not required to provide further controls or timings. The device will automatically
provide adequate internally generated program pulses and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data P olling), DQ6 (Toggle Bit)
or RY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being
programmed.
The programming operation is completed when the data on DQ7 is equivalent to data written to this bit at
which the devices return to the read mode and plogram addresses are no longer latched. Therefore, the
devices require that a valid address to the devices be supplied by the system at this particular instance.
Hence Data Polling requires the same address which is being programmed.
If hardware reset occurs during the programming operation, the data being written is not guaranteed.
Programming is allowed in any address sequence and across sector boundaries. Beware that a data “0”
cannot be programmed back to a “1”. Attempting to do so may result in either failure condition or an apparent
success according to the data polling algorithm. But a read from Reset mode will show that the data is still
“0”. Only erase operations can convert “0”s to “1”s.
Note that attempting to program a “1” over a “0” will result in programming failure. This precaution is the
same with Fujitsu standard NOR devices. Figure 22 illustrates the Embedded ProgramTM Algorithm using
typical command strings and bus operations.
Program Suspend/Resume
The Program Suspend command allows the system to interrupt a program operation so that data can be
read from any address. Writing the Program Suspend command (B0h) during Embedded Program operation
immediately suspends the programming. The Program Suspend command can also be issued during a
programming operation while an erase is suspended. Refer to "Erase Suspend/Resume" for the detail.
When the Program Suspend command is written during a programming process, the device halts the program
operation within 1us and updates the status bits.After the program operation has been suspended, the system
can read data from any address. The data at program-suspended address is not valid. Normal read timing
and command definitions apply.
After the Program Resume command (30h) is written, the device reverts to programming. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard
program operation. See "Write Operation Status" for more information.
The system also writes the Autoselect command sequence in the Program Suspend mode. The device allows
reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in
the memory. When the device e xits the Autoselect mode, the device re verts to the Program Suspend mode,
and is ready for another valid operation. See "Autoselect Command Sequence" for more information.
The system must write the Program Resume command to exit from the Program Suspend mode and continue
the programming operation. Further writes of the Resume command are ignored. Another Program Suspend
command can be written after the device resumes programming.
Advance Info. ( AE0.3E ) 27
MBM29PL32TM/BM 90/10
Write Buffer Progr amming Operations
Write Buffer Programming allows the system write to series of 16 words in one programming operation. This
results in faster effective word programming time than the standard programming algorithms. The Write
Buffer Programming command sequence is initiated by first writing two unlock cycles. This is follo wed b y a
third write cycle selecting the Sector Address in which programming will occur. In forth cycle contains both
Sector Address and unique code for data bus width will be loaded into the page buffer at the Sector Address
in which programming will occur.
The system then writes the starting address/data combination. This “starting address” must be the same
Sector Address used in third and fourth cycles and its lower addresses of A3 to A0 should be 0h. All subsequent
address must be incremented by 1. Addresses are latched on the falling edge of CE or WE, whichever
happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising
edge of CE or WE (whichever happens first) starts programming. Upon executing the Write Buffer
Programming Operations command sequence, the system is not required to provide further controls or
timings. The device will automatically provide adequate internally generated program pulses and v erify the
programmed cell margin.
DQ7(Data Polling), DQ6(Toggle Bit), DQ5(Exceeded Timing Limits), DQ1(Write-to-Buffer Abort) should be
monitored to determine the device status during Write Buffer Programming. In addition to these functions,
it is also possible to indicate to the host system that Write Buffer Programming Operations are either in
progress or have been completed by RY/BY. See Table9 "Hardware Sequence Flags".
The Data polling techniques described in Figure 24 should be used while monitoring the last address location
loaded into the write buffer. In addition, it is not neccessary to specify an address in Toggle Bit techniques
described in Figure 25. The automatic programing operation is completed when the data on DQ7 is equivalent
to the data written to this bit at which time the device returns to the read mode and addresses are no longer
latched ( See Table9 " Hardware Sequence Flags").
The write-buffer programming operation can be suspended using the standard program suspend/resume
commands.
Once the write buffer programming is set, the system must then write the “Program Buffer to Flash” command
at the Sector Address. Any other address/data combination will abort the Write Buffer Programming operation
and the de vice will continue busy state.
The Write Buffer Programming Sequence can be ABORTED by doing the following :
• Different Sector Address is asserted.
• Wr ite data other tha n the “Program Buffer to Flash" comma nd after the sp ecified number of “dat a load”
cycles.
A “Write-to-Buffer-Abort Reset” command sequence must be written to the device to return to read mode.
(See Table 3 for details on this command sequence.)
28 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Chip Erase
Chip erase is a six bus cycle operation. It begins two “unlock” write cycles followed by writing the “set-up”
command, and two “unlock” write cycles followed b y the chip erase command which invok es the Embedded
Erase algorithm.
The device does not require the user to program the device prior to erase. Upon e xecuting the Embedded
Erase Algorithm the devices automatically programs and verifies the entire memory for an all zero data
pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or
timings during these operations.
The system can determine the erase operation status by using DQ7 (Data Polling), DQ6 (Toggle Bit I) and
DQ2 (Toggle Bit II) or R Y/BY output signal. The chip erase begins on the rising edge of the last CE or WE,
whichever happens first from last command sequence and completes when the data on DQ7 is “1” (See
Write Operation Status section.) at which time the device returns to read mode.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing
the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command.
Multiple sectors may be erased concurrently by writing the same six bus cycle operations. This sequence
is followed b y writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than Erase Time-out time(tTOW). Otherwise that command will
not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during
this time to guarantee this condition. The interrupts can reoccur after the last Sector Erase command is
written. A time-out of “tTOW” from the rising edge of last CE or WE, whichever happens first, will initiate the
execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first
occurs within the “tTOW” time-out window the timer is reset (monitor DQ3 to determine if the sector erase timer
window is still open, see section DQ3, Sector Erase Timer). Resetting the devices once execution has begun
will corrupt the data in the sector . In that case, restart the erase on those sectors and allow them to complete
(refer to the Write Operation Status). Loading the sector erase buffer may be done in any sequence and with
any number of sectors (0 to 70).
Sector erase does not require the user to program the devices prior to erase. The devices automatically
program all memory locations in the sector(s) to be erased prior to electrical erase using the Embedded
Erase Algorithm. When erasing a sector, the remaining unselected sectors remain unaffected. The system
is not required to provide any controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit)
or RY/BY.
The sector erase begins after the “tTOW” time-out from the rising edge of CE or WE whichever happens first
for the last sect or erase command pulse and completes when the data on DQ7 is “1” (see Write Operation
Status section), at which the devices return to the read mode. Data polling and Toggle Bit must be performed
at an address within any of the sectors being erased.
Advance Info. ( AE0.3E ) 29
MBM29PL32TM/BM 90/10
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt Sector Erase operation and then perform read
or programming to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation within the time-out period for sector erase. Writting the Erase Suspend command (B0h) during
the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the "Erase Resume" command (30h) resumes the erase operation.
When the "Erase Suspend" command is written during the Sector Erase operation, the device takes maximum
of “tSPD” to suspend the erase operation. When the devices enter the erase-suspended mode, the RY/BY
output pin will be at Hi-Z and the DQ7 bit will be at logic “1” and DQ6 will stop toggling. The user must use
the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation is suspended, the devices default to the erase-suspend-read mode. Reading data
in this mode is the same as reading from the standard read mode, except that the data must be read from
sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while
the device is in the erase-suspend-read mode will cause DQ2 to toggle. see the section on DQ2.
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
it is the same as programming in the regular Program mode, except that the data must be programmed to
sectors that are not erase-suspended. Reading successively from the erase-suspended sector while the
devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended
Program operation is detected by the Data polling of DQ7 or by the Toggle Bit I of DQ6, which is the same
as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be
read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes
of the Resume command at this point will be ignored. Another Erase Suspend command can be written after
the chip has resumed erasing.
Fast Mode Set/Rese t
The device has F ast Mode function. It dispenses with the initial two unclock cycles required in the standard
program command sequence by writing F ast Mode command into the command register . In this mode, the
required bus cycle for programming consists of two cycles instead of four bus cycles in standard program
command. Do not write erase command in this mode. The read operation is also ex ecuted after exiting this
mode. To exit from this mode, write Fast Mode Reset command into the command register. (Refer to the
Figure 29.) The VCC active current is required even CE = V IH during Fast Mode.
Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is e xecuted by writing program set-up command (A0h) and data write cycles (PA/PD). see Figure
29.
Extended Sector Group Pro tect ion
In addition to normal sector group protection, the device has Extended Sector Group Protection as extended
function. This function enables protection of the sector group by forcing VID on RESET pin and writes a
command sequence. Unlike conv entional procedures, it is not necessary to force VID and control timing for
contr ol pi ns . The onl y RE SET pin requires VID for sector group protection in this mode. The extended sector
group protection requires VID on RESE T pin. Wit h this co ndi tion, the op er at ion is initia te d b y writin g the se t-
up command (60h) into the command register . Then the sector group addresses pins (A20, A19, A18, A17, A16
and A15) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set VIL for
the other addresses pins is recommended), and write extended sector group protection command (60h). A
sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector
30 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
group addresses pins (A20, A19, A18, A17, A16 and A15) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set
and write a command (40h). Following the command write, a logical “1” at device output DQ0 will produce
for protected sector in the read operation. If the output data is logical “0”, write the extended sector group
protection command (60h) again. To terminate the operation, set RESET pin to VIH. (Ref er to the F igures 20
and 28.)
Query Command (CFI : Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-
compatible software support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98h) into the command register. Following the
command write, a read cycle from specific address retrieves device information. Please note that output
data of upper byte (DQ15 to DQ8) is “0”. Ref er to the CFI code table. To terminate operation, it is necessary
to write the Reset command sequence into the register. (See Table 7.)
HiddenROM (Hi-ROM) Mode
(1) HiddenROM (Hi-ROM) Region
The HiddenROM (Hi-ROM) feature provides a Flash memory region that the system may access through a
new command sequence. This is primarily intended for customers who wish to use an Electronic Serial
Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is
protected, any further modification of that region is impossible. This ensures the security of the ESN once
the product is shipped to the field.
The Hi-ROM region is 256 bytes / 128 words in length. After the system writes the Hi-ROM Entry command
sequence, it may read the Hi-ROM region by using device addresses A 6 to A0 (A20 to A7 are al l “0 ”). That is ,
the device sends only program command that would normally be sent to the address to the Hi-ROM region.
This mode of operation continues until the system issues the Exit Hi-ROM command sequence, or until
power is removed from the device. On power-up, or following a hardware reset, the device rev erts to sending
commands to the address.
If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more
information.
(2) HiddenROM (Hi-ROM) Entry Command
The de vice has a Hi-ROM area with One Time Protect function. This area is to enter the security code and
to unable the change of the code once set. Programming is allowed in this area until it is protected. Howev er,
once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required.
The Hi-ROM area is 256 bytes / 128 words. This area is in SA0 . Therefore, write the Hi-ROM entry command
sequence to enter the Hi-ROM area. It is called Hi-ROM mode when the Hi-ROM area appears.
Sectors other than the block area SA0 can be read during Hi-ROM mode. Read/program of the Hi-ROM
area is possible during Hi-ROM mode. Write the Hi-ROM reset command sequence to exit the Hi-ROM mode.
(3) HiddenROM (Hi-ROM) Program Command
To pro gram the data to the Hi-ROM area, wr ite t he Hi-ROM program comm and seque nce dur ing Hi- ROM
mode. This command is the same as the usual program command, except that it needs to write the command
dur ing Hi-ROM mode. There fore the detect ion of compl etion method is t he sam e as in the past, using th e
DQ7 data poo ling, DQ6 Toggle bit or RY/BY. You should pay atte ntion to the ad dress to b e programmed. If
an address not in the Hi-ROM area is selected, the previous data will be deleted.
Advance Info. ( AE0.3E ) 31
MBM29PL32TM/BM 90/10
(4) HiddenROM (Hi-ROM) Protect Command
There are two methods to protect the Hi-ROM area. One is to write the sector group protect setup command
(60h) , set the sector address in the H i-ROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the
sector group protect command (60h) during the Hi-ROM mode. The same command sequence may be used
because it is the same as the extension sector group protect in the past, except that it is in the Hi-ROM mode
and does not apply high voltage to the RESET pin. Please refer to above mentioned “Extended Sector Group
Protection” for details of sector group protect setting.
The other me thod is to apply high voltage (VID) to A9 a nd OE, set th e sector addres s in the Hi-ROM area
and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and ap ply the write pu lse during th e Hi-ROM mode. To verify the
protect circuit, apply high voltage (VID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address
in the Hi -ROM area, and read. When “1” appea rs on DQ 0, the protect s etting is comp leted. “ 0” will appear
on DQ0 if it is not pr otecte d. Apply write p uls e a gai n. The sa me c om man d s eque nce c oul d be us ed for the
above method because other than the Hi-ROM mode, it is the same as the sector group protect previously
mentioned.
Take note that other secto r groups will be affected if an add ress ot her than those for the Hi-ROM area is
selected for the sector group address, so please be ca reful. Pay close attention that once it is protected,
protection CANNOT BE CANCELLED.
32 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Write Operation Status
Detailed in Table 9 are all the status flags which can determine the status of the device for current mode
operation. During sector erase, the part provides the status flags automatically to the I/O ports. The
information on DQ2 is address sensitive. If an address from an erasing sector is consecutively read, then
the DQ2 bit will toggle. How e ver DQ2 will not toggle if an address from a non-erasing sector is consecutively
read. This allows the user to determine which sectors are erasing.
Once erase suspend is entered address sensitivity still applies. If the address of a non-erasing sector (one
available for read) is provided, then stored data can be read from the device. If the address of an erasing
sector (one unavailable for read) is applied, the device will output its status bits.
*1: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.
*2: Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
*3: DQ1 indicates the Write-to-Buffer ABORT status during Write-Buffer-Programming operations.
*4: The Data P olling algorithm detailed in Figure 24 should be used for Write-Buffer-Programming operations.
Note that DQ7 during Write-Buff er-Programming indicates the data-bar f or DQ7 data for the LAST LOADED
WRITE-BUFFER ADDRESS location.
Table 9 Hardware Sequence Flags
Status DQ7DQ6DQ5DQ3DQ2DQ1 *3
In Progress
Embedded Program Algorithm DQ7Toggle 0 0 1 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle *1 N/A
Program
Suspend
Mode
Program-Suspend-Read
(Progra m Sus pen ded Sector) Data Data Data Data Data Data
Program-Suspend-Read
(Non-Program Suspended Sector) Data Data Data Data Data Data
Erase
Suspend
Mode
Erase-Suspend-Read
(Erase Suspended Se ctor) 1100
Toggle*1 N/A
Erase-Suspend-Read
(Non-Erase Suspended Sector) Data Data Data Data Data Data
Erase-Suspend-Program
(Non-Erase Suspended Sector) DQ7Toggle 0 0 1 *2 N/A
Exceeded
Time Limits
Embedded Program Algorithm DQ7Toggle 1 0 1 N/A
Embedded Erase Algorithm 0 Toggle 1 1 N/A N/A
Erase
Suspend
Mode Erase-Suspend-Program
(Non-Erase Suspended Sector) DQ7Toggle 1 0 N/A N/A
Write to
Buffer *4
BUSY State DQ7Toggle 0 N/A N/A 0
Exceeded Timing Limits DQ7Toggle 1 N/A N/A 0
ABORT State DQ7Toggle 0 N/A N/A 1
Advance Info. ( AE0.3E ) 33
MBM29PL32TM/BM 90/10
DQ7
Data Polling
The devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read de vices will produce
re v erse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read
the device will produce true data last written to DQ7. Du rin g t h e E mb e dd e d Erase Alg o rithm , an at t e mpt to
read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm,
an attempt to read device will produce a “1” at the DQ7 output. The flowchart for Data P olling (DQ7) is shown
in Figure 24.
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
F or chip erase and sector erase, the Data P olling is valid after the rising edge of the sixth write pulse in the
six write pulse sequence. Data P olling must be perf ormed at sector addresses of sectors being erased, not
protected sectors. Otherwise, the status may become invalid.
If a program address falls within a protected sector, Data polling on DQ7 is active for approximately 1 µs,
then the device returns to read mode. After an erase command sequence is written, if all sectors selected
f or er as ing ar e pr ote cte d, Dat a Polling on DQ7 is active f or approximately 100 µs, then the device returns to
read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change
asynchronously while the output enable (OE) is asserted low. This means that the device is driving status
information on DQ7 at one instant of time, and then that byte’s valid data the next. Depending on when the
system samples the DQ7 output, it may read the status or valid data. Even if the device completes the
Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may still be invalid.
The valid data on DQ7 to DQ0 will be read on the successive read attempts.
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erace Suspendmode or sector erase time-out.
See Figure 12 for the Data Polling timing specifications and diagram.
DQ6
Toggle Bit I
The device also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling)
data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or
Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive
attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the
four write pulse sequences. F or chip erase and sector erase, the Toggle Bit I is v alid after the rising edge of
the sixth write pulse in the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In programm operation, if the sector being written to is protected, the Toggle bit will toggle for about 1 µs
and then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except
for the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit f or about 100
µs and then drop back into read mode, having data kept remained.
Either CE or OE toggling will cause the DQ6 to toggle. See Figure 13 for the Toggle Bit I timing specifications
and diagram.
34 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition indicating that the program or erase cycle
was not successfully completed. Data P olling is the only operating function of the device under this condition.
The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE
and WE pins will control the output disable functions as described in Table 2.
The DQ5 f ailure condition may also appear if a user tries to program a non blank location without pre-erase.
In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system
nev er reads a valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits,
the DQ5 bit will indi cat e a “1”. Not e th at thi s is not a device f a ilur e co ndi tio n si nce the device w as inco rrec tly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Eras e Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector
erase command sequence.
If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ3 ma y be used to
determine whether the sector erase timer window is still open. If DQ3 is “1” the internally controlled erase
cycle has begun. If DQ3 is “0”, the device will accept additional sector erase commands. To insure the
command has been accepted, the system software should check the status of DQ3 prior to and follo wing
each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may
not have been accepted.
See Table 9, Hardware Sequence Flags.
DQ2
Toggle Bit II
This Toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm.
If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector
will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from
the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also Table 9 and Figure 14.
Furthermore, DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2
toggles if this bit is read from an erasing sector.
Reading Toggle Bits DQ6 / DQ2
Whenever the system in itially begi ns reading Togg le bit status , it must read DQ7 to DQ0 at lea st twice in a
row to deter mine wheth er a Tog gle bit i s toggl ing . Ty pic ally a sy stem would note and s tore th e value of the
Toggle bit after the first read. After the second read, the system would compare the new v alue of the Toggle
bit with the f ir st. If the Toggl e b it i s not toggling, the d evice has co mpl ete d th e program or erase operatio n.
The system can read array data on DQ7 to DQ0 on the following read cycle.
Advance Info. ( AE0.3E ) 35
MBM29PL32TM/BM 90/10
However, if, after the init ial two read cycles, the sy stem deter mines that the To ggle bit is still tog gling, the
system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should
then determine again whether the Toggle bit is toggling, since the Toggle bit may hav e stopped toggling just
as DQ 5 went high. If the Toggle bit is no longer toggling, the de vice has successfully completed the program
or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the Toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the Toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it ma y choose to perf orm other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine
the status of the operation. (Refer to Figure 25.)
Table 10 Toggle Bit Status
*1: : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.
*2: : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
DQ1
Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a
"1" The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to
reading array data. See "Write Buffer Programming Operations" section for more details.
RY/BY
Ready/Busy
The device provides a RY/BY open-drain output pin to indicate to the host system that the Embedded
Algorithms are either in progress or has been completed. If the output is low, the device is busy with either
a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. If the device is placed in an Erase Suspend mode, the RY/BY output will be high, by means of
connecting with a pull-up resister to VCC.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an
erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will
indicate a busy condition during the RESET pulse. See Figure 15 and 17 for a detailed timing diagram. The
RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
Word/Byte Confi guration
BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high,
the device operates in the word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin
is driven low, the device operates in byte (8-bit) mode. In this mode, DQ15/A-1 pin becomes the lowest address
bit, and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and
hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored.
Mode DQ7DQ6DQ2
Program DQ7Toggle 1
Erase 0 Toggle Toggle *1
Erase-Suspend-Read
(Erase-Suspended Sector) 11Toggle
*1
Erase-Suspend-Program DQ7Toggle 1 *2
36 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious
system lev el signals that ma y e xist during power transitions. During power up the device automatically reset
the internal state machine in Read mode. Also, with its control register architecture, alteration of memory
contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-
up and power-down transitions or system noise.
(1) Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC
less than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when VCC is above VLKO.
If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.
(2) Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
(3) Logical Inhibit
Wr i tin g is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE
must be a logical zero while OE is a logical one.
(4) Power-up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of
WE. The internal state machine is automatically reset to read mode on power-up.
(5) Sector Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids
both write and erase commands that are addressed to protected sectors.
Any commands to write or erase addressed to protected sector are ignored .
Advance Info. ( AE0.3E ) 37
MBM29PL32TM/BM 90/10
n
nn
nABSOLUTE MAXIMUM RATINGS
*1: Voltage is defined on the basis of VSS = GND = 0V.
*2: Minimum DC voltage on input or I/O pins is –0.5 V . During voltage transitions, input or I/O pins may undershoot
VSS to –0.2 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During
voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns
*3: Minimum DC input voltage is –0.5V. During voltage transitions, these pins may undershoot VSS to –0.2 V for
periods o f up to 2 0 ns.V oltage differen ce bet ween in put and suppl y vo ltage ( VIN–VCC) dose not exceed to
+9.0 V. Maximum DC input voltage is +12.5 V which may overshoot to +14.0 V for periods of up to 20 ns .
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
n
nn
nRECOMMENDED OPERATING RANGES Note *1
Notes: *1. Operating ranges define those limits between which the functionality of the device is guaranteed.
*2. Voltage is defined on the basis of VSS = GND = 0V.
W ARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device
is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses , operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their FUJITSU representatives beforehand.
Parameter Symbol Rating Unit
Min. Max.
Storage Temperature Tstg –55 +125 °C
Ambient Temperature with Power Applied TA–40 +85 °C
Voltage with Respect to Ground All Pins Except
A9, OE, and RESET *1,*2 VIN, VOUT –0.5 VCC +0.5 V
Power Supply Voltage *1 VCC –0.5 +4.0 V
A9, OE, and RESET *1,*3 VIN –0.5 +12.5 V
WP/ACC *1,*3 VACC –0.5 +12.5 V
Parameter Symbol Value Unit
Min. Max.
Ambient Temperature 90 TA–20 +70 °C
10 –20 +70
VCC Supply Voltage *2 VCC +3.0 +3.6 V
38 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
n
nn
nMAXIMU M OVERSHOOT/UNDERSHOOT
Figure 1 Maximum Undershoot Waveform
+0.6 V
–0.5 V
20 ns
–2.0 V 20 ns
20 ns
Figure 2 Maximum Over shoot Waveform 1
+2.0 V
VCC +0.5 V
20 ns
VCC +2.0 V 20 ns
20 ns
Figure 3 Maximum Overshoot Waveform 2
VCC +0.5 V
+12.5 V
20 ns
+14.0 V 20 ns
20 ns
Note: This waveform is applied for A9, OE, RESET, and A CC.
Advance Info. ( AE0.3E ) 39
MBM29PL32TM/BM 90/10
n
nn
nELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Description Symbol Conditions Min. Typ. Max. Unit
Input Leakage Current ILI VIN = VSS to VCC,
VCC = VCC Max. WP/ACC pin –2.0 — +2.0 µA
Others –1.0 — +1.0
Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max. –1.0 — +1.0 µA
A9, OE, RESET Inputs
Leakage Current ILIT VCC = VCC Max.,
A9, OE, RESET = 12.5 V — — 35 µA
VCC Active Current
(Read ) *1,*2 ICC1
CE = VIL, OE = VIH,
f = 5 MHz Word — 18 20
mA
Byte — 16 20
CE = VIL, OE = VIH,
f = 10 MHz Word — 35 50
Byte — 35 50
VCC Active Current
(Intra-Page Read ) *2 ICC2 CE = VIL, OE = VIH, tPRC = 25ns, 4-Word — 30 50 m A
VCC Active Current
(Program / Erase) *2,*3 ICC3 CE = VIL, OE = VIH —5060mA
VCC Standby Current *2 ICC4 CE = VCC ±0.3 V, RESET = VCC ±0.3 V,
OE = VIH, WP/ACC = VCC ±0.3 V —15µA
VCC Reset Current *2 ICC5 RESET = VCC ±0.3 V,
WP/ACC = VCC ±0.3 V —15µA
VCC Automatic Sleep Current
*3,*4 ICC6 CE = VSS ±0.3 V, RESET = VCC ±0.3 V,
VIN = VCC ±0.3V or Vss ±0.3V,
WP/ACC = VCC ±0.3 V —15µA
VCC Active Current
(Erase-Suspend-Program) *2 ICC7 CE = VIL, OE = VIH —5060mA
ACC Accelerated Program
Current IACC CE = VIL, OE = VIH,
Vcc = Vc c Max.,
WP/ACC =VACC Max.
WP/ACC pin — — 20 mA
Vcc Pin — — 60
Input Low Level VIL — –0.5 — 0.6 V
Input High Level VIH —0.7×VCC —VCC +
0.3 V
Voltage for WP/ACC Sector
Protection/Unprotection and
Program Acceleration VACC VCC = 2.7 V to 3.6 V 11.5 12.0 12.5 V
Voltage for Autoselect, and
Temporary Sector Unprotected VID VCC = 2.7 V to 3.6 V 11.5 12.0 12.5 V
Output Low Voltage Le vel VOL IOL = 4.0 mA, VCC = VCC Min. — — 0.45 V
Output High Voltage Level VOH IOH = –2.0 mA, VCC = VCC Min. 0.85×VCC ——V
Low VCC Lock-Out Voltage VLKO —2.3—2.5V
40 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Notes: *1.The lCC current listed includes both the DC operating current and the frequency dependent compo-
nent.
*2.Maximum ICC values are tested with VCC = VCC Max.
*3.lCC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
*4.Automatic sleep mode enables the low power mode when address remain stable for tACC + 30 ns.
Advance Info. ( AE0.3E ) 41
MBM29PL32TM/BM 90/10
2. AC Characteristics
• Read Only Operations Charac teristics
Parameter Symbols Description Condition Value*1 Unit
90 10JEDEC Standard
tAVAV tRC Read Cycle Time — Min. 90 100 ns
tAVQV tACC Address to Output Delay CE = VIL,
OE = VIL Max. 90 100 ns
tELQV tCE Chip Enable to Output Delay OE = VIL Max. 90 100 ns
—t
PRC Page Read Cycle Time — Max. 25 30 ns
—t
PACC Page Address to Output Delay CE = VIL,
OE = VIL Max. 25 30 ns
tGLQV tOE Output Enable to Output Delay — Max. 25 30 ns
tEHQZ tDF Chip Enable to Output High-Z — Max. 25 30 ns
—t
OEH Output Enable
Hold Time Read — Min. 0 ns
Toggle and Data Polling — Min. 10 ns
tGHQZ tDF Output Enable to Output High-Z — Max. 25 30 ns
tAXQX tOH Output Hold Time From Addresses,
CE or OE, Whicheve r Occurs First —Min. 0 ns
—t
READY RESET Pin Low to Read Mode — Max. 20 µs
Note: *1. Test Conditions;
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or VCC
Timing measurement reference level
Input : VCC / 2
Output : VCC / 2
Figure 4 Test Conditions
CL
3.3 V
Diodes = IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
IN3064
or Equivalent
6.2 kΩ
42 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
• Write (Erase/Program) Operations
(Continued)
Parameter Symbols Parameter Value Unit
90 10JEDEC Standard
tAVAV tWC Write Cycle Time Min. 90 100 ns
tAVWL tAS Address Setup Time Min. 0 ns
—t
ASO Address Setup Time to OE Low During
Toggle Bit Polling Min. 15 ns
tWLAX tAH Address Hold Time Min. 45 ns
—t
AHT Address Hold Time from CE or OE High
During Toggle Bit Polling Min. 0 ns
tDVWH tDS Data Setup Time Min. 35 ns
tWHDX tDH Data Hold Time Min. 0 ns
—t
OES Output Enable Setup Time Min. 0 ns
—t
CEPH CE High During Toggle Bit Polling Min. 20 ns
—t
OEPH OE Hig h During Toggle Bi t Polling Min. 20 ns
tGHWL tGHWL Read Recover Time Before Write
(OE High to WE Low) Min. 0 ns
tGHEL tGHEL Read Recover Time Before Write
(OE High to CE Low) Min. 0 ns
tELWL tCS CE Setup Time Min. 0 ns
tWLEL tWS WE Setup Time Min. 0 ns
tWHEH tCH CE Hold Time Min. 0 ns
tEHWH tWH WE Hold Time Min. 0 ns
tELEH tCP CE Pulse Width Min. 35 ns
tWLWH tWP Write Pulse Width Min. 35 ns
tEHEL tCPH CE Pulse Width High Min. 25 ns
tWHWL tWPH Write Pulse Width High Min. 30 ns
tWHWH1 tWHWH1
Effective Page
Programming Time
(Write Buffer Progra mming) Per Word Typ. 23.5 µs
Programming Time Word Typ. 100
tWHWH2 tWHWH2 Sector Erase Operation *1 Typ. 1.0 sec
—t
VCS VCC Setup Time Min. 50 µs
—t
PB Recovery Time From RY/BY Min. 0 ns
Advance Info. ( AE0.3E ) 43
MBM29PL32TM/BM 90/10
(Continued)
Notes: *1.This does not include the preprogramming time.
*2.This timing is for Sector Group Protection operation.
*3.This timing is for Accelerated Program operation.
n
nn
nERASE AND PROGRAMMING PERFORMANCE
Parameter Symbols Parameter Value Unit
90 10JEDEC Standard
—t
BUSY Erase/Pr ogram Valid to RY/BY Delay Max. 90 ns
—t
VIDR Rise Time to VID *2 Min. 500 ns
—t
VACCR Rise Time to VACC *3 Min. 500 ns
—t
VLHT Voltage Transition Time *2 Min. 4 µs
—t
WPP Write Pulse Width *2 Min. 100 µs
—t
OESP OE Setup Time to WE Active *2 Min. 4 µs
—t
CSP CE Setup Time to WE Active *2 Min. 4 µs
—t
RP RESET Pulse Width Min. 500 ns
—t
RH RESET High Time Bef o re Read Min. 100 ns
—t
EOE Delay Time from Embedded Output Enable Max. 90 100 ns
—t
TOW Erase Time-out Time Min. 50 µs
—t
SPD Erase Suspend Transition Time Max. 20 µs
Parameter Limits Unit Comments
Min. Typ. Max.
Sector Erase Time — 1 15 sec Excludes programming time prior to
erasure
Programming Time — 100 3000 µs
Excludes system-level overhead
Effective P age Programming
Time
(Wri te Buf fer Programming) — 23.5 — µs
Chip Programming Time — — 600 sec
Absolute Maximum
Programming Time
(16 words)
——6
ms Non programming within the same
page
— — T.B.D Programming within the same page
Erase/Program Cycle 100,000 — — cycles —
44 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
n
nn
nTSOP (I) PIN CAPACITANCE
Note:Test conditions TA = 25°C, f = 1.0 MHz
n
nn
nFBGA PIN CAPACITANCE
Note:Test conditions TA = 25°C, f = 1.0 MHz
Parameter
Symbol Parameter Description Test Setup Typ. Max. Unit
CIN Input Capacitance VIN = 0 T.B.D T.B.D pF
COUT Output Capa ci tan ce VOUT = 0 T.B.D T.B.D pF
CIN2 Control Pin Capacitance VIN = 0 T.B.D T.B.D pF
CIN3 WP/ACC Pin Capacitance VIN = 0 T.B.D T.B.D pF
Parameter
Symbol Parameter Description Test Setup Typ. Max. Unit
CIN Input Capacitance VIN = 0 T.B.D T.B.D pF
COUT Output Capa ci tan ce VOUT = 0 T.B.D T.B.D pF
CIN2 Control Pin Capacitance VIN = 0 T.B.D T.B.D pF
CIN3 WP/ACC Pin Capacitance VIN = 0 T.B.D T.B.D pF
Advance Info. ( AE0.3E ) 45
MBM29PL32TM/BM 90/10
n
nn
nSWITCHING WAVEFORMS
• Key to Switching Waveforms
Figure 5 Read Operation Timing Diagram
WAVEFORM INPUTS OUTPUTS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
“H” or “L”
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing
State
Unknown
Center Line is
High-
Impedance
“Off” State
WE
OE
CE
t
ACC
t
DF
t
CE
t
OH
t
OE
Data
t
RC
Addresses Addresses Stable
High-Z Output Valid High-Z
t
OEH
46 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
RESET
t ACC
t OH
Data
t RC
Addresses Addresses Stable
High-Z Output Valid
t RH
CE
t RP t RH t CE
Figure 7 Hardware Reset/Read Operation Timing Diagram
Data
A1 to A0
(A-1)
A20 to A2
CE
OE
WE
Aa Ab Ac
tRC
tACC
tCE
tOE
tOH tOH tOH
tDF
tPACC tPACC
tOEH
tPRC
Da Db Dc
Address Valid
High-Z
Figure 6 Page Read Operation Timing Diagram
Advance Info. ( AE0.3E ) 47
MBM29PL32TM/BM 90/10
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at word address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles out of four bus cycle sequence.
tCH
tWP tWHWH1
tWC tAH
CE
OE
tRC
Addresses
Data
tAS
tOE
tWPH
tGHWL
tDH
DQ7
PD
A0h DOUT
WE
555h PA PA
tOH
Data Polling3rd Bus Cycle
tCS tCE
tDS
DOUT
tDF
Figure 8 Alternate WE Controlled Program Operation Timing Diagram
48 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
t CP
t DS
t WHWH1
t WC t AH
WE
OE
Addresses
Data
t AS
t CPH
t DH
DQ 7
A0h D OUT
CE
555h PA PA
Data Polling3rd Bus Cycle
t WS t WH
t GHEL
PD
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at word address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles out of four bus cycle sequence.
Figure 9 Alternate CE Controlled Program Operation Timing Diagram
Advance Info. ( AE0.3E ) 49
MBM29PL32TM/BM 90/10
Address
Data
VCC
CE
OE
WE
555h 2AAh 555h 555h 2AAh SA*
tWC tAS tAH
tCS
tGHWL
tCH
tWP
tDS
tVCS
tDH
tWPH
AAh 55h 80h AAh 55h 30h
10h for Chip Erase
RY/BY
tBUSY
SA*
30h
tTOW
* SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for Chip
Erase.
Figure 10 Chip/Sector Erase Operation Timing Diagram
50 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Figure 11 Erase Suspend Operation Timing Diagram
Address
Data
CE
WE
XXXh
tWC
tCS tCH
tWP
tDS
B0h
RY/BY
tSPD
Advance Info. ( AE0.3E ) 51
MBM29PL32TM/BM 90/10
tOEH
tCH tOE
tCE
tDF
tEOE
tBUSY
tWHWH1 or 2
CE
DQ7
RY/BY
DQ6 to DQ0
DQ7DQ7 =
Valid Data
DQ6 to DQ0 =
Output Flag DQ6 to DQ0
Valid Data
OE
WE
Address
High-Z
High-Z
Data
Data
*
VA
*DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 12 Data Polling during Embedded Algorithm Operation Timing Diagram
52 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
* :DQ6 stops toggling (The de vice has completed the Embedded operation).
tDH tOE tCE
CE
WE
OE
DQ 6/DQ2
Address
RY/BY
Data Toggle
Data Toggle
Data Toggle
Data Stop
Toggling Output
Valid
*
tBUSY
tOEHtOEH
tOEPH
tAHT tAHTtASO tAS
tCEPH
Figure 13 Toggle Bit l Timing Diagramduring Embedded Algorithm Operations
* :DQ2 is read from the erase-suspended sector.
DQ2*
DQ6
Figure 14 DQ2 vs. DQ6
WE Erase
Erase
Suspend
Enter
Embedded
Erasing
Erase Suspend
Read
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase Erase
Complete
Toggle
DQ
2
and DQ
6
with OE or CE
Advance Info. ( AE0.3E ) 53
MBM29PL32TM/BM 90/10
Rising edge of the last WE signal
CE
RY/BY
WE
tBUSY
Entire programming
or erase operations
Figure 15 RY/BY Timing Diagram during Program/Erase Operation Timing Diagram
54 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
Figure 16 RESET Timing Diagram ( Not during Embedded Algorithms )
RESET
tREADY
CE, OE
tRH
tRP
Figure 17 RESET Timing Diagram ( During Embedded Algorithms )
tRP
RESET
tREADY
RY/BY
WE
tRB
Advance Info. ( AE0.3E ) 55
MBM29PL32TM/BM 90/10
t
VLHT
SGAX
A
20
, A
19
, A
18
, A
17
, A
16
A
15
, A
14
, A
13
, A
12
SGAY
A
6
, A
3
, A
2
, A
0
A
9
V
IH
t
VLHT
OE
V
IH
t
VLHT
t
VLHT
t
OESP
t
WPP
t
CSP
WE
CE
t
OE
01h
Data
V
CC
A
1
t
VCS
V
ID
V
ID
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
Figure 18 Sector Group Protection Timing Diagram
56 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
RESET
CE
WE
RY/BY t
VLHT
Program or Erase Command Sequence t
VLHT
t
VIDR
V
ID
Unprotection period
t
VCS
t
VLHT
V
CC
V
SS
, V
IL
or V
IH
Figure 19 Temporary Sector Group Unprotection Timing Diagram
Advance Info. ( AE0.3E ) 57
MBM29PL32TM/BM 90/10
SGAX: Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (min)
SGAY
RESET
OE
WE
CE
Data
A
1
V
CC
A
6
, A
3
, A
2
, A
0
Add SGAXSGAX
60h
01h
40h
60h
60h
TIME-OUT
t
VCS
t
VLHT
t
VIDR
t
OE
Figure 20 Extended Sector Group Protection Timing Diagram
58 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
V
CC
CE
WE
t
VLHT
Program Command Sequence t
VLHT
t
VCS
t
VACCR
V
ACC
t
VLHT
Acceleration period
ACC
Figure 21 Accelerated Program Timing Diagram
Advance Info. ( AE0.3E ) 59
MBM29PL32TM/BM 90/10
n
nn
nFLOW CHART
EMBEDDED ALGORITHMS
555h/AAh
555h/A0h
2AAh/55h
Program Address/Program Data
Programming Completed
Last Address
?
Increment Address
Verify Data
?
Data Polling
Program Command Sequence (Address/Command):
Write Program
Command Sequence
(See Below)
Start
No
No
Yes
Yes
Embedded
Program
Algorithm
in program
Figure 22 Embedded ProgramTM Algorithm
Notes: The sequence is applied for Word ( ×16 ) mode.
The addresses differ from Byte ( × 8 ) mode.
60 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
555h/AAh
555h/80h
2AAh/55h
555h/AAh
555h/10h
2AAh/55h
555h/AAh
555h/80h
2AAh/55h
555h/AAh
Sector Address
/30h
Sector Address
/30h
Sector Address
/30h
2AAh/55h
Erasure Completed
Data = FFh
?
Data Polling
Write Erase
Command Sequence
(See Below)
Start
No
Yes
Embedded
Erase
Algorithm
in progress
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
Additional sector
erase commands
are optional.
EMBEDDED ALGORITHMS
Figure 23 Embedded EraseTM Algorithm
Notes: The sequence is applied for Word ( ×16 ) mode.
The addresses differ from Byte ( × 8 ) mode.
Advance Info. ( AE0.3E ) 61
MBM29PL32TM/BM 90/10
DQ 7 = Data?
*
No
No
DQ 7 = Data?
DQ 5 = 1?
Yes
Yes
No
Read Byte
(DQ 7 to DQ 0)
Addr. = VA
Read Byte
(DQ 7 to DQ 0)
Addr. = VA
Yes
Start
Fail Pass
* :DQ7 is re checked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
VA = Valid address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple sector
erases operation
= Any of the sector addresses within
the sector not being protected
during chip erase operation
Figure 24 Data Polling Algorithm
62 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
*1 : Read Toggle bit twice to determine whether it is toggling.
*2 : Recheck Toggle bit because it may stop toggling as DQ5 changes to “1”.
DQ6 = Toggle
DQ5 = 1?
Read DQ7 to DQ0
Addr. = "H" or "L"
Read DQ7 to DQ0
Addr. = VA
Read DQ7 to DQ0
Twice
Addr. = "H" or "L"
Start
No
No
No
Yes
Yes
Yes
*1
*1, 2
Program/Erase
Operation Not
Complete.Write
Reset Command
Program/Erase
Operation
Complete
DQ6 = Toggle
?
?
Figure 25 Toggle Bit Algorithm
Advance Info. ( AE0.3E ) 63
MBM29PL32TM/BM 90/10
Start
No No
No
Yes
Yes Yes
Data = 01h?
Device Failed
PLSCNT = 25?
PLSCNT = 1
Remove VID from A9
Write Reset Command
Remove VID from A9
Write Reset Command
Sector Group Protection
Completed
Protect Another Sector
Group?
Increment PLSCNT
Read from Sector Group
Addr. = SGA, A1 = VIH
A6 = A3 = A2 = A0 = VIL
Setup Sector Group Addr.
(A20, A19, A18, A17, A16,
A15, A14, A13, A12)
OE = VID, A9 = VID
CE = VIL, RESET = VIH
A6 = A3 = A2 = A0 = VIL, A1 = VIH
Activate WE Pulse
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
()
Figure 26 Sector Group Protection Algorithm
* :A-1 is VIL in Byte ( × 8 ) mode.
64 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
RESET = V
ID
(Note 1)
Perform Erase or
Program Operations
RESET = V
IH
Start
Temporary Sector Group
Unprotection Completed
(Note 2)
Notes: 1. All protected sector groups are unprotected.
2. All previously protected sector groups are protected.
Figure 27 Temporary Sector Group Unprotection Algorithm
Advance Info. ( AE0.3E ) 65
MBM29PL32TM/BM 90/10
To Protect Sect or Group
Yes
No
No
PLSCNT = 1
Protection Othe r Sector
Start
Sector Group Protection
Extended Sector Group
Completed
Remove VID from RESET
Write Reset Command
RESET = VID
Wait to 4 µs
Protection Entry?
To Setup Sector Group
Protection Write XXXh/60h
Write 60h to Sector Address
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Time Out 250 µs
To Verify Sector Group Protection
Write 40h to Sector Address
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Data = 01h?
Group ?
Device is Operating in
Temporary Sector Group
Read from Sector Group
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Increment PLSCNT
No
Yes
Yes
Unprotection Mode
Address
Setup Next Sector Group
Address
No
Yes
PLSCNT = 25?
Device Failed
Remove VID from RESET
Write Reset Command
Figure 28 Extended Sector Group Protection Algorithm
66 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
XXXh/A0h
555h/20h
Verify Data? No
Program Address/Program Data
Data Polling
Last Address
?
Programming Completed
XXXh/90h
XXXh/F0h
Increment Address No
Yes
Yes
Set Fast Mode
In Fast Program
Reset Fast Mode
Figure 29 Embedded ProgramTM Algorithm for Fast Mode
Notes: The sequence is applied for Word ( ×16 ) mode.
The addresses differ from Byte ( × 8 ) mode.
Advance Info. ( AE0.3E ) 67
MBM29PL32TM/BM 90/10
n
nn
n ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29PL32TM/BM 90 TN
DEVICE NUMBER/DESCRIPTION
32 Mega-bit (4M × 8/2M × 16) MirrorFlash with Page Mode,
Boot Sector
3.0 V-only Read, Program, and Erase
PACKAGE TYPE
TN = 48-Pin Thin Small Outline Package
(TSOP(I)) Standard Pinout
PBT = 48-Ball Fine pitch Ball Grid Array
Package (FBGA)
SPEED OPTION
90 = 90ns access time
10 = 100ns access time
68 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
n
nn
nPACKAGE DIMENSIONS
–
.003
+.001
–
0.08
+0.03
.007
0.17
"A" (Stand off height)
0.10(.004)
(Mounting
height)
(.472
±
.008)
12.00
±
0.20*
*
LEAD No.
48
2524
1
(.004
±
.002)
0.10(.004)
M
1.10
+0.10
–
0.05
+.004
–
.002
.043
0.10
±
0.05
(.009
±
.002)
0.22
±
0.05
TYP
0.50(.020)
(.453)
11.50REF
(.787
±
.008)
20.00
±
0.20
(.724
±
.008)
18.40
±
0.20
INDEX
2001 FUJITSU LIMITED F48029S-c-4-5
C
0~8
˚
0.25(.010)
0.60
±
0.15
(.024
±
.006)
Details of "A" part
48-pin plastic TSOP(I)
(FPT-48P-M19)
C
2002 FUJITSU LIMITED B48020S-c-1-1
8.00
±
0.10(.315
±
.004)
0.38
±
0.10(.015
±
.004)
(Stand off)
(Mounting height)
6.00
±
0.10
(.236
±
.004)
0.10(.004)
0.80(.031)TYP
(5.60(.220))
(4.00(.157))
48-ø0.45
±
0.05
(48-ø.018
±
.002)
M
ø0.08(.003)
HGFEDCBA
6
5
4
3
2
1
.043
–.005
+.003
–0.13
+0.12
1.08
(INDEX AREA)
48-ball plastic FBGA
(BGA-48P-M20)
Advance Info. ( AE0.3E ) 69
MBM29PL32TM/BM 90/10
MEMO
70 ( AE0.3E ) Advance Info.
MBM29PL32TM/BM 90/10
MEMO
Advance Info. ( AE0.3E ) 71
MBM29PL32TM/BM 90/10
MEMO
MBM29PL32LM 90/10
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Marketing Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
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Tel: +81-3-5322-3353
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
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3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
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Fax: +1-408-922-9179
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Am Siebenstein 6-10,
D-63303 Dreie ich-Bu ch schlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fme.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-6281-0770
Fax: +65-6281-0220
http://www.fmal.fujitsu.com/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam- Gu,S eo ul 135 -2 80
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
F0212
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended t o be inco rporated in devices fo r actual us e. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manu factured a s cont em plated (1 ) for use acc omp anyi ng fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraf t fligh t control, air traffic
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launch control in weapon system), or (2) for use requiring
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satellite).
Please note that Fujitsu will not be liable against you and/or any
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Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
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equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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