Features
Max transient supply voltage VCC 40 V
Operating voltage range VCC 4 to 28 V
Typ. on-state resistance (per Ch) RON 40 mΩ
Current limitation (typ) ILIMH 34 A
Standby current (max) ISTBY 0.5 µA
• AEC-Q100 qualified
• General
– Single channel smart high-side driver with MultiSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS outputs
• MultiSense diagnostic functions
– Multiplexed analog feedback of: load current with high precision
proportional current mirror, VCC supply voltage and TCHIP device
temperature
– Overload and short to ground (power limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
– Sense enable/disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Configurable latch-off on overtemperature or power limitation with
dedicated fault reset pin
– Loss of ground and loss of VCC
– Reverse battery with external components
– Electrostatic discharge protection
Applications
• All types of Automotive resistive, inductive and capacitive loads
• Specially intended for Automotive Turn Indicators (up to P27W or SAE1156 and
R5W paralleled or LED Rear Combinations)
• Protected supply for ADAS systems: radars and sensors
Description
The devices are single channel high-side drivers manufactured using ST proprietary
VIPower® M0-7 technology and housed in PowerSSO-16 and SO-8 packages. The
Product status link
VN7040AJ
VN7040AS
High-side driver with MultiSense analog feedback for automotive applications
VN7040AJ, VN7040AS
Datasheet
DS10829 - Rev 4 - July 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
devices are designed to drive 12 V automotive grounded loads through a 3 V and 5 V
CMOS-compatible interface, and to provide protection and diagnostics.
The devices integrate advanced protective functions such as load current limitation,
overload active management by power limitation and overtemperature shutdown with
configurable latch-off.
A FaultRST pin unlatches the output in case of fault or disables the latch-off
functionality.
A dedicated multifunction multiplexed analog output pin delivers sophisticated
diagnostic functions including high precision proportional load current sense, supply
voltage feedback and chip temperature sense, in addition to the detection of overload
and short circuit to ground, short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to be disabled during the module low-
power mode as well as external sense resistor sharing among similar devices.
VN7040AJ, VN7040AS
DS10829 - Rev 4 page 2/53
1Block diagram and pin description
Figure 1. Block diagram
Control & Diagnostic
VCC
VON
Limitation
Current
Limitation
VCC – OUT
Clamp
Internal supply
OUTPUT
MUX
Current
Sense
GND
Undervoltage
shut-down
VCC – GND
Clamp
Fault
T
Short to VCC
Open-Load in OFF
Overtemperature
Power Limitation
T
VSENSEH
INPUT
SEL0
SEL1
SEn
MultiSense
FaultRST
VCC
Gate Driver
GAPGCFT00328
Table 1. Pin functions
Name Function
VCC Battery connection.
OUTPUT Power outputs.
GND Ground connection. Must be reverse battery protected by an external diode / resistor network.
INPUT Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch
state.
MultiSense Multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current,
supply voltage or chip temperature.
SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin.
SEL0,1 Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer.
FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets
the outputs in auto-restart mode.
VN7040AJ, VN7040AS
Block diagram and pin description
DS10829 - Rev 4 page 3/53
Figure 2. Configuration diagram (top view)
1
2
3
4
5
6
MultiSense
FaultRST OUTPUT
7
8
SEn
N.C.
16
15
14
13
12
11
N.C.
N.C.
OUTPUT
OUTPUT
10
9
OUTPUT
N.C.
N.C.
SEL1
GND
INPUT
TAB = VCC
PowerSSO-16
GAPG2601151129CFT
SEL0
1
2
3
4 5
6
MultiSense
OUTPUT
7
8
SEn
OUTPUT
VCC
VCC
GND
INPUT
SO-8
Table 2. Suggested connections for unused and not connected pins
Connection / pin MultiSense N.C. Output Input SEn, SELx, FaultRST
Floating Not allowed X (1) X X X
To ground Through 1 kΩ resistor X Not allowed Through 15 kΩ resistor Through 15 kΩ resistor
1. X: do not care.
VN7040AJ, VN7040AS
Block diagram and pin description
DS10829 - Rev 4 page 4/53
2Electrical specification
Figure 3. Current and voltage conventions
VIN
OUTPUT0,1
CS
FaultRST
SEn
SEL0
INPUT0,1
IIN
ISEL
ISEn
IFR
IGND
VSENSE
VOUT
VCC
VFn
IS
IOUT
ISENSE
VCC
VSEL
VSEn
VFR
GADG2203170950PS
Note: VF = VOUT - VCC during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the rating listed in Table 3. Absolute maximum ratings may cause permanent damage
to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table
below for extended periods may affect device reliability.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 38
V
-VCC Reverse DC supply voltage 0.3
VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 Ω) 40 V
VCCJS Maximum jump start voltage for single pulse short-circuit protection 28 V
-IGND DC reverse ground pin current 200 mA
IOUT OUTPUT DC output current Internally limited
A
-IOUT Reverse DC output current 11
IIN INPUT DC input current
-1 to 10 mA
ISEn SEn DC input current
ISEL SEL0,1 DC input current
IFR FaultRST DC input current
VFR FaultRST DC input voltage 7.5 V
ISENSE
MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10
mA
MultiSense pin DC output current in reverse (VCC < 0 V) -20
EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 °C) 36 mJ
VN7040AJ, VN7040AS
Electrical specification
DS10829 - Rev 4 page 5/53
Symbol Parameter Value Unit
VESD
Electrostatic discharge (JEDEC 22A-114F)
• INPUT
• MultiSense
• SEn, SEL0,1, FaultRST
• OUTPUT
• VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature -40 to 150
°C
Tstg Storage temperature -55 to 150
2.2 Thermal data
Table 4. Thermal data
Symbol Parameter
Typ. value
Unit
SO-8 PowerSSO-16
Rthj-board Thermal resistance junction-board (JEDEC JESD 51-8) (1) 29 6.2
°C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2)(2) 67 57
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2) 45 23.5
1. Device mounted on four-layers 2s2p PCB
2. Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
2.3 Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 4 13 28 V
VUSD Undervoltage shutdown 4 V
VUSDReset Undervoltage shutdown reset 5 V
VUSDhyst Undervoltage shutdown
hysteresis 0.3 V
RON On-state resistance
IOUT = 2.5 A; Tj = 25°C 40
mΩ
IOUT = 2.5 A; Tj = 150°C 80
IOUT = 2.5 A; VCC = 4 V; Tj = 25°C 60
Vclamp Clamp voltage
IS = 20 mA; 25°C < Tj < 150°C 41 46 52 V
IS = 20 mA; Tj = -40°C 38 V
VN7040AJ, VN7040AS
Thermal data
DS10829 - Rev 4 page 6/53
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISTBY
Supply current in standby at
VCC = 13 V (1)
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 25°C
0.5
µA
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 85°C (2)
0.5
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 125°C
3
tD_STBY Standby mode blanking time
VCC = 13 V;
VIN = VOUT = VFR = VSEL0,1 = 0 V;
VSEn = 5 V to 5 V
60 300 550 µs
IS(ON) Supply current VCC = 13 V; VSEn = 0 V;
VSEL0,1 = VFR = 0 V; VIN = 5 V; IOUT = 0 A 3 5 mA
IGND(ON)
Control stage current
consumption in ON-state. All
channels active.
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1 = 0 V; VIN = 5 V; IOUT = 2 A 6 mA
IL(off)
Off-state output current at
VCC = 13 V
VIN = VOUT = 0 V; VCC = 13 V; Tj = 25°C 0 0.01 0.5
µA
VIN = VOUT = 0 V; VCC = 13 V; Tj = 125°C 0 3
VFOutput - VCC diode voltage IOUT = -2.5 A; Tj = 150°C 0.7 V
1. PowerMOS leakage included.
2. Parameter specified by design; not subjected to production test.
Table 6. Switching
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) (1) Turn-on delay time at Tj = 25 °C
RL = 5.2 Ω
10 40 120
µs
td(off) (1) Turn-off delay time at Tj = 25 °C 10 35 100
(dVOUT/dt)on (1) Turn-on voltage slope at Tj = 25 °C
RL = 5.2 Ω
0.1 0.24 0.7
V/µs
(dVOUT/dt)off (1) Turn-off voltage slope at Tj = 25 °C 0.1 0.28 0.7
WON Switching energy losses at turn-on (twon) RL = 5.2 Ω — 0.32 0.4 (2) mJ
WOFF Switching energy losses at turn-off (twoff) RL = 5.2 Ω — 0.33 0.4(2) mJ
tSKEW (1) Differential Pulse skew (tPHL - tPLH) RL = 5.2 Ω -40 10 60 µs
1. See Figure 6. Switching time and Pulse skew.
2. Parameter guaranteed by design and characterization; not subjected to production test.
Table 7. Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
INPUT characteristics
VIL Input low level voltage 0.9 V
IIL Low level input current VIN = 0.9 V 1 µA
VN7040AJ, VN7040AS
Main electrical characteristics
DS10829 - Rev 4 page 7/53
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIH Input high level voltage 2.1 V
IIH High level input current VIN = 2.1 V 10 µA
VI(hyst) Input hysteresis voltage 0.2 V
VICL Input clamp voltage
IIN = 1 mA 5.3 7.2
V
IIN = -1 mA -0.7
FaultRST characteristics (VN7040AJ only)
VFRL Input low level voltage 0.9 V
IFRL Low level input current VIN = 0.9 V 1 µA
VFRH Input high level voltage 2.1 V
IFRH High level input current VIN = 2.1 V 10 µA
VFR(hyst) Input hysteresis voltage 0.2 V
VFRCL Input clamp voltage
IIN = 1 mA 5.3 7.5
V
IIN = -1 mA -0.7
SEL0,1 characteristics (7 V < VCC < 18 V) (VN7040AJ only)
VSELL Input low level voltage 0.9 V
ISELL Low level input current VIN = 0.9 V 1 µA
VSELH Input high level voltage 2.1 V
ISELH High level input current VIN = 2.1 V 10 µA
VSEL(hyst) Input hysteresis voltage 0.2 V
VSELCL Input clamp voltage
IIN = 1 mA 5.3 7.2
V
IIN = -1 mA -0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL Input low level voltage 0.9 V
ISEnL Low level input current VIN = 0.9 V 1 µA
VSEnH Input high level voltage 2.1 V
ISEnH High level input current VIN = 2.1 V 10 µA
VSEn(hyst) Input hysteresis voltage 0.2 V
VSEnCL Input clamp voltage
IIN = 1 mA 5.3 7.2
V
IIN = -1 mA -0.7
VN7040AJ, VN7040AS
Main electrical characteristics
DS10829 - Rev 4 page 8/53
Table 8. Protections
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
ILIMH DC short circuit current
VCC = 13 V 24 34
48
A
4 V < VCC < 18 V (1)
ILIML
Short circuit current
during thermal cycling
VCC = 13 V;
TR < Tj < TTSD
13
TTSD Shutdown temperature 150 175 200
°C
TRReset temperature(1) TRS + 1 TRS + 7
TRS Thermal reset of fault
diagnostic indication VFR = 0 V; VSEn = 5 V 135
THYST
Thermal hysteresis(TTSD -
TR)(1) 7
ΔTJ_SD Dynamic temperature Tj = -40°C; VCC = 13 V 60 K
tLATCH_RST Fault reset time for output
unlatch (only for VN7040AJ)(1)
VFR = 5 V to 0 V; VSEn = 5 V;
VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V 3 10 20 µs
VDEMAG Turn-off output voltage clamp
IOUT = 2 A; L = 6 mH; Tj = -40°C VCC - 38 V
IOUT = 2 A; L = 6 mH; Tj = 25°C to
150°C VCC - 41 VCC - 46 VCC - 52 V
VON Output voltage drop limitation IOUT = 0.25 A 20 mV
1. Parameter guaranteed by design and characterization; not subjected to production test.
Table 9. MultiSense
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSENSE_CL MultiSense clamp voltage
VSEn = 0 V; ISENSE = 1 mA -17 -12
V
VSEn = 0 V; ISENSE = -1 mA 7
CurrentSense characteristics
KOL IOUT/ISENSE
IOUT = 0.01 A; VSENSE = 0.5 V;
VSEn = 5 V 530
dKcal/Kcal (1) (2) Current sense ratio drift at
calibration point
IOUT = 0.01 A to 0.03 A; Ical = 30 mA;
VSENSE = 0.5 V; VSEn = 5 V -30 30 %
KLED IOUT/ISENSE
IOUT = 0.05 A; VSENSE = 0.5 V;
VSEn = 5 V 900 1800 2650
dKLED/KLED (1) (2) Current sense ratio drift IOUT = 0.05 A; VSENSE = 0.5 V;
VSEn = 5 V -25 25 %
K0IOUT/ISENSE
IOUT = 0.25 A; VSENSE = 0.5 V;
VSEn = 5 V 940 1550 2200
dK0/K0 (1) (2) Current sense ratio drift IOUT = 0.25 A; VSENSE = 0.5 V;
VSEn = 5 V -20 20 %
K1IOUT/ISENSE
IOUT = 0.5 A; VSENSE = 4 V;
VSEn = 5 V 1000 1400 1920
VN7040AJ, VN7040AS
Main electrical characteristics
DS10829 - Rev 4 page 9/53
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
dK1/K1 (1) (2) Current sense ratio drift IOUT = 0.5 A; VSENSE = 4 V;
VSEn = 5 V -15 15 %
K2IOUT/ISENSE
IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V 1140 1350 1710
dK2/K2 (1) (2) Current sense ratio drift IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V -10 10 %
K3IOUT/ISENSE
IOUT = 4.5 A; VSENSE = 4 V;
VSEn = 5 V 1200 1340 1470
dK3/K3 (1) (2) Current sense ratio drift IOUT = 4.5 A; VSENSE = 4 V;
VSEn = 5 V -5 5 %
ISENSE0 MultiSense leakage current
MultiSense disabled: VSEn = 0 V 0 0.5
µA
MultiSense disabled:
-1 V < VSENSE < 5 V(1) -0.5 0.5
MultiSense enabled: VSEn = 5 V;
Channel ON; IOUT = 0 A; Diagnostic
selected; VIN = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; IOUT = 0 A
0 2
MultiSense enabled: VSEn = 5 V;
Channel OFF; Diagnostic selected:
VIN = 0 V; VSEL0 = 0 V; VSEL1 = 0 V
0 2
VOUT_MSD (1) Output voltage for MultiSense
shutdown
VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; RSENSE = 2.7 kΩ;
IOUT = 2.5 A
5 V
VSENSE_SAT Multisense saturation voltage
VCC = 7 V; RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; IOUT = 4.5 A; Tj = 150°C
5 V
ISENSE_SAT (1) CS saturation current
VCC = 7 V; VSENSE = 4 V; VIN = 5 V;
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
4 mA
IOUT_SAT (1) Output saturation current
VCC = 7 V; VSENSE = 4 V; VIN = 5 V;
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
6 A
OFF-state diagnostic
VOL OFF-state open-load voltage
detection threshold
VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V 2 3 4 V
IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL -100 -15 µA
tDSTKON
OFF-state diagnostic delay
time from falling edge of
INPUT (see )Figure
9. TDSTKON
VIN = 5 V to 0 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A;
VOUT = 4 V
100 350 700 µs
tD_OL_V
Settling time for valid OFF-
state open load diagnostic
indication from rising edge of
SEn
VIN = 0 V; VFR = 0 V; VSEL0 = 0 V;
VSEL1 = 0 V; VOUT = 4 V; VSEn = 0 V
to 5 V
60 µs
tD_VOL
OFF-state diagnostic delay
time from rising edge of VOUT
VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; VOUT = 0 V to 4 V 5 30 µs
Chip temperature analog feedback (VN7040AJ only)
VN7040AJ, VN7040AS
Main electrical characteristics
DS10829 - Rev 4 page 10/53
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSENSE_TC
MultiSense output voltage
proportional to chip
temperature
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V;
VIN = 0 V; RSENSE = 1 kΩ; Tj = -40°C 2.325 2.41 2.495 V
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V;
VIN = 0 V; RSENSE = 1 kΩ; Tj = 25°C 1.985 2.07 2.155 V
VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V;
VIN = 0 V; RSENSE = 1 kΩ; Tj = 125°C 1.435 1.52 1.605 V
dVSENSE_TC/dT(1) Temperature coefficient Tj = -40°C to 150°C -5.5 mV/
K
Transfer function VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
VCC supply voltage analog feedback (VN7040AJ only)
VSENSE_VCC
MultiSense output voltage
proportional to VCC supply
voltage
VCC = 13 V; VSEn = 5 V; VSEL0 = 5 V;
VSEL1 = 5 V; VIN = 0 V;
RSENSE = 1 kΩ
3.16 3.23 3.3 V
Transfer function (3) VSENSE_VCC = VCC / 4
Fault diagnostic feedback (see Table 10. Truth table)
VSENSEH MultiSense output voltage in
fault condition
VCC = 13 V; VIN = 0 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A;
VOUT = 4 V; RSENSE = 1 kΩ;
5 6.6 V
ISENSEH MultiSense output current in
fault condition VCC = 13 V; VSENSE = 5 V 7 20 30 mA
MultiSense timings (current sense mode - see Figure 7. MultiSense timings (current sense mode)) (4)
tDSENSE1H Current sense settling time
from rising edge of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 5.2 Ω 60 µs
tDSENSE1L Current sense disable delay
time from falling edge of SEn
VIN = 5 V; VSEn = 5 V to 0 V;
RSENSE = 1 kΩ; RL = 5.2 Ω 5 20 µs
tDSENSE2H Current sense settling time
from rising edge of INPUT
VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 5.2 Ω 100 250 µs
ΔtDSENSE2H
Current sense settling time
from rising edge of IOUT
(dynamic response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ;
ISENSE = 90 % of ISENSEMAX;
RL = 5.2 Ω
100 µs
tDSENSE2L
Current sense turn-off delay
time from falling edge of
INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 5.2 Ω 50 250 µs
MultiSense timings (chip temperature sense mode - see Figure 8. Multisense timings (chip temperature and VCC sense mode)
(VN7040AJ only))(4)
tDSENSE3H
VSENSE_TC settling time from
rising edge of SEn
VSEn = 0 V to 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; RSENSE = 1 kΩ 60 µs
tDSENSE3L
VSENSE_TC disable delay time
from falling edge of SEn
VSEn = 5 V to 0 V; VSEL0 = 0 V;
VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs
MultiSense timings (VCC voltage sense mode - see Figure 8. Multisense timings (chip temperature and VCC sense mode)
(VN7040AJ only)) (4)
tDSENSE4H
VSENSE_VCC settling time from
rising edge of SEn
VSEn = 0 V to 5 V; VSEL0 = 5 V;
VSEL1 = 5 V; RSENSE = 1 kΩ 60 µs
tDSENSE4L
VSENSE_VCC disable delay
time from falling edge of SEn
VSEn = 5 V to 0 V; VSEL0 = 5 V;
VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs
VN7040AJ, VN7040AS
Main electrical characteristics
DS10829 - Rev 4 page 11/53
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
MultiSense timings (Multiplexer transition times) (VN7040AJ only)(4)
tD_CStoTC
MultiSense transition delay
from current sense to TC
sense
VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V to 5 V; IOUT = 1.25 A;
RSENSE = 1 kΩ
60 µs
tD_TCtoCS
MultiSense transition delay
from TC sense to current
sense
VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V to 0 V; IOUT = 1.25 A;
RSENSE = 1 kΩ
20 µs
tD_CStoVCC
MultiSense transition delay
from current sense to VCC
sense
VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V;
VSEL1 = 0 V to 5 V; IOUT = 1.25 A;
RSENSE = 1 kΩ
60 µs
tD_VCCtoCS
MultiSense transition delay
from VCC sense to current
sense
VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V;
VSEL1 = 5 V to 0 V; IOUT = 1.25 A;
RSENSE = 1 kΩ
20 µs
tD_TCtoVCC
MultiSense transition delay
from TC sense to VCC sense
VCC = 13 V; Tj = 125°C; VSEn = 5 V;
VSEL0 = 0 V to 5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20 µs
tD_VCCtoTC
MultiSense transition delay
from VCC sense to TC sense
VCC = 13 V; Tj = 125°C; VSEn = 5 V;
VSEL0 = 5 V to 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20 µs
1. Parameter specified by design; not subjected to production test.
2. All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
3. VCC sensing and TC are referred to GND potential.
4. Transition delays are measured up to +/- 10% of final conditions.
Figure 4. IOUT/ISENSE versus IOUT
0
500
1000
1500
2000
2500
3000
0 1 2 3 4 5
K-factor
IOUT [A]
Max
Min
Typ
GAPGCFT01210
VN7040AJ, VN7040AS
Main electrical characteristics
DS10829 - Rev 4 page 12/53
Figure 5. Current sense accuracy versus IOUT
GAPGCFT01211
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0 1 2 3 4 5
%
IOUT [A]
Current sense uncalibrated precision
Current sense calibrated precision
Figure 6. Switching time and Pulse skew
VOUT
t
Vcc
twon
80% Vcc
20% Vcc
twoff
INPUT
td(on)
tpLH tpHL
td(off)
t
dVOUT/dt
ON OFF
dVOUT/dt
VN7040AJ, VN7040AS
Main electrical characteristics
DS10829 - Rev 4 page 13/53
Figure 7. MultiSense timings (current sense mode)
CURRENT SENSE
IN1
SEn
IOUT1
tDSENSE2H tDSENSE1L tDSENSE2L
tDSENSE1H
SEL0
SEL1 Low
High
Low
High
Low
High
Figure 8. Multisense timings (chip temperature and VCC sense mode) (VN7040AJ only)
SENSE
SEn
VCC
tDSENSE4H tDSENSE4L tDSENSE3L
tDSENSE3H
SEL0
SEL1 Low
High
Low
High
Low
High
VSENSE = VSENSE_VCC
VSENSE = VSENSE_TC
VCC VOLTAGE SENSE MODE CHIP TEMPERATURE SENSE MODE
GAPGCFT00319
VN7040AJ, VN7040AS
Main electrical characteristics
DS10829 - Rev 4 page 14/53
Figure 9. TDSTKON
TDSTKON
VINPUT
VOUT
MultiSense
VOUT > VOL
GAPG2609141140CFT
Table 10. Truth table
Mode Conditions INXFR (1) SEn SELX (1) OUTXMultiSense Comments
Standby All logic inputs low L L L L L Hi-Z Low quiescent current
consumption
Normal
Nominal load connected;
Tj < 150 °C
L X
See (2)
LSee (2)
H L H See (2) Outputs configured for
auto-restart
H H H See (2) Outputs configured for
latch-off(1)
Overload
Overload or short to GND
causing:
Tj > TTSD or
ΔTj > ΔTj _SD
L X
See (2)
LSee (2)
H L H See (2) Output cycles with
temperature hysteresis
H H L See (2) Output latches-off(1)
Undervoltage VCC < VUSD (falling) X X X X L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
OFF-state
diagnostics
Short to VCC L X
See (2)
HSee (2)
Open-load L X H See (2) External pull-up
Negative output
voltage Inductive loads turn-off L X See (2) < 0 V See (2)
1. VN7040AJ only
2. Refer to Table 11. MultiSense multiplexer addressing
Table 11. MultiSense multiplexer addressing
SEn SEL1SEL0MUX channel
MultiSense output
Normal mode Overload OFF-state diag. (1) Negative output
SO-8
VN7040AJ, VN7040AS
Main electrical characteristics
DS10829 - Rev 4 page 15/53
SEn SEL1SEL0MUX channel
MultiSense output
Normal mode Overload OFF-state diag. (1) Negative output
L N.A. N.A. N.A. Hi-Z
H N.A. N.A. Channel diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z
PowerSSO-16
H L L Channel diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z
H L H Channel diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z
H H L TCHIP Sense VSENSE = VSENSE_TC
H H H VCC Sense VSENSE = VSENSE_VCC
1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low,
Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN = 0; OUT = L (latched); MUX
channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN = 0; OUT = latched, VOUT > VOL; MUX channel =
channel 0 diagnostic; Mutisense = VSENSEH
2.4 Waveforms
Figure 10. Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD)
Logic
high
Input
tt > tlatchRST Fault Reset
Multisense
voltage
Output
Voltage
Output
current
Sense
enable
Logic
high
Logic
high
Junction temperature << TTDS
60°
Logic
high
Hard
short
circuit
Internal
Δ Tj
fault
detection
VsenseH
IlimH
Vout
<5V Vout
<5V
GADG1703171451PS
VN7040AJ, VN7040AS
Waveforms
DS10829 - Rev 4 page 16/53
Figure 11. Latch functionality - behavior in hard short-circuit condition
Thermal shut down
cycling
in AutoRestart mode
Logic
high
Logic
high
Logic
high
Logic
high
Hard
short
circuit
VsenseH
IlimH
IlimL
TAMB
TTSD
TR
Input
Fault Reset
Multisense
voltage
Output
Voltage
Output
current
Junction
temperature
Sense
enable
Internal
fault
detection
tt > tlatchRST
Vout <5V Vout <5V
Figure 12. Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off)
60°
Logic
high
Logic
high
Logic
high
Logic
high
Hard
short
circuit
VsenseH
TAMB
TTSD
Input
Fault Reset
Multisense
voltage
Output
Voltage
Output
current
Junction
temperature
Chip
temperature
Sense
enable
Internal
fault
detection
IlimH
IlimL
Vout <5V Vout <5V
GADG2103171742PS
VN7040AJ, VN7040AS
Waveforms
DS10829 - Rev 4 page 17/53
Figure 13. Standby mode activation
Figure 14. Standby state diagram
GAPGCFT00598
Normal Operation
Stand-by Mode
t > t D_STBY
INx = Low
AND
FaultRST = Low
AND
SEn = Low
AND
SELx = Low
INx = High
OR
FaultRST = High
OR
SEn = High
OR
SELx = High
VN7040AJ, VN7040AS
Waveforms
DS10829 - Rev 4 page 18/53
2.5 Electrical characteristics curves
Figure 15. OFF-state output current
Figure 16. Standby current
Figure 17. IGND(ON) vs. Tcase
Figure 18. Logic Input high level voltage
VN7040AJ, VN7040AS
Electrical characteristics curves
DS10829 - Rev 4 page 19/53
Figure 19. Logic Input low level voltage
Figure 20. High level logic input current
Figure 21. Low level logic input current
Figure 22. Logic Input hysteresis voltage
Figure 23. FaultRST Input clamp voltage
Figure 24. Undervoltage shutdown
VN7040AJ, VN7040AS
Electrical characteristics curves
DS10829 - Rev 4 page 20/53
Figure 25. On-state resistance vs. Tcase
Figure 26. On-state resistance vs. VCC
Figure 27. Turn-on voltage slope
Figure 28. Turn-off voltage slope
Figure 29. Won vs. Tcase
Figure 30. Woff vs. Tcase
VN7040AJ, VN7040AS
Electrical characteristics curves
DS10829 - Rev 4 page 21/53
Figure 31. ILIMH vs. Tcase
Figure 32. OFF-state open-load voltage detection
threshold
Figure 33. Vsense clamp vs. Tcase
Figure 34. Vsenseh vs. Tcase
VN7040AJ, VN7040AS
Electrical characteristics curves
DS10829 - Rev 4 page 22/53
3Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature
swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to
automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the
voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-
mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it
automatically switches off and the diagnostic indication is triggered. According to the voltage level on the
FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or
remains off (FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other
components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current
flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a
safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative
voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor
energy to be dissipated without damaging the device.
VN7040AJ, VN7040AS
Protections
DS10829 - Rev 4 page 23/53
4Application information
Figure 35. Application diagram
VDD
OUT
OUT
OUT
OUT
ADC in
OUT
GND
GND
GND GND
Logic
OUTPUT
GND
FaultRST
INPUT
SEn
SEL
VCC
Multisense
Current mirror
Rprot
Rprot
Rprot
Rprot
Rprot
+5V
R
GND
Rsense
D
GND
Cext
GND GND
Dld
GAPG0810141031CFT
4.1 GND protection network against reverse battery
Figure 36. Simplified internal structure
MCU
INPUT
SEn
Multisense
FaultRST
Vcc
OUTPUT
GND
Rprot
Rprot
Rprot
Rprot
Dld
Rsense
5V
RGND DGND
GND
GAPGCFT00809
VN7040AJ, VN7040AS
Application information
DS10829 - Rev 4 page 24/53
4.1.1 Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of
the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the
microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares
the same diode/resistor network.
4.2 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the supply lines and injected
into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12. ISO 7637-2 - electrical transient
conduction along supply line.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO
7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed
through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function
does not perform as designed during the test but returns automatically to normal operation after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test Pulse
2011(E)
Test pulse severity level with
Status II functional
performance status
Minimum number
of pulses or test
time
Burst cycle / pulse
repetition time Pulse duration and pulse
generator internal
impedance
Level US (1) min max
1 III -112 V 500 pulses 0.5 s 2 ms, 10 Ω
2a III +55 V 500 pulses 0.2 s 5 s 50 µs, 2 Ω
3a IV -220 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b IV +150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 (2) IV -7 V 1 pulse 100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B (3) 40 V 5 pulse 1 min 400 ms, 2 Ω
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3. With 40 V external suppressor referred to ground (-40°C < Tj < 150 °C).
4.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be
pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from
latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller and the current
required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
VN7040AJ, VN7040AS
Immunity against transient electrical disturbances
DS10829 - Rev 4 page 25/53
Recommended values: Rprot = 15 kΩ
4.4 Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin (MultiSense) delivering the
following signals:
• Current monitor: current mirror of channel output current
• VCC monitor: voltage propotional to VCC
• TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and
SEn pins, according to the address map in MultiSense multiplexer addressing Table.
Figure 37. MultiSense and diagnostic – block diagram
1
n
R
R
V
MUX
I
I
T
0
VCC
Gate Driver
VCC – OUT
Clamp
Limitation
Current
Power Limitation
Overtemperature
Open-Load in OFF
Short to VCC K factor
Sense
Current
Control & Diagnostic
shut-down
Undervoltage
Internal Supply
Clamp
VCC – GND
Diagnostic
Fault
SENSEH
CURRENT
MONITOR
GND
INPUT
SEL
SEL
SE
SENSE
PROT
To µC ADC
SENSE
FaultRST
Fault OUT
OUT
CS
GADG2004171456PS
VN7040AJ, VN7040AS
MultiSense - analog current sense
DS10829 - Rev 4 page 26/53
4.4.1 Principle of Multisense signal generation
Figure 38. MultiSense block diagram
INPUT
Vcc
OUT
To uC ADC
RPROT RSENSE
Main MOSSense MOS
Vbat Monitor
Temperature monitor
Fault
MULTISENSE
Multisense Switch Block
Current sense
GAPGCFT01040
Current monitor
When current mode is selected in the MultiSense, this output is capable to provide:
• Current mirror proportional to the load current in normal operation, delivering current proportional to the load
according to known ratio named K
• Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using
an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using
simple equations
Current provided by MultiSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
• VSENSE is voltage measurable on RSENSE resistor
• ISENSE is current provided from MultiSense pin in current output mode
• IOUT is current flowing through output
VN7040AJ, VN7040AS
MultiSense - analog current sense
DS10829 - Rev 4 page 27/53
• K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric
factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying
ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin which is switched to a
“current limited” voltage source, VSENSEH.
In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH.
The typical behavior in case of overload or hard short circuit is shown in Waveforms section.
Figure 39. Analogue HSD – open-load detection in off-state
15k
15k
15k
15k
15k
+5V
R
GN D
4.7k
Vbat
Rsense
15k
V
DD
OUT
OUT
OUT
OUT
ADC in
GND
OUT
100nF
GND
GND GND GND GND GND
100nF/ 50V
CEXT
D
GN D
10 nF /100V
GND
Microcontroller
OUTPUT
Vbat
Rpull-up
External
Pull -Up
switch
Logic
GND
FaultRST
INPUT
SEn
SEL
V
CC
Multisense
Cu rrent mirro r
OUTPUT
GAPGCFT00635
VN7040AJ, VN7040AS
MultiSense - analog current sense
DS10829 - Rev 4 page 28/53
Figure 40. Open-load / short to VCC condition
VSENSEH
VSENSE = 0
VSENSEH
tDSTKON
VSENSE
VSENSE
VIN
Pull-up connected
Pull-up
disconnected
Open-load
Short to VCC
Table 13. MultiSense pin levels in off-state
Condition Output MultiSense SEn
Open-load
VOUT > VOL
Hi-Z L
VSENSEH H
VOUT < VOL
Hi-Z L
0 H
Short to VCC VOUT > VOL
Hi-Z L
VSENSEH H
Nominal VOUT < VOL
Hi-Z L
0 H
4.4.2 TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to device GND. Care must
be taken in case a GND network protection is used, because a voltage shift is generated between the device
GND and the microcontroller input GND reference.
Figure 41. GND voltage shift shows the link between VMEASURED and the real VSENSE signal.
VN7040AJ, VN7040AS
MultiSense - analog current sense
DS10829 - Rev 4 page 29/53
Figure 41. GND voltage shift
To uC ADC
VSENSE
VPROT
Multisense voltage mode
- VSENSEH
- VCC monitor
- TCASE monitor
GND
SEn
SEL0
OUT0
VCC
Multisense
SEL1
IN0
FaultRST
RPROT
4.7k
DGND
RSENSE
VMEASURED
RPROT
VBAT
100nF/50V
GAPGCFT01136
VCC monitor
Battery monitoring channel provides VSENSE = VCC / 4.
Case temperature monitor
Case temperature monitor is capable of providing information about the actual device temperature. Since a diode
is used for temperature sensing, the following equation describes the link between temperature and output
VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C)).
4.4.3 Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the
device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature
of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive
supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby
current consumption to increase in normal conditions, i.e. when load is connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation:
Equation
R
PU < V
PU - 4
IL(off2)min @ 4V
VN7040AJ, VN7040AS
MultiSense - analog current sense
DS10829 - Rev 4 page 30/53
5Maximum demagnetization energy (VCC = 16 V)
Figure 43. Maximum turn off current versus inductance
GAPGCFT01147
0.1
1
10
100
0.1 1 10 100 1000
I (A)
L (mH)
VN7040Ax - Maximum turn off Current versus inductance
VN7040Ax - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
Note: Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the
temperature specified above for curves A and B.
VN7040AJ, VN7040AS
Maximum demagnetization energy (VCC = 16 V)
DS10829 - Rev 4 page 31/53
6Package and PCB thermal data
6.1 PowerSSO-16 thermal data
Figure 44. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 45. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 14. PCB properties
Dimension Value
Board finish thickness 1.6 mm +/- 10%
Board dimension 77 mm x 86 mm
Board Material FR4
Copper thickness (top and bottom layers) 0.070 mm
Copper thickness (inner layers) 0.035 mm
Thermal vias separation 1.2 mm
Thermal via diameter 0.3 mm +/- 0.08 mm
Copper thickness on vias 0.025 mm
Footprint dimension (top layer) 2.2 mm x 3.9 mm
Heatsink copper area dimension (bottom layer) Footprint, 2 cm2 or 8 cm2
VN7040AJ, VN7040AS
Package and PCB thermal data
DS10829 - Rev 4 page 32/53
Figure 46. PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on)
GAPGCFT01141
30
40
50
60
70
80
90
0 2 4 6 8 10
RTHjamb
RTHjamb
RTHj_amb on 4Layer PCB: 23.5°C/W
Figure 47. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
GAPGCFT01142
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000
ZTH (°C/W)
Time (s)
Cu=foot print
Cu=2 cm2
Cu=8 cm2
4 Layer
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
VN7040AJ, VN7040AS
PowerSSO-16 thermal data
DS10829 - Rev 4 page 33/53
Figure 48. Thermal fitting model of a double-channel HSD in PowerSSO-16
Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 15. Thermal parameters
Area/island (cm2)Footprint 2 8 4L
R1 (°C/W) 1.1
R2 (°C/W) 3
R3 (°C/W) 7 7 7 5
R4 (°C/W) 16 6 6 4
R5 (°C/W) 30 20 10 3
R6 (°C/W) 26 20 18 7
C1 (W.s/°C) 0.0004
C2 (W.s/°C) 0.008
C3 (W.s/°C) 0.1
C4 (W.s/°C) 0.2 0.3 0.3 0.4
C5 (W.s/°C) 0.4 1 1 4
C6 (W.s/°C) 3 5 7 18
VN7040AJ, VN7040AS
PowerSSO-16 thermal data
DS10829 - Rev 4 page 34/53
6.2 SO-8 thermal data
Figure 49. S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 50. SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 16. PCB properties
Dimension Value
Board finish thickness 1.6 mm +/- 10%
Board dimension 77 mm x 86 mm
Board Material FR4
Copper thickness (top and bottom layers) 0.070 mm
Copper thickness (inner layers) 0.035 mm
Thermal vias separation 1.2 mm
Thermal via diameter 0.3 mm +/- 0.08 mm
Copper thickness on vias 0.025 mm
Heatsink copper area dimension (bottom layer) Footprint, 2 + 2 cm2 or 8 + 8 cm2
VN7040AJ, VN7040AS
SO-8 thermal data
DS10829 - Rev 4 page 35/53
Figure 51. SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on)
GAPGCFT01145
50
55
60
65
70
75
80
85
90
95
100
0 2 4 6 8 10
RTHjamb
RTHjamb
RTHj_amb on 4Layer PCB: 45°C/W
Figure 52. SO-8 thermal impedance junction ambient single pulse (one channel on)
GAPGCFT01146
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000
ZTH (°C/W)
Time (s)
Cu=8 cm2
Cu=2 cm2
Cu=foot print
4 Layer
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
VN7040AJ, VN7040AS
SO-8 thermal data
DS10829 - Rev 4 page 36/53
Figure 53. Thermal fitting model of a double-channel HSD in SO-8
Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 17. Thermal parameters
Area/island (cm2)Footprint 2 8 4L
R1 (°C/W) 1.5
R2 (°C/W) 3.3
R3 (°C/W) 10
R4 (°C/W) 28 17 17 17
R5 (°C/W) 24 12 9 4
R6 (°C/W) 30 23 19 9
C1 (W.s/°C) 0.0004
C2 (W.s/°C) 0.008
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.1
C5 (W.s/°C) 0.4 0.8 0.8 0.8
C6 (W.s/°C) 3 7 11 22
VN7040AJ, VN7040AS
SO-8 thermal data
DS10829 - Rev 4 page 37/53
7Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
7.1 PowerSSO-16 package information
Figure 54. PowerSSO-16 package outline
GAPG1605141159CFT
8017965_Rev_8
Bottom view
Top view
Section A-A
Section B-B
θ1
θ3
θ2
h
h
R1
R
L1
L
B
B
GAUGE PLANE
S
θ
b1
cc1
b
BASE METAL
WITH PLATING
E2
D2
AA2
A1 b
SEATING PLANE
for dual gauge only
for dual gauge only
ccc C
C
H
eee C
ggg
ggg A-B DC
A-B DC
e
index area
(0.25D x 0.75E1)
2x N/2 TIPS
2x
1.2
aaa C D
N
123
D
EE1
f f f
ddd
C
bbb C
C D
A-B
AD
B
2x
AN/2
A
Table 18. PowerSSO-16 mechanical data
Ref.
Dimensions
Millimeters
Min. Typ. Max.
Θ 0° 8°
Θ1 0°
Θ2 5° 15°
Θ3 5° 15°
VN7040AJ, VN7040AS
Package information
DS10829 - Rev 4 page 38/53
Ref.
Dimensions
Millimeters
Min. Typ. Max.
A 1.70
A1 0.00 0.10
A2 1.10 1.60
b 0.20 0.30
b1 0.20 0.25 0.28
c 0.19 0.25
c1 0.19 0.20 0.23
D 4.9 BSC
D1 2.90 3.50
e 0.50 BSC
E 6.00 BSC
E1 3.90 BSC
E2 2.20 2.80
h 0.25 0.50
L 0.40 0.60 0.85
L1 1.00 REF
N 16
R 0.07
R1 0.07
S 0.20
Tolerance of form and position
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.08
eee 0.10
fff 0.10
ggg 0.15
VN7040AJ, VN7040AS
PowerSSO-16 package information
DS10829 - Rev 4 page 39/53
7.2 SO-8 package information
Figure 55. SO-8 package outline
GAPG1605141113CFT
0016023_H
Table 19. SO-8 mechanical data
Ref.
Dimensions
Millimeters
Min. Typ. Max.
A 1.75
A1 0.10 0.25
A2 1.25
b 0.28 0.48
c 0.17 0.23
D 4.80 4.90 5.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27
h 0.25 0.50
L 0.40 1.27
L1 1.04
k 0º 8º
ccc 0.10
VN7040AJ, VN7040AS
SO-8 package information
DS10829 - Rev 4 page 40/53
7.3 PowerSSO-16 packing information
Figure 56. PowerSSO-16 reel 13"
Access Hole at
Slot Location
( 40 mm min.)
If present,
tape slot in core
for tape start:
2.5 mm min. width x
10.0 mm min. depth
C
N
W2
W1
D
A
B
TAPG2004151655CFT
Table 20. Reel dimensions
Description Value(1)
Base quantity 2500
Bulk quantity 2500
A (max) 330
B (min) 1.5
C (+0.5, -0.2) 13
D (min) 20.2
N 100
W1 (+2 /-0) 12.4
W2 (max) 18.4
1. All dimensions are in mm.
VN7040AJ, VN7040AS
PowerSSO-16 packing information
DS10829 - Rev 4 page 41/53
Figure 57. PowerSSO-16 carrier tape
0.30 ±0.05 1.55 ±0.05
1.6 ±0.1
R 0.5
Typical
K1
K0
B0
P2
2.0 ±0.1
P0
4.0 ±0.1
P1A0
F
W
1.75 ±0.1
SECTION X - X
SECTION Y - Y
REF 4.18
REF 0.6
REF 0.5
X
X
Y Y
GAPG2204151242CFT
Table 21. PowerSSO-16 carrier tape dimensions
Description Value(1)
A06.50 ± 0.1
B05.25 ± 0.1
K02.10 ± 0.1
K11.80 ± 0.1
F 5.50 ± 0.1
P18.00 ± 0.1
W 12.00 ± 0.3
1. All dimensions are in mm.
Figure 58. PowerSSO-16 schematic drawing of leader and trailer tape
Embossed carrier
Carrier tape
Round sprocket holes
Elongated sprocket holes
Top cover tape
(32 mm tape and wider)
Top cover tape
Trailer
160 mm minimum
Leader
100 mm min.
400 mm minimumComponents
User direction feed
Punched carrier
8 mm & 12 mm only
END START
GAPG2004151511CFT
VN7040AJ, VN7040AS
PowerSSO-16 packing information
DS10829 - Rev 4 page 42/53
7.4 SO-8 packing information
Figure 59. Reel for SO-8
Access Hole at
Slot Location
( 40 mm min.)
If present,
tape slot in core
for tape start:
2.5 mm min. width x
10.0 mm min. depth
C
N
W2
W1
D
A
B
TAPG2004151655CFT
Table 22. Reel dimensions
Description Value(1)
Base quantity 2500
Bulk quantity 2500
A (max) 330
B (min) 1.5
C (+0.5, -0.2) 13
D (min) 20.2
N 100
W1 (+2/ -0) 12.4
W2 (max) 18.4
1. All dimensions are in mm.
VN7040AJ, VN7040AS
SO-8 packing information
DS10829 - Rev 4 page 43/53
Figure 60. SO-8 carrier tape
GAPG2105151447CFT
Table 23. SO-8 carrier tape dimensions
Description Value(1)
A06.50 ± 0.1
B05.30 ± 0.1
K02.20 ± 0.1
K11.90 ± 0.1
F 5.50 ± 0.1
P18.00 ± 0.1
W 12.00 ± 0.3
1. All dimensions are in mm.
Figure 61. SO-8 schematic drawing of leader and trailer tape
VN7040AJ, VN7040AS
SO-8 packing information
DS10829 - Rev 4 page 44/53
7.5 PowerSSO-16 marking information
Figure 62. PowerSSO-16 marking information
Spe cial function digit
&: Engineering sample
<blank>: Commercial sample
PowerSSO-16 TOP VIEW
(not to scale)
GADG0310161234SMD
Parts marked as ‘&’ are not yet qualified and therefore not approved for use in production. ST is not responsible
for any consequences resulting from such use. In no event will ST be liable for the customer using any of these
engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
7.6 SO-8 marking information
Figure 63. SO-8 marking information
1 2 3 45678
Marking area
Special function digit
&: Engineering sample
<blank>: Commercial sample
GAPG2705151558CFT
SO-8 TOP VIEW
(not in scale)
Note: Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of
each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other
purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in
production and/or in reliability qualification trials.
Commercial Samples: fully qualified parts from ST standard production with no usage restrictions
VN7040AJ, VN7040AS
PowerSSO-16 marking information
DS10829 - Rev 4 page 45/53
8Order codes
Table 24. Device summary
Package
Order codes
Tape and reel
PowerSSO-16 VN7040AJTR
SO-8 VN7040ASTR
VN7040AJ, VN7040AS
Order codes
DS10829 - Rev 4 page 46/53
Revision history
Table 25. Document revision history
Date Revision Changes
04-Jun-2015 1 Initial release.
20-Jul-2015 2
Updated cover image.
Updated Table 4: "Thermal data"
Updated following sections:
•Section 6.1: "PowerSSO-16 thermal data"
•Section 6.2: "SO-8 thermal data"
02-Oct-2016 3
Updated the following:
• Features list on the cover page
•Figure 61: "PowerSSO-16 marking information"
02-Jul-2018 4 Minor text changes in Section 4.4.2 TCASE and VCC monitor.
VN7040AJ, VN7040AS
DS10829 - Rev 4 page 47/53
Contents
1Block diagram and pin description .................................................3
2Electrical specification.............................................................5
2.1 Absolute maximum ratings.......................................................5
2.2 Thermal data ..................................................................6
2.3 Main electrical characteristics ....................................................6
2.4 Waveforms ...................................................................16
2.5 Electrical characteristics curves .................................................18
3Protections .......................................................................23
3.1 Power limitation ...............................................................23
3.2 Thermal shutdown.............................................................23
3.3 Current limitation ..............................................................23
3.4 Negative voltage clamp ........................................................23
4Application information...........................................................24
4.1 GND protection network against reverse battery....................................24
4.1.1 Diode (DGND) in the ground line............................................24
4.2 Immunity against transient electrical disturbances ..................................25
4.3 MCU I/Os protection ...........................................................25
4.4 Multisense - analog current sense ...............................................26
4.4.1 Principle of Multisense signal generation .....................................26
4.4.2 TCASE and VCC monitor .................................................29
4.4.3 Short to VCC and OFF-state open-load detection ...............................30
5Maximum demagnetization energy (VCC = 16 V)...................................31
6Package and PCB thermal data ...................................................32
6.1 PowerSSO-16 thermal data .....................................................32
6.2 SO-8 thermal data.............................................................34
7Package information..............................................................38
7.1 PowerSSO-16 package information ..............................................38
7.2 SO-8 package information ......................................................39
7.3 PowerSSO-16 packing information ...............................................40
VN7040AJ, VN7040AS
Contents
DS10829 - Rev 4 page 48/53
7.4 SO-8 packing information.......................................................42
7.5 PowerSSO-16 marking information...............................................44
7.6 SO-8 marking information ......................................................45
8Order codes ......................................................................46
Revision history .......................................................................47
VN7040AJ, VN7040AS
Contents
DS10829 - Rev 4 page 49/53
List of tables
Table 1. Pin functions .......................................................................3
Table 2. Suggested connections for unused and not connected pins .......................................4
Table 3. Absolute maximum ratings .............................................................5
Table 4. Thermal data.......................................................................6
Table 5. Power section ......................................................................6
Table 6. Switching .........................................................................7
Table 7. Logic inputs........................................................................7
Table 8. Protections ........................................................................9
Table 9. MultiSense ........................................................................9
Table 10. Truth table ....................................................................... 15
Table 11. MultiSense multiplexer addressing ....................................................... 15
Table 12. ISO 7637-2 - electrical transient conduction along supply line .................................... 25
Table 13. MultiSense pin levels in off-state ........................................................ 29
Table 14. PCB properties .................................................................... 32
Table 15. Thermal parameters ................................................................. 34
Table 16. PCB properties .................................................................... 35
Table 17. Thermal parameters ................................................................. 37
Table 18. PowerSSO-16 mechanical data ......................................................... 38
Table 19. SO-8 mechanical data ............................................................... 40
Table 20. Reel dimensions ................................................................... 41
Table 21. PowerSSO-16 carrier tape dimensions .................................................... 42
Table 22. Reel dimensions ................................................................... 43
Table 23. SO-8 carrier tape dimensions .......................................................... 44
Table 24. Device summary ................................................................... 46
Table 25. Document revision history ............................................................. 47
VN7040AJ, VN7040AS
List of tables
DS10829 - Rev 4 page 50/53
List of figures
Figure 1. Block diagram ....................................................................3
Figure 2. Configuration diagram (top view)........................................................4
Figure 3. Current and voltage conventions........................................................5
Figure 4. IOUT/ISENSE versus IOUT ............................................................ 12
Figure 5. Current sense accuracy versus IOUT .................................................... 13
Figure 6. Switching time and Pulse skew ........................................................ 13
Figure 7. MultiSense timings (current sense mode)................................................. 14
Figure 8. Multisense timings (chip temperature and VCC sense mode) (VN7040AJ only) ....................... 14
Figure 9. TDSTKON ....................................................................... 15
Figure 10. Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD)......................... 16
Figure 11. Latch functionality - behavior in hard short-circuit condition..................................... 17
Figure 12. Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off) ................ 17
Figure 13. Standby mode activation ............................................................ 18
Figure 14. Standby state diagram.............................................................. 18
Figure 15. OFF-state output current ............................................................ 19
Figure 16. Standby current .................................................................. 19
Figure 17. IGND(ON) vs. Tcase ................................................................ 19
Figure 18. Logic Input high level voltage ......................................................... 19
Figure 19. Logic Input low level voltage.......................................................... 20
Figure 20. High level logic input current.......................................................... 20
Figure 21. Low level logic input current .......................................................... 20
Figure 22. Logic Input hysteresis voltage......................................................... 20
Figure 23. FaultRST Input clamp voltage......................................................... 20
Figure 24. Undervoltage shutdown ............................................................. 20
Figure 25. On-state resistance vs. Tcase ......................................................... 21
Figure 26. On-state resistance vs. VCC ......................................................... 21
Figure 27. Turn-on voltage slope .............................................................. 21
Figure 28. Turn-off voltage slope .............................................................. 21
Figure 29. Won vs. Tcase ................................................................... 21
Figure 30. Woff vs. Tcase ................................................................... 21
Figure 31. ILIMH vs. Tcase ................................................................... 22
Figure 32. OFF-state open-load voltage detection threshold ........................................... 22
Figure 33. Vsense clamp vs. Tcase ............................................................. 22
Figure 34. Vsenseh vs. Tcase ................................................................. 22
Figure 35. Application diagram................................................................ 24
Figure 36. Simplified internal structure .......................................................... 24
Figure 37. MultiSense and diagnostic – block diagram ............................................... 26
Figure 38. MultiSense block diagram ........................................................... 27
Figure 39. Analogue HSD – open-load detection in off-state ........................................... 28
Figure 40. Open-load / short to VCC condition ..................................................... 29
Figure 41. GND voltage shift ................................................................. 30
Figure 43. Maximum turn off current versus inductance............................................... 31
Figure 44. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ................................. 32
Figure 45. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ................................. 32
Figure 46. PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on).............. 33
Figure 47. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .................... 33
Figure 48. Thermal fitting model of a double-channel HSD in PowerSSO-16 ................................ 34
Figure 49. S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) ........................................ 35
Figure 50. SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) ....................................... 35
Figure 51. SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) .................... 36
VN7040AJ, VN7040AS
List of figures
DS10829 - Rev 4 page 51/53
Figure 52. SO-8 thermal impedance junction ambient single pulse (one channel on)........................... 36
Figure 53. Thermal fitting model of a double-channel HSD in SO-8....................................... 37
Figure 54. PowerSSO-16 package outline ........................................................ 38
Figure 55. SO-8 package outline .............................................................. 40
Figure 56. PowerSSO-16 reel 13" ............................................................. 41
Figure 57. PowerSSO-16 carrier tape ........................................................... 42
Figure 58. PowerSSO-16 schematic drawing of leader and trailer tape .................................... 42
Figure 59. Reel for SO-8 .................................................................... 43
Figure 60. SO-8 carrier tape ................................................................. 44
Figure 61. SO-8 schematic drawing of leader and trailer tape........................................... 44
Figure 62. PowerSSO-16 marking information ..................................................... 45
Figure 63. SO-8 marking information ........................................................... 45
VN7040AJ, VN7040AS
List of figures
DS10829 - Rev 4 page 52/53
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VN7040AJ, VN7040AS
DS10829 - Rev 4 page 53/53