VN7040AJ, VN7040AS Datasheet High-side driver with MultiSense analog feedback for automotive applications Features Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 40 m Current limitation (typ) ILIMH 34 A Standby current (max) ISTBY 0.5 A * * * Product status link VN7040AJ VN7040AS * AEC-Q100 qualified General - Single channel smart high-side driver with MultiSense analog feedback - Very low standby current - Compatible with 3 V and 5 V CMOS outputs MultiSense diagnostic functions - Multiplexed analog feedback of: load current with high precision proportional current mirror, VCC supply voltage and TCHIP device temperature - Overload and short to ground (power limitation) indication - Thermal shutdown indication - OFF-state open-load detection - Output short to VCC detection - Sense enable/disable Protections - Undervoltage shutdown - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin - Loss of ground and loss of VCC - - Reverse battery with external components Electrostatic discharge protection Applications * * * All types of Automotive resistive, inductive and capacitive loads Specially intended for Automotive Turn Indicators (up to P27W or SAE1156 and R5W paralleled or LED Rear Combinations) Protected supply for ADAS systems: radars and sensors Description The devices are single channel high-side drivers manufactured using ST proprietary VIPower(R) M0-7 technology and housed in PowerSSO-16 and SO-8 packages. The DS10829 - Rev 4 - July 2018 For further information contact your local STMicroelectronics sales office. www.st.com VN7040AJ, VN7040AS devices are designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, and to provide protection and diagnostics. The devices integrate advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module lowpower mode as well as external sense resistor sharing among similar devices. DS10829 - Rev 4 page 2/53 VN7040AJ, VN7040AS Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram VCC Internal supply VCC - GND Clamp Undervoltage shut-down Control & Diagnostic VCC - OUT Clamp FaultRST INPUT Gate Driver SEL1 T VCC VON Limitation SEL0 Current Limitation MultiSense MUX SEn Power Limitation Overtemperature T Short to VCC Open-Load in OFF Current Sense Fault GND VSENSEH OUTPUT GAPGCFT00328 Table 1. Pin functions Name VCC OUTPUT GND INPUT MultiSense Battery connection. Power outputs. Ground connection. Must be reverse battery protected by an external diode / resistor network. Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state. Multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin. SEL0,1 Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer. FaultRST DS10829 - Rev 4 Function Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode. page 3/53 VN7040AJ, VN7040AS Block diagram and pin description Figure 2. Configuration diagram (top view) PowerSSO-16 INPUT FaultRST SEn GND SEL0 SEL1 MultiSense N.C. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 OUTPUT OUTPUT OUTPUT OUTPUT N.C. N.C. N.C. N.C. TAB = V CC SO-8 INPUT SEn GND MultiSense 8 7 6 5 1 2 3 4 VCC OUTPUT OUTPUT VCC GAPG2601151129CFT Table 2. Suggested connections for unused and not connected pins Connection / pin MultiSense N.C. Output Input SEn, SELx, FaultRST Floating Not allowed X (1) X X X To ground Through 1 k resistor X Not allowed Through 15 k resistor Through 15 k resistor 1. X: do not care. DS10829 - Rev 4 page 4/53 VN7040AJ, VN7040AS Electrical specification 2 Electrical specification Figure 3. Current and voltage conventions IS VCC FaultRST I SEn I OUT OUTPUT 0,1 CS SEL 0 VSEn V OUT I SENSE SE n I SEL VFR VCC VFn I FR VSENSE I IN VSEL INPUT 0,1 VIN I GND GADG2203170950PS Note: VF = VOUT - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3. Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Parameter Unit VCC DC supply voltage 38 -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 ) 40 V VCCJS Maximum jump start voltage for single pulse short-circuit protection 28 V -IGND DC reverse ground pin current 200 mA IOUT OUTPUT DC output current Internally limited -IOUT Reverse DC output current 11 IIN SEn DC input current ISEL SEL0,1 DC input current IFR FaultRST DC input current VFR EMAX V A INPUT DC input current ISEn ISENSE DS10829 - Rev 4 Value -1 to 10 mA FaultRST DC input voltage 7.5 V MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 MultiSense pin DC output current in reverse (VCC < 0 V) -20 Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 C) 36 mA mJ page 5/53 VN7040AJ, VN7040AS Thermal data Symbol Parameter Value Unit 4000 V 2000 V 4000 V Electrostatic discharge (JEDEC 22A-114F) VESD * INPUT * MultiSense * SEn, SEL0,1, FaultRST * OUTPUT 4000 V VCC 4000 V 750 V * VESD Tj Tstg 2.2 Charge device model (CDM-AEC-Q100-011) Junction operating temperature -40 to 150 Storage temperature -55 to 150 C Thermal data Table 4. Thermal data Symbol Parameter Rthj-board Typ. value SO-8 PowerSSO-16 Thermal resistance junction-board (JEDEC JESD 51-8) (1) 29 6.2 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2)(2) 67 57 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2) 45 23.5 Unit C/W 1. Device mounted on four-layers 2s2p PCB 2. Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace 2.3 Main electrical characteristics 7 V < VCC < 28 V; -40C < Tj < 150C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. Table 5. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit 4 13 28 V VCC Operating supply voltage VUSD Undervoltage shutdown 4 V Undervoltage shutdown reset 5 V VUSDReset VUSDhyst Undervoltage shutdown hysteresis 0.3 IOUT = 2.5 A; Tj = 25C RON Vclamp DS10829 - Rev 4 On-state resistance Clamp voltage V 40 IOUT = 2.5 A; Tj = 150C 80 IOUT = 2.5 A; VCC = 4 V; Tj = 25C 60 IS = 20 mA; 25C < Tj < 150C 41 IS = 20 mA; Tj = -40C 38 46 52 m V V page 6/53 VN7040AJ, VN7040AS Main electrical characteristics Symbol Parameter Test conditions Supply current in standby at VCC = 13 V (1) ISTBY Min. Typ. Max. VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 25C 0.5 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 85C (2) 0.5 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 125C 3 Unit A VCC = 13 V; tD_STBY Standby mode blanking time 60 VIN = VOUT = VFR = VSEL0,1 = 0 V; VSEn = 5 V to 5 V Supply current VCC = 13 V; VSEn = 0 V; VSEL0,1 = VFR = 0 V; VIN = 5 V; IOUT = 0 A Control stage current consumption in ON-state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V; VIN = 5 V; IOUT = 2 A IL(off) Off-state output current at VCC = 13 V VIN = VOUT = 0 V; VCC = 13 V; Tj = 25C 0 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125C 0 VF Output - VCC diode voltage IOUT = -2.5 A; Tj = 150C IS(ON) IGND(ON) 300 550 s 3 5 mA 6 mA 0.01 0.5 3 A 0.7 V Unit 1. PowerMOS leakage included. 2. Parameter specified by design; not subjected to production test. Table 6. Switching VCC = 13 V; -40C < Tj < 150C, unless otherwise specified Symbol td(on) Parameter (1) Test conditions Turn-on delay time at Tj = 25 C td(off) (1) Turn-off delay time at Tj = 25 C (dVOUT/dt)on (1) Turn-on voltage slope at Tj = 25 C (1) Turn-off voltage slope at Tj = 25 C (dVOUT/dt)off Min. Typ. Max. 10 40 120 10 35 100 0.1 0.24 0.7 0.1 0.28 0.7 RL = 5.2 RL = 5.2 s V/s WON Switching energy losses at turn-on (twon) RL = 5.2 -- 0.32 0.4 (2) mJ WOFF Switching energy losses at turn-off (twoff) RL = 5.2 -- 0.33 0.4(2) mJ Differential Pulse skew (tPHL - tPLH) RL = 5.2 -40 10 60 s Max. Unit 0.9 V tSKEW (1) 1. See Figure 6. Switching time and Pulse skew. 2. Parameter guaranteed by design and characterization; not subjected to production test. Table 7. Logic inputs 7 V < VCC < 28 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. INPUT characteristics DS10829 - Rev 4 VIL Input low level voltage IIL Low level input current VIN = 0.9 V 1 A page 7/53 VN7040AJ, VN7040AS Main electrical characteristics 7 V < VCC < 28 V; -40C < Tj < 150C Symbol Parameter Test conditions VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage Min. Typ. Max. 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA A V 5.3 IIN = -1 mA Unit 7.2 -0.7 V FaultRST characteristics (VN7040AJ only) VFRL Input low level voltage IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL Input clamp voltage 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V V 5.3 IIN = -1 mA A 7.5 -0.7 V SEL0,1 characteristics (7 V < VCC < 18 V) (VN7040AJ only) VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage ISELH High level input current VSEL(hyst) Input hysteresis voltage VSELCL Input clamp voltage 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V V 5.3 IIN = -1 mA A 7.2 -0.7 V SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL DS10829 - Rev 4 Input clamp voltage 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA IIN = -1 mA V A V 5.3 7.2 -0.7 V page 8/53 VN7040AJ, VN7040AS Main electrical characteristics Table 8. Protections 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter ILIMH Test conditions DC short circuit current ILIML TTSD VCC = 13 V 4 V < VCC < 18 V Short circuit current VCC = 13 V; during thermal cycling TR < Tj < TTSD Reset TRS Thermal reset of fault diagnostic indication temperature(1) THYST Thermal hysteresis(TTSD TR)(1) TJ_SD Dynamic temperature tLATCH_RST Typ. 24 34 Max. Unit 48 (1) A 13 Shutdown temperature TR Min. 150 175 TRS + 1 TRS + 7 VFR = 0 V; VSEn = 5 V 200 C 135 7 Tj = -40C; VCC = 13 V 60 VFR = 5 V to 0 V; VSEn = 5 V; Fault reset time for output unlatch (only for VN7040AJ)(1) VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V 3 IOUT = 2 A; L = 6 mH; Tj = -40C VCC - 38 VCC - 41 VDEMAG Turn-off output voltage clamp IOUT = 2 A; L = 6 mH; Tj = 25C to 150C VON Output voltage drop limitation IOUT = 0.25 A K 10 20 s V VCC - 46 VCC - 52 20 V mV 1. Parameter guaranteed by design and characterization; not subjected to production test. Table 9. MultiSense 7 V < VCC < 18 V; -40C < Tj < 150C Symbol VSENSE_CL Parameter MultiSense clamp voltage Test conditions Min. VSEn = 0 V; ISENSE = 1 mA -17 VSEn = 0 V; ISENSE = -1 mA Typ. Max. Unit -12 7 V CurrentSense characteristics KOL dKcal/Kcal (1) (2) KLED dKLED/KLED (1) (2) K0 dK0/K0 (1) (2) K1 DS10829 - Rev 4 IOUT/ISENSE IOUT = 0.01 A; VSENSE = 0.5 V; VSEn = 5 V 530 Current sense ratio drift at calibration point IOUT = 0.01 A to 0.03 A; Ical = 30 mA; VSENSE = 0.5 V; VSEn = 5 V -30 IOUT/ISENSE IOUT = 0.05 A; VSENSE = 0.5 V; VSEn = 5 V 900 Current sense ratio drift IOUT = 0.05 A; VSENSE = 0.5 V; VSEn = 5 V -25 IOUT/ISENSE IOUT = 0.25 A; VSENSE = 0.5 V; VSEn = 5 V 940 Current sense ratio drift IOUT = 0.25 A; VSENSE = 0.5 V; VSEn = 5 V -20 IOUT/ISENSE IOUT = 0.5 A; VSENSE = 4 V; VSEn = 5 V 30 % 1800 2650 25 % 1550 2200 20 % 1000 1400 1920 page 9/53 VN7040AJ, VN7040AS Main electrical characteristics 7 V < VCC < 18 V; -40C < Tj < 150C Symbol dK1/K1 (1) (2) K2 dK2/K2 (1) (2) K3 dK3/K3 (1) (2) Parameter Test conditions Min. Current sense ratio drift IOUT = 0.5 A; VSENSE = 4 V; VSEn = 5 V -15 IOUT/ISENSE IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V Current sense ratio drift IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V IOUT/ISENSE IOUT = 4.5 A; VSENSE = 4 V; VSEn = 5 V Current sense ratio drift IOUT = 4.5 A; VSENSE = 4 V; VSEn = 5 V -5 5 MultiSense disabled: VSEn = 0 V 0 0.5 -0.5 0.5 MultiSense enabled: VSEn = 5 V; Channel ON; IOUT = 0 A; Diagnostic selected; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A 0 2 MultiSense enabled: VSEn = 5 V; Channel OFF; Diagnostic selected: VIN = 0 V; VSEL0 = 0 V; VSEL1 = 0 V 0 2 MultiSense disabled: -1 V < VSENSE < 5 V(1) ISENSE0 MultiSense leakage current Typ. Max. Unit 15 % 1140 1350 1710 -10 10 % 1200 1340 1470 % A VOUT_MSD (1) Output voltage for MultiSense shutdown VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; RSENSE = 2.7 k; IOUT = 2.5 A VSENSE_SAT Multisense saturation voltage VCC = 7 V; RSENSE = 2.7 k; VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 4.5 A; Tj = 150C 5 V CS saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150C 4 mA Output saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150C 6 A ISENSE_SAT (1) IOUT_SAT (1) 5 V OFF-state diagnostic VOL OFF-state open-load voltage detection threshold VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL -100 tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see )Figure 9. TDSTKON VIN = 5 V to 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; VOUT = 4 V 100 tD_OL_V Settling time for valid OFFstate open load diagnostic indication from rising edge of SEn VIN = 0 V; VFR = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT = 4 V; VSEn = 0 V to 5 V tD_VOL OFF-state diagnostic delay time from rising edge of VOUT VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT = 0 V to 4 V 2 3 350 5 4 V -15 A 700 s 60 s 30 s Chip temperature analog feedback (VN7040AJ only) DS10829 - Rev 4 page 10/53 VN7040AJ, VN7040AS Main electrical characteristics 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter MultiSense output voltage proportional to chip temperature VSENSE_TC dVSENSE_TC/dT(1) Temperature coefficient Transfer function Test conditions Min. VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 k; Tj = -40C 2.325 2.41 2.495 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 k; Tj = 25C 1.985 2.07 2.155 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 k; Tj = 125C 1.435 1.52 1.605 V -5.5 mV/ K Tj = -40C to 150C Typ. Max. Unit VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) VCC supply voltage analog feedback (VN7040AJ only) VSENSE_VCC MultiSense output voltage proportional to VCC supply voltage Transfer function (3) VCC = 13 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 k 3.16 3.23 3.3 V 6.6 V 30 mA 60 s VSENSE_VCC = VCC / 4 Fault diagnostic feedback (see Table 10. Truth table) VSENSEH MultiSense output voltage in fault condition VCC = 13 V; VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; VOUT = 4 V; RSENSE = 1 k; 5 ISENSEH MultiSense output current in fault condition VCC = 13 V; VSENSE = 5 V 7 20 MultiSense timings (current sense mode - see Figure 7. MultiSense timings (current sense mode)) (4) tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 k; RL = 5.2 tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 k; RL = 5.2 5 20 s tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 k; RL = 5.2 100 250 s tDSENSE2H Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 k; ISENSE = 90 % of ISENSEMAX; RL = 5.2 100 s tDSENSE2L Current sense turn-off delay time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 k; RL = 5.2 250 s 50 MultiSense timings (chip temperature sense mode - see Figure 8. Multisense timings (chip temperature and VCC sense mode) (VN7040AJ only))(4) tDSENSE3H VSENSE_TC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 k 60 s tDSENSE3L VSENSE_TC disable delay time from falling edge of SEn VSEn = 5 V to 0 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 k 20 s MultiSense timings (VCC voltage sense mode - see Figure 8. Multisense timings (chip temperature and VCC sense mode) (VN7040AJ only)) (4) DS10829 - Rev 4 tDSENSE4H VSENSE_VCC settling time from VSEn = 0 V to 5 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 k rising edge of SEn 60 s tDSENSE4L VSENSE_VCC disable delay time from falling edge of SEn VSEn = 5 V to 0 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 k 20 s page 11/53 VN7040AJ, VN7040AS Main electrical characteristics 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit MultiSense timings (Multiplexer transition times) (VN7040AJ only)(4) tD_CStoTC MultiSense transition delay from current sense to TC sense VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V to 5 V; IOUT = 1.25 A; RSENSE = 1 k 60 s tD_TCtoCS MultiSense transition delay from TC sense to current sense VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V to 0 V; IOUT = 1.25 A; RSENSE = 1 k 20 s tD_CStoVCC MultiSense transition delay from current sense to VCC sense VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 0 V to 5 V; IOUT = 1.25 A; RSENSE = 1 k 60 s tD_VCCtoCS MultiSense transition delay from VCC sense to current sense VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V to 0 V; IOUT = 1.25 A; RSENSE = 1 k 20 s tD_TCtoVCC MultiSense transition delay from TC sense to VCC sense VCC = 13 V; Tj = 125C; VSEn = 5 V; VSEL0 = 0 V to 5 V; VSEL1 = 5 V; RSENSE = 1 k 20 s tD_VCCtoTC MultiSense transition delay from VCC sense to TC sense VCC = 13 V; Tj = 125C; VSEn = 5 V; VSEL0 = 5 V to 0 V; VSEL1 = 5 V; RSENSE = 1 k 20 s 1. Parameter specified by design; not subjected to production test. 2. All values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. 3. VCC sensing and TC are referred to GND potential. 4. Transition delays are measured up to +/- 10% of final conditions. Figure 4. IOUT/ISENSE versus IOUT 3000 2500 Max Min K-factor 2000 Typ 1500 1000 500 0 0 1 2 3 4 5 IOUT [A] GAPGCFT01210 DS10829 - Rev 4 page 12/53 VN7040AJ, VN7040AS Main electrical characteristics Figure 5. Current sense accuracy versus IOUT 65 60 55 50 45 40 35 % 30 25 20 15 10 5 0 Current sense uncalibrated precision Current sense calibrated precision 0 1 2 3 4 5 IOUT [A] GAPGCFT01211 Figure 6. Switching time and Pulse skew twon VOUT twoff Vcc 80% Vcc ON OFF dVOUT/dt dVOUT/dt 20% Vcc t INPUT td(off) td(on) tpLH tpHL t DS10829 - Rev 4 page 13/53 VN7040AJ, VN7040AS Main electrical characteristics Figure 7. MultiSense timings (current sense mode) IN1 High SEn Low High SEL0 Low High SEL1 Low IOUT1 CURRENT SENSE tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L Figure 8. Multisense timings (chip temperature and VCC sense mode) (VN7040AJ only) High SEn Low High SEL0 Low High SEL1 Low VCC VSENSE = VSENSE_VCC VSENSE = VSENSE_TC SENSE tDSENSE4H tDSENSE4L VCC VOLTAGE SENSE MODE tDSENSE3H tDSENSE3L CHIP TEMPERATURE SENSE MODE GAPGCFT00319 DS10829 - Rev 4 page 14/53 VN7040AJ, VN7040AS Main electrical characteristics Figure 9. TDSTKON VINPUT VOUT VOUT > VOL MultiSense TDSTKON GAPG2609141140CFT Table 10. Truth table Mode Conditions Standby All logic inputs low Normal Overload Undervoltage OFF-state diagnostics Negative output voltage INX FR (1) SEn SELX (1) OUTX MultiSense L L L X H L H Overload or short to GND causing: Hi-Z L See (2) H See (2) Outputs configured for auto-restart H H See (2) Outputs configured for latch-off(1) L X L See (2) Tj > TTSD or H L H See (2) Output cycles with temperature hysteresis Tj > Tj _SD H H L See (2) Output latches-off(1) VCC < VUSD (falling) X X L Hi-Z Re-start when VCC > VUSD + L Hi-Z H See (2) H See (2) <0V See (2) See (2) Tj < 150 C Short to VCC L X Open-load L X Inductive loads turn-off L X L Low quiescent current consumption L Nominal load connected; L Comments See (2) X X See (2) See (2) VUSDhyst (rising) External pull-up 1. VN7040AJ only 2. Refer to Table 11. MultiSense multiplexer addressing Table 11. MultiSense multiplexer addressing SEn SEL1 SEL0 MUX channel MultiSense output Normal mode Overload OFF-state diag. (1) Negative output SO-8 DS10829 - Rev 4 page 15/53 VN7040AJ, VN7040AS Waveforms SEn SEL1 SEL0 MUX channel L N.A. N.A. N.A. H N.A. N.A. Channel diagnostic MultiSense output Normal mode Overload OFF-state diag. (1) Negative output VSENSE = VSENSEH Hi-Z Hi-Z ISENSE = 1/K * IOUT VSENSE = VSENSEH PowerSSO-16 H L L Channel diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L H Channel diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H L TCHIP Sense VSENSE = VSENSE_TC H H H VCC Sense VSENSE = VSENSE_VCC 1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN = 0; OUT = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN = 0; OUT = latched, VOUT > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH 2.4 Waveforms Figure 10. Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD) Logic high Sense enable Logic high Input Logic high t t > t latch RST I limH Fault Reset Output current Junction temperature << TTDS Tj 60 Logic high Hard short circuit VsenseH Internal fault detection Vout <5V Vout <5V Output Voltage Multisense voltage GADG1703171451PS DS10829 - Rev 4 page 16/53 VN7040AJ, VN7040AS Waveforms Figure 11. Latch functionality - behavior in hard short-circuit condition Logic high Sense enable Logic high Input Logic high t t > t latch RST I lim H Fault Reset Output current I lim L TTSD TR TAMB Junction temperature Thermal shut down cycling in AutoRestart mode Logic high Hard short circuit Internal fault detection Vout <5V Vout <5V VsenseH Output Voltage Multisense voltage Figure 12. Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off) Logic high Sense enable Logic high Input Logic high Fault Reset I lim H Output current I lim L TTSD Junction temperature Chip temperature 60 TAMB Logic high Hard short circuit VsenseH Internal fault detection Vout <5V Vout <5V Output Voltage Multisense voltage GADG2103171742PS DS10829 - Rev 4 page 17/53 VN7040AJ, VN7040AS Waveforms Figure 13. Standby mode activation Figure 14. Standby state diagram Normal Operation t > t D_STBY INx = Low AND FaultRST = Low AND SEn = Low AND SELx = Low INx = High OR FaultRST = High OR SEn = High OR SELx = High Stand-by Mode GAPGCFT00598 DS10829 - Rev 4 page 18/53 VN7040AJ, VN7040AS Electrical characteristics curves 2.5 Electrical characteristics curves Figure 15. OFF-state output current Figure 16. Standby current Iloff [nA] ISTBY [A] 600 1 0.9 500 Vcc = 13V 0.8 400 0.7 Off State Vcc = 13V Vin = Vout = 0 300 0.6 0.5 0.4 200 0.3 0.2 100 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPGCFT01191 GAPGCFT01190 Figure 17. IGND(ON) vs. Tcase Figure 18. Logic Input high level voltage IGND(ON) [mA] ViH, VFRH, VSELH, VSEnH [V] 3.5 2 1.8 3.0 1.6 2.5 1.4 Vcc = 13V Iout0 = Iout1 = 2.5A 2.0 1.2 1 1.5 0.8 0.6 1.0 0.4 0.5 0.2 0 0.0 -50 -25 0 25 50 75 100 125 150 175 GAPGCFT01192 DS10829 - Rev 4 -50 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPGCFT01193 page 19/53 VN7040AJ, VN7040AS Electrical characteristics curves Figure 19. Logic Input low level voltage VilL VFRL, VSELL, VSEnL [V] Figure 20. High level logic input current IiH, IFRH, ISELH, ISEnH [A] 2 4 1.8 3.5 1.6 3 1.4 2.5 1.2 1 2 0.8 1.5 0.6 1 0.4 0.5 0.2 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPGCFT01195 GAPGCFT01194 Figure 21. Low level logic input current Figure 22. Logic Input hysteresis voltage Vi(hyst), VFR(hyst), VSEL(hyst), VSEn(hyst) [V] IiL, IFRL, ISELL, ISEnL [A] 1 4 0.9 3.5 0.8 3 0.7 2.5 0.6 2 0.5 0.4 1.5 0.3 1 0.2 0.5 0.1 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPGCFT01196 GAPGCFT01197 Figure 23. FaultRST Input clamp voltage Figure 24. Undervoltage shutdown VUSD [V] VFRCL [V] 8 8 7 7 Iin = 1mA 6 6 5 5 4 4 3 3 2 2 1 Iin = -1mA 0 1 0 -1 -50 -25 0 25 50 75 100 125 150 175 GAPGCFT01198 DS10829 - Rev 4 -50 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPGCFT01199 page 20/53 VN7040AJ, VN7040AS Electrical characteristics curves Figure 25. On-state resistance vs. Tcase Figure 26. On-state resistance vs. VCC Ron [mOhm] Ron [mOhm] 100 100 90 90 80 80 70 70 Iout = 2.5A Vcc = 13V 60 50 40 40 30 30 20 20 10 10 0 -25 0 T = 125 C 60 50 -50 T = 150 C 25 50 75 100 125 150 175 T = 25 C T = -40 C 0 0 5 10 15 T [C] 20 25 30 GAPGCFT01200 40 GAPGCFT01201 Figure 27. Turn-on voltage slope Figure 28. Turn-off voltage slope (dVout/dt)On [V/s] (dVout/dt)Off [V/s] 1 1 0.9 0.9 0.8 0.8 Vcc = 13V Rl = 5.2 0.7 Vcc = 13V Rl = 5.2 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPGCFT01202 GAPGCFT01203 Figure 29. Won vs. Tcase Figure 30. Woff vs. Tcase Woff [mJ] Won [mJ] 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 T [C] -50 -25 0 25 50 75 100 125 150 175 T [C] GAPGCFT01204 DS10829 - Rev 4 35 Vcc [V] GAPGCFT01205 page 21/53 VN7040AJ, VN7040AS Electrical characteristics curves Figure 32. OFF-state open-load voltage detection threshold Figure 31. ILIMH vs. Tcase Ilimh [A] VOL [V] 40 4 35 3.5 3 30 Vcc = 13V 2.5 25 2 20 1.5 1 15 0.5 10 -50 -25 0 25 50 75 100 125 150 175 0 -50 T [C] -25 0 25 50 75 100 125 150 175 T [C] GAPGCFT01206 GAPGCFT01207 Figure 33. Vsense clamp vs. Tcase Figure 34. Vsenseh vs. Tcase VSENSEH [V] VSENSE_CL [V] 10 10 9 9 8 8 7 Iin = 1mA 7 6 6 5 5 4 4 3 3 2 2 1 Iin = -1mA 0 1 0 -1 -50 -25 0 25 50 75 100 125 150 175 GAPGCFT01208 DS10829 - Rev 4 -50 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPGCFT01209 page 22/53 VN7040AJ, VN7040AS Protections 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing Tj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as Tj exceeds the safety level of Tj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermomechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. DS10829 - Rev 4 page 23/53 VN7040AJ, VN7040AS Application information 4 Application information Figure 35. Application diagram +5V VDD OUT VCC Rprot OUT FaultRST INPUT Rprot OUT Logic OUT Rprot SEn Rprot SEL Dld OUTPUT Rprot ADC in Multisense Current mirror GND Cext Rsense OUT R GND D GND GND GND GND GND GND GND 4.1 GAPG0810141031CFT GND protection network against reverse battery Figure 36. Simplified internal structure 5V Vcc Rprot Rprot INPUT SEn MCU Dld Rprot FaultRST OUTPUT Rprot Multisense GND Rsense D GND R GND GND DS10829 - Rev 4 GAPGCFT00809 page 24/53 VN7040AJ, VN7040AS Immunity against transient electrical disturbances 4.1.1 Diode (DGND) in the ground line A resistor (typ. RGND = 4.7 k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12. ISO 7637-2 - electrical transient conduction along supply line. Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: "The function does not perform as designed during the test but returns automatically to normal operation after the test". Table 12. ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US (1) 1 III -112 V 500 pulses 0.5 s 2a III +55 V 500 pulses 0.2 s 5s 50 s, 2 3a IV -220 V 1h 90 ms 100 ms 0.1 s, 50 3b IV +150 V 1h 90 ms 100 ms 0.1 s, 50 IV -7 V 1 pulse 4 (2) min max 2 ms, 10 100 ms, 0.01 Load dump according to ISO 16750-2:2010 Test B (3) 40 V 5 pulse 1 min 400 ms, 2 1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. 2. Test pulse from ISO 7637-2:2004(E). 3. With 40 V external suppressor referred to ground (-40C < Tj < 150 C). 4.3 MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup 20 mA; VOHC 4.5 V 7.5 k Rprot 140 k. DS10829 - Rev 4 page 25/53 VN7040AJ, VN7040AS MultiSense - analog current sense Recommended values: Rprot = 15 k 4.4 Multisense - analog current sense Diagnostic information on device and load status are provided by an analog output pin (MultiSense) delivering the following signals: * Current monitor: current mirror of channel output current * VCC monitor: voltage propotional to VCC * TCASE: voltage propotional to chip temperature Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. Figure 37. MultiSense and diagnostic - block diagram VCC VCC - GND Clamp Internal Supply Undervoltage shut-down Control & Diagnostic FaultRST VCC - OUT Clamp INPUT Gate Driver T SEL1 SEL 0 SE n RPROT Current Limitation I SENSE CS Fault Diagnostic MUX Short to VCC Open-Load in OFF To C ADC R SENSE CURRENT MONITOR GND Power Limitation Overtemperature K factor Current Sense Fault IOUT OUT VSENSEH GADG2004171456PS DS10829 - Rev 4 page 26/53 VN7040AJ, VN7040AS MultiSense - analog current sense 4.4.1 Principle of Multisense signal generation Figure 38. MultiSense block diagram Vcc INPUT Sense MOS Main MOS OUT Current sense Vbat Monitor Temperature monitor Multisense Switch Block Fault MULTISENSE To uC ADC RPROT RSENSE GAPGCFT01040 Current monitor When current mode is selected in the MultiSense, this output is capable to provide: * Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K * Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by MultiSense output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE * ISENSE = RSENSE * IOUT/K Where: * VSENSE is voltage measurable on RSENSE resistor DS10829 - Rev 4 * ISENSE is current provided from MultiSense pin in current output mode * IOUT is current flowing through output page 27/53 VN7040AJ, VN7040AS MultiSense - analog current sense * K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin which is switched to a "current limited" voltage source, VSENSEH. In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH. The typical behavior in case of overload or hard short circuit is shown in Waveforms section. Figure 39. Analogue HSD - open-load detection in off-state +5V Vbat Vbat 100nF/ 50V 100nF Rpull-up GND Microcontroller GND VDD V CC OUT FaultRST 15k INPUT External Pull -Up switch OUT Logic 15k SEn OUT SEL 15k OUT OUTPUT OUTPUT Multisense Cu rrent mirror 15k GND ADC in 15k Rsense RGN D 4.7k DGN D 10nF /100V OUT 15k GND GND DS10829 - Rev 4 CEXT GND GND GND GND GAPGCFT00635 page 28/53 VN7040AJ, VN7040AS MultiSense - analog current sense Figure 40. Open-load / short to VCC condition VIN VSENSE Pull-up connected VSENSEH Open-load VSENSE = 0 VSENSE Pull-up disconnected tDSTKON Short to VCC VSENSEH Table 13. MultiSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL MultiSense SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H TCASE and VCC monitor In this case, MultiSense output operates in voltage mode and output level is referred to device GND. Care must be taken in case a GND network protection is used, because a voltage shift is generated between the device GND and the microcontroller input GND reference. Figure 41. GND voltage shift shows the link between VMEASURED and the real VSENSE signal. DS10829 - Rev 4 page 29/53 VN7040AJ, VN7040AS MultiSense - analog current sense Figure 41. GND voltage shift VBAT 100nF/50V Multisense voltage mode - VSENSEH - VCC monitor - TCASE monitor FaultRST VCC IN0 SEn OUT0 SEL0 SEL1 RPROT VMEASURED RSENSE VPROT VSENSE Multisense To uC ADC RPROT 4.7k GND DGND GAPGCFT01136 VCC monitor Battery monitoring channel provides VSENSE = VCC / 4. Case temperature monitor Case temperature monitor is capable of providing information about the actual device temperature. Since a diode is used for temperature sensing, the following equation describes the link between temperature and output VSENSE level: VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 C to 150 C)). 4.4.3 Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: Equation RPU < DS10829 - Rev 4 VPU - 4 IL(off2)min @ 4V page 30/53 VN7040AJ, VN7040AS Maximum demagnetization energy (VCC = 16 V) 5 Maximum demagnetization energy (VCC = 16 V) Figure 43. Maximum turn off current versus inductance VN7040Ax - Maximum turn off Current versus inductance 100 10 1 I (A) VN7040Ax - Single Pulse Repetitive pulse Tjstart=100C Repetitive pulse Tjstart=125C 0.1 0.1 Note: 1 L (mH) 10 100 1000 GAPGCFT01147 Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. DS10829 - Rev 4 page 31/53 VN7040AJ, VN7040AS Package and PCB thermal data 6 Package and PCB thermal data 6.1 PowerSSO-16 thermal data Figure 44. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 45. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 14. PCB properties DS10829 - Rev 4 Dimension Value Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 2.2 mm x 3.9 mm Heatsink copper area dimension (bottom layer) Footprint, 2 cm2 or 8 cm2 page 32/53 VN7040AJ, VN7040AS PowerSSO-16 thermal data Figure 46. PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHjamb 90 RTHjamb 80 70 60 50 40 30 0 2 4 6 8 10 RTHj_amb on 4Layer PCB: 23.5C/W GAPGCFT01141 Figure 47. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ZTH (C/W) 100 10 1 Cu=foot print Cu=2 cm2 Cu=8 cm2 4 Layer 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) GAPGCFT01142 Equation: pulse calculation formula ZTH = RTH * + ZTHtp (1 - ) where = tP/T DS10829 - Rev 4 page 33/53 VN7040AJ, VN7040AS PowerSSO-16 thermal data Figure 48. Thermal fitting model of a double-channel HSD in PowerSSO-16 Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15. Thermal parameters DS10829 - Rev 4 Area/island (cm2) Footprint R1 (C/W) 1.1 R2 (C/W) 3 R3 (C/W) 2 8 4L 7 7 7 5 R4 (C/W) 16 6 6 4 R5 (C/W) 30 20 10 3 R6 (C/W) 26 20 18 7 C1 (W.s/C) 0.0004 C2 (W.s/C) 0.008 C3 (W.s/C) 0.1 C4 (W.s/C) 0.2 0.3 0.3 0.4 C5 (W.s/C) 0.4 1 1 4 C6 (W.s/C) 3 5 7 18 page 34/53 VN7040AJ, VN7040AS SO-8 thermal data 6.2 SO-8 thermal data Figure 49. S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 50. SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 16. PCB properties DS10829 - Rev 4 Dimension Value Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Heatsink copper area dimension (bottom layer) Footprint, 2 + 2 cm2 or 8 + 8 cm2 page 35/53 VN7040AJ, VN7040AS SO-8 thermal data Figure 51. SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHjamb 100 95 RTHjamb 90 85 80 75 70 65 60 55 50 0 2 4 6 8 10 RTHj_amb on 4Layer PCB: 45C/W GAPGCFT01145 Figure 52. SO-8 thermal impedance junction ambient single pulse (one channel on) ZTH (C/W) 100 10 1 Cu=8 cm2 Cu=2 cm2 Cu=foot print 4 Layer 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) GAPGCFT01146 Equation: pulse calculation formula ZTH = RTH * + ZTHtp (1 - ) where = tP/T DS10829 - Rev 4 page 36/53 VN7040AJ, VN7040AS SO-8 thermal data Figure 53. Thermal fitting model of a double-channel HSD in SO-8 Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 17. Thermal parameters DS10829 - Rev 4 Area/island (cm2) Footprint R1 (C/W) 1.5 R2 (C/W) 3.3 R3 (C/W) 10 R4 (C/W) 2 8 4L 28 17 17 17 R5 (C/W) 24 12 9 4 R6 (C/W) 30 23 19 9 C1 (W.s/C) 0.0004 C2 (W.s/C) 0.008 C3 (W.s/C) 0.05 C4 (W.s/C) 0.1 C5 (W.s/C) 0.4 0.8 0.8 0.8 C6 (W.s/C) 3 7 11 22 page 37/53 VN7040AJ, VN7040AS Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 PowerSSO-16 package information Figure 54. PowerSSO-16 package outline Bottom view ggg D2 C A-B D ggg C A-B D Section A-A E2 h 2 h 1 R1 H B for dual gauge only eee C GAUGE PLANE S A2 A R B L 3 ccc C e L1 SEATING PLANE A1 b ddd C CD 2x f f f C A-B D A N Section B-B D A b WITH PLATING 1.2 for dual gauge only c c1 E1 E index area (0.25D x 0.75E1) b1 2x BASE METAL aaa C D Top view 2x N/2 TIPS bbb C 1 2 3 A N/2 B 8017965_Rev_8 GAPG1605141159CFT Table 18. PowerSSO-16 mechanical data Dimensions Millimeters Ref. Min. DS10829 - Rev 4 Typ. Max. 0 8 1 0 2 5 15 3 5 15 page 38/53 VN7040AJ, VN7040AS PowerSSO-16 package information Dimensions Ref. Millimeters Min. Typ. A Max. 1.70 A1 0.00 0.10 A2 1.10 1.60 b 0.20 0.30 b1 0.20 c 0.19 c1 0.19 D D1 0.25 0.28 0.25 0.20 0.23 4.9 BSC 2.90 3.50 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 2.20 2.80 h 0.25 0.50 L 0.40 0.60 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 0.85 Tolerance of form and position DS10829 - Rev 4 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 page 39/53 VN7040AJ, VN7040AS SO-8 package information 7.2 SO-8 package information Figure 55. SO-8 package outline 0016023_H GAPG1605141113CFT Table 19. SO-8 mechanical data Dimensions Millimeters Ref. Min. Typ. A 1.75 A1 0.10 A2 1.25 b 0.28 0.48 c 0.17 0.23 D 4.80 4.90 5.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 0.25 1.27 h 0.25 0.50 L 0.40 1.27 L1 k ccc DS10829 - Rev 4 Max. 1.04 0 8 0.10 page 40/53 VN7040AJ, VN7040AS PowerSSO-16 packing information 7.3 PowerSSO-16 packing information Figure 56. PowerSSO-16 reel 13" Access Hole at Slot Location ( 40 mm min.) W2 N D A C W1 B If present, tape slot in core for tape start: 2.5 mm min. width x 10.0 mm min. depth TAPG2004151655CFT Table 20. Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 12.4 W2 (max) 18.4 1. All dimensions are in mm. DS10829 - Rev 4 page 41/53 VN7040AJ, VN7040AS PowerSSO-16 packing information Figure 57. PowerSSO-16 carrier tape P0 P2 4.0 0.1 2.0 0.1 0.30 0.05 X 1.55 0.05 1.75 0.1 1.6 0.1 F W B0 R 0.5 Typical Y K1 Y X K0 P1 A0 SECTION X - X REF 4.18 REF 0.6 REF 0.5 SECTION Y - Y GAPG2204151242CFT Table 21. PowerSSO-16 carrier tape dimensions Description Value(1) A0 6.50 0.1 B0 5.25 0.1 K0 2.10 0.1 K1 1.80 0.1 F 5.50 0.1 P1 8.00 0.1 W 12.00 0.3 1. All dimensions are in mm. Figure 58. PowerSSO-16 schematic drawing of leader and trailer tape Embossed carrier Punched carrier 8 mm & 12 mm only END Carrier tape Round sprocket holes START Top cover tape Elongated sprocket holes (32 mm tape and wider) Trailer 160 mm minimum Top cover tape Components 100 mm min. Leader 400 mm minimum User direction feed GAPG2004151511CFT DS10829 - Rev 4 page 42/53 VN7040AJ, VN7040AS SO-8 packing information 7.4 SO-8 packing information Figure 59. Reel for SO-8 Access Hole at Slot Location ( 40 mm min.) W2 A N D C W1 B If present, tape slot in core for tape start: 2.5 mm min. width x 10.0 mm min. depth TAPG2004151655CFT Table 22. Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2/ -0) 12.4 W2 (max) 18.4 1. All dimensions are in mm. DS10829 - Rev 4 page 43/53 VN7040AJ, VN7040AS SO-8 packing information Figure 60. SO-8 carrier tape GAPG2105151447CFT Table 23. SO-8 carrier tape dimensions Description Value(1) A0 6.50 0.1 B0 5.30 0.1 K0 2.20 0.1 K1 1.90 0.1 F 5.50 0.1 P1 8.00 0.1 W 12.00 0.3 1. All dimensions are in mm. Figure 61. SO-8 schematic drawing of leader and trailer tape DS10829 - Rev 4 page 44/53 VN7040AJ, VN7040AS PowerSSO-16 marking information 7.5 PowerSSO-16 marking information Figure 62. PowerSSO-16 marking information Special function digit &: Engineering sample <blank>: Commercial sample PowerSSO-16 TOP VIEW (not to scale) GADG0310161234SMD Parts marked as `&' are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 7.6 SO-8 marking information Figure 63. SO-8 marking information Marking area 1 2 3 4 5 6 7 8 Special function digit &: Engineering sample <blank>: Commercial sample SO-8 TOP VIEW (not in scale) GAPG2705151558CFT Note: DS10829 - Rev 4 Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions page 45/53 VN7040AJ, VN7040AS Order codes 8 Order codes Table 24. Device summary Package DS10829 - Rev 4 Order codes Tape and reel PowerSSO-16 VN7040AJTR SO-8 VN7040ASTR page 46/53 VN7040AJ, VN7040AS Revision history Table 25. Document revision history Date Revision 04-Jun-2015 1 Changes Initial release. Updated cover image. Updated Table 4: "Thermal data" 20-Jul-2015 2 Updated following sections: * Section 6.1: "PowerSSO-16 thermal data" * Section 6.2: "SO-8 thermal data" Updated the following: 02-Oct-2016 02-Jul-2018 DS10829 - Rev 4 3 4 * Features list on the cover page * Figure 61: "PowerSSO-16 marking information" Minor text changes in Section 4.4.2 TCASE and VCC monitor. page 47/53 VN7040AJ, VN7040AS Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 4 2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.1 Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.1 GND protection network against reverse battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 Diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 Multisense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.1 Principle of Multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.2 TCASE and VCC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4.3 Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Maximum demagnetization energy (VCC = 16 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 6 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 7 6.1 PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 SO-8 thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 7.1 PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3 PowerSSO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DS10829 - Rev 4 page 48/53 VN7040AJ, VN7040AS Contents 8 7.4 SO-8 packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.5 PowerSSO-16 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.6 SO-8 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 DS10829 - Rev 4 page 49/53 VN7040AJ, VN7040AS List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suggested connections for unused and not connected pins . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiSense multiplexer addressing . . . . . . . . . . . . . . . . . . . ISO 7637-2 - electrical transient conduction along supply line MultiSense pin levels in off-state . . . . . . . . . . . . . . . . . . . . PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 carrier tape dimensions . . . . . . . . . . . . . . . . Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . DS10829 - Rev 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 . 6 . 6 . 7 . 7 . 9 . 9 15 15 25 29 32 34 35 37 38 40 41 42 43 44 46 47 page 50/53 VN7040AJ, VN7040AS List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. DS10829 - Rev 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration diagram (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current sense accuracy versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching time and Pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiSense timings (current sense mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multisense timings (chip temperature and VCC sense mode) (VN7040AJ only) . . . . . . . . . . TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD) . . . . . . . . . . . . Latch functionality - behavior in hard short-circuit condition. . . . . . . . . . . . . . . . . . . . . . . . Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off) . . . Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGND(ON) vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Input low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Input hysteresis voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FaultRST Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF-state open-load voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vsense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vsenseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiSense and diagnostic - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiSense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analogue HSD - open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum turn off current versus inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on) . PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) . . . . . . . Thermal fitting model of a double-channel HSD in PowerSSO-16 . . . . . . . . . . . . . . . . . . . S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 12 13 13 14 14 15 16 17 17 18 18 19 19 19 19 20 20 20 20 20 20 21 21 21 21 21 21 22 22 22 22 24 24 26 27 28 29 30 31 32 32 33 33 34 35 35 36 page 51/53 VN7040AJ, VN7040AS List of figures Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. DS10829 - Rev 4 SO-8 thermal impedance junction ambient single pulse (one channel on) . Thermal fitting model of a double-channel HSD in SO-8 . . . . . . . . . . . . . PowerSSO-16 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 reel 13" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 schematic drawing of leader and trailer tape . . . . . . . . . . Reel for SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 schematic drawing of leader and trailer tape. . . . . . . . . . . . . . . . . PowerSSO-16 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 37 38 40 41 42 42 43 44 44 45 45 page 52/53 VN7040AJ, VN7040AS IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2018 STMicroelectronics - All rights reserved DS10829 - Rev 4 page 53/53