LTC3787
1
3787fc
n Industrial
n Automotive
n Medical
n Military
TYPICAL APPLICATION
n 2-Phase Operation Reduces Required Input and
Output Capacitance and Power Supply Induced Noise
n Synchronous Operation for Highest Efficiency and
Reduced Heat Dissipation
n Wide VIN Range: 4.5V to 38V (40V Abs Max) and
Operates Down to 2.5V After Start-Up
n Output Voltage Up to 60V
n ±1% 1.200V Reference Voltage
n RSENSE or Inductor DCR Current Sensing
n 100% Duty Cycle Capability for Synchronous MOSFET
n Low Quiescent Current: 135A
n Phase-Lockable Frequency (75kHz to 850kHz)
n Programmable Fixed Frequency (50kHz to 900kHz)
n Power Good Output Voltage Monitor
n Low Shutdown Current, IQ < 8µA
n Internal LDO Powers Gate Drive from VBIAS or EXTVCC
n Thermally Enhanced Low Profile 28-Pin 4mm × 5mm
QFN Package and Narrow SSOP Package
FEATURES DESCRIPTION
PolyPhase Synchronous
Boost Controller
The LTC
®
3787 is a high performance PolyPhase
®
single
output synchronous boost converter controller that drives
two N-channel power MOSFET stages out-of-phase.
Multiphase operation reduces input and output capacitor
requirements and allows the use of smaller inductors than
the single-phase equivalent. Synchronous rectification in-
creases efficiency, reduces power losses and eases thermal
requirements, enabling high power boost applications.
A 4.5V to 38V input supply range encompasses a wide
range of system architectures and battery chemistries.
When biased from the output of the boost converter or
another auxiliary supply, the LTC3787 can operate from
an input supply as low as 2.5V after start-up. The operat-
ing frequency can be set for a 50kHz to 900kHz range or
synchronized to an external clock using the internal PLL.
PolyPhase operation allows the LTC3787 to be configured
for 2-, 3-, 4-, 6- and 12-phase operation.
The SS pin ramps the output voltage during start-up. The
PLLIN/MODE pin selects Burst Mode
®
operation, pulse-
skipping mode or forced continuous mode at light loads.
APPLICATIONS
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, OPTI-LOOP and PolyPhase
are registered trademarks and No RSENSE and ThinSOT are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by
U. S. Patents, including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258.
15nF
4.7µF
8.66k
12.1k
VOUT
24V AT 10A
VIN
VIN 4.5V TO 24V START-UP VOLTAGE
OPERATES THROUGH TRANSIENTS DOWN TO 2.5V
0.1µF
100pF
220µF
TG1
BOOST1
SW1
BG1
FREQ
SS SGND
SENSE1+
SENSE1–
VFB
ITH
VBIAS
LTC3787
INTVCC
PLLIN/MODE
TG2
BOOST2
SW2
BG2
SENSE2+
SENSE2–
PGND
0.1µF 0.1µF
4.7µF
232k
3787 TA01a
47µF
3.3µH
3.3µH
4m 4m
12V to 24V/10A 2-Phase Synchronous Boost Converter
OUTPUT CURRENT (A)
40
EFFICIENCY (%)
POWER LOSS (mW)
50
60
70
80
3787 TA01b
30
20
10
0
90
100
10
100
1000
1
0.1
10000
0.01 0.1 1 10
BURST EFFICIENCY
BURST LOSS
VIN = 12V
VOUT = 24V
Burst Mode OPERATION
FIGURE 10 CIRCUIT
0.0001 0.0010.00001
Efficiency and Power Loss
vs Output Current
LTC3787
2
3787fc
ABSOLUTE MAXIMUM RATINGS
VBIAS ........................................................ –0.3V to 40V
BOOST1 and BOOST2 ................................ –0.3V to 76V
SW1 and SW2 ............................................ –0.3V to 70V
RUN ............................................................. –0.3V to 8V
Maximum Current Sourced into Pin
From Source >8V ..............................................100µA
PGOOD, PLLIN/MODE ................................. –0.3V to 6V
INTVCC, (BOOST1 - SW1), (BOOST2 - SW2) ...–0.3V to 6V
(Notes 1, 3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
GN PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ILIM
SENSE1+
SENSE1–
FREQ
PHASMD
CLKOUT
PLLIN/MODE
SGND
RUN
SS
SENSE2–
SENSE2+
VFB
ITH
PGOOD
SW1
TG1
BOOST1
BG1
VBIAS
PGND
EXTVCC
INTVCC
BG2
BOOST2
TG2
SW2
NC
TJMAX = 125°C, θJA = 90°C/W
9 10
TOP VIEW
29
GND
UFD PACKAGE
28-LEAD (4mm s 5mm) PLASTIC QFN
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
FREQ
PHASMD
CLKOUT
PLLIN/MODE
SGND
RUN
SS
SENSE2–
BOOST1
BG1
VBIAS
PGND
EXTVCC
INTVCC
BG2
BOOST2
SENSE1–
SENSE1+
ILIM
PGOOD
SW1
TG1
SENSE2+
VFB
ITH
NC
SW2
TG2
7
17
18
19
20
21
22
16
815
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE CONNECTED TO GND
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3787EUFD#PBF LTC3787EUFD#TRPBF 3787 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LTC3787IUFD#PBF LTC3787IUFD#TRPBF 3787 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LTC3787HUFD#PBF LTC3787HUFD#TRPBF 3787 28-Lead (4mm × 5mm) Plastic QFN –40°C to 150°C
LTC3787MPUFD#PBF LTC3787MPUFD#TRPBF 3787 28-Lead (4mm × 5mm) Plastic QFN –55°C to 150°C
LTC3787EGN#PBF LTC3787EGN#TRPBF LTC3787GN 28-Lead Plastic SSOP –40°C to 125°C
LTC3787IGN#PBF LTC3787IGN#TRPBF LTC3787GN 28-Lead Plastic SSOP –40°C to 125°C
LTC3787HGN#PBF LTC3787HGN#TRPBF LTC3787GN 28-Lead Plastic SSOP –40°C to 150°C
LTC3787MPGN#PBF LTC3787MPGN#TRPBF LTC3787GN 28-Lead Plastic SSOP –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
EXTVCC ........................................................ –0.3V to 6V
SENSE1+, SENSE1–, SENSE2+, SENSE2– ... –0.3V to 40V
(SENSE1+ - SENSE1–), (SENSE2+ - SENSE2–) ...–0.3V to 0.3V
ILIM, SS, ITH, FREQ, PHASMD, VFB .....–0.3V to INTVCC
Operating Junction Temperature
Range (Note 2) ........................................–55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
LTC3787
3
3787fc
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = 12V, unless otherwise noted (Note 2).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
VBIAS Chip Bias Voltage Operating Range 4.5 38 V
VFB Regulated Feedback Voltage ITH = 1.2V (Note 4) l1.188 1.200 1.212 V
IFB Feedback Current (Note 4) ±5 ±50 nA
VREFLNREG Reference Line Voltage Regulation VBIAS = 6V to 38V 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 0.7V
l0.01 0.1 %
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 2V
l–0.01 –0.1 %
gmError Amplifier Transconductance ITH = 1.2V 2 mmho
IQInput DC Supply Current
Pulse-Skipping or Forced Continuous Mode
Sleep Mode
Shutdown
(Note 5)
RUN = 5V; VFB = 1.25V (No Load)
RUN = 5V; VFB = 1.25V (No Load)
RUN = 0V
1.2
135
8
300
20
mA
µA
µA
UVLO INTVCC Undervoltage Lockout Thresholds VINTVCC Ramping Up
VINTVCC Ramping Down
l
l3.6
4.1
3.8
4.3 V
V
VRUN RUN Pin ON Threshold VRUN Rising l1.18 1.28 1.38 V
VRUNHYS RUN Pin Hysteresis 100 mV
IRUNHYS RUN Pin Hysteresis Current VRUN > 1.28V 4.5 µA
IRUN RUN Pin Current VRUN < 1.28V 0.5 µA
ISS Soft-Start Charge Current VSS = GND 7 10 13 µA
VSENSE1,2(MAX) Maximum Current Sense Threshold VFB = 1.1V, ILIM = INTVCC
VFB = 1.1V, ILIM = Float
VFB = 1.1V, ILIM = GND
l
l
l
90
68
42
100
75
50
110
82
56
mV
mV
mV
VSENSE(MATCH) Matching Between VSENSE1(MAX) and
VSENSE2(MAX)
VFB = 1.1V, ILIM = INTVCC
VFB = 1.1V, ILIM = Float
VFB = 1.1V, ILIM = GND
l
l
l
–12
–10
–9
0
0
0
12
10
9
mV
mV
mV
VSENSE(CM) SENSE Pins Common Mode Range (BOOST
Converter Input Supply Voltage VIN)
2.5 38 V
ISENSE1,2+SENSE+ Pin Current VFB = 1.1V, ILIM = Float 200 300 µA
ISENSE1,2–SENSE– Pin Current VFB = 1.1V, ILIM = Float ±1 µA
tr(TG1,2) Top Gate Rise Time CLOAD = 3300pF (Note 6) 20 ns
tf(TG1,2) Top Gate Fall Time CLOAD = 3300pF (Note 6) 20 ns
tr(BG1,2) Bottom Gate Rise Time CLOAD = 3300pF (Note 6) 20 ns
tr(BG1,2) Bottom Gate Fall Time CLOAD = 3300pF (Note 6) 20 ns
RUP(TG1,2) Top Gate Pull-Up Resistance 1.2
RDN(TG1,2) Top Gate Pull-Down Resistance 1.2
RUP(TG1,2) Bottom Gate Pull-Up Resistance 1.2
RDN(TG1,2) Bottom Gate Pull-Down Resistance 1.2
tD(TG/BG) Top Gate Off to Bottom Gate On Switch-On
Delay Time
CLOAD = 3300pF (Each Driver) 70 ns
tD(BG/TG) Bottom Gate Off to Top Gate On Switch-On
Delay Time
CLOAD = 3300pF (Each Driver) 70 ns
DFBG1,2(MAX) Maximum BG Duty Factor 96 %
tON(MIN) Minimum BG On-Time (Note 7) 110 ns
LTC3787
4
3787fc
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Linear Regulator
VINTVCC(VIN) Internal VCC Voltage 6V < VBIAS < 38V, VEXTVCC = 0 5.2 5.4 5.6 V
VLDO INT INTVCC Load Regulation ICC = 0mA to 50mA 0.5 2 %
VINTVCC(EXT) Internal VCC Voltage VEXTVCC = 6V 5.2 5.4 5.6 V
VLDO EXT INTVCC Load Regulation ICC = 0mA to 40mA, VEXTVCC = 6V 0.5 2 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive l4.5 4.8 5 V
VLDOHYS EXTVCC Hysteresis 250 mV
Oscillator and Phase-Locked Loop
fPROG Programmable Frequency RFREQ = 25k
RFREQ = 60k
RFREQ = 100k
335
105
400
760
465
kHz
kHz
kHz
fLOW Lowest Fixed Frequency VFREQ = 0V 320 350 380 kHz
fHIGH Highest Fixed Frequency VFREQ = INTVCC 488 535 585 kHz
fSYNC Synchronizable Frequency PLLIN/MODE = External Clock l75 850 kHz
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.2 0.4 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPGOOD PGOOD Trip Level VFB with Respect to Set Regulated Voltage
V
FB Ramping Negative
Hysteresis
–12 –10
2.5
–8 %
%
V
FB Ramping Positive
Hysteresis
810
2.5
12 %
%
tPGOOD(DELAY) PGOOD Delay PGOOD Going High to Low 25 µs
BOOST1 and BOOST2 Charge Pump
IBOOST1,2 BOOST Charge Pump Available Output
Current
VSW1,2 = 12V; VBOOST1,2 – VSW1,2 = 4.5V;
FREQ = 0V, Forced Continuous or
Pulse-Skipping Mode
55 µA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = 12V, unless otherwise noted (Note 2).
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3787 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3787E is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3787I is guaranteed over the –40°C to 125°C operating junction
temperature range, the LTC3787H is guaranteed over the –40°C to 150°C
operating temperature range and the LTC3787MP is tested and guaranteed
over the full –55°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors. The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula: TJ = TA + (PD • θJA), where θJA = 43°C/W for the QFN package
and θJA = 90°C/W for the SSOP package.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC3787 is tested in a feedback loop that servos VFB to the
output of the error amplifier while maintaining ITH at the midpoint of the
current limit range.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: see Minimum On-Time Considerations in the Applications
Information section.
LTC3787
5
3787fc
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
Burst Mode Operation
Load Step
Forced Continuous Mode
Load Step
Pulse-Skipping Mode
Efficiency and Power Loss
vs Output Current
Efficiency and Power Loss
vs Output Current
Efficiency vs Load Current
OUTPUT CURRENT (A)
40
EFFICIENCY (%)
POWER LOSS (mW)
50
60
70
80
10
3787 G01
30
20
10
0
90
100
10
100
1000
1
0.1
10000
0.01 0.1 1
BURST EFFICIENCY
PULSE-SKIPPING
EFFICIENCY
FORCED CONTINUOUS
MODE EFFICIENCY
BURST LOSS
PULSE-SKIPPING
LOSS
FORCED CONTINUOUS
MODE LOSS
VIN = 12V
VOUT = 24V
FIGURE 10 CIRCUIT
OUTPUT CURRENT (A)
40
EFFICIENCY (%)
POWER LOSS (mW)
50
60
70
80
3787 G02
30
20
10
0
90
100
10
100
1000
1
0.1
10000
0.01 0.1 1 10
BURST EFFICIENCY
BURST LOSS
VIN = 12V
VOUT = 24V
Burst Mode OPERATION
FIGURE 10 CIRCUIT
0.0001 0.0010.00001
INPUT VOLTAGE (V)
0
90
EFFICIENCY (%)
92
94
96
510 15 20
98
100
91
93
95
97
99
25
3
7
8
7
G03
VOUT = 12V
VIN = 12V
ILOAD = 2A
FIGURE 10 CIRCUIT
VOUT = 24V
VOUT
500mV/DIV
INDUCTOR
CURRENT
5A/DIV
LOAD STEP
5A/DIV
VIN = 12V
VOUT = 24V
LOAD STEP FROM 100mA TO 5A
FIGURE 10 CIRCUIT
200µs/DIV 3787 G04
VOUT
500mV/DIV
INDUCTOR
CURRENT
5A/DIV
LOAD STEP
5A/DIV
VIN = 12V
VOUT = 24V
LOAD STEP FROM 100mA TO 5A
FIGURE 10 CIRCUIT
200µs/DIV 3787 G05
VOUT
500mV/DIV
INDUCTOR
CURRENT
5A/DIV
LOAD STEP
5A/DIV
VIN = 12V
VOUT = 24V
LOAD STEP FROM 100mA TO 5A
FIGURE 10 CIRCUIT
200µs/DIV 3787 G06
LTC3787
6
3787fc
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Current at Light Load Soft Start-Up
Regulated Feedback Voltage
vs Temperature
PULSE-SKIPPING
MODE
Burst Mode
OPERATION
5A/DIV
FORCED
CONTINUOUS MODE
VIN = 12V
VOUT = 24V
ILOAD = 200µA
FIGURE 10 CIRCUIT
5µs/DIV 3787 G07
0V
VOUT
5V/DIV
VIN = 12V
VOUT = 24V
FIGURE 10 CIRCUIT
20ms/DIV 3787 G08
Shutdown Current vs Temperature
Soft-Start Pull-Up Current
vs Temperature
Shutdown Current vs Input Voltage
015
510 2025 30 35 40
INPUT VOLTAGE (V)
SHUTDOWN CURRENT (µA)
10
20
5
0
15
3787 G12
TEMPERATURE (°C)
–60
REGULATED FEEDBACK VOLTAGE (V)
1.209
15
3787 G09
1.200
1.194
–35 –10 40
1.191
1.188
1.212
1.206
1.203
1.197
65 90 140115
TEMPERATURE (°C)
SOFT-START CURRENT (µA)
10.5
3787 G10
9.0
11.0
10.0
9.5
–60 15
–35 –10 40 65 90 140115
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
7.0
9.5
10.0
10.5
11.0
6.0
8.5
6.5
9.0
5.5
5.0
8.0
7.5
3787 G11
–60 15
–35 –10 40 65 90 140115
VIN = 12V
LTC3787
7
3787fc
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current vs Temperature
EXTVCC Switchover and INTVCC
Voltages vs Temperature
INTVCC Line Regulation
Shutdown (RUN) Threshold
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
INTVCC vs INTVCC Load Current
015
510 20
25 30 35 40
INPUT VOLTAGE (V)
INTVCC VOLTAGE (V)
4.7
5.2
5.3
5.4
5.5
5.0
4.6
5.1
4.5
4.9
4.8
3
7
8
7
G
1
6
INTVCC LOAD CURRENT (mA)
0
INTVCC VOLTAGE (V)
5.35
5.40
5.45
140
5.30
5.25
40 80
20 180
60 100 160
120 200
5.20
5.00
5.10
5.05
5.15
5.50
3787 G17
EXTVCC = 0V
EXTVCC = 6V
VIN = 12V
–60 15
–35 –10 40 65 90 140115
TEMPERATURE (°C)
QUIESCENT CURRENT (µA)
3787 G13
140
120
110
180
160
170
150
130
VIN = 12V
VFB = 1.25V
RUN = GND
–60 15
–35 –10 40 65 90 140115
TEMPERATURE (°C)
RUN PIN VOLTAGE (V)
3787 G14
1.25
1.15
1.10
1.40
1.35
1.30
1.20 RUN FALLING
RUN RISING
TEMPERATURE (°C)
INTVCC VOLTAGE (V)
3.6
4.1
4.2
4.3
4.4
3.9
3.5
4.0
3.4
3.8
3.7
3787 G15
–60 15
–35 –10 40 65 90 140115
INTVCC RISING
INTVCC FALLING
TEMPERATURE (°C)
4.0
EXTVCC AND INTVCC VOLTAGE (V)
4.2
4.6
4.8
5.0
6.0
5.4
4.4
5.6
5.8
5.2
3787 G18
–60 15
–35 –10 40 65 90 140115
INTVCC
EXTVCC RISING
EXTVCC FALLING
LTC3787
8
3787fc
SENSE Pin Input Current
vs Temperature
Oscillator Frequency
vs Temperature
Maximum Current Sense
Threshold vs ITH Voltage
SENSE Pin Input Current
vs VSENSE Voltage
SENSE Pin Input Current
vs ITH Voltage
Oscillator Frequency
vs Input Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
15
510 2025 30 35 40
INPUT VOLTAGE (V)
OSCILLATOR FREQUENCY (kHz)
344
354
356
358
360
350
342
352
340
348
346
3
7
8
7
G
2
0
FREQ = GND
ITH VOLTAGE (V)
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
80
120
100
0.6 1.0
3787 G21
40
0
0.2 0.4 0.8 1.2 1.4
–40
60
20
–20
–60
ILIM = GND
ILIM = FLOAT
ILIM = INTVCC
Burst Mode
OPERATION
PULSE-SKIPPING MODE
FORCED CONTINUOUS MODE
ITH VOLTAGE (V)
0
SENSE CURRENT (µA)
122.5
0
80
40
160
200
240
120
20
100
60
180
220
260
140
0.5 1.5 3
3787 G23
SENSE+ PIN
SENSE– PIN
VSENSE = 12V ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
VSENSE COMMON MODE VOLTAGE (V)
2.5
SENSE CURRENT (µA)
17.5 27.5 32.5
0
80
40
160
200
240
120
20
100
60
180
220
260
140
7.5 12.5 22.5 37.5
3787 G24
SENSE+ PIN
SENSE– PIN
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
TEMPERATURE (°C)
300
FREQUENCY (kHz)
350
600
450
500
550
400
3787 G19
–60 15
–35 –10 40 65 90 140115
FREQ = INTVCC
FREQ = GND
TEMPERATURE (°C)
SENSE CURRENT (µA)
0
80
40
160
200
240
120
20
100
60
180
220
260
140
3787 G22
–60 15
–35 –10 40 65 90 140115
SENSE– PIN
SENSE+ PIN
VSENSE = 12V
ILIM = FLOAT
LTC3787
9
3787fc
TYPICAL PERFORMANCE CHARACTERISTICS
PIN FUNCTIONS
FREQ (Pin 1/Pin 4): Frequency Control Pin for the Internal
VCO. Connecting the pin to GND forces the VCO to a fixed
low frequency of 350kHz. Connecting the pin to INTVCC
forces the VCO to a fixed high frequency of 535kHz. The
frequency can be programmed from 50kHz to 900kHz
by connecting a resistor from the FREQ pin to GND. The
resistor and an internal 20A source current create a volt-
age used by the internal oscillator to set the frequency.
Alternatively, this pin can be driven with a DC voltage to
vary the frequency of the internal oscillator.
PHASMD (Pin 2/Pin 5): This pin can be floated, tied to
SGND, or tied to INTVCC to program the phase relationship
between the rising edges of BG1 and BG2, as well as the
phase relationship between BG1 and CLKOUT.
CLKOUT (Pin 3/Pin 6): A Digital Output Used for Daisy-
chaining Multiple LTC3787 ICs in Multiphase Systems. The
PHASMD pin voltage controls the relationship between BG1
and CLKOUT. This pin swings between SGND and INTVCC.
PLLIN/MODE (Pin 4/Pin 7): External Synchronization Input
to Phase Detector and Forced Continuous Mode Input.
When an external clock is applied to this pin, it will force
the controller into forced continuous mode of operation
and the phase-locked loop will force the rising BG1 signal
to be synchronized with the rising edge of the external
clock. When not synchronizing to an external clock, this
input determines how the LTC3787 operates at light loads.
Pulling this pin to ground selects Burst Mode operation.
An internal 100k resistor to ground also invokes Burst
Mode operation when the pin is floated. Tying this pin
to INTVCC forces continuous inductor current operation.
Tying this pin to a voltage greater than 1.2V and less than
INTVCC – 1.3V selects pulse-skipping operation. This can
be done by adding a 100k resistor between the PLLIN/
MODE pin and INTVCC.
SGND (Pin 5/Pin 8): Signal Ground. All small-signal
components and compensation components should
connect to this ground, which in turn connects to PGND
at a single point.
RUN (Pin 6/Pin 9): Run Control Input. Forcing this pin
below 1.28V shuts down the controller. Forcing this pin
below 0.7V shuts down the entire LTC3787, reducing
quiescent current to approximately 8µA. An external
resistor divider connected to VIN can set the threshold
for converter operation. Once running, a 4.5µA current is
sourced from the RUN pin allowing the user to program
hysteresis using the resistor values.
Maximum Current Sense
Threshold vs Duty Cycle Charge Pump Charging Current
vs Operating Frequency
DUTY CYCLE (%)
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
80
100
70
60
40
20 40
10 90
30 50 80
60 100
20
0
120
3787 G25
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
(QFN/SSOP)
Charge Pump Charging Current
vs Switch Voltage
SWITCH VOLTAGE (V)
5
0
CHARGE PUMP CHARGING CURRENT (µA)
20
30
80
50
15 25 30
10
60
70
40
10 20 35 40
3787 G27
FREQ = INTVCC
FREQ = GND
OPERATING FREQUENCY (kHz)
50
0
CHARGE PUMP CHARGING CURRENT (µA)
20
30
80
50
250 450 550
10
60
70
40
150 350 650 750
3787 G26
T = 130°C
T = 155°C
T = 25°C
T = –45°C
T = –60°C
LTC3787
10
3787fc
PIN FUNCTIONS
(QFN/SSOP)
SS (Pin 7/Pin 10): Output Soft-Start Input. A capacitor to
ground at this pin sets the ramp rate of the output voltage
during start-up.
SENSE2– , SENSE1– (Pin 8, Pin 28/Pin 11, Pin 3): Nega-
tive Current Sense Comparator Input. The (–) input to the
current comparator is normally connected to the negative
terminal of a current sense resistor connected in series
with the inductor.
SENSE2+, SENSE1+ (Pin 9, Pin 27/Pin 12, Pin 2): Posi-
tive Current Sense Comparator Input. The (+) input to the
current comparator is normally connected to the positive
terminal of a current sense resistor. The current sense resis-
tor is normally placed at the input of the boost controller in
series with the inductor. This pin also supplies power to the
current comparator. The common mode voltage range on
SENSE+ and SENSE– pins is 2.5V to 38V (40V abs max).
VFB (Pin 10/Pin 13): Error Amplifier Feedback Input. This
pin receives the remotely sensed feedback voltage from
an external resistive divider connected across the output.
ITH (Pin 11/Pin 14): Current Control Threshold and Error
Amplifier Compensation Point. The voltage on this pin sets
the current trip threshold.
NC (Pin 12/Pin 15): No Connect.
SW2, SW1 (Pin 13, Pin 24/Pin 16, Pin 27): Switch Node.
Connect to the source of the synchronous N-channel
MOSFET, the drain of the main N-channel MOSFET and
the inductor.
TG2, TG1 (Pin 14, Pin 23/Pin 17, Pin 26): Top Gate. Con-
nect to the gate of the synchronous N-channel MOSFET.
BOOST2, BOOST1 (Pin 15, Pin 22/Pin 18, Pin 25): Float-
ing power supply for the synchronous N-channel MOSFET.
Bypass to SW with a capacitor and supply with a Schottky
diode connected to INTVCC.
PGND (Pin 19/Pin 22): Driver Power Ground. Connects
to the sources of bottom (main) N-channel MOSFETs and
the (–) terminal(s) of CIN and COUT.
BG2, BG1 (Pin 16, Pin 21/Pin 19, Pin 24): Bottom Gate.
Connect to the gate of the main N-channel MOSFET.
INTVCC (Pin 17/Pin 20): Output of Internal 5.4V LDO.
Power supply for control circuits and gate drivers. De-
couple this pin to GND with a minimum 4.7F low ESR
ceramic capacitor.
EXTVCC (Pin 18/Pin 21): External Power Input. When this
pin is between 4.8V and 6V, an internal switch bypasses
the internal regulator and supply power to INTVCC directly
from EXTVCC. Do not float this pin. It can be connected to
ground when not used.
VBIAS (Pin 20/Pin 23): Main Supply Pin. It is normally
tied to the input supply VIN or to the output of the boost
converter. A bypass capacitor should be tied between this
pin and the signal ground pin. The operating voltage range
on this pin is 4.5V to 38V (40V abs max).
PGOOD (Pin 25/Pin 28): Power Good Indicator. Open-drain
logic output that is pulled to ground when the output volt-
age is more than ±10 % away from the regulated output
voltage. To avoid false trips the output voltage must be
outside the range for 25s before this output is activated.
ILIM (Pin 26/Pin 1): Current Comparator Sense Voltage
Range Input. This pin is used to set the peak current
sense voltage in the current comparator. Connect this pin
to SGND, open, and INTVCC to set the peak current sense
voltage to 50mV, 75mV and 100mV, respectively.
GND (Exposed Pad Pin 29) UFD Package: Ground. Must
be soldered to the PCB for rated thermal performance.
LTC3787
11
3787fc
BLOCK DIAGRAM
SLEEP
SWITCHING
LOGIC
AND
CHARGE
PUMP
+
–
4.8V
3.8V
VBIAS
VIN
CIN
INTVCC
PLLIN/
MODE
PGOOD
+
–
1.32V
1.08V
+
–
–
–
+
–
+VFB
EXTVCC
5.4V
LDO
VCO
PFD
SW
0.425V
SENS LO
BOOST
TG CB
COUT
VOUT
DB
CLKOUT
PGND
BG
INTVCC
VFB
S
RQ
EA
1.32V
SS
1.2V
RSENSE
0.5µA/
4.5µA
10µA
11V
SHDN
–
+
SHDN
2.5V
–
+
RC
SS
SENS
LO
ITH CC
CSS
CC2
0.7V
2.8V
SLOPE COMP
2mV
+
–
–
+
SENSE–
SENSE+
SHDN
CLK2
CLK1
RUN
SGND
INTVCC
FREQ
DUPLICATE FOR SECOND CONTROLLER CHANNEL
+–
+
–L
+
–
EN
5.4V
LDO
EN
20µA
100k
SYNC
DET
ILIM
PHASMD
OV
3787 BD
CURRENT
LIMIT
ICMP IREV
OPERATION
Main Control Loop
The LTC3787 uses a constant-frequency, current mode
step-up architecture with the two controller channels
operating out of phase. During normal operation, each
external bottom MOSFET is turned on when the clock for
that channel sets the RS latch, and is turned off when the
main current comparator, ICMP, resets the RS latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin (which is generated with an external resistor divider
connected across the output voltage, VOUT, to ground), to
the internal 1.200V reference voltage. In a boost converter,
the required inductor current is determined by the load
current, VIN and VOUT. When the load current increases,
it causes a slight decrease in VFB relative to the reference,
which causes the EA to increase the ITH voltage until the
average inductor current in each channel matches the new
requirement based on the new load current.
After the bottom MOSFET is turned off each cycle, the
top MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current comparator,
IR, or the beginning of the next clock cycle.
LTC3787
12
3787fc
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is tied to a voltage less than 4.8V,
the VBIAS LDO (low dropout linear regulator) supplies
5.4V from VBIAS to INTVCC. If EXTVCC is taken above
4.8V, the VBIAS LDO is turned off and an EXTVCC LDO is
turned on. Once enabled, the EXTVCC LDO supplies 5.4V
from EXTVCC to INTVCC. Using the EXTVCC pin allows the
INTVCC power to be derived from an external source, thus
removing the power dissipation of the VBIAS LDO.
Shutdown and Start-Up (RUN and SS Pins)
The two internal controllers of the LTC3787 can be shut
down using the RUN pin. Pulling this pin below 1.28V
shuts down the main control loops for both phases.
Pulling this pin below 0.7V disables both controllers and
most internal circuits, including the INTVCC LDOs. In this
state, the LTC3787 draws only 8A of quiescent current.
NOTE: Do not apply a heavy load for an extended time
while the chip is in shutdown. The top MOSFETs will be
turned off during shutdown and the output load may cause
excessive dissipation in the body diodes.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to
a higher voltage (for example, VIN), as long as the maxi-
mum current into the RUN pin does not exceed 100A.
An external resistor divider connected to VIN can set the
threshold for converter operation. Once running, a 4.5A
current is sourced from the RUN pin allowing the user to
program hysteresis using the resistor values.
The start-up of the controller’s output voltage VOUT is
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 1.2V internal reference, the
LTC3787 regulates the VFB voltage to the SS pin voltage
instead of the 1.2V reference. This allows the SS pin to
be used to program a soft-start by connecting an external
capacitor from the SS pin to SGND. An internal 10A
pull-up current charges this capacitor creating a voltage
ramp on the SS pin. As the SS voltage rises linearly from
0V to 1.2V (and beyond up to INTVCC), the output voltage
rises smoothly to its final value.
Light Load Current Operation—Burst Mode Operation,
Pulse-Skipping or Continuous Conduction
(PLLIN/MODE Pin)
The LTC3787 can be enabled to enter high efficiency
Burst Mode operation, constant-frequency, pulse-skipping
mode or forced continuous conduction mode at low
load currents. To select Burst Mode operation, tie the
PLLIN/MODE pin to ground (e.g., SGND). To select
forced continuous operation, tie the PLLIN/MODE pin to
INTVCC. To select pulse-skipping mode, tie the PLLIN/
MODE pin to a DC voltage greater than 1.2V and less
than INTVCC – 1.3V.
When the controller is enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
approximately 30% of the maximum sense voltage even
though the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the required
current, the error amplifier EA will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off.
In sleep mode much of the internal circuitry is turned off
and the LTC3787 draws only 135A of quiescent current.
In sleep mode the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low and the controller resumes normal
operation by turning on the bottom external MOSFET on
the next cycle of the internal oscillator.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the top external MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous current operation.
OPERATION
LTC3787
13
3787fc
OPERATION
In forced continuous operation or when clocked by an
external clock source to use the phase-locked loop (see
the Frequency Selection and Phase-Locked Loop section),
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined by the voltage on the ITH pin, just as
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantages of lower output
voltage ripple and less interference to audio circuitry, as
it maintains constant-frequency operation independent
of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3787 operates in PWM pulse-skipping mode
at light loads. In this mode, constant-frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator ICMP may remain tripped for several cycles
and force the external bottom MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3787’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTVCC, or programmed through an external resistor. Tying
FREQ to SGND selects 350kHz while tying FREQ to INTVCC
selects 535kHz. Placing a resistor between FREQ and SGND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 6.
A phase-locked loop (PLL) is available on the LTC3787
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3787’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of the first controller’s external bottom MOSFET
to the rising edge of the synchronizing signal. Thus, the
turn-on of the second controller’s external bottom MOSFET
is 180 or 240 degrees out-of-phase to the rising edge of
the external clock source.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of BG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3787’s PLL is from
approximately 55kHz to 1MHz, and is guaranteed to lock
to an external clock source whose frequency is between
75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3787 features two pins, CLKOUT and PHASMD,
that allow other controller ICs to be daisychained with
the LTC3787 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
between the two internal controllers, as summarized in
Table 1. The phases are calculated relative to the zero
degrees phase being defined as the rising edge of the
bottom gate driver output of controller 1 (BG1). Depend-
ing on the phase selection, a PolyPhase application with
LTC3787
14
3787fc
OPERATION
multiple LTC3787s can be configured for 2-, 3-, 4- , 6- and
12-phase operation.
Table 1.
VPHASMD CONTROLLER 2 PHASE (°C) CLKOUT PHASE (°C)
GND 180 60
Floating 180 90
INTVCC 240 120
CLKOUT is disabled when the controller is in shutdown
or in sleep mode.
Operation When VIN > Regulated VOUT
When VIN rises above the regulated VOUT voltage, the boost
controller can behave differently depending on the mode,
inductor current and VIN voltage. In forced continuous
mode, the loop works to keep the top MOSFET on con-
tinuously once VIN rises above VOUT. The internal charge
pump delivers current to the boost capacitor to maintain
a sufficiently high TG voltage. The amount of current the
charge pump can deliver is characterized by two curves
in the Typical Performance Characteristics section.
In pulse-skipping mode, if VIN is between 100% and
110% of the regulated VOUT voltage, TG turns on if the
inductor current rises above a certain threshold and turns
off if the inductor current falls below this threshold. This
threshold current is set to approximately 6%, 4% or
3% of the maximum ILIM current when the ILIM pin is
grounded, floating or tied to INTVCC, respectively. If the
controller is programmed to Burst Mode operation under
this same VIN window, then TG remains off regardless of
the inductor current.
If VIN rises above 110% of the regulated VOUT voltage in
any mode, the controller turns on TG regardless of the
inductor current. In Burst Mode operation, however, the
internal charge pump turns off if the chip is asleep. With
the charge pump off, there would be nothing to prevent
the boost capacitor from discharging, resulting in an
insufficient TG voltage needed to keep the top MOSFET
completely on. To prevent excessive power dissipation
across the body diode of the top MOSFET in this situation,
the chip can be switched over to forced continuous mode
to enable the charge pump or a Schottky diode can also
be placed in parallel to the top MOSFET.
Power Good
The PGOOD pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the VFB pin voltage is not
within ±10% of the 1.2V reference voltage. The PGOOD
pin is also pulled low when the corresponding RUN pin
is low (shut down). When the VFB pin voltage is within
the ±10% requirement, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to a
source of up to 6V (abs max).
Operation at Low SENSE Pin Common Mode Voltage
The current comparator in the LTC3787 is powered directly
from the SENSE+ pin. This enables the common mode
voltage of the SENSE+ and SENSE– pins to operate at as
low as 2.5V, which is below the UVLO threshold. The figure
on the first page shows a typical application in which the
controller’s VBIAS is powered from VOUT while the VIN
supply can go as low as 2.5V. If the voltage on SENSE+
drops below 2.5V, the SS pin will be held low. When the
SENSE voltage returns to the normal operating range, the
SS pin will be released, initiating a new soft-start cycle.
BOOST Supply Refresh and Internal Charge Pump
Each top MOSFET driver is biased from the floating
bootstrap capacitor, CB, which normally recharges during
each cycle through an external diode when the bottom
MOSFET turns on. There are two considerations for keep-
ing the BOOST supply at the required bias level. During
start-up, if the bottom MOSFET is not turned on within
100s after UVLO goes low, the bottom MOSFET will be
forced to turn on for ~400ns. This forced refresh gener-
ates enough BOOST-SW voltage to allow the top MOSFET
ready to be fully enhanced instead of waiting for the initial
few cycles to charge up. There is also an internal charge
pump that keeps the required bias on BOOST. The charge
pump always operates in both forced continuous mode
and pulse-skipping mode. In Burst Mode operation, the
charge pump is turned off during sleep and enabled when
the chip wakes up. The internal charge pump can normally
supply a charging current of 55A.
LTC3787
15
3787fc
The Typical Application on the first page is a basic LTC3787
application circuit. LTC3787 can be configured to use either
inductor DCR (DC resistance) sensing or a discrete sense
resistor (RSENSE) for current sensing. The choice between
the two current sensing schemes is largely a design trade-
off between cost, power consumption and accuracy. DCR
sensing is becoming popular because it does not require
current sensing resistors and is more power-efficient,
especially in high current applications. However, current
sensing resistors provide the most accurate current limits
for the controller. Other external component selection is
driven by the load requirement, and begins with the se-
lection of RSENSE (if RSENSE is used) and inductor value.
Next, the power MOSFETs are selected. Finally, input and
output capacitors are selected. Note that the two control-
ler channels of the LTC3787 should be designed with the
same components.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the cur-
rent comparators. The common mode input voltage range
of the current comparators is 2.5V to 38V. The current
sense resistor is normally placed at the input of the boost
controller in series with the inductor.
APPLICATIONS INFORMATION
The SENSE+ pin also provides power to the current com-
parator. It draws ~200A during normal operation. There
is a small base current of less than 1A that flows into
the SENSE– pin. The high impedance SENSE– input to the
current comparators allows accurate DCR sensing.
Filter components mutual to the sense lines should be
placed close to the LTC3787, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
close to the switching node, to prevent noise from coupling
into sensitive small-signal nodes.
Figure 1. Sense Lines Placement with
Inductor or Sense Resistor
(2a) Using a Resistor to Sense Current (2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
VIN
TO SENSE FILTER,
NEXT TO THE CONTROLLER
INDUCTOR OR RSENSE 3787 F01
TG
SW
BG
LTC3787
INTVCC
BOOST
SENSE+
SENSE–
(OPTIONAL)
VBIAS VIN
VOUT
SGND
3787 F02a
TG
SW
BG
INDUCTOR
DCR
L
LTC3787
INTVCC
BOOST
SENSE+
SENSE–
R2C1
R1
VBIAS VIN
VOUT
PLACE C1 NEAR SENSE PINS
SGND
3787 F02b
(R1||R2) • C1 = L
DCR RSENSE(EQ) = DCR • R2
R1 + R2
LTC3787
16
3787fc
APPLICATIONS INFORMATION
Sense Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX). When the ILIM pin is grounded, floating or
tied to INTVCC, the maximum threshold is set to 50mV,
75mV or 100mV, respectively. The current comparator
threshold sets the peak of the inductor current, yielding
a maximum average inductor current, IMAX, equal to the
peak value less half the peak-to-peak ripple current, ∆IL.
To calculate the sense resistor value, use the equation:
RSENSE =VSENSE(MAX)
IMAX +ΔIL
2
The actual value of IMAX for each channel depends on the
required output current IOUT(MAX) and can be calculated
using:
IMAX =IOUT(MAX)
2
⎛
⎝
⎜⎞
⎠
⎟•VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
When using the controller in low VIN and very high voltage
output applications, the maximum inductor current and
correspondingly the maximum output current level will
be reduced due to the internal compensation required to
meet stability criterion for boost regulators operating at
greater than 50% duty factor. A curve is provided in the
Typical Performance Characteristics section to estimate
this reduction in peak inductor current level depending
upon the operating duty factor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3787 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor can be less than 1m
for high current inductors. In a high current application
requiring such an inductor, conduction loss through a
sense resistor could reduce the efficiency by a few percent
compared to DCR sensing.
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature. Consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the induct-
or value calculation section, the target sense resistor
value is:
RSENSE(EQUIV) =VSENSE(MAX)
IMAX +ΔIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the maximum current sense threshold
(VSENSE(MAX)).
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C.
A conservative value for the maximum inductor temperature
(TL(MAX)) is 100°C.
LTC3787
17
3787fc
APPLICATIONS INFORMATION
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RD=RSENSE(EQUIV)
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1F to 0.47F.
This forces R1|| R2 to around 2k, reducing error that might
have been caused by the SENSE– pin’s ±1A current.
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
R1||R2 =L
(DCR at 20°C)•C1
The sense resistor values are:
R1=R1||R2
RD
;R2=R1• RD
1−RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at VIN = 1/2VOUT:
PLOSS_R1 =(VOUT −VIN )•V
IN
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are in-
terrelated in that higher operating frequencies allow the
use of smaller inductor and capacitor values. Why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge and switching losses. Also, at
higher frequency the duty cycle of body diode conduction
is higher, which results in lower efficiency. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL decreases with higher
inductance or frequency and increases with higher VIN:
ΔIL=VIN
f•L 1−VIN
VOUT
⎛
⎝
⎜⎞
⎠
⎟
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3(IMAX). The maximum
∆IL occurs at VIN = 1/2VOUT.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease. Once the value of L is known, an
inductor with low DCR and low core losses should be
selected.
LTC3787
18
3787fc
APPLICATIONS INFORMATION
Power MOSFET Selection
Two external power MOSFETs must be selected for each
controller in the LTC3787: one N-channel MOSFET for the
bottom (main) switch, and one N-channel MOSFET for the
top (synchronous) switch.
The peak-to-peak gate drive levels are set by the INTVCC
voltage. This voltage is typically 5.4V during start-up
(see EXTVCC pin connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
Pay close attention to the BVDSS specification for the
MOSFETs as well; many of the logic level MOSFETs are
limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturer’s data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result
is then multiplied by the ratio of the application applied
VDS to the gate charge curve specified VDS. When the IC
is operating in continuous mode, the duty cycles for the
top and bottom MOSFETs are given by:
Main Switch Duty Cycle =VOUT −VIN
VOUT
Synchronous Switch Duty Cycle =VIN
VOUT
If the maximum output current is IOUT(MAX) and each chan-
nel takes one half of the total output current, the MOSFET
power dissipations in each channel at maximum output
current are given by:
PMAIN =(VOUT −VIN )VOUT
V2IN
•IOUT(MAX)
2
⎛
⎝
⎜⎞
⎠
⎟
2
•1+δ
()
•R
DS(ON) +k•V
3OUT •IOUT(MAX)
2•V
IN
•C
MILLER •f
PSYNC =VIN
VOUT
•IOUT(MAX)
2
⎛
⎝
⎜⎞
⎠
⎟
2
•1+δ
()
•RDS(ON)
where δ is the temperature dependency of RDS(ON) (ap-
proximately 1) is the effective driver resistance at the
MOSFET’s Miller threshold voltage. The constant k, which
accounts for the loss caused by reverse recovery current,
is inversely proportional to the gate drive current and has
an empirical value of 1.7.
Both MOSFETs have I2R losses while the bottom N-channel
equation includes an additional term for transition losses,
which are highest at low input voltages. For high VIN the
high current efficiency generally improves with larger
MOSFETs, while for low VIN the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the bottom switch duty factor is low or dur-
ing overvoltage when the synchronous switch is on close
to 100% of the period.
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
LTC3787
19
3787fc
APPLICATIONS INFORMATION
CIN and COUT Selection
The input ripple current in a boost converter is relatively
low (compared with the output ripple current), because this
current is continuous. The input capacitor CIN voltage rating
should comfortably exceed the maximum input voltage.
Although ceramic capacitors can be relatively tolerant of
overvoltage conditions, aluminum electrolytic capacitors
are not. Be sure to characterize the input voltage for any
possible overvoltage transients that could apply excess
stress to the input capacitors.
The value of CIN is a function of the source impedance, and
in general, the higher the source impedance, the higher the
required input capacitance. The required amount of input
capacitance is also greatly affected by the duty cycle. High
output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.
In a boost converter, the output has a discontinuous current,
so COUT must be capable of reducing the output voltage
ripple. The effects of ESR (equivalent series resistance) and
the bulk capacitance must be considered when choosing
the right capacitor for a given output ripple voltage. The
steady ripple voltage due to charging and discharging
the bulk capacitance in a single phase boost converter
is given by:
VRIPPLE =IOUT(MAX) •(V
OUT −VIN(MIN))
COUT •V
OUT •f V
where COUT is the output filter capacitor.
The steady ripple due to the voltage drop across the ESR
is given by:
∆VESR = IL(MAX) • ESR
The LTC3787 is configured as a 2-phase single output
converter where the outputs of the two channels are
connected together and both channels have the same
duty cycle. With 2-phase operation, the two channels
are operated 180 degrees out-of-phase. This effectively
interleaves the output capacitor current pulses, greatly
reducing the output capacitor ripple current. As a result,
the ESR requirement of the capacitor can be relaxed.
Because the ripple current in the output capacitor is a
square wave, the ripple current requirements for the output
capacitor depend on the duty cycle, the number of phases
and the maximum output current. Figure 3 illustrates the
normalized output capacitor ripple current as a function of
duty cycle in a 2-phase configuration. To choose a ripple
current rating for the output capacitor, first establish the
duty cycle range based on the output voltage and range
of input voltage. Referring to Figure 3, choose the worst-
case high normalized ripple current as a percentage of the
maximum load current.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings (e.g., OS-CON and POSCAP).
Figure 3. Normalized Output Capacitor Ripple
Current (RMS) for a Boost Converter
0.1
IORIPPLE /IOUT
0.9
3787 F03
0.3 0.5 0.7 0.8
0.2 0.4 0.6
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
DUTY CYCLE OR (1-VIN /VOUT)
1-PHASE
2-PHASE
PolyPhase Operation
For output loads that demand high current, multiple
LTC3787s can be cascaded to run out-of-phase to provide
more output current and at the same time to reduce input
and output voltage ripple. The PLLIN/MODE pin allows the
LTC3787 to synchronize to the CLKOUT signal of another
LTC3787. The CLKOUT signal can be connected to the
PLLIN/MODE pin of the following LTC3787 stage to line
up both the frequency and the phase of the entire system.
LTC3787
20
3787fc
APPLICATIONS INFORMATION
Tying the PHASMD pin to INTVCC, SGND or floating
generates a phase difference (between PLLIN/MODE
and CLKOUT) of 240°, 60° or 90°, respectively, and a
phase difference (between CH1 and CH2) of 120°, 180°
or 180°. Figure 4 shows the connections necessary for
3-, 4-, 6- or 12-phase operation. A total of 12 phases can
be cascaded to run simultaneously out-of-phase with
respect to each other.
Figure 4. PolyPhase Operation
VOUT
SS
CLKOUT
0,180
(4d) 12-Phase Operation
(4c) 6-Phase Operation
(4b) 4-Phase Operation
3787 F04
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
+60 +60
+60 +60
+90
SS
CLKOUT
60,240
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
SS
CLKOUT
120,300
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
SS
CLKOUT
210,30
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
+60 +60
SS
CLKOUT
270,90
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
SS
CLKOUT
330,150
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
VOUT
SS
CLKOUT
0,180
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
SS
CLKOUT
60,240
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
SS
CLKOUT
120,300
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
+90
VOUT
SS
CLKOUT
0,180
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
SS
CLKOUT
90,270
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
(4a) 3-Phase Operation
+120
VOUT
INTVCC
SS
CLKOUT
0,240
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
SS
CLKOUT
120, CHANNEL 2 NOT USED
PLLIN/MODE
PHASMD
LTC3787
VFB ITH
RUN
LTC3787
21
3787fc
APPLICATIONS INFORMATION
Setting Output Voltage
The LTC3787 output voltage is set by an external feedback
resistor divider carefully placed across the output, as shown
in Figure 5. The regulated output voltage is determined by:
VOUT =1.2V 1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
Great care should be taken to route the VFB line away
from noise sources, such as the inductor or the SW line.
Also keep the VFB node as small as possible to avoid
noise pickup.
INTVCC Regulators
The LTC3787 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power at
the INTVCC pin from either the VBIAS supply pin or the
EXTVCC pin depending on the connection of the EXTVCC
pin. INTVCC powers the gate drivers and much of the
LTC3787’s internal circuitry. The VBIAS LDO and the
EXTVCC LDO regulate INTVCC to 5.4V. Each of these can
supply at least 50mA and must be bypassed to ground with
a minimum of 4.7F ceramic capacitor. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3787 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the VBIAS
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
pin is less than 4.8V, the VBIAS LDO is enabled. In this
case, power dissipation for the IC is highest and is equal
to VBIAS • IINTVCC. The gate charge current is dependent
on operating frequency, as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
Electrical Characteristics. For example, at 70°C ambient
temperature, the LTC3787 INTVCC current is limited to less
than 32mA in the QFN package from a 40V VBIAS supply
when not using the EXTVCC supply:
T
J = 70°C + (32mA)(40V)(43°C/W) = 125°C
In an SSOP package, the INTVCC current is limited to
less than 15mA from a 40V supply when not using the
EXTVCC supply:
T
J = 70°C + (15mA)(40V)(90°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
= INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above 4.8V, the
VIN LDO is turned off and the EXTVCC LDO is enabled. The
EXTVCC LDO remains on as long as the voltage applied to
Figure 6. Using the SS Pin to Program Soft-Start
LTC3787
SS
CSS
SGND
3787 F06
Soft-Start (SS Pin)
The start-up of VOUT is controlled by the voltage on the
SS pin. When the voltage on the SS pin is less than the
internal 1.2V reference, the LTC3787 regulates the VFB
pin voltage to the voltage on the SS pin instead of 1.2V.
Soft-start is enabled by simply connecting a capacitor from
the SS pin to ground, as shown in Figure 6. An internal
10A current source charges the capacitor, providing a
linear ramping voltage at the SS pin. The LTC3787 will
regulate the VFB pin (and hence, VOUT) according to the
voltage on the SS pin, allowing VOUT to rise smoothly
from VIN to its final regulated value. The total soft-start
time will be approximately:
tSS =CSS •1.2V
10µA
Figure 5. Setting Output Voltage
LTC3787
VFB
VOUT
RB
RA
3787 F05
LTC3787
22
3787fc
APPLICATIONS INFORMATION
EXTVCC remains above 4.55V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 5.4V, so while EXTVCC
is less than 5.4V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 5.4V, up to an absolute maximum of 6V,
INTVCC is regulated to 5.4V.
Significant thermal gains can be realized by powering
INTVCC from an external supply. Tying the EXTVCC pin
to a 5V supply reduces the junction temperature in the
previous example from 125°C to 79°C in a QFN package:
T
J = 70°C + (32mA)(5V)(43°C/W) = 77°C
and from 125°C to 74°C in an SSOP package:
T
J = 70°C + (15mA)(5V)(90°C/W) = 77°C
If more current is required through the EXTVCC LDO than
is specified, an external Schottky diode can be added be-
tween the EXTVCC and INTVCC pins. Make sure that in all
cases EXTVCC ≤ VBIAS (even at start-up and shutdown).
The following list summarizes possible connections for
EXTVCC:
EXTVCC Grounded. This will cause INTVCC to be powered
from the internal 5.4V regulator resulting in an efficiency
penalty at high input voltages.
EXTVCC Connected to an External Supply. If an external
supply is available in the 5V to 6V range, it may be used
to provide power. Ensure that EXTVCC is always lower
than VBIAS.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside
MOSFETs. Capacitor CB in the Block Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When one of the topside MOSFETs is to be turned
on, the driver places the CB voltage across the gate and
source of the desired MOSFET. This enhances the MOSFET
and turns on the topside switch. The switch node volt-
age, SW, rises to VOUT and the BOOST pin follows. With
the topside MOSFET on, the boost voltage is above the
output voltage: VBOOST = VOUT + VINTVCC. The value of
the boost capacitor CB needs to be 100 times that of the
total input capacitance of the topside MOSFET(s). The
reverse breakdown of the external Schottky diode must
be greater than VOUT(MAX).
The external diode DB can be a Schottky diode or silicon
diode, but in either case it should have low leakage and fast
recovery. Pay close attention to the reverse leakage at high
temperatures where it generally increases substantially.
Each of the topside MOSFET drivers includes an internal
charge pump that delivers current to the bootstrap capaci-
tor from the BOOST pin. This charge current maintains
the bias voltage required to keep the top MOSFET on
continuously during dropout/overvoltage conditions. The
Schottky/silicon diodes selected for the topside drivers
should have a reverse leakage less than the available output
current the charge pump can supply. Curves displaying
the available charge pump current under different operat-
ing conditions can be found in the Typical Performance
Characteristics section.
A leaky diode DB in the boost converter can not only
prevent the top MOSFET from fully turning on but it can
also completely discharge the bootstrap capacitor CB and
create a current path from the input voltage to the BOOST
pin to INTVCC. This can cause INTVCC to rise if the diode
leakage exceeds the current consumption on INTVCC.
This is particularly a concern in Burst Mode operation
where the load on INTVCC can be very small. The external
Schottky or silicon diode should be carefully chosen such
that INTVCC never gets charged up much higher than its
normal regulation voltage.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on-chip
(such as an INTVCC short to ground), the overtemperature
shutdown circuitry will shut down the LTC3787. When the
junction temperature exceeds approximately 170°C, the
overtemperature circuitry disables the INTVCC LDO, causing
the INTVCC supply to collapse and effectively shut down
LTC3787
23
3787fc
APPLICATIONS INFORMATION
the entire LTC3787 chip. Once the junction temperature
drops back to approximately 155°C, the INTVCC LDO turns
back on. Long term overstress (TJ > 125°C) should be
avoided as it can degrade the performance or shorten
the life of the part.
Since the shutdown may occur at full load, beware that
the load current will result in high power dissipation in
the body diodes of the top MOSFETs. In this case, PGOOD
output may be used to turn the system load off.
Phase-Locked Loop and Frequency Synchronization
The LTC3787 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the bottom MOSFET of channel 1 to be locked
to the rising edge of an external clock signal applied to
the PLLIN/MODE pin. The turn-on of channel 2’s bot-
tom MOSFET is thus 180 degrees out-of-phase with the
external clock. The phase detector is an edge-sensitive
digital type that provides zero degrees phase shift between
the external and internal oscillators. This type of phase
detector does not exhibit false lock to harmonics of the
external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced continu-
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than fOSC,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP , holds the voltage at the VCO input.
Typically, the external clock (on the PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.2V.
Note that the LTC3787 can only be synchronized to an
external clock whose frequency is within range of the
LTC3787’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
Figure 7. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
FREQ PIN RESISTOR (k)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3787 F07
400
200
500
700
900
300
100
065 75 85 95 105 115 125
LTC3787
24
3787fc
APPLICATIONS INFORMATION
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2.
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTVCC DC Voltage 535kHz
Resistor DC Voltage 50kHz to 900kHz
Any of the Above External Clock Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3787 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on-
time limit.
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time,
the controller will begin to skip cycles but the output will
continue to be regulated. More cycles will be skipped when
VIN increases. Once VIN rises above VOUT, the loop keeps
the top MOSFET continuously on. The minimum on-time
for the LTC3787 is approximately 110ns.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency
can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of
the losses in LTC3787 circuits: 1) IC VBIAS current, 2)
INTVCC regulator current, 3) I2R losses, 4) bottom MOS-
FET transition losses, 5) body diode conduction losses.
1. The VBIAS current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VBIAS current typically
results in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
3. DC I2R losses. These arise from the resistances of the
MOSFETs, sensing resistor, inductor and PC board traces
and cause the efficiency to drop at high output currents.
4. Transition losses apply only to the bottom MOSFET(s),
and become significant only when operating at low
input voltages. Transition losses can be estimated from:
Transition Loss =(1.7) V3
OUT
VIN
•IOUT(MAX)
2•CRSS •f
5. Body diode conduction losses are more significant at
higher switching frequency. During the dead time, the loss
in the top MOSFETs is IOUT • VDS, where VDS is around
0.7V. At higher switching frequency, the dead time be-
comes a good percentage of switching cycle and causes
the efficiency to drop.
Other hidden losses, such as copper trace and internal
battery resistances, can account for an additional efficiency
degradation in portable systems. It is very important to
include these system-level losses during the design phase.
LTC3787
25
3787fc
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD(ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 10 circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout
is complete and the particular output capacitor type and
value have been determined. The output capacitors must
be selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1s to
10s will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET and load resistor directly across
the output capacitor and driving the gate with an ap-
propriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is
in the feedback loop and is the filtered and compensated
control loop response.
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de-
creasing CC. If RC is increased by the same factor that CC
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • CLOAD. Thus, a 10F capacitor would
require a 250s rise time, limiting the charging current
to about 200mA.
Design Example
As a design example, assume VIN = 12V (nominal),
VIN = 22V (max), VOUT = 24V, IOUT(MAX) = 8A, VSENSE(MAX) =
75mV, and f = 350kHz.
The components are designed based on single channel
operation. The inductance value is chosen first based on
a 30% ripple current assumption. Tie the PLLIN/MODE
pin to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
ΔIL=VIN
f•L 1−VIN
VOUT
⎛
⎝
⎜⎞
⎠
⎟
The largest ripple happens when VIN = 1/2VOUT = 12V,
where the average maximum inductor current for each
channel is:
IMAX =IOUT(MAX)
2
⎛
⎝
⎜⎞
⎠
⎟•VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟=8A
APPLICATIONS INFORMATION
LTC3787
26
3787fc
A 6.8H inductor will produce a 31% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
RSENSE ≤75mV
9.25A =0.008Ω
Choosing 1% resistors: RA = 5k and RB = 95.3k yields an
output voltage of 24.072V.
The power dissipation on the top side MOSFET in each chan-
nel can be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: RDS(ON) = 0.012, CMILLER = 150pF.
At maximum input voltage with T (estimated) = 50°C:
PMAIN =(24V – 12V) 24V
(12V)2•(4A)2
•1+(0.005)(50°C–25°C)
⎡
⎣⎤
⎦• 0.008Ω
+(1.7)(24V)34A
12V (150pF)(350kHz)=0.7W
COUT is chosen to filter the square current in the output.
The maximum output current peak is:
IOUT(PEAK) =8• 1+31%
2
⎛
⎝
⎜⎞
⎠
⎟=9.3A
A low ESR (5m) capacitor is suggested. This capacitor
will limit output voltage ripple to 46.5mV (assuming ESR
dominate ripple).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 8. Figure 9 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Put the bottom N-channel MOSFETs MBOT1 and MBOT2
and the top N-channel MOSFETs MTOP1 and MTOP2
in one compact area with COUT .
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
CINTVCC must return to the combined COUT (–) terminals.
The path formed by the bottom N-channel MOSFET
and the capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the source terminals
of the bottom MOSFETs.
3. Does the LTC3787 VFB pin’s resistive divider connect to
the (+) terminal of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground and placed close to the VFB pin. The feedback
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
4. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1F ceramic capacitor placed
immediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2) and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and, therefore, should be kept on
the output side of the LTC3787 and occupy a minimal
PC trace area.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
APPLICATIONS INFORMATION
LTC3787
27
3787fc
Figure 8. Recommended Printed Circuit Layout Diagram
Figure 9. Branch Current Waveforms
L1
SW1
RSENSE1
VIN
CIN
RIN
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
SW2
3787 F09
RL
VOUT
L2
RSENSE2
COUT
APPLICATIONS INFORMATION
SENSE1+
SENSE1–
SENSE2+
SENSE2–
VFB
ITH
SGND
EXTVCC
RUN
FREQ
SS
PLLIN/MODE
PGOOD
TG1
SW1
BOOST1
BG1
VBIAS
INTVCC
PGND
BG2
TG2
BOOST2
SW2
CB1
CB2
VIN
VOUT
LTC3787
L2
L1
M2
M3
3787 F08
VPULL-UP RSENSE1
RSENSE2
M1
M4
GND
ILIM
PHSMD
CLKOUT
+
fIN
+
+
LTC3787
28
3787fc
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over the
input voltage range down to dropout and until the output
load drops below the low current operation threshold—
typically 10% of the maximum designed current level in
Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both controllers be turned on at the same time. A particu-
larly difficult region of operation is when one controller
channel is nearing its current comparator trip point while
the other channel is turning on its bottom MOSFET. This
occurs around the 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
Reduce VIN from its nominal level to verify operation with
high duty cycle. Check the operation of the undervoltage
lockout circuit by further lowering VIN while monitoring
the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling.
An embarrassing problem which can be missed in an oth-
erwise properly working switching regulator, results when
the current sensing leads are hooked up backwards. The
output voltage under this improper hook-up will still be
maintained, but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
APPLICATIONS INFORMATION
LTC3787
29
3787fc
TYPICAL APPLICATIONS
MBOT2
MTOP2
SENSE1+
SENSE1–
SENSE2+
SENSE2–
VFB
ITH
SGND
EXTVCC
RUN
FREQ
SS
PLLIN/MODE
PGOOD
TG1
SW1
BOOST1
BG1
VBIAS
INTVCC
PGND
BG2
TG2
BOOST2
SW2
CB1, 0.1µF
COUTA1
22µF
s 4
CB2, 0.1µF
CINT
4.7µF
RB
232k
LTC3787
L2
3.3µH
L1
3.3µH
MTOP1
MBOT1
100k
3787 F10
INTVCC RSENSE1
4m
CSS, 0.1µF
RA, 12.1k
CITHA, 220pF
RITH, 8.66k
CITH, 15nF
RSENSE2
4m
D1
D2
ILIM
PHASMD
CLKOUT
+COUTB1
220µF
COUTA2
22µF
s 4
+COUTB2
220µF
CIN
22µF
s 2
VIN
5V TO 24V
VOUT
24V, 10A*
CIN, COUTA1, COUTA2: TDK C4532X5R1E226M
COUTB1, COUTB2: SANYO, 50CE220LX
L1, L2: PULSE PA1494.362NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H
D1, D2: BAS140W
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
Figure 10. High Efficiency 2-Phase 24V Boost Converter
Figure 11. High Efficiency 2-Phase 28V Boost Converter
MBOT2
MTOP2
SENSE1+
SENSE1–
SENSE2+
SENSE2–
VFB
ITH
SGND
EXTVCC
RUN
FREQ
SS
PLLIN/MODE
PGOOD
TG1
SW1
BOOST1
BG1
VBIAS
INTVCC
PGND
BG2
TG2
BOOST2
SW2
CB1, 0.1µF
COUTA1
6.8µF
× 4
CB2, 0.1µF
CINT
4.7µF
RB
271k
LTC3787
L2
3.3µH
L1
3.3µH
MTOP1
MBOT1
100k
3787 F11
INTVCC RSENSE1
4m
CSS, 0.1µF
RA, 12.1k
CITHA, 220pF
RITH, 8.66k
CITH, 15nF
RSENSE2
4m
D1
D2
ILIM
PHASMD
CLKOUT
+COUTB1
220µF
COUTA2
6.8µF
× 4
+COUTB2
220µF
CIN
6.8µF
× 4
VIN
5V TO 28V
VOUT
28V, 8A
CIN, COUTA1, COUTA2: TDK C4532X7RIH685K
COUTB1, COUTB2: SANYO, 50CE220LX
L1, L2: PULSE PA1494.362NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H
D1, D2: BAS140W
LTC3787
30
3787fc
TYPICAL APPLICATIONS
Figure 12. High Efficiency 2-Phase 36V Boost Converter
MBOT2
MTOP2
SENSE1+
SENSE1–
SENSE2+
SENSE2–
VFB
ITH
SGND
EXTVCC
RUN
FREQ
SS
PLLIN/MODE
PGOOD
TG1
SW1
BOOST1
BG1
VBIAS
INTVCC
PGND
BG2
TG2
BOOST2
SW2
CB1, 0.1µF
COUTA1
6.8µF
× 4
CB2, 0.1µF
CINT
4.7µF
RB
348k
LTC3787
L2
10.2µH
L1
10.2µH
MTOP1
MBOT1
100k
3787 F12
INTVCC RSENSE1
5m
CSS, 0.1µF
RA, 12.1k
CITHA, 220pF
RITH, 3.57k
CITH, 15nF
RSENSE2
5m
D1
D2
ILIM
PHASMD
CLKOUT
+COUTB1
220µF
COUTA2
6.8µF
× 4
+COUTB2
220µF
CIN
6.8µF
× 4
VIN
5V TO 36V
VOUT
36V, 6A
CIN, COUTA1, COUTA2: TDK C4532X7RIH685K
COUTB1, COUTB2: SANYO, 50CE220LX
L1, L2: PULSE PA2050.103NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJICO652DPB
D1, D2: BAS170W
Figure 13. High Efficiency 2-Phase 48V Boost Converter
MBOT2
MTOP2
SENSE1+
SENSE1–
SENSE2+
SENSE2–
VFB
ITH
SGND
EXTVCC
RUN
FREQ
SS
PLLIN/MODE
PGOOD
TG1
SW1
BOOST1
BG1
VBIAS
INTVCC
PGND
BG2
TG2
BOOST2
SW2
CB1, 0.1µF
COUTA1
6.8µF
× 4
CB2, 0.1µF
CINT
4.7µF
RB
475k
LTC3787
L2
16µH
L1
16µH
MTOP1
MBOT1
100k
3787 F13
INTVCC RSENSE1
8m
CSS, 0.1µF
RA, 12.1k
CITHA, 220pF
RITH, 23.7k
CITH, 10nF
RSENSE2
8m
D1
D2
ILIM
PHASMD
CLKOUT
+COUTB1
220µF
COUTA2
6.8µF
× 4
+COUTB2
220µF
CIN
6.8µF
× 4
VIN
5V TO 38V
VOUT
48V, 4A
CIN, COUTA1, COUTA2: TDK C4532X7RIH685K
COUTB1, COUTB2: SANYO, 63CE220K
L1, L2: PULSE PA2050.163NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJK0652DPB
D1, D2: BAS170W
LTC3787
31
3787fc
Figure 14. High Efficiency 2-Phase 24V Boost Converter with Inductor DCR Current Sensing
TYPICAL APPLICATIONS
MBOT2
MTOP2
SENSE1+
SENSE1–
SENSE2–
SENSE2+
VFB
ITH
SGND
EXTVCC
RUN
FREQ
SS
PLLIN/MODE
PGOOD
TG1
SW1
BOOST1
BG1
VBIAS
INTVCC
PGND
BG2
TG2
BOOST2
SW2
CB1, 0.1µF
COUTA1
6.8µF
s 4
RS2
26.1k
1%
CB2, 0.1µF
CINT
4.7µF
RS
232k
1%
LTC3787
L2
10.2µH
L1
10.2µH
MTOP1
MBOT1
100k
3787 F14
INTVCC
INTVCC
CSS, 0.1µF
RA
12.1k, 1%
CITHA, 220pF
RITH, 8.87k, 1%
CITH, 15nF
D1
D3
D2
RFREQ, 41.2k
RS1, 53.6, 1%
ILIM
PHASMD
CLKOUT
+COUTB1
220µF
C2
0.1µF
COUTA2
6.8µF
s 4
+COUTB2
220µF
CINA
22µF
s 4
VIN
5V TO 24V VOUT
24V, 8A
C4
0.1µF
C3
0.1µF
C1
0.1µF
+CINB
220µF
COUTA1, COUTA2: C4532x7R1H685K
COUTB1, COUTB2: SANYO 63CE220KX
CINA: TDK C4532X5R1E226M
CINB: SANYO 50CE220AX
L1, L2: PULSE PA2050.103NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJK0305
D1, D2: BAS140W
D3, D4: DIODES INC. B340B
D4
RS4
26.1k
1%
RS3, 53.6k, 1%
LTC3787
32
3787fc
Figure 15. 4-Phase Single Output Boost Converter
TYPICAL APPLICATIONS
MBOT2
MTOP2
SENSE2+
SENSE2–
SENSE1–
SENSE1+
VFB
ITH
SGND
EXTVCC
INTVCC
RUN
FREQ
SS
PLLIN/MODE
PGOOD
TG1
SW1
BOOST1
BG1
VBIAS
INTVCC
PGND
BG2
TG2
BOOST2
SW2
CB1, 0.1µF
COUTA1
22µF
s 4
CB2, 0.1µF
CINT1
4.7µF
RB
232k
LTC3787
L2
3.3µH
L1
3.3µH
MTOP1
MBOT1
100k
INTVCC RSENSE1
4m
CSS, 0.1µF
RA, 12.1k
CITHA, 220pF
RITH, 8.66k
CITH, 15nF
RSENSE2
4m
D1
D2
ILIM
PHASMD
CLKOUT
+COUTB1
220µF
VOUT
24V, 20A*
VIN
5V to 24V
COUTA2
22µF
s 4
+COUTB2
220µF
CINA
22µF
s 4
+CINB
220µF
MBOT4
MTOP4
SENSE2+
SENSE2–
SENSE1–
SENSE1+
VFB
ITH
SGND
EXTVCC
RUN
FREQ
SS
PLLIN/MODE
PGOOD
TG1
SW1
BOOST1
BG1
VBIAS
INTVCC
PGND
BG2
TG2
BOOST2
SW2
CB3, 0.1µF
COUTA3
22µF
s 4
CB4, 0.1µF
CINT2
4.7µF
LTC3787
L4
3.3µH
L3
3.3µH
MTOP3
MBOT3
100k
INTVCC RSENSE3
4m
RSENSE4
4m
D3
D4
ILIM
PHASMD
CLKOUT
+COUTB3
220µF
COUTA4
22µF
s 4
+COUTB4
220µF
3787 F15
CINA, COUTA1, COUTA2, COUTA3, COUTA4: TDK C4532X5R1E226M
CINB, COUTB1, COUTB2, COUTB3, COUTB4: SANYO, 50CE220LX
L1, L2, L3, L4: PULSE PA1494.362NL
MBOT1, MBOT2, MBOT3, MBOT4, MTOP1, MTOP2, MTOP3, MTOP4: RENESAS HAT2169H
D1, D2, D3, D4: BAS140W
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
LTC3787
33
3787fc
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
.386 – .393*
(9.804 – 9.982)
GN28 REV B 0212
12
345678 9 10 11 12
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
202122232425262728 19 18 17
13 14
1615
.016 – .050
(0.406 – 1.270)
.015 ±.004
(0.38 ±0.10) w 45°
0° – 8° TYP
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.033
(0.838)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
LTC3787
34
3787fc
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
4.00 ± 0.10
(2 SIDES)
2.50 REF
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ± 0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0506 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
2.65 ± 0.05
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
2.65 ± 0.10
3.65 ± 0.10
3.65 ± 0.05
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3787
35
3787fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/10 Updated PGND, BG2, BG1, INTVCC and EXTVCC Pin numbers
Updated Block Diagram
Updated Figures 11, 12, 13
Updated Related Parts
10
11
29, 30
36
B 9/11 Updated graphs on TA01b, G02, G09, G10, G11, G13, G14, G15, G18, G19, G22, and G26.
Updated the Storage Temperature Range
Updated Topside MOSFET Driver Supply (CB, DB) section
Updated Related Parts List
1, 5, 6, 7, 8, 9
2
22
36
C 4/12 Added H and MP grades 2, 4
LTC3787
36
3787fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
LT 0412 REV C • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC3788/LTC3788-1 Multiphase, Dual Output Synchronous Step-Up
Controller
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to
900kHz Fixed Operating Frequency, 5mm × 5mm QFN-32, SSOP-28
LTC3786 Low IQ Synchronous Step-Up Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to
900kHz Fixed Operating Frequency, 3mm × 3mm QFN-32, MSOP-16E
LTC3862/LTC3862-1 Multiphase, Dual Channel Single Output Current
Mode Step-Up DC/DC Controller
4V ≤ VIN ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed Operating
Frequency, SSOP-24, TSSOP-24, 5mm × 5mm QFN-24
LT3757/LT3758 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V/100V, 100kHz to 1MHz Fixed Operating Frequency,
3mm × 3mm DFN-10 and MSOP-10E
LTC1871/LTC1871-1/
LTC1871-7
Wide Input Range, No RSENSE Low Quiescent Current
Flyback, Boost and SEPIC Controller
2.5V ≤ VIN ≤ 36V, 50kHz to 1MHz Fixed Operating Frequency, IQ = 250µA ,
MSOP-10
LTC3859 Low IQ, Triple Output Buck/Buck/Boost Synchronous
DC/DC Controller
All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to
2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST)
Up to 60V, IQ = 55µA
LTC3789 High Efficiency Synchronous 4-Switch Buck-Boost
DC/DC Controller
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, 4mm × 5mm QFN-28 and SSOP-2
Figure 16. PolyPhase Application
TG1
BG1 0°
I1
I1
I2
I3
I4
BOOST: 24V, 5A
REFER TO FIGURE 15 FOR APPLICATION CIRCUITS * RIPPLE CURRENT CANCELLATION INCREASES THE RIPPLE
FREQUENCY AND REDUCES THE RMS INPUT/OUTPUT RIPPLE
CURRENT, THUS SAVING INPUT/OUTPUT CAPACITORS
3787 F16
PHASMD
LTC3787
CLKOUT
CIN
12V
24V, 20A
TG2
BG2 180°
I2
BOOST: 24V, 5A
TG1
BG1 90°
90,270
+90° I3
BOOST: 24V, 5A
PHASMD
LTC3787
CLKOUT
TG2
BG2 270°
I4
BOOST: 24V, 5A
COUT ICOUT
IIN
I*IN
I*COUT