TDA9898HN/V3,557 - NXP Semiconductors

1. General description

The Integrated Circuit (IC) is suitable for Intermediate Frequency (IF) processing including

global multistandard Analog TV (ATV), Digital Video Broadcast (DVB) and mono FM radio

using only 1 IC and 1 to 3 ﬁxed Surface Acoustic Waves (SAWs) (application dependent).

TDA9898 includes, TDA9897 excludes L and L-accent standard.

2. Features

2.1 General

n5 V supply voltage

nI2C-bus control over all functions

nFour I2C-bus addresses provided; selection by programmable Module Address (MAD)

nThree I2C-bus voltage level supported; selection via pin BVS

nSeparate gain controlled ampliﬁers with input selector and conversion for incoming IF

[analog Vision IF (VIF) or Sound IF (SIF) or Digital TV (DTV)] allows the use of

different ﬁlter shapes and bandwidths

nAll conventional ATV standards applicable by using DTV bandwidth window (SAW)

ﬁlter

nTwo 4 MHz reference frequency stages; the ﬁrst one operates as crystal oscillator, the

second one as external signal input

nStabilizer circuit for ripple rejection and to achieve constant output signals

nSmallest size, simplest application

nElectroStatic Discharge (ESD) protection for all pins

2.2 Analog TV processing

nGain controlled wideband VIF ampliﬁer; AC-coupled

nMultistandard true synchronous demodulation with active carrier regeneration: very

linear demodulation, good intermodulation ﬁgures, reduced harmonics and excellent

pulse response

nIntegrated Nyquist processing, providing additionally image suppression for high

adjacent channel selectivity

nOptional use of conventional Nyquist ﬁlter to support a wide range of applications

nGated phase detector for L and L-accent standards

nFully integrated VIF Voltage-Controlled Oscillator (VCO), alignment-free, frequencies

switchable for all negative and positive modulated standards via I2C-bus

nVIF Automatic Gain Control (AGC) detector for gain control; operating as a peak sync

detector for negative modulated signals and as a peak white detector for positive

modulated signals

TDA9897; TDA9898

Multistandard hybrid IF processing

Rev. 04 — 25 May 2009 Product data sheet

Product data sheet Rev. 04 — 25 May 2009 2 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

nOptimized AGC modes for negative modulation; e.g. very fast reaction time for VIF and

SIF

nPrecise fully digital Automatic Frequency Control (AFC) detector with 4-bit

Digital-to-Analog Converter (DAC); AFC bits can be read-out via I2C-bus

nHigh precise Tuner AGC (TAGC) TakeOver Point (TOP) for negative modulated

standards; TOP adjust via I2C-bus

nTAGC TOP for positive standards and Received Signal Strength Indication (RSSI);

adjustable via I2C-bus or alternatively by potentiometer

nFully integrated Sound Carrier (SC) trap for any ATV standard (SC at 4.5 MHz,

5.5 MHz, 6.0 MHz and 6.5 MHz)

nSIF AGC for gain controlled SIF ampliﬁer and high-performance single-reference

Quasi Split Sound (QSS) mixer

nFully integrated sound BP ﬁlter supporting any ATV standard

nOptional use of external FM or AM sound BP ﬁlter

nAM sound demodulation for L and L-accent standard

nAlignment-free selective FM Phase-Locked Loop (PLL) demodulator with high linearity

and low noise; external FM input

nPort function

nVIF AGC voltage monitor output or port function

nTAGC voltage monitor output or port function

nVIF AFC current or tuner, VIF, SIF or FM AGC voltage monitor output

n2nd SIF output, gain controlled by internal SIF AGC or by internal FM carrier AGC for

Digital Signal Processor (DSP)

nFully integrated BP ﬁlter for 2nd SIF at 4.5 MHz, 5.5 MHz, 6.0 MHz or 6.5 MHz

2.3 Digital TV processing

nApplicable for terrestrial and cable TV reception

n70 dB variable gain wideband IF ampliﬁer (AC-coupled)

nGain control via external control voltage (0 V to 3 V)

n2 V (p-p) differential low IF (downconverted) output or 1 V (p-p) 1st IF output for direct

Analog-to-Digital Converter (ADC) interfacing

nDVB downconversion with integrated selectivity for Low IF (LIF)

nIntegrated anti-aliasing tracking low-pass ﬁlter

nFully integrated synthesizer controlled oscillator with excellent phase noise

performance

nSynthesizer frequencies for a wide range of world wide DVB standards (for IF center

frequencies of e.g. 34.5 MHz, 36 MHz, 44 MHz and 57 MHz)

nTAGC detector for independent tuner gain control loop applications

nTAGC operating as peak detector, fast reaction time due to additional speed-up

detector

nPort function

nTAGC voltage monitor output

Product data sheet Rev. 04 — 25 May 2009 3 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

2.4 FM radio mode

nGain controlled wideband Radio IF (RIF) ampliﬁer; AC-coupled

nBuffered RIF ampliﬁer wideband output, gain controlled by internal RIF AGC

nUse of external FM sound BP ﬁlter

n2nd RIF output, gain controlled by internal RIF AGC or by internal FM carrier AGC for

DSP

nAlignment-free selective FM PLL demodulator with high linearity and low noise

nPrecise fully digital AFC detector with 4-bit DAC; AFC bits read-out via I2C-bus

nPort function

nRadio AFC or tuner, RIF or FM AGC voltage monitor output

3. Applications

nAnalog and digital TV front-end applications for TV sets, recording applications and

personal computer cards

4. Quick reference data

Table 1. Quick reference data

=5V; T

amb

=25

Symbol Parameter Conditions Min Typ Max Unit

VPsupply voltage [1] 4.5 5.0 5.5 V

IPsupply current ATV QSS; B/G standard;

sound carrier trap on;

sound BP on

- - 175 mA

Analog TV signal processing

Video part

Vi(IF)(RMS) RMS IF input voltage lower limit at −1 dB video

output signal - 60 100 µV

GVIF(cr) control range VIF gain 60 66 - dB

fVIF VIF frequency see Table 24 ---MHz

∆fVIF(dah) digital acquisition help VIF

frequency window related to fVIF

all standards except M/N - ±2.3 - MHz

M/N standard - ±1.8 - MHz

Vo(video)(p-p) peak-to-peak video output voltage positive or negative

modulation; normal mode

and sound carrier on;

W6[1] = 0; W4[7] = 0;

W7[4] = 0; see Figure 10

1.7 2.0 2.3 V

Gdif differential gain

“ITU-T J.63 line 330”

[2][3]

B/G standard - - 5 %

L standard - - 7 %

ϕdif differential phase

“ITU-T J.63 line 330”

[2][3]

B/G standard - 2 4 deg

L standard - 2 4 deg

Product data sheet Rev. 04 — 25 May 2009 4 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Bvideo(−3dB) −3 dB video bandwidth trap bypass mode and

sound carrier off; AC load:

CL<20pF, R

L>1kΩ

[4] 68- MHz

αSC1 ﬁrst sound carrier attenuation M/N standard;

f=f

SC1 = 4.5 MHz;

see Figure 21

[4] 38--dB

B/G standard;

f=f

SC1 = 5.5 MHz;

see Figure 23

[4] 35--dB

(S/N)wweighted signal-to-noise ratio normal mode and sound

carrier on; B/G standard;

50 % grey video signal;

uniﬁed weighting ﬁlter

(

“ITU-T J.61”

);

see Figure 20

[2][5] 53 57 - dB

PSRRCVBS power supply ripple rejection on

pin CVBS normal mode and sound

carrier on; fripple =70Hz;

video signal; grey level;

positive and negative

modulation; see Figure 11

[2] 14 20 - dB

∆IAFC/∆fVIF change of AFC current with VIF

frequency AFC TV mode [6] 0.85 1.05 1.25 µA/kHz

Audio part

Vo(AF)(RMS) RMS AF output voltage FM: QSS mode;

27 kHz FM deviation;

50 µs de-emphasis

430 540 650 mV

AM: 54 % modulation 400 500 600 mV

THD total harmonic distortion FM: 50 µs de-emphasis;

FM deviation: for TV mode

27 kHz and for radio mode

22.5 kHz

- 0.15 0.50 %

AM: 54 % modulation;

BP on; see Figure 33 - 0.5 1.0 %

f−3dB(AF) AF cut-off frequency W3[2] = 0; W3[4] = 0;

without de-emphasis;

FM window

width = 237.5 kHz

80 100 - kHz

(S/N)w(AF) AF weighted signal-to-noise ratio

“ITU-R BS.468-4”

FM: 27 kHz FM deviation;

50 µs de-emphasis; vision

carrier unmodulated;

FM PLL only

48 56 - dB

AM: BP off 44 50 - dB

PSRR power supply ripple rejection fripple = 70 Hz; see Figure 11 14 20 - dB

Table 1. Quick reference data

…continued

=5V; T

amb

=25

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 5 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Vo(RMS) RMS output voltage IF intercarrier single-ended

to GND; see Figure 9 and

Table 21

B/G standard;

SC1 on; SC2 off;

internal BP via FM AGC

90 140 180 mV

L standard; without

modulation; W7[5] = 0;

internal BP + 6 dB

90 140 180 mV

FM sound part

Vi(FM)(RMS) RMS FM input voltage gain controlled operation;

W1[1:0] = 10 or

W1[1:0] = 11 or

W1[1:0] = 01; see Figure 9

2 - 300 mV

∆IAFC/∆fRIF change of AFC current with RIF

frequency AFC radio mode [6] 0.85 1.05 1.25 µA/kHz

αAM AM suppression referenced to 27 kHz

FM deviation;

50 µs de-emphasis;

AM: f = 1 kHz; m = 54 %

35 46 - dB

Digital TV signal processing

Digital direct IF

Vo(dif)(p-p) peak-to-peak differential output

voltage between pin OUT2A and

pin OUT2B [7]

W4[7] = 0 - 1.0 1.1 V

W4[7] = 1 - 0.50 0.55 V

GIF(max) maximum IF gain output peak-to-peak level to

input RMS level ratio [8] -83-dB

GIF(cr) control range IF gain [8] 60 66 - dB

PSRR power supply ripple rejection residual spurious at nominal

differential output voltage

dependent on power supply

ripple

[8]

fripple =70Hz - 60 - dB

fripple = 20 kHz - 60 - dB

Digital low IF

Vo(dif)(p-p) peak-to-peak differential output

voltage between pin OUT1A and

pin OUT1B; W4[7] = 0 [7] -2-V

GIF(max) maximum IF gain output peak-to-peak level to

input RMS level ratio [8] -89-dB

GIF(cr) control range IF gain [8] 60 66 - dB

fsynth synthesizer frequency see Table 34 and Table 35 ---MHz

Table 1. Quick reference data

…continued

=5V; T

amb

=25

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 6 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] Values of video and sound parameters can be decreased at VP= 4.5 V.

[2] AC load; CL< 20 pF and RL>1kΩ. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound

carrier traps.

[3] Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps.

[4] The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 23. In this way the full composite video

spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p).

[5] Measurement using 200 kHz high-pass ﬁlter, 5 MHz low-pass ﬁlter and subcarrier notch ﬁlter (

“ITU-T J.64”

[6] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The

AFC steepness can be changed by resistors R1 and R2.

[7] With single-ended load for fIF < 45 MHz RL≥1kΩ and CL≤5 pF to ground and for fIF = 45 MHz to 60 MHz RL=1kΩ and CL≤3 pF to

ground.

[8] This parameter is not tested during production and is only given as application information.

[9] Noise level is measured without input signal but AGC adjusted corresponding to the given input level.

[10] Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off.

[11] The tolerance of the reference frequency determines the accuracy of VIFAFC, RIFAFC, FM demodulator center frequency, maximum

FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.

ϕn(synth) synthesizer phase noise with 4 MHz crystal oscillator

reference; fsynth = 31 MHz;

fIF =36MHz

at 1 kHz [8] 89 99 - dBc/Hz

at 10 kHz [8] 89 99 - dBc/Hz

at 100 kHz [8] 98 102 - dBc/Hz

at 1.4 MHz [8] 115 119 - dBc/Hz

αripple(pb)LIF low IF pass-band ripple 6 MHz bandwidth - - 2.7 dB

7 MHz bandwidth - - 2.7 dB

8 MHz bandwidth - - 2.7 dB

αstpb stop-band attenuation 8 MHz band; f = 15.75 MHz 30 40 - dB

αimage image rejection −10 MHz to 0 MHz; BP on 30 34 - dB

C/N carrier-to-noise ratio at fo= 4.9 MHz;

Vi(IF) = 10 mV (RMS);

see Figure 37

[8][9][10] 112 118 - dBc/Hz

Reference frequency input from external source

fref reference frequency W7[7] = 0 [11] -4-MHz

Vref(RMS) RMS reference voltage W7[7] = 0; see Figure 34

and Figure 46 15 150 500 mV

Table 1. Quick reference data

…continued

=5V; T

amb

=25

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 7 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

5. Ordering information

Table 2. Ordering information

Type number Package

Name Description Version

TDA9897HL/V3 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 ×7×1.4 mm SOT313-2

TDA9897HN/V3 HVQFN48 plastic thermal enhanced very thin quad ﬂat package; no leads;

48 terminals; body 7 ×7×0.85 mm SOT619-1

TDA9898HL/V3 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 ×7×1.4 mm SOT313-2

TDA9898HN/V3 HVQFN48 plastic thermal enhanced very thin quad ﬂat package; no leads;

48 terminals; body 7 ×7×0.85 mm SOT619-1

Product data sheet Rev. 04 — 25 May 2009 8 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

6. Block diagram

Fig 1. Block diagram of TDA9898 (continued in Figure 2)

001aai732

TDA9898

I2C-BUS

SIF AGC

SYNTHESIZER

VCO

VIF PLL

ACQUISITION

HELP

PEAK

AGC

TUNER

VIF AFC

TOP2

TOP1

NYQUIST

FILTER

VIF AGC

FM peak

AGCDIN

IF3A

IF3B

SDA

IF2A

IF2B

2, 18, 37 TOP2 LFVIF LFSYN1

optional tuner

AGC TOP for

positive

modulation and

radio signal

strength detector

onset

11 13

i.c.

TAGC

CIFAGC 5

IF1A

IF1B

AM average

SCL

i.c.

SYNTHESIZER

AND VCO standard

ADRSEL

BVS

GNDD

sideband (L-accent)

LFSYN2

CTAGC

838 GDS

standard

sideband

SIDEBAND

FILTER

SOUND

CARRIER

TRAP

trap reference

GROUP

DELAY

EQUALIZER

I2C-BUS TOPPOS

AND RSSI

RSSI

DETECTOR

AND

L STANDARD

TUNER

AGC

n.c.

DECODER I2C-BUS

TOPNEG

GND

Product data sheet Rev. 04 — 25 May 2009 9 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Optional.

(2) Connect resistor if input or crystal is not used.

Fig 2. Block diagram of TDA9898 (continued from Figure 1)

001aai733

TDA9898

SIF AGC

TAGC

FM AGC

port

I2C-bus

AFC

LFFM

4 MHz FREQUENCY

REFERENCE

EXTERNAL SOUND

BAND-PASS FILTER(1)

46 39

SUPPLY

OUTPUT

SWITCH

BP on/off

SWITCH

43, 44

port

40, 41 15

GNDA EXTFILO

BAND-PASS

FILTER

DEMODULATOR

AGC

NB PLL

29 OUT2A

OUT2B

OUT1A

OUT1B

EXTFMI

MPP

PORT3

CDEEM

CAF AUD

33 CVBS

EXTFILI

4 MHz reference

input

R(2)

OPTXTALFREF

port

VIF

AGC PORT1

PORT2

VIF AGC

+3 dB

Product data sheet Rev. 04 — 25 May 2009 10 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Fig 3. Block diagram of TDA9897 (continued in Figure 4)

001aai734

TDA9897

I2C-BUS

SIF AGC

SYNTHESIZER

VCO

VIF PLL

ACQUISITION

HELP

PEAK

AGC

TUNER

VIF AFC

NYQUIST

FILTER

VIF AGC

FM peak

AGCDIN

IF3A

IF3B

SDA

IF2A

IF2B

2, 5, 18, 37 TOP2 LFVIF LFSYN1

optional tuner

AGC TOP for

positive

modulation and

radio signal

strength detector

onset

11 13

i.c.

TAGC

IF1A

IF1B

AM average

SCL

i.c.

SYNTHESIZER

AND VCO standard

ADRSEL

BVS

GNDD

sideband

LFSYN2

CTAGC

838 GDS

standard

sideband

SIDEBAND

FILTER

SOUND

CARRIER

TRAP

trap reference

GROUP

DELAY

EQUALIZER

RSSI

DETECTOR

AND

L STANDARD

TUNER

AGC

n.c.

DECODER I2C-BUS

TOPNEG

GND

TOP2

TOP1

I2C-BUS TOPPOS

AND RSSI

Product data sheet Rev. 04 — 25 May 2009 11 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Optional.

(2) Connect resistor if input or crystal is not used.

Fig 4. Block diagram of TDA9897 (continued from Figure 3)

001aai735

TDA9897

SIF AGC

TAGC

FM AGC

port

I2C-bus

AFC

LFFM

4 MHz FREQUENCY

REFERENCE

EXTERNAL SOUND

BAND-PASS FILTER(1)

46 39

SUPPLY

BP on/off

OUTPUT

SWITCH

43, 44

port

40, 41 15

+3 dB

GNDA EXTFILO

BAND-PASS

FILTER

DEMODULATOR

AGC

NB PLL

29 OUT2A

OUT2B

OUT1A

OUT1B

EXTFMI

MPP

PORT3

CDEEM

CAF AUD

33 CVBS

EXTFILI

4 MHz reference

input

R(2)

OPTXTALFREF

port

VIF

AGC PORT1

PORT2

VIF AGC

Product data sheet Rev. 04 — 25 May 2009 12 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

7. Pinning information

7.1 Pinning

(1) Not connected for TDA9897HL.

Fig 5. Pin conﬁguration for LQFP48

TDA9897HL

TDA9898HL

LFSYN2 AGCDIN

n.c. PORT2

IF3A GDS

IF3B CVBS

CIFAGC(1) BVS

IF1A AUD

IF1B OUT2B

CTAGC OUT2A

IF2A CAF

IF2B OUT1B

TOP2 OUT1A

PORT1 ADRSEL

LFVIF GND

i.c. TAGC

EXTFILO FREF

MPP i.c.

EXTFILI VP

n.c. VP

LFFM PORT3

CDEEM GNDA

EXTFMI GNDA

GNDD OPTXTAL

SDA

SCL

LFSYN1

n.c.

008aaa150

Product data sheet Rev. 04 — 25 May 2009 13 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

7.2 Pin description

(1) Not connected for TDA9897HN.

Fig 6. Pin conﬁguration for HVQFN48

008aaa151

TDA9897HN

TDA9898HN

ADRSEL

TOP2

PORT1

OUT1A

IF2B OUT1B

IF2A CAF

CTAGC OUT2A

IF1B OUT2B

IF1A AUD

CIFAGC(1) BVS

IF3B CVBS

IF3A GDS

n.c. PORT2

LFSYN2 AGCDIN

LFVIF

i.c.

EXTFILO

MPP

EXTFILI

n.c.

LFFM

CDEEM

EXTFMI

GNDD

SDA

SCL

GND

TAGC

FREF

i.c.

PORT3

GNDA

OPTXTAL

LFSYN1

n.c.

12 25

11 26

10 27

9 28

8 29

7 30

6 31

5 32

4 33

3 34

2 35

1 36

terminal 1

index area

Transparent top view

Table 3. Pin description

Symbol Pin Description

LFSYN2 1 loop ﬁlter synthesizer 2 (conversion synthesizer)

n.c. 2 not connected

IF3A 3 IF symmetrical input 3 for sound

IF3B 4

CIFAGC 5 TDA9898: IFAGC capacitor; L standard

TDA9897: not connected

IF1A 6 IF symmetrical input 1 for vision or digital

IF1B 7

CTAGC 8 TAGC capacitor

IF2A 9 IF symmetrical input 2 for vision or digital

IF2B 10

TOP2 11 TOP potentiometer for positive modulated standards and RSSI reference

PORT1 12 digital port function 1 or VIFAGC monitor output

LFVIF 13 loop ﬁlter VIF PLL

i.c. 14 internally connected; connect to ground

EXTFILO 15 output to external ﬁlter

Product data sheet Rev. 04 — 25 May 2009 14 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] Recommendation: Leave this pin open or use a capacitor to GND, as shown in the application diagrams in

Figure 47,Figure 48 and Figure 49.

MPP 16 multipurpose pin: VIF AGC or SIF AGC or FM AGC or TAGC or VIF AFC or

FM AFC monitor output

EXTFILI 17 input from external ﬁlter

n.c. 18 not connected

LFFM 19 loop ﬁlter FM PLL

CDEEM 20 de-emphasis capacitor

EXTFMI 21 external FM input

GNDD 22 digital ground

SDA 23 I2C-bus data input and output

SCL 24 I2C-bus clock input

ADRSEL 25 address select

OUT1A 26 low IF or 2nd sound intercarrier symmetrical output

OUT1B 27

CAF 28 Direct Current (DC) decoupling capacitor

OUT2A 29 1st Digital IF (DIF) symmetrical output

OUT2B 30

AUD 31 audio signal output

BVS 32 I2C-bus voltage select

CVBS 33 composite video signal output

GDS 34 additional video group delay select; leave open for default operation[1]

PORT2 35 digital port function 2

AGCDIN 36 AGC input for DIF ampliﬁer for e.g. input from channel decoder AGC

n.c. 37 not connected

LFSYN1 38 loop ﬁlter synthesizer 1 (ﬁlter control synthesizer)

OPTXTAL 39 optional quartz input

GNDA 40 analog ground

GNDA 41 analog ground

PORT3 42 digital port function 3 or TAGC monitor output

VP43 supply voltage

VP44 supply voltage

i.c. 45 internally connected; connect to ground

FREF 46 4 MHz reference input

TAGC 47 TAGC output

GND 48 ground; plateau connection

Table 3. Pin description

…continued

Symbol Pin Description

Product data sheet Rev. 04 — 25 May 2009 15 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

8. Functional description

8.1 IF input switch

Different signal bandwidth can be handled by using two signal processing chains with

individual gain control.

Switch conﬁguration allows independent selection of ﬁlter for analog VIF and for analog

SIF (used at same time) or DIF.

The switch takes into account correct signal selection for TAGC in the event of VIF and

DIF signal processing.

8.2 VIF demodulator

ATV demodulation using 6 MHz DVB window (band-pass) ﬁlter (for 6 MHz, 7 MHz or

8 MHz channel width).

IF frequencies adapted to enable the use of different ﬁlter conﬁgurations. The Nyquist

processing is integrated. The integrated Nyquist processing provides also adjacent

channel suppression. Sideband switch supplies selection of lower or upper sideband (e.g.

for L-accent).

For optional use of standard Nyquist ﬁlter the integrated Nyquist processing can be

switched off.

Equalizer provides optimum pulse response at different standards [e.g. to cope with

higher demands for Liquid Crystal Display (LCD) TV].

Integrated sound traps.

Sound trap reference independent from received 2nd sound IF (reference taken from

integrated reference synthesizer).

IF level selection provides an optimum adaptation of the demodulator to high linearity or

low noise.

8.3 VIF AGC and tuner AGC

8.3.1 Mode selection of VIF AGC

Peak white AGC for positive modulation mode with adaptation for speed up and black level

AGC (using proven system from TDA9886).

For negative modulation mode equal response times for increasing or decreasing input

level (optimum for amplitude fading) or normal peak AGC or ultra fast peak AGC.

8.3.2 VIF AGC monitor

VIFAGC DC voltage monitor output (with expanded internal characteristic).

VIFAGC read out via I2C-bus (for IF level indication) with zero-calibration via TOP setting

(TOP setting either via I2C-bus or via TOP potentiometer).

Product data sheet Rev. 04 — 25 May 2009 16 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

8.3.3 Tuner AGC

Independent integral tuner gain control loop (not nested with VIFAGC). Integral

characteristic provides high control accuracy.

Accurate setting of tuner control onset (TOP) for integral tuner gain control loop via

I2C-bus.

For L standard, TAGC remains VIF AGC nested, as from ﬁeld experience in the past this

narrowband TAGC gives best performance.

Thus two switchable TAGC systems for negative/DIF and positive modulation

implemented.

L standard tuner time constant switching integrated (= speed up function in the event of

step into high input levels), to speed up settling time.

For TOP setting at L standard, additional adjustment via optional potentiometer or I2C-bus

is provided.

Tuner AGC status bit provided.

8.4 DIF/SIF FM and AM sound AGC

External AGC control input for DIF. DIF includes direct IF and low IF.

Integrated gain control loop for SIF.

AGC control for FM SIF related to used SAW bandwidth.

Peak AGC control in the event of FM SIF.

Ultra fast SIFAGC time constant when VIF AGC set to ultra fast mode.

Slow average AGC control in the event of AM sound.

AM sound AGC related to AM sound carrier level.

Fast AM sound AGC in the event of fast VIF AGC (speed up).

SIF/FM AGC DC voltage monitor output with expanded internal characteristic.

8.5 Frequency phase-locked loop for VIF

Basic function as previous TDA9887 design.

PLL gating mode for positive and negative modulation, optional.

PLL optimized for either overmodulation or strong multipath.

Product data sheet Rev. 04 — 25 May 2009 17 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

8.6 DIF/SIF converter stage

Frequency conversion with sideband suppression.

Selection mode of upper or lower sideband for pass or suppression.

Suppression around zero for frequency conversion.

Conversion mode selection via synthesizer for DIF and radio mode or via VIF Frequency

Phase-Locked Loop (FPLL) for TV QSS sound (FM/AM).

External BP ﬁlter (e.g. for 4.5 MHz) for additional ﬁltering, optional.

Bypass mode selection for use of external ﬁlter.

Integrated SIF BP tracking ﬁlter for chroma suppression.

Integrated tracking ﬁlters for LIF.

Symmetrical output stages for direct IF, LIF and 2nd SIF (intercarrier signal).

Second narrowband gain control loop for 2nd SIF via FM PLL.

8.7 Mono sound demodulator

8.7.1 FM PLL narrowband demodulation

Additional external input for either TV or radio intercarrier signal.

FM carrier selection independent from VIF trap, because VIF trap uses reference via

synthesizer.

FM wide and ultra wide mode with adapted loop bandwidth and different selectable

FM acquisition window widths to cope with FM overmodulation conditions.

8.7.2 AM sound demodulation

AM sound envelope detector.

L and L-accent standard without SAW switching (done by sideband selection of SIF

converter).

8.8 Audio ampliﬁer

Different gain settings for FM sound to adapt to different FM deviation.

Switchable de-emphasis for FM sound.

Automatic mute function when FM PLL is unlocked.

Forced mute function.

Output ampliﬁer for AM sound.

Product data sheet Rev. 04 — 25 May 2009 18 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

8.9 Synthesizer

The synthesizer supports SIF/DIF frequency conversion. A large set of synthesizer

frequencies in steps of 0.5 MHz enables ﬂexible combination of SAW ﬁlter and required

conversion frequency.

Synthesizer loop internally adapted to divider ratio range for optimum phase noise

requirement (loop bandwidth).

Synthesizer reference either via 4 MHz crystal or via an external source. Individual pins

for crystal and external reference allows optimum interface deﬁnition and supports use of

custom reference frequency offset.

8.10 I2C-bus transceiver and slave address

Four different I2C-bus device addresses to enable application with multi-IC use.

I2C-bus transceiver input ports can handle three different I2C-bus voltages.

Read-out functions as TDA9887 plus additional read out of VIFAGC and VIFLOCK,

BLCKLEV and TAGC status.

9. I2C-bus control

Table 4. Slave address detection

Slave address Selectable address bit Pin ADRSEL

A3 A0

MAD1 0 1 GND

MAD2 0 0 VP

MAD3 1 1 resistor to GND

MAD4 1 0 resistor to VP

Table 5. Slave addresses

For MAD activation via pin ADRSEL: see Table 4.

Slave address Bit

Name Value A6 A5 A4 A3 A2 A1 A0

MAD1 43h 1000011

MAD2 42h 1000010

MAD3 4Bh 1001011

MAD4 4Ah 1001010

Product data sheet Rev. 04 — 25 May 2009 19 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

9.1 Read format

[1] If no IF input is applied, then bit AFCWIN can be logic 1 due to the fact that the VCO is forced to the AFC

window border for fast lock-in behavior.

[2] All standards except M/N standard.

[3] M/N standard.

[4] Typical time constant of FM carrier detection is 50 ms. The minimal recommended wait time for read out is

80 ms.

Fig 7. I2C-bus read format (slave transmits data)

Table 6. R1 - data read register 1 bit allocation

7 6 5 4 3 2 1 0

AFCWIN BLCKLEV CARRDET AFC4 AFC3 AFC2 AFC1 PONR

Table 7. R1 - data read register 1 bit description

Bit Symbol Description

7 AFCWIN AFC window[1]

1 = VCO in ±1.6 MHz AFC window[2]

1 = VCO in ±0.8 MHz AFC window[3]

0 = VCO out of ±1.6 MHz AFC window[2]

0 = VCO out of ±0.8 MHz AFC window[3]

6 BLCKLEV black level detection

1 = black level detected

0 = no black level detected

5 CARRDET FM carrier detection[4]

1 = detection (FM PLL is locked and level is less than 6 dB below gain

controlled range of FM AGC)

0 = no detection

4 to 1 AFC[4:1] automatic frequency control; see Table 8

0 PONR power-on reset

1 = after power-on reset or after supply breakdown

0 = after a successful reading of the status register

001aad167

A6 to A0 R/W D7 to D0

slave address 1 data (R1) data (R2)

D7 to D0

S BYTE 1 A BYTE 2 A NABYTE 3 P

from master to slave S = START condition

A = acknowledge

NA = not acknowledge

P = STOP condition

from slave to master

Product data sheet Rev. 04 — 25 May 2009 20 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] In ATV mode f means vision intermediate frequency; in radio mode f means radio intermediate frequency.

Table 8. Automatic frequency control bits

nom

is the nominal frequency.

Bit f[1]

AFC4 AFC3 AFC2 AFC1

R1[4] R1[3] R1[2] R1[1]

0111≤(fnom −187.5 kHz)

0110f

nom −162.5 kHz

0101f

nom −137.5 kHz

0100f

nom −112.5 kHz

0011f

nom −87.5 kHz

0010f

nom −62.5 kHz

0001f

nom −37.5 kHz

0000f

nom −12.5 kHz

1111f

nom + 12.5 kHz

1110f

nom + 37.5 kHz

1101f

nom + 62.5 kHz

1100f

nom + 87.5 kHz

1011f

nom + 112.5 kHz

1010f

nom + 137.5 kHz

1001f

nom + 162.5 kHz

1000≥(fnom + 187.5 kHz)

Table 9. R2 - data read register 2 bit allocation

7 6 5 4 3 2 1 0

VIFLOCK TAGC VAGC5 VAGC4 VAGC3 VAGC2 VAGC1 VAGC0

Table 10. R2 - data read register 2 bit description

Bit Symbol Description

7 VIFLOCK VIF PLL lock-in detection

1 = VIF PLL is locked

0 = VIF PLL is not locked

6 TAGC tuner AGC

1 = active

0 = inactive

5 to 0 VAGC[5:0] AGC level detector; VIF AGC in ATV mode, SIFAGC in radio mode and

DIFAGC in DTV mode; see Table 11

Product data sheet Rev. 04 — 25 May 2009 21 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Table 11. AGC bits

Bit Typical

∆VAGC(VIF)

(V)

VAGC5 VAGC4 VAGC3 VAGC2 VAGC1 VAGC0

R2[5] R2[4] R2[3] R2[2] R2[1] R2[0]

1111110 (TOP)

[1]

111110−0.04

111101−0.08

111100−0.12

111011−0.16

111010−0.20

111001−0.24

111000−0.28

110111−0.32

110110−0.36

110101−0.40

110100−0.44

110011−0.48

110010−0.52

110001−0.56

110000−0.60

101111−0.64

101110−0.68

101101−0.72

101100−0.76

101011−0.80

101010−0.84

101001−0.88

101000−0.92

100111−0.96

100110−1.00

100101−1.04

100100−1.08

100011−1.12

100010−1.16

100001−1.20

100000−1.24

011111−1.28

011110−1.32

011101−1.36

011100−1.40

011011−1.44

011010−1.48

011001−1.52

Product data sheet Rev. 04 — 25 May 2009 22 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] The reference of 0 (TOP) can be adjusted via TOPPOS[4:0] (register W10; see Table 47 and Table 45) or

via potentiometer at pin TOP2.

011000−1.56

010111−1.60

010110−1.64

010101−1.68

010100−1.72

010011−1.76

010010−1.80

010001−1.84

010000−1.88

001111−1.92

001110−1.96

001101−2.00

001100−2.04

001011−2.08

001010−2.12

001001−2.16

001000−2.20

000111−2.24

000110−2.28

000101−2.32

000100−2.36

000011−2.40

000010−2.44

000001−2.48

000000−2.52

Table 11. AGC bits

…continued

Bit Typical

∆VAGC(VIF)

(V)

VAGC5 VAGC4 VAGC3 VAGC2 VAGC1 VAGC0

R2[5] R2[4] R2[3] R2[2] R2[1] R2[0]

Product data sheet Rev. 04 — 25 May 2009 23 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

9.2 Write format

9.2.1 Subaddress

Fig 8. I2C-bus write format (slave receives data)

001aad166

A6 to A0 R/W A7 to A0 bits 7 to 0

slave address

from master to slave S = START condition

A = acknowledge

P = STOP condition

0 subaddress data 1 data n

bits 7 to 0

from slave to master

S BYTE 1 A BYTE 2 A ABYTE 3 BYTE n A P

Table 12. W0 - subaddress register bit allocation

7 6 5 4 3 2 1 0

A7 A6 A5 A4 A3 A2 A1 A0

Table 13. W0 - subaddress register bit description

Bit Symbol Description

7 to 4 A[7:4] has to be set to logic 0

3 to 0 A[3:0] subaddress; see Table 14

Table 14. Subaddress control bits

Bit Mode

A3 A2 A1 A0

0 0 0 0 subaddress for register W1

0 0 0 1 subaddress for register W2

0 0 1 0 subaddress for register W3

0 0 1 1 subaddress for register W4

0 1 0 0 subaddress for register W5

0 1 0 1 subaddress for register W6

0 1 1 0 subaddress for register W7

0 1 1 1 subaddress for register W8

1 0 0 0 subaddress for register W9

1 0 0 1 subaddress for register W10

1 0 1 0 subaddress for register W11

Product data sheet Rev. 04 — 25 May 2009 24 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] See Table 17 for detailed description of W1.

[2] See Table 23 for detailed description of W2.

[3] See Table 27 for detailed description of W3.

[4] See Table 29 for detailed description of W4.

[5] See Table 33 for detailed description of W5.

[6] See Table 37 for detailed description of W6.

[7] See Table 40 for detailed description of W7.

[8] See Table 42 for detailed description of W8.

[9] See Table 44 for detailed description of W9.

[10] See Table 47 for detailed description of W10.

[11] See Table 50 for detailed description of W11.

9.2.2 Description of data bytes

Table 15. I2C-bus write register overview

The register setting after power-on is not speciﬁed.

W1[1] RADIO STD1 STD0 TV 0 0 FM EXTFIL

W2[2] MOD STD4 STD3 STD2 SB PLL GATE TRAP

W3[3] RESCAR AMUTE FMUTE FMWIDE0 DEEMT DEEM AGAIN1 AGAIN0

W4[4] VIFLEVEL BP MPPS1 MPPS0 AMMODE IFIN1 IFIN0 VIFIN

W5[5] FSFREQ1 FSFREQ0 SFREQ5 SFREQ4 SFREQ3 SFREQ2 SFREQ1 SFREQ0

W6[6] TAGC1 TAGC0 AGC2 AGC1 FMWIDE1 TWOFLO VIDEO1V7 DIRECT

W7[7] EXTFILO VAGC SIFLEVEL VIDLEVEL PORT1 MODEP1 FILOUTBP NYQOFF

W8[8] FEATURE AVIDRED MODEP3 TAGCIN3 FORCESP PORT3 PORT2 0

W9[9] DAGCSLOPE TAGCIS TAGCTC TOPNEG4 TOPNEG3 TOPNEG2 TOPNEG1 TOPNEG0

W10[10] 0 READTAGC XPOTPOS TOPPOS4 TOPPOS3 TOPPOS2 TOPPOS1 TOPPOS0

W11[11] 0 0 OFFSETN OFFSETP BLACKAGC GDEQ VIFIN3 VIF31875

Table 16. W1 - data write register bit allocation

7 6 543210

RADIO STD1 STD0 TV 0 0 FM EXTFIL

Table 17. W1 - data write register bit description

Bit Symbol Description

7 RADIO FM mode

1 = radio

0 = ATV/DTV

6 and 5 STD[1:0] 2nd sound IF; see Table 18 and Table 19

4 TV TV mode

1 = ATV QSS

0 = DTV; direct IF or LIF; depends on setting of TV mode (W6[0])

3 and 2 - 0 = ﬁxed value

1 and 0 FM and EXTFIL FM and output switching; see Table 21

Product data sheet Rev. 04 — 25 May 2009 25 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Table 18. Intercarrier sound BP and FM PLL frequency select for ATV, QSS mode

For description of bit MOD refer to Table 23 and bits FSFREQ[1:0] are described in Table 33.

Bit fFMPLL

(MHz) Sound BP

RADIO MOD STD1 STD0 FSFREQ1 FSFREQ0

W1[7] W2[7] W1[6] W1[5] W5[7] W5[6]

0 1 0 0 X X 4.5 M/N standard

0 1 0 1 X X 5.5 B/G standard

0 1 1 0 X X 6.0 I standard

0 1 1 1 X X 6.5 D/K standard

0 0 1 1 X X off L/L-accent standard

Table 19. Intercarrier sound BP and FM PLL frequency select for radio

For description of bit MOD refer to Table 23 and bits FSFREQ[1:0] are described in Table 33.

Bit fFMPLL

(MHz) Sound BP

RADIO MOD STD1 STD0 FSFREQ1 FSFREQ0

W1[7] W2[7] W1[6] W1[5] W5[7] W5[6]

1 1 X X 0 0 4.5 M/N standard

1 1 X X 0 1 5.5 B/G standard

1 1 X X 1 0 6.0 I standard

1 1 X X 1 1 6.5 D/K standard

Table 20. Intercarrier sound FM PLL frequency select for radio 10.7 MHz

For description of bit MOD refer to Table 23 and for BP refer to Table 29.

Bit fFMPLL (MHz)

BP MOD RADIO

W4[6] W2[7] W1[7]

0 0 1 10.7

Product data sheet Rev. 04 — 25 May 2009 26 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Table 21. 2nd intercarrier and sound I/O switching

Switch input numbering in accordance with Figure 9.

AMMODE MOD FM EXTFIL Audio

mode Input signal selection Signal at OUT1A and OUT1B Mono sound

Input switch Output switch

W4[3] W2[7] W1[1] W1[0] FM

input AM

input Signal

path Input Signal path Demodulation

via

X 100 FM

sound 1 X internal 6 internal BP via FM AGC internal BP

X 1 0 1 2 X EXTFILI 7 internal BP external BP

X 1 1 0 3 X EXTFMI 7 internal BP external input

X 1 1 1 2 X EXTFILI 6 external BP via FM AGC external BP

0 000 AM

sound 1 1 5 internal 6 internal BP + 6 dB internal BP

0 0 0 1 X 5 internal 7 internal BP internal BP

0 0 1 0 X 5 internal 7 internal BP internal BP

0 0 1 1 2 5 EXTFILI 6 external BP internal BP

1 000 AM

sound 2 2 4 EXTFILI 7 internal BP external BP

1 0 0 1 X 5 internal 7 internal BP internal BP

1 0 1 0 X 5 internal 7 internal BP internal BP

1 0 1 1 2 4 EXTFILI 6 external BP external BP

Fig 9. Signal path for intercarrier (2nd SIF) processing

008aaa145

FM PLL

BAND-PASS

BYPASS

W7.1 = 1

external filter output external filter input

EXTFILO

input

switch

output

switch

AM:

fixed-gain

amplifier

EXTFILI

OUT1A

OUT1B

external FM input

EXTFMI

W7.1 = 0

3 dB

internal 7

FM:

AGC

amplifier

3input

switch

5AM

DEMODULATOR

Product data sheet Rev. 04 — 25 May 2009 27 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Table 22. W2 - data write register bit allocation

7 6 5 4 3 2 1 0

MOD STD4 STD3 STD2 SB PLL GATE TRAP

Table 23. W2 - data write register bit description

Bit Symbol Description

7 MOD modulation

1 = negative; FM mono sound at ATV

0 = positive; AM mono sound at ATV

6 to 4 STD[4:2] vision IF; see Table 24

3 SB sideband for sound IF and digital low IF

1 = upper

0 = lower

2 PLL operating modes; see Table 25

1 GATE PLL gating

1 = on; fPC =f

VIF ±175 kHz

0 = off

0 TRAP sound trap

1=on

0 = bypass

Product data sheet Rev. 04 — 25 May 2009 28 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] Register W11 is logical AND protected by bit W8[7]. Therefore it is required to set W8[7] = 1 to enable pass

of any W11 bit.

Table 24. Vision IF

Bit fVIF (MHz) Sideband

in case of

W7[0] = 0

VIF31875 NYQOFF MOD STD4 STD3 STD2 TV=1

(QSS)

W11[0][1] W7[0] W2[7] W2[6] W2[5] W2[4]

X X X 0 0 0 38.0 low

X X X 0 0 1 38.375 low

X X X 0 1 0 38.875 low

X X X 0 1 1 39.875 low

X X 1 1 0 0 45.75 low

X X 1 1 0 1 58.75 low

X X 1 1 1 0 46.25 low

X X 1 1 1 1 59.25 low

0 0 0 1 0 0 32.25 high

0 0 0 1 0 1 32.625 high

0 0 0 1 1 0 33.125 high

0 0 0 1 1 1 33.625 high

1 X 0 1 0 0 31.875 high

X 1 0 1 0 1 33.9 -

1 0 0 1 0 1 33.9 high

1 X 0 1 1 0 35.0 high

1 X 0 1 1 1 36.0 high

Table 25. VIF PLL gating and detector mode

Bit Gating and detector mode

MOD PLL

W2[7] W2[2]

0 0 0 % gating in positive modulation mode (W2[1] = 1)

0 1 36 % gating in positive modulation mode (W2[1] = 1)

10π mode on; optimized for overmodulation in negative modulation mode;

fPC =f

VIF ±175 kHz

11π mode off; optimized for multipath in negative modulation mode;

fPC =f

VIF ±175 kHz

Product data sheet Rev. 04 — 25 May 2009 29 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Table 26. W3 - data write register bit allocation

7 6 5 4 3 2 1 0

RESCAR AMUTE FMUTE FMWIDE0 DEEMT DEEM AGAIN1 AGAIN0

Table 27. W3 - data write register bit description

Bit Symbol Description

7 RESCAR video gain correction for residual carrier

1 = 20 % residual carrier

0 = 10 % residual carrier

6 AMUTE auto mute

1=on

0 = off

5 FMUTE forced mute

1=on

0 = off

4 FMWIDE0 FM window (W6[3] = 0)

1 = 475 kHz; normal FM phase detector steepness

0 = 237.5 kHz; high FM phase detector steepness

3 DEEMT de-emphasis time

1=50µs

0=75µs

2 DEEM de-emphasis

1=on

0 = off

1 and 0 AGAIN[1:0] audio gain

00=0dB

01 = −6dB

10 = −12 dB (only for FM mode)

11 = −18 dB (only for FM mode)

Product data sheet Rev. 04 — 25 May 2009 30 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] Not recommended in combination with internal video level set to reduced (W7[4] = 1).

[1] Intercarrier output level based on wideband AGC of SIF ampliﬁer.

[2] Intercarrier output level based on narrowband AGC of FM ampliﬁer.

Table 28. W4 - data write register bit allocation

7 6 5 4 3 2 1 0

VIFLEVEL BP MPPS1 MPPS0 AMMODE IFIN1 IFIN0 VIFIN

Table 29. W4 - data write register bit description

Bit Symbol Description

7 VIFLEVEL control of internal VIF mixer input level (W1[4] = 1) and OUT1/OUT2

output level; see Table 30

1 = reduced[1]

0 = normal

6 BP SIF/DIF BP

1 = on (bit W6[0] = 0; see Table 37)

0 = bypass

5 and 4 MPPS[1:0] AGC or AFC output; see Table 31

3 AMMODE AM mode extension; see Table 21

1 = second selection set

0 = ﬁrst selection set

2 and 1 IFIN[1:0] DIF/SIF input

00 = IF1A/B input

01 = IF3A/B input

10 = not used

11 = IF2A/B input

0 VIFIN VIF input (W11[1] = 0)

1 = IF1A/B input

0 = IF2A/B input

Table 30. List of output signals at OUT1 and OUT2

Bit Output signal at

TV DIRECT FM EXTFIL OUT1A,

OUT1B OUT2A,

OUT2B

W1[4] W6[0] W1[1] W1[0]

0 0 X X low IF off

0 1 X X off direct IF

1 X 0 0 intercarrier[1] off

1 X 0 1 intercarrier[2] off

1 X 1 0 intercarrier[2] off

1 X 1 1 intercarrier[1] off

Product data sheet Rev. 04 — 25 May 2009 31 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Table 31. Output mode at pin MPP for ATV or radio mode

Bit Pin MPP output mode

VAGC RADIO MPPS1 MPPS0

W7[6] W1[7] W4[5] W4[4]

0 X 0 0 gain control voltage of FM PLL

0 X 0 1 gain control voltage of SIFampliﬁer

0 X 1 0 TAGC monitor voltage

0011AFC current output, VIF PLL

0111AFC current output, radio mode

1 X 0 0 gain control voltage of VIFampliﬁer

Table 32. W5 - data write register bit allocation

7 6 5 4 3 2 1 0

FSFREQ1 FSFREQ0 SFREQ5 SFREQ4 SFREQ3 SFREQ2 SFREQ1 SFREQ0

Table 33. W5 - data write register bit description

Bit Symbol Description

7 and 6 FSFREQ[1:0] DTV ﬁlter or sound trap selection for video

ATV; sound trap; TV = 1; see Table 16 and Table 17

00 = M/N standard (4.5 MHz)

01 = B/G standard (5.5 MHz)

10 = I standard (6.0 MHz)

11 = D/K and L/L-accent standard (6.5 MHz)

DTV (low IF); upper BP cut-off frequency; TV = 0; see Table 16 and

Table 17

00 = 7.0 MHz

01 = 8.0 MHz

10 = 9.0 MHz

11 = recommended mode for direct IF; W6[0] = 1

5 to 0 SFREQ[5:0] synthesizer frequencies; see Table 34 and Table 35

Product data sheet Rev. 04 — 25 May 2009 32 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Table 34. DIF/SIF synthesizer frequencies (using bit TWOFLO = 0)

Bit fsynth (MHz)

SFREQ5 SFREQ4 SFREQ3 SFREQ2 SFREQ1 SFREQ0

W5[5] W5[4] W5[3] W5[2] W5[1] W5[0]

11111122.0

11111022.5

11110123.0

11110023.5

11101124.0

11101024.5

11100125.0

11100025.5

11011126.0

11011026.5

11010127.0

11010027.5

11001128.0

11001028.5

11000129.0

11000029.5

10111130.0

10111030.5

10110131.0

10110031.5

10101132.0

10101032.5

10100133.0

10100033.5

10011134.0

10011034.5

10010135.0

10010035.5

10001136.0

10001036.5

10000137.0

10000037.5

01111138.0

01111038.5

01110139.0

01110039.5

01101140.0

01101040.5

01100141.0

Product data sheet Rev. 04 — 25 May 2009 33 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

01100041.5

01011142.0

01011042.5

01010143.0

01010043.5

01001144.0

01001044.5

01000145.0

01000045.5

00111146.0

00111046.5

00110147.0

00110047.5

00101148.0

00101048.5

00100149.0

00100049.5

00011150.0

00011050.5

00010151.0

00010051.5

00001152.0

00001052.5

00000153.0

00000053.5

Table 35. DIF/SIF synthesizer frequency for Japan (using bit TWOFLO = 1)

Bit fsynth (MHz)

SFREQ5 SFREQ4 SFREQ3 SFREQ2 SFREQ1 SFREQ0

W5[5] W5[4] W5[3] W5[2] W5[1] W5[0]

11001057

Table 34. DIF/SIF synthesizer frequencies (using bit TWOFLO = 0)

…continued

Bit fsynth (MHz)

SFREQ5 SFREQ4 SFREQ3 SFREQ2 SFREQ1 SFREQ0

W5[5] W5[4] W5[3] W5[2] W5[1] W5[0]

Product data sheet Rev. 04 — 25 May 2009 34 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] In TAGC integral loop mode the pin TAGC provides sink and source currents for control. TakeOver Point

(TOP) is set via register TOPNEG W9[4:0].

Table 36. W6 - data write register bit allocation

7 6 5 4 3 2 1 0

TAGC1 TAGC0 AGC2 AGC1 FMWIDE1 TWOFLO VIDEO1V7 DIRECT

Table 37. W6 - data write register bit description

Bit Symbol Description

7 and 6 TAGC[1:0] tuner AGC mode[1]

00 = TAGC integral loop mode; all currents off

01 = TAGC integral loop mode; source current off

10 = TAGC integral loop mode

11 = TAGC derived from IFAGC; recommended for positive modulated

signals

5 and 4 AGC[2:1] AGC mode and behavior; see Table 38

3 FMWIDE1 FM window

1 = 1 MHz

0 = see Table 27 bit FMWIDE0

2 TWOFLO synthesizer frequency selection

1 = Japan mode (57 MHz)

0 = synthesizer mode

1 VIDEO1V7 video output level selection; sound carrier trap set to on (W2[0] = 1);

see Table 22 and Table 23

1 = 1.7 V at CVBS

0 = 2.0 V at CVBS

0 DIRECT direct IF at DTV mode; TV set to DTV (W1[4] = 0); see Table 16 and

Table 17

1 = direct IF output

0 = low IF output

Table 38. AGC mode and behavior

Bit VIF AGC

mode SIF AGC

mode

MOD FORCESP AGC2 AGC1

W2[7] W8[3] W6[5] W6[4]

0 0 0 0 normal normal

0 0 0 1 minimum gain minimum gain

0 0 1 0 normal normal

0 0 1 1 normal fast

0 1 X X fast fast

1 X 0 0 normal normal

1 X 0 1 minimum gain minimum gain

1 X 1 0 2nd normal

1 X 1 1 2nd fast fast

Product data sheet Rev. 04 — 25 May 2009 35 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] Not recommended in combination with internal IF level set to reduced (W4[7] = 1).

[2] At internal Nyquist processing off (W7[0] = 1) it is mandatory to set the internal video level to normal

(W7[4] = 0).

Table 39. W7 - data write register bit allocation

7 6 5 4 3 2 1 0

EXTFILO VAGC SIFLEVEL VIDLEVEL PORT1 MODEP1 FILOUTBP NYQOFF

Table 40. W7 - data write register bit description

Bit Symbol Description

7 EXTFILO mute of output buffer of pin EXTFILO

1 = mute

0 = normal

6 VAGC gain control voltage of VIF ampliﬁer at pin MPP; see Table 31

5 SIFLEVEL SIF level reduction

1 = internal SIF level is reduced by 6 dB (only for AM sound)

0 = internal SIF level is normal

4 VIDLEVEL video level reduction

1 = internal video level is reduced by 6 dB[1]

0 = internal video level is normal

3 PORT1 output state; port 1 mode selection set to logic output port (W7[2] = 1)

1 = output port is HIGH (external pull-up resistor needed)

0 = output port is LOW

2 MODEP1 port 1 mode selection; pin PORT1

1 = logic output port; level controlled by bit PORT1 (W7[3])

0 = monitor output of VIF AGC voltage

1 FILOUTBP external ﬁlter output signal source; see Figure 9

1 = signal for external ﬁlter is obtained behind internal BP ﬁlter

0 = signal for external ﬁlter is obtained behind SIF mixer

0 NYQOFF internal Nyquist processing; see Table 24

1 = internal Nyquist processing off[2]

0 = internal Nyquist processing on

Product data sheet Rev. 04 — 25 May 2009 36 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Table 41. W8 - data write register bit allocation

7 6 5 4 3 2 1 0

FEATURE AVIDRED MODEP3 TAGCIN3 FORCESP PORT3 PORT2 0

Table 42. W8 - data write register bit description

Bit Symbol Description

7 FEATURE feature enable

1 = feature PORT2; PORT3 monitor output of TAGC voltage and data

write register W11[7:0] enabled

0 = feature disabled; pin PORT2 and pin PORT3 set to high-ohmic;

data write register W11[7:0] = 0000 0000

6 AVIDRED automatic reduction of internal video level for PC / SC < 11.0 dB

1 = enabled

0 = disabled

5 MODEP3 port 3 mode selection; pin PORT3

1 = logic output port; level controlled by bit PORT3 (W8[2])

0 = monitor output of TAGC voltage

4 TAGCIN3 TAGC IF input selection; feature enable set to enable (W8[7] = 1)

1 = IF3A and IF3B input

0 = IF1A and IF1B input or IF2A and IF2B input depends on VIF input

selection (W4[0])

3 FORCESP VIF AGC and SIF AGC fast mode activation; modulation setting

(W2[7] = 0)

1 = forced

0 = automatic; dependent on video level

2 PORT3 output state; feature enable set to enable (W8[7] = 1); port 3 mode

selection set to logic output port (W8[5] = 1)

1 = output port is HIGH (external pull-up resistor needed)

0 = output port is LOW

1 PORT2 output state; feature enable set to enable (W8[7] = 1)

1 = output port is HIGH (external pull-up resistor needed)

0 = output port is LOW

0 - 0 = ﬁxed value

Product data sheet Rev. 04 — 25 May 2009 37 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] Average step size is 1.255 dB typical.

[2] See Table 53 for parameter tuner takeover point accuracy (αacc(set)TOP).

Table 43. W9 - data write register bit allocation

7 6 5 4 3 2 1 0

DAGCSLOPE TAGCIS TAGCTC TOPNEG4 TOPNEG3 TOPNEG2 TOPNEG1 TOPNEG0

Table 44. W9 - data write register bit description

Bit Symbol Description

7 DAGCSLOPE AGCDIN input characteristic; see Figure 44

1 = high voltage for high gain

0 = low voltage for high gain

6 TAGCIS tuner AGC IF input (TOP1)

1 = inverse to VIF input

0 = aligned to VIF input

5 TAGCTC tuner AGC charge current (TOP1)

1 = high

0 = normal

4 to 0 TOPNEG[4:0] TOP adjustment for integral loop mode (TOP1); recommended for negative modulation;

see Table 45

Table 45. Tuner takeover point adjustment bits W9[4:0]

Bit TOP adjustment

(dBµV)[1]

TOPNEG4 TOPNEG3 TOPNEG2 TOPNEG1 TOPNEG0

W9[4] W9[3] W9[2] W9[1] W9[0]

1111198.5 typical

:::::see

Figure 13

1000079.3[2]

:::::seeFigure 13

0000059.6 typical

Table 46. W10 - data write register bit allocation

7 6 5 4 3 2 1 0

0 READTAGC XPOTPOS TOPPOS4 TOPPOS3 TOPPOS2 TOPPOS1 TOPPOS0

Table 47. W10 - data write register bit description

Bit Symbol Description

7 - 0 = ﬁxed value

6 READTAGC signal source for TAGC read-out on R2[6]

1 = inverse to used TAGC detector (integral or IF based)

0 = aligned to used TAGC detector (integral or IF based)

Product data sheet Rev. 04 — 25 May 2009 38 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] See Table 53 for parameter tuner takeover point accuracy (αacc(set)TOP2).

5 XPOTPOS TOP derived from IFAGC via I2C-bus or potentiometer (TOP2)

1 = TOP adjustment by external potentiometer at pin TOP2

0 = see Table 48

4 to 0 TOPPOS[4:0] TOP adjustment for TAGC derived from IFAGC (TOP2); recommended for positive

modulation; see Table 48

Table 47. W10 - data write register bit description

…continued

Bit Symbol Description

Table 48. Tuner takeover point adjustment bits W10[4:0]

Bit TOP adjustment

(dBµV)

TOPPOS4 TOPPOS3 TOPPOS2 TOPPOS1 TOPPOS0

W10[4] W10[3] W10[2] W10[1] W10[0]

1111199.0 typical

:::::see

Figure 13

1000078.5[1]

:::::seeFigure 13

0000056.9 typical

Table 49. W11 - data write register bit allocation

7 6 5 4 3 2 1 0

0 0 OFFSETN OFFSETP BLACKAGC GDEQ VIFIN3 VIF31875

Table 50. W11 - data write register bit description[1]

Bit Symbol Description

7 and 6 - 0 = ﬁxed value

5 OFFSETN VIF PLL offset sink current (approximately 0.6 µA)

1 = enabled (requires W11[4] = 0)

0 = disabled

4 OFFSETP VIF PLL offset source current (approximately 0.6 µA)

1 = enabled (requires W11[5] = 0)

0 = disabled

3 BLACKAGC black level AGC

1 = disabled

0 = enabled

2 GDEQ activate group delay equalizer

1 = on (if pin 34 is open-circuit)

1 = off (if pin 34 is connected to ground)

0 = off (if pin 34 is open-circuit)

0 = on (if pin 34 is connected to ground)

1 VIFIN3 VIF input selection

1 = IF3A and IF3B input

0 = IF1A and IF1B input or IF2A and IF2B input depends on VIF input selection (W4[0])

Product data sheet Rev. 04 — 25 May 2009 39 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] Register W11 is logical AND protected by bit W8[7]. Therefore it is required to set W8[7] = 1 to enable pass of any W11 bit.

10. Limiting values

[1] Class 2 according to JESD22-A114.

[2] Class B according to EIA/JESD22-A115.

11. Thermal characteristics

0 VIF31875 VIF frequency selection for global ATV application inclusive DVB-T; see Table 24

1 = 31.875 MHz

0 = 32.250 MHz

Table 50. W11 - data write register bit description[1]

…continued

Bit Symbol Description

Table 51. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VPsupply voltage - 5.5 V

Vnvoltage on any other pin all pins except ground 0 VPV

tsc short-circuit time to ground or VP-10 s

Tstg storage temperature −40 +150 °C

Tamb ambient temperature −20 +70 °C

Tcase case temperature TDA9898HL (LQFP48) - 105 °C

TDA9898HN (HVQFN48) - 115 °C

TDA9897HL (LQFP48) - 105 °C

TDA9897HN (HVQFN48) - 115 °C

Vesd electrostatic discharge voltage human body model [1] -±3000 V

machine model [2] -±300 V

Table 52. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient in free air; 2 layer board

TDA9898HL (LQFP48) 67 K/W

TDA9898HN (HVQFN48) 48 K/W

TDA9897HL (LQFP48) 67 K/W

TDA9897HN (HVQFN48) 48 K/W

Rth(j-c) thermal resistance from junction to case

TDA9898HL (LQFP48) 19 K/W

TDA9898HN (HVQFN48) 10 K/W

TDA9897HL (LQFP48) 19 K/W

TDA9897HN (HVQFN48) 10 K/W

Product data sheet Rev. 04 — 25 May 2009 40 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

12. Characteristics

12.1 Analog TV signal processing

Table 53. Characteristics

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supply; pin VP

VPsupply voltage [1] 4.5 5.0 5.5 V

IPsupply current ATV QSS; B/G standard;

sound carrier trap on;

sound BP on

- - 175 mA

Power-on reset

VP(POR) power-on reset supply

voltage for start of reset at

decreasing supply voltage [2] 2.5 3.0 3.5 V

for end of reset at

increasing supply voltage;

I2C-bus transmission

enable

[2] - 3.3 4.4 V

VIF ampliﬁer; pins IF1A and IF1B or pins IF2A and IF2B or pins IF3A and IF3B

VIinput voltage - 1.95 - V

Ri(dif) differential input resistance [3] -2 -kΩ

Ci(dif) differential input

capacitance [3] -3 -pF

Vi(IF)(RMS) RMS IF input voltage lower limit at −1 dB video

output signal - 60 100 µV

upper limit at +1 dB video

output signal 150 190 - mV

permissible overload [4] - - 320 mV

∆GIF IF gain variation difference between picture

and sound carrier; within

AGC range; ∆f = 5.5 MHz

- 0.7 - dB

GVIF(cr) control range VIF gain 60 66 - dB

f−3dB(VIF)l lower VIF cut-off frequency - 15 - MHz

f−3dB(VIF)u upper VIF cut-off frequency - 80 - MHz

VIF PLL and true synchronous video demodulator[5]

VLFVIF voltage on pin LFVIF (DC) 0.9 - 3.6 V

fVCO(max) maximum VCO frequency fVCO =2f

PC 120 140 - MHz

fVIF VIF frequency see Table 24 -- -MHz

∆fVIF(dah) digital acquisition help VIF

frequency window related to fVIF

all standards except

M/N -±2.3 - MHz

M/N standard - ±1.8 - MHz

Product data sheet Rev. 04 — 25 May 2009 41 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

tacq acquisition time [6] - - 30 ms

Vlock(min)(RMS) RMS minimum lock-in

voltage measured on active IF

input pins;

maximum IF gain;

negative modulationmode

W2[7] = 1 and PLL set to

overmodulation mode

W2[2] = 0 and W2[1] = 0

-3070µV

Tcy(dah) digital acquisition help

cycle time -64-µs

tw(dah) digital acquisition help

pulse width 64 - - µs

Ipul(acq)VIF VIF acquisition pulse

current sink or source 21 - 33 µA

KO(VIF) VIF VCO steepness ∆fVIF /∆VLFVIF - 26 - MHz/V

KD(VIF) VIF phase detector

steepness ∆IVPLL /∆ϕVCO(VIF) -33-µA/rad

Ioffset(VIF) VIF offset current −10 +1µA

Video output 2 V; pin CVBS[7]

Normal mode (sound carrier trap active) and sound carrier on

Vo(video)(p-p) peak-to-peak video output

voltage positive or negative

modulation; W6[1] = 0;

see Figure 10

W4[7] = 0; W7[4] = 0 1.7 2.0 2.3 V

W4[7] = 1; W7[4] = 0 1.7 2.0 2.3 V

W4[7] = 0; W7[4] = 1 1.7 2.0 2.3 V

∆Vo(CVBS) CVBS output voltage

difference difference between

L and B/G standard;

W3[7] = 0

W4[7] = 0; W7[4] = 0 −240 - +240 mV

W4[7] = 1; W7[4] = 0 −240 - +240 mV

W4[7] = 0; W7[4] = 1 −240 - +240 mV

difference between

I and B/G standard;

20 % residual carrier at

I standard; W3[7] = 1

W4[7] = 0; W7[4] = 0 −100 - +100 mV

W4[7] = 1; W7[4] = 0 −100 - +100 mV

W4[7] = 0; W7[4] = 1 −100 - +100 mV

Vvideo/Vsync video voltage to sync

voltage ratio 2.0 2.33 2.75

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 42 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Vsyncl sync level voltage W4[7] = 0; W7[4] = 0 1.0 1.2 1.4 V

W4[7] = 1; W7[4] = 0 0.9 1.2 1.5 V

W4[7] = 0; W7[4] = 1 0.9 1.2 1.5 V

Vclip(video)u upper video clipping

voltage VP−1.2 VP−1- V

Vclip(video)l lower video clipping voltage - 0.4 0.9 V

ROoutput resistance [3] -- 30Ω

Ibias(int) internal bias current (DC) for emitter-follower 1.5 2.0 - mA

Isink(o)(max) maximum output sink

current AC and DC 1 - - mA

Isource(o)(max) maximum output source

current AC and DC 3.9 - - mA

∆Vo(CVBS) CVBS output voltage

difference 50 dB gain control - - 0.5 dB

30 dB gain control - - 0.1 dB

∆Vblt/VCVBS black level tilt to CVBS

voltage ratio negative modulation - - 1 %

∆Vblt(v)/VCVBS vertical black level tilt to

CVBS voltage ratio worst case in L standard;

vision carrier modulated

by test line [Vertical

Interval Test Signal

(VITS)] only

-- 3%

Gdif differential gain

“ITU-T J.63 line 330”

[8]

B/G standard - - 5 %

L standard - - 7 %

ϕdif differential phase

“ITU-T J.63 line 330”

[8]

B/G standard - 2 4 deg

L standard - 2 4 deg

(S/N)wweighted signal-to-noise

ratio B/G standard; 50 % grey

video signal; uniﬁed

weighting ﬁlter

(

“ITU-T J.61”

);

see Figure 20

[9] 53 57 - dB

(S/N)unw unweighted signal-to-noise

ratio M/N standard;50 IREgrey

video signal;

see Figure 20

47 51 - dB

VPC(rsd)(RMS) RMS residual picture

carrier voltage fundamental wave and

harmonics -2 5mV

∆fPC(p-p) peak-to-peakpicturecarrier

frequency variation 3 % residual carrier;

50 % serration pulses;

L standard

[3] - - 12 kHz

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 43 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

∆ϕ phase difference 0 % residual carrier;

50 % serration pulses;

L standard; L-gating = 0 %

[3] -- 3%

αH(video) video harmonics

suppression AC load: CL<20pF,

RL>1kΩ[10] 35 40 - dB

αsp spurious suppression [11] 40 - - dB

PSRRCVBS power supply ripple

rejection on pin CVBS fripple =70Hz;

video signal; grey level;

positive and negative

modulation; see Figure 11

14 20 - dB

M/N standard inclusive Korea; see Figure 21[12]

αripple(resp)f frequency response ripple 0.5 MHz to 2.5 MHz −1.5 - +1 dB

2.5 MHz to 3.6 MHz −2 - +1 dB

3.6 MHz to 3.8 MHz −3 - +1 dB

3.8 MHz to 4.2 MHz −16 - +1 dB

αSC1 ﬁrst sound carrier

attenuation f=f

SC1 = 4.5 MHz 38 - - dB

f=f

SC1 ±60 kHz 29 - - dB

αSC2 second sound carrier

attenuation f=f

SC2 = 4.724 MHz 25 - - dB

f=f

SC2 ±60 kHz 16 - - dB

td(grp)CC color carrier group delay

time f = 3.58 MHz; including

transmitter pre-correction;

see Figure 22

[13] −75 −50 +75 ns

B/G standard; see Figure 23[12]

αripple(resp)f frequency response ripple 0.5 MHz to 3.2 MHz −1.5 - +1 dB

3.2 MHz to 4.5 MHz −3 - +1 dB

4.5 MHz to 4.8 MHz −5 - +1 dB

4.8 MHz to 5 MHz −12 - +1 dB

αSC1 ﬁrst sound carrier

attenuation f=f

SC1 = 5.5 MHz 35 - - dB

f=f

SC1 ±60 kHz 26 - - dB

αSC2 second sound carrier

attenuation f=f

SC2 = 5.742 MHz 25 - - dB

f=f

SC2 ±60 kHz 16 - - dB

αSC(NICAM) NICAM sound carrier

attenuation fcar(NICAM) = 5.85 MHz;

f=f

car(NICAM) ±250 kHz 12 - - dB

αattenuation f = f(N+1)ch = 7 MHz 21 - - dB

f=f

(N+1)ch ±750 kHz 5 - - dB

td(grp)CC color carrier group delay

time f = 4.43 MHz; including

transmitter pre-correction;

see Figure 24

[13] −75 −10 +75 ns

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 44 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

I standard; see Figure 25[12]

αripple(resp)f frequency response ripple 0.5 MHz to 3.2 MHz −1.5 - +1 dB

3.2 MHz to 4.5 MHz −2 - +1 dB

4.5 MHz to 5 MHz −4 - +1 dB

5 MHz to 5.5 MHz −12 - +1 dB

αSC1 ﬁrst sound carrier

attenuation f=f

SC1 = 6.0 MHz 35 - - dB

f=f

SC1 ±60 kHz 26 - - dB

αSC(NICAM) NICAM sound carrier

attenuation fcar(NICAM) = 6.55 MHz;

f=f

car(NICAM) ±250 kHz 12 - - dB

td(grp)CC color carrier group delay

time f = 4.43 MHz;

see Figure 26 [13] −75 −15 +75 ns

D/K standard; see Figure 27[12]

αripple(resp)f frequency response ripple 0.5 MHz to 3.1 MHz −1.5 - +1 dB

3.1 MHz to 4.5 MHz −2 - +1 dB

4.5 MHz to 4.8 MHz −4 - +1 dB

4.8 MHz to 5.1 MHz −6 - +1 dB

αSC1 ﬁrst sound carrier

attenuation f=f

SC1 = 6.5 MHz 35 - - dB

f=f

SC1 ±60 kHz 26 - - dB

αSC2(us) second sound carrier

attenuation (upper side) f=f

SC2 = 6.742 MHz 25 - - dB

f=f

SC2 ±60 kHz 16 - - dB

αSC2(ls) second sound carrier

attenuation (lower side) f=f

SC2 = 6.258 MHz 25 - - dB

f=f

SC2 ±60 kHz 16 - - dB

αSC(NICAM) NICAM sound carrier

attenuation fcar(NICAM) = 5.85 MHz;

f=f

car(NICAM) ±250 kHz 6- - dB

td(grp)CC color carrier group delay

time f = 4.28 MHz; including

transmitter pre-correction;

see Figure 28

[13] −50 0 +100 ns

L standard; see Figure 29[12]

αripple(resp)f frequency response ripple 0.5 MHz to 3.2 MHz −1.5 - +1 dB

3.2 MHz to 4.5 MHz −2 - +1 dB

4.5 MHz to 4.8 MHz −4 - +1 dB

4.8 MHz to 5.3 MHz −12 - +1 dB

αSC(NICAM) NICAM sound carrier

attenuation fcar(NICAM) = 5.85 MHz;

f=f

car(NICAM) ±250 kHz 5- - dB

αSC(AM) AM sound carrier

attenuation f=f

SC(AM) = 6.5 MHz 38 - - dB

f=f

SC(AM) ±30 kHz 29 - - dB

td(grp)CC color carrier group delay

time f = 4.28 MHz; including

transmitter pre-correction;

see Figure 30

−75 −5 +75 ns

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 45 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Video output 1.7 V; pin CVBS; see Figure 50, optional CVBS buffer at setting W6[1] = 1

Normal mode (sound carrier trap active) and sound carrier on

Vo(video)(p-p) peak-to-peak video output

voltage positive or negative

modulation; W6[1] = 1;

see Figure 10

W4[7] = 0; W7[4] = 0 1.44 1.7 1.96 V

W4[7] = 1; W7[4] = 0 1.44 1.7 1.96 V

W4[7] = 0; W7[4] = 1 1.44 1.7 1.96 V

Vsyncl sync level voltage W4[7] = 0; W7[4] = 0 1.0 1.2 1.4 V

W4[7] = 1; W7[4] = 0 0.9 1.2 1.5 V

W4[7] = 0; W7[4] = 1 0.9 1.2 1.5 V

Video output 1.1 V; pin CVBS

Trap bypass mode and sound carrier off[12]

Vo(video)(p-p) peak-to-peak video output

voltage see Figure 10 - 1.1 - V

Vsyncl sync level voltage - 1.5 - V

Vclip(video)u upper video clipping

voltage VP− 1.2 VP− 1- V

Vclip(video)l lower video clipping voltage - 0.4 0.9 V

Bvideo(−3dB) −3 dB video bandwidth AC load: CL<20pF,

RL>1kΩ6 8 - MHz

(S/N)wweighted signal-to-noise

ratio B/G standard; 50 % grey

video signal; uniﬁed

weighting ﬁlter

(

“ITU-T J.61”

);

see Figure 20

[9] 54 - - dB

(S/N)unw unweighted signal-to-noise

ratio M/N standard;50 IREgrey

video signal;

see Figure 20

[9] 47 51 - dB

VIF AGC

Pin MPP

Vmonitor(VIFAGC) VIFAGC monitor voltage [3] 0.5 - 4.5 V

VAGC AGC voltage see Figure 12; Vi(IF) set to

1 mV (60 dBµV) 2.0 - 2.5 V

10 mV (80 dBµV) 2.4 - 3.0 V

200 mV (106 dBµV) 3.0 - VPV

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 46 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

tresp response time increasing VIF step;

negative modulation [14]

normal mode - 100 - µs/dB

2nd mode - 9 - µs/dB

fast 2nd mode - 3 - µs/dB

increasing VIF step;

positive modulation [14]

normal mode - 100 - µs/dB

fast mode - 5 - µs/dB

decreasing VIF step;

negative modulation [14]

normal mode - 70 - µs/dB

2nd mode - 250 - µs/dB

2nd mode (speed-up) [15] -20-µs/dB

fast 2nd mode - 80 - µs/dB

fast 2nd mode

(speed-up) [15] -6 -µs/dB

decreasing VIF step;

positive modulation [14]

20 dB - 900 - ms

normal mode - 180 - ms/dB

fast mode; W8[3] = 1 - 3 - ms/dB

fast mode (speed-up) [16] - 24 - ms/dB

αth(fast)VIF VIF fast mode threshold L standard −10 −6−2dB

∆VVAGC(step) VIFAGC voltage difference

(step) see Table 11 - 40 - mV/bit

Pin CIFAGC

Ich(max) maximum charge current L standard; normal mode;

W8[3] = 0 75 100 125 µA

L standard; fast mode;

W8[3] = 1 - 2.0 - mA

Ich(add) additional charge current L standard: in the event of

missing VITS pulses and

no white video content

- 100 - nA

Idch discharge current L standard; normal mode;

W8[3] = 0 -35-nA

L standard; fast mode;

W8[3] = 1 or speed-up - 1.4 - µA

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 47 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Tuner AGC; pin TAGC

TAGC integral loop mode (W6[7:6] = 10); TAGC is current output; applicable for negative modulation only; unmodulated VIF;

see Table 44 and Figure 13

Vi(IF)(RMS) RMS IF input voltage for TOP1; at starting point

of tuner AGC takeover;

Isink(TAGC) = 100 µA

W9[4:0] = 0 0000 - 59.6 - dBµV

W9[4:0] = 1 0000 - 78.3 - dBµV

W9[4:0] = 1 1111 - 98.5 - dBµV

αacc(set)TOP1 TOP1 setting accuracy −2 - +2 dB

Isource source current TAGC charge current

W9[5] = 0 0.20 0.33 0.45 µA

W9[5] = 1 1.6 2.5 3.4 µA

fast mode activated by

internal level detector;

W9[5] = 0

71115µA

fast mode activated by

internal level detector;

W9[5] = 1

60 90 120 µA

Isink sink current TAGC discharge current;

VTAGC =1V 375 500 625 µA

∆αacc(set)TOP1/∆T TOP1 setting accuracy

variation with temperature W9[4:0] = 1 0000 - 0.006 0.02 dB/K

RLload resistance [3] 50 - - MΩ

Vsat(u) upper saturation voltage pin operating as current

output VP−0.3 - - V

Vsat(l) lower saturation voltage pin operating as current

output - - 0.3 V

αth(fast)AGC AGC fast mode threshold activated by internal fast

AGC detector; I2C-bus

setting corresponds to

W9[4:0] = 1 0000

[3] 6 8 10 dB

tddelay time before activating; Vi(IF)

below αth(fast)AGC

40 60 80 ms

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 48 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

TAGC loop based on VIFAGC (W6[7:6] = 11); TAGC is voltage output; applicable for TV mode: positive modulation and

optional for negative modulation); see Table 47,Figure 13 and Figure 14

Vi(IF)(RMS) RMS IF input voltage for TOP2; at starting point

of tuner AGC takeover;

VTAGC = 3.5 V

RTOP2 =22kΩ or

W10[5:0] = 00 0000 - 56.9 - dBµV

RTOP2 =10kΩ or

W10[5:0] = 01 0000 - 78.5 - dBµV

RTOP2 =0kΩ-98-dBµV

W10[5:0] = 01 1111 - 99 - dBµV

αacc(set)TOP2 TOP2 setting accuracy −8 - +8 dB

∆αacc(set)TOP2/∆T TOP2 setting accuracy

variation with temperature VTAGC = 3.5 V - 0.03 0.07 dB/K

VOoutput voltage no tuner gain reduction 4.5 - VPV

maximum tuner gain

reduction 0.2 - 0.6 V

∆Gslip(TAGC) TAGC slip gain offset tuner gain voltage from

0.6 V to 3.5 V 35 8dB

TOP adjust 2; pin TOP2; IF based TAGC loop mode; see Figure 14

VTOP2 voltage on pin TOP2 (DC) pin open-circuit - 3.5 - V

RIinput resistance - 27 - kΩ

RTOP2 resistance on pin TOP2 adjustment of VIFAGC

based TAGC loop

W10[5] = 1; external

resistor operation 0 - 22 kΩ

W10[5] = 0; forced

I2C-bus operation 100 - - kΩ

Pin CTAGC

VCTAGC voltage on pin CTAGC [3] 0.2 - 0.55VPV

ILleakage current sink or source [3] - - 10 nA

ROoutput resistance equivalent time constant

resistance [3] -10-MΩ

Pin MPP output characteristic

General

Vsat(u) upper saturation voltage VP−0.8 VP−0.5 - V

Vsat(l) lower saturation voltage - 0.5 0.8 V

Io(max) maximum output current sink or source [3] 350 - - µA

ROoutput resistance [3] - 1.3 3 kΩ

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 49 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

AGC monitor (voltage output)

Gvvoltage gain voltage on pin MPP to

internal control voltage;

see Table 31

[17]

VIFAGC; see Figure 12 -6 -dB

SIFAGC; see Figure 16 -6 -dB

FM AGC; see Figure 15 -6 -dB

TAGC; see Figure 12 -0 -dB

AFC monitor (current output)

Iooutput current sink or source;

see Figure 17 and

Figure 18

[18][19]

100 kHz VIF deviation 80 - 160 µA

200 kHz VIF deviation 160 200 240 µA

1.5 MHz VIF deviation 160 - 240 µA

AFC TV mode

∆IAFC/∆fVIF change of AFC current with

VIF frequency [19] 0.85 1.05 1.25 µA/kHz

fVIFacc(dig) digital accuracy of VIF

frequency read-out via I2C-bus;

R1[4:1] = f0; fref = 4 MHz [20] −20 - +20 kHz

fVIFacc(a) analog accuracy of VIF

frequency IAFC = 0 A; fref = 4 MHz [20] −20 - +20 kHz

AFC radio mode

∆IAFC/∆fRIF change of AFC current with

RIF frequency [19] 0.85 1.05 1.25 µA/kHz

fRIFacc(dig) digital accuracy of RIF

frequency read-out via I2C-bus;

R1[4:1] = f0; fref = 4 MHz [20] −10 - +10 kHz

fRIFacc(a) analog accuracy of RIF

frequency IAFC = 0 A; fref = 4 MHz [20] −10 - +10 kHz

Pin PORT1 or pin PORT3 operating as voltage monitor

Vsat(u) upper saturation voltage VP−0.8 VP−0.5 - V

Vsat(l) lower saturation voltage - 0.5 0.8 V

Io(max) maximum output current sink or source [3] 10 - - µA

ROoutput resistance [3] - 1.3 3 kΩ

Gvvoltage gain voltage ratio: pin PORT1

to internal VIF AGC

voltage

[3][17] -6 -dB

voltage ratio: pin PORT3

to internal TAGC voltage [3][17] -0 -dB

SIF ampliﬁer; pins IF1A and IF1B or pins IF2A and IF2B or pins IF3A and IF3B

VIinput voltage - 1.95 - V

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 50 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Ri(dif) differential input resistance - 2 - kΩ

Ci(dif) differential input

capacitance -3 -pF

Vi(SIF)(RMS) RMS SIF input voltage FM mode; −3 dB at

intercarrier output

pins OUT1A and OUT1B;

without FM AGC;

see Table 21

- 60 100 µV

AM mode; −3 dB at

AF output pin AUD -4070µV

FM mode; +1 dB at

intercarrier output

pins OUT1A and OUT1B;

without FM AGC;

see Table 21

150 190 - mV

AM mode; +1 dB at

AF output pin AUD 70 140 - mV

permissible overload - - 320 mV

GSIF(cr) control range SIF gain FM and AM mode 60 66 - dB

f−3dB(SIF)l lower SIF cut-off frequency - 7 - MHz

f−3dB(SIF)u upper SIF cut-off frequency - 80 - MHz

SIF AGC detector; pin MPP; see Figure 16

tresp response time increasing or decreasing

SIF step of 20 dB;

AM mode; fast AGC

increasing - 8 - ms

decreasing - 10 - ms

increasing or decreasing

SIF step of 20 dB;

AM mode; slow AGC

increasing - 65 - ms

decreasing - 125 - ms

increasing or decreasing

SIF step of 20 dB;

FM mode; normal AGC

increasing - 0.09 - ms

decreasing - 28 - ms

increasing or decreasing

SIF step of 20 dB;

FM mode; fast AGC

increasing - 0.03 - ms

decreasing - 4 - ms

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 51 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

VAGC(SIF) SIF AGC voltage FM mode

VSIF = 100 µV 1.2 - 2.1 V

VSIF = 10 mV 2.4 - 3.2 V

VSIF = 140 mV 3.1 - VPV

AM mode

VSIF = 100 µV 1.4 - 2.3 V

VSIF = 10 mV 2.6 - 3.4 V

VSIF = 70 mV 3.2 - VPV

Conversion synthesizer PLL; pin LFSYN2 (radio mode)

VLFSYN2 voltage on pin LFSYN2 1 - 3 V

KOVCO steepness ∆fVCO /∆VLFSYN2 - 31 - MHz/V

KDphase detector steepness ∆ILFSYN2 /∆ϕVCO;

see Table 57;

fVCO selection:

22 MHz to 29.5 MHz - 32 - µA/rad

30 MHz to 37.5 MHz - 38 - µA/rad

38 MHz to 45.5 MHz - 47 - µA/rad

46 MHz to 53.5 MHz - 61 - µA/rad

57 MHz - 61 - µA/rad

Io(PD) phase detector output

current sink or source;

fVCO selection:

22 MHz to 29.5 MHz - 200 - µA

30 MHz to 37.5 MHz - 238 - µA

38 MHz to 45.5 MHz - 294 - µA

46 MHz to 53.5 MHz - 384 - µA

57 MHz - 384 - µA

ϕn(synth) synthesizer phase noise with 4 MHz crystal

oscillator reference;

fsynth = 31 MHz;

fIF =36MHz

at 1 kHz [3] 89 99 - dBc/Hz

at 10 kHz [3] 89 99 - dBc/Hz

at 100 kHz [3] 98 102 - dBc/Hz

at 1.4 MHz [3] 115 119 - dBc/Hz

αsp spurious suppression multiple of ∆f = 500 kHz [3] 50 - - dBc

ILleakage current synthesizer spurious

performance > 50 dBc [3] - - 10 nA

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 52 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

PSRR power supply ripple

rejection residual spurious at

nominal differential output

voltage dependent on

power supply ripple at

70 Hz; see Figure 11

-50-dB

Single reference QSS intercarrier mixer; pins OUT1A and OUT1B

VOUT1A voltage on pin OUT1A (DC) 1.8 2.0 2.2 V

VOUT1B voltage on pin OUT1B (DC) 1.8 2.0 2.2 V

Ibias(int) internal bias current (DC) for emitter-follower 2.0 2.5 - mA

Isink(o)(max) maximum output sink

current DC and AC 1.4 1.7 - mA

Isource(o)(max) maximum output source

current DC and AC; with external

resistor to GND 3.0 - - mA

ROoutput resistance output active;

single-ended to GND -- 25Ω

output inactive; internal

resistance to GND - 800 - Ω

Vo(RMS) RMS output voltage IF intercarrier

single-ended to GND;

B/G standard;

SC1 on; SC2 off;

see Figure 9 and Table 21

internal BP via FM AGC 90 140 180 mV

internal BP 90 170 230 mV

IF intercarrier

single-ended to GND;

L standard;

without modulation;

see Figure 9 and Table 21

W7[5] = 0;

internal BP + 6 dB 90 140 180 mV

W7[5] = 1;

internal BP + 6 dB 45 70 90 mV

W7[5] = 0; internal BP 45 70 90 mV

W7[5] = 1; internal BP 20 35 45 mV

f−3dB(ic)u upper intercarrier cut-off

frequency internal sound band-pass

off 11 15 - MHz

αimage image rejection band-pass off;

−8 MHz to 0 MHz 24 28 - dB

Vinterf(RMS) RMS interference voltage fundamental wave and

harmonics -2 5mV

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 53 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

AM intercarrier from pin EXTFILI to pins OUT1A and OUT1B

G gain IF intercarrier; L standard;

without modulation -5 -dB

Band-pass mode

fccenter frequency QSS mode;

BP selection for standard

M/N - 4.7 - MHz

B/G - 5.75 - MHz

I - 6.25 - MHz

D/K - 6.25 - MHz

L/L-accent - 6.05 - MHz

radio mode;

BP selection for standard

M/N - 4.7 - MHz

B/G - 5.75 - MHz

I - 6.25 - MHz

D/K - 6.25 - MHz

f−3dB(BP)u upper BP cut-off frequency fc+ 0.5 fc+ 0.65 fc+ 0.8 MHz

f−3dB(BP)l lower BP cut-off frequency fc−0.5 fc−0.65 fc−0.8 MHz

αstpb stop-band attenuation 20 30 - dB

αCC color carrier attenuation QSS mode;

BP selection for standard

M/N; fCC = 3.58 MHz 15 23 - dB

B/G; fCC = 4.43 MHz 22 30 - dB

I; fCC = 4.43 MHz 20 28 - dB

D/K; fCC = 4.28 MHz 20 28 - dB

L/L-accent;

fCC = 4.28 MHz 20 28 - dB

External ﬁlter output; pin EXTFILO

VEXTFILO voltage on pin EXTFILO

(DC) 1.8 2.0 2.2 V

VEXTFILO(p-p) peak-to-peak voltage on

pin EXTFILO IF intercarrier; SC1 on;

SC2 off 420 620 820 mV

IF intercarrier; L standard;

without modulation

W7[5] = 0 210 310 410 mV

W7[5] = 1 105 155 205 mV

Io(max) maximum output current AC and DC 1 - - mA

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 54 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

FM PLL demodulator

fFMPLL FM PLL frequency see Table 18 and Table 20 - 4.5 - MHz

- 5.5 - MHz

- 6.0 - MHz

- 6.5 - MHz

- 10.7 - MHz

FM PLL ﬁlter; pin LFFM

VLFFM voltage on pin LFFM fFMPLL = 4.5 MHz 1.5 1.9 3.3 V

fFMPLL = 5.5 MHz 1.5 2.2 3.3 V

fFMPLL = 6.0 MHz 1.5 2.35 3.3 V

fFMPLL = 6.5 MHz 1.5 2.5 3.3 V

fFMPLL = 10.7 MHz 1.5 2.3 3.3 V

Tcy(dah) digital acquisition help

cycle time -64-µs

tw(dah) digital acquisition help

pulse width -16-µs

Io(dah) digital acquisition help

output current sink or source

W3[4] = 0; W6[3] = 0;

FM window

width = 237.5 kHz

14 18 22 µA

W3[4] = 1; W6[3] = 0;

FM window

width = 475 kHz

28 36 44 µA

W3[4] = 0; W6[3] = 1;

FM window

width = 1 MHz

14 18 22 µA

W3[4] = 1; W6[3] = 1;

FM window

width = 1 MHz

28 36 44 µA

KD(FM) FM phase detector

steepness ∆IFMPLL /∆ϕVCO(FM)

W3[4] = 0; W6[3] = 0;

FM window

width = 237.5 kHz

- 5.5 - µA/rad

W3[4] = 1; W6[3] = 0;

FM window

width = 475 kHz

- 14.5 - µA/rad

W3[4] = 0; W6[3] = 1;

FM window

width = 1 MHz

- 5.5 - µA/rad

W3[4] = 1; W6[3] = 1;

FM window

width = 1 MHz

- 14.5 - µA/rad

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 55 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

KO(FM) FM VCO steepness ∆fFMPLL /∆VLFFM

f < 10 MHz - 3.3 - MHz/V

f = 10.7 MHz - 5.9 - MHz/V

Ioffset(FM) FM offset current W6[3] = 0; W3[4] = 0 −1.5 0 +1.5 µA

W6[3] = 0; W3[4] = 1 −2.5 0 +2.5 µA

FM intercarrier input; pins EXTFMI and EXTFILI; see Figure 9

|Zi|input impedance AC-coupled via 4 pF - 20 - kΩ

Vi(FM)(RMS) RMS FM input voltage gain controlled operation;

W1[1:0] = 10 or

W1[1:0] = 11 or

W1[1:0] = 01

2 - 300 mV

Vlock(min)(RMS) RMS minimum lock-in

voltage W1[1:0] = 10 or

W1[1:0] = 11 or

W1[1:0] = 01

- - 1.5 mV

Vdet(FM)min(RMS) RMS minimum FM carrier

detection voltage W1[1:0] = 10 or

W1[1:0] = 11 or

W1[1:0] = 01

- - 1.8 mV

FM demodulator part; audio output; pin AUD

Vo(AF)(RMS) RMS AF output voltage QSS mode;

25 kHz FM deviation;

75 µs de-emphasis

400 500 600 mV

QSS mode;

27 kHz FM deviation;

50 µs de-emphasis

430 540 650 mV

QSS mode;

55 kHz FM deviation;

50 µs de-emphasis

900 - 1300 mV

radio mode;

22.5 kHz FM deviation;

75 µs de-emphasis

360 450 540 mV

∆Vo(AF)/∆T AF output voltage variation

with temperature - 1.1 ×10−37×10−3dB/K

THD total harmonic distortion 50 µs de-emphasis;

FM deviation: for

TV mode 27 kHz and for

radio mode 22.5 kHz

- 0.15 0.50 %

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 56 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

∆fAF(max) maximum AF frequency

deviation THD < 2 %; pre-emphasis

off; fAF = 400 Hz [21]

W3[1:0] = 00 (audio

gain = 0 dB) ±55 - - kHz

W3[1:0] = 01 (audio

gain = −6 dB) ±110 - - kHz

W3[1:0] = 10 (audio

gain = −12 dB) ±170 - - kHz

W3[1:0] = 11 (audio

gain = −18 dB) and

W3[4] = 1 (FM window

width = 475 kHz)

±380 - - kHz

fAF(max) maximum AF frequency THD < 2 %;

pre-emphasis off [3]

FM window

width = 237.5 kHz;

−6 dB audio gain;

FM deviation 100 kHz

15 - - kHz

FM window

width = 475 kHz;

−18 dB audio gain;

FM deviation 300 kHz

15 - - kHz

f−3dB(AF) AF cut-off frequency W3[2] = 0; W3[4] = 0;

without de-emphasis;

FM window

width = 237.5 kHz

80 100 - kHz

(S/N)w(AF) AF weighted

signal-to-noise ratio 27 kHz FM deviation;

50 µs de-emphasis; vision

carrier unmodulated;

FM PLL only;

“ITU-R BS.468-4”

48 56 - dB

(S/N)unw(AF) AF unweighted

signal-to-noise ratio radio mode (10.7 MHz);

22.5 kHz FM deviation;

75 µs de-emphasis

-58-dB

VSC(rsd)(RMS) RMS residual sound carrier

voltage fundamental wave and

harmonics; without

de-emphasis

-- 2mV

αAM AM suppression referenced to 27 kHz

FM deviation;

50 µs de-emphasis;

AM: f = 1 kHz; m = 54 %

35 46 - dB

PSRR power supply ripple

rejection fripple =70Hz;

see Figure 11 14 20 - dB

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 57 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Audio ampliﬁer

Audio output; pin AUD

ROoutput resistance [3] - - 300 Ω

VOoutput voltage 2.0 2.4 2.7 V

RLload resistance AC-coupled [3] 10 - - kΩ

DC-coupled [3] 100 - - kΩ

CLload capacitance [3] -- 1nF

Vo(AF)(RMS) RMS AF output voltage 25 kHz FM deviation;

75 µs de-emphasis;

see Table 27

0 dB 400 500 600 mV

−6 dB - 250 - mV

−12 dB - 125 - mV

−18 dB - 62.5 - mV

AM; m = 54 %;

see Table 27

0 dB 400 500 600 mV

−6 dB - 250 - mV

f−3dB(AF)u upper AF cut-off frequency W3[2] = 0 (without

de-emphasis) [22] - 150 - kHz

f−3dB(AF)l lower AF cut-off frequency W3[2] = 0 (without

de-emphasis) [23] -20-Hz

αmute mute attenuation of AF signal 70 - - dB

∆Vjmp jump voltage difference

(DC) switching AF output to

mute state or vice versa;

activated by digital

acquisition help W3[6] = 1

or via W3[5]

-±50 ±150 mV

PSRR power supply ripple

rejection fripple =70Hz;

see Figure 11 14 20 - dB

De-emphasis network; pin CDEEM

VOoutput voltage - 2.4 - V

ROoutput resistance W3[3:2] = 11 (50 µs

de-emphasis) 8.5 - 14 kΩ

W3[3:2] = 01 (75 µs

de-emphasis) 13 - 21 kΩ

VAF(RMS) RMS AF voltage fAF = 400 Hz;

Vo(AF) = 500 mV (RMS);

0 dB attenuation

- 170 - mV

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 58 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

AF decoupling

Pin CAF

Vdec decoupling voltage (DC) fFMPLL = 4.5 MHz 1.5 1.9 3.3 V

fFMPLL = 5.5 MHz 1.5 2.2 3.3 V

fFMPLL = 6.0 MHz 1.5 2.35 3.3 V

fFMPLL = 6.5 MHz 1.5 2.5 3.3 V

fFMPLL = 10.7 MHz 1.5 2.3 3.3 V

ILleakage current ∆VAUD <±50 mV (p-p);

0 dB attenuation -- ±25 nA

Io(max) maximum output current sink or source 1.15 1.5 1.85 µA

FM operation[24][25]

Single reference QSS AF performance; pin AUD[26]

(S/N)w(SC1) ﬁrst sound carrier weighted

signal-to-noise ratio PC / SC1 > 40 dB at

pins IF1A and IF1B or

IF2AandIF2B;27 kHz FM

deviation; BP off;

“ITU-R BS.468-4”

black picture 45 50 - dB

white picture 45 50 - dB

6 kHz sine wave

(black-to-white

modulation)

43 47 - dB

250 kHz square wave

(black-to-white

modulation)

45 50 - dB

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 59 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Single reference QSS AF performance with external FM demodulator connected to OUT1A and OUT1B[27]

(S/N)w(SC1) ﬁrst sound carrier weighted

signal-to-noise ratio PC / SC1 > 40 dB at

pins IF1A and IF1B or

IF2A and IF2B; 27 kHz

FM deviation; BP off;

“ITU-R BS.468-4”

black picture 53 58 - dB

white picture 50 53 - dB

6 kHz sine wave

(black-to-white

modulation)

44 48 - dB

250 kHz square wave

(black-to-white

modulation)

40 45 - dB

sound carrier

subharmonics;

f = 2.75 MHz ±3 kHz

45 51 - dB

sound carrier

subharmonics;

f = 2.87 MHz ±3 kHz

46 52 - dB

(S/N)w(SC2) second sound carrier

weighted signal-to-noise

ratio

with external reference

FM demodulator;

PC / SC2 > 40 dB at

pins IF1A and IF1B or

IF2A and IF2B; 27 kHz

(54 % FM deviation);

BP off;

“ITU-R BS.468-4”

black picture 48 55 - dB

white picture 46 51 - dB

6 kHz sine wave

(black-to-white

modulation)

42 46 - dB

250 kHz square wave

(black-to-white

modulation)

29 34 - dB

sound carrier

subharmonics;

f = 2.75 MHz ±3 kHz

44 50 - dB

sound carrier

subharmonics;

f = 2.87 MHz ±3 kHz

45 51 - dB

AM operation

L standard; pin AUD

Vo(AF)(RMS) RMS AF output voltage 54 % modulation 400 500 600 mV

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 60 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

THD total harmonic distortion 54 % modulation; BP on;

see Figure 33 - 0.5 1.0 %

BAF(−3dB) −3 dB AF bandwidth 12 18 - kHz

(S/N)w(AF) AF weighted

signal-to-noise ratio

“ITU-R BS.468-4”

BP on 38 42 - dB

BP off 44 50 - dB

composite IF;

PC / SC = 10 dB; VIF

modulation = color bar;

“ITU-R BS.468-4”

;

SAW ﬁlter application

see Figure 47; BP on

-40-dB

Reference frequency

General

fref reference frequency [28] -4 -MHz

Reference frequency generation with crystal; pin OPTXTAL

VOPTXTAL voltage on pin OPTXTAL

(DC) pin open-circuit 2.3 2.6 2.9 V

Riinput resistance [3] -2 -kΩ

Rrsn(xtal) crystal resonance

resistance - - 200 Ω

Cpull pull capacitance [29] -- -pF

Rswoff(OPTXTAL) switch-off resistance on pin

OPTXTAL to switch off crystal input

by external resistor wired

between pin OPTXTAL

and GND

0.22 - 4.7 kΩ

Iswoff switch-off current Rswoff(OPTXTAL) = 0.22 kΩ- - 5000 µA

Rswoff(OPTXTAL) = 3.3 kΩ- 500 - µA

Reference frequency input from external source; pin OPTXTAL

VOPTXTAL voltage on pin OPTXTAL

(DC) pin open-circuit 2.3 2.6 2.9 V

Riinput resistance [3] -2 -kΩ

Vref(RMS) RMS reference voltage 80 - 400 mV

ROoutput resistance of external reference

signal source [3] - 2 4.7 kΩ

Cdec decoupling capacitance to external reference

signal source [3] 22 100 - pF

Reference frequency input from external source; pin FREF

VFREF voltage on pin FREF (DC) pin open-circuit 2.2 2.5 2.8 V

Riinput resistance [3] 50 - - kΩ

fref reference frequency [28] -4 -MHz

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 61 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Vref(RMS) RMS reference voltage see Figure 34 15 150 500 mV

ROoutput resistance of external reference

signal source; AC-coupled - - 4.7 kΩ

Cdec decoupling capacitance to external reference

signal source 22 100 - pF

Rswoff(FREF) switch-off resistance on

pin FREF to switch off reference

signal input by external

resistor wired between

pin FREF and GND

3.9 - 27 kΩ

Iswoff switch-off current Rswoff(FREF) = 3.9 kΩ- - 100 µA

Rswoff(FREF) =22kΩ-25-µA

Group delay select; pin GDS; see Figure 24 and Table 50

VGDS voltage on pin GDS pin open-circuit - VP-V

Isink(I) input sink current pin connected to VP-- 1µA

Isource(I) input source current pin connected to GND - - 72 µA

VIinput voltage GDEQ on; W11[2] = 0;

pin connected to GND 0 - 0.46VPV

GDEQ on; W11[2] = 1;

pin open-circuit 0.58VP-V

GDEQ off; W11[2] = 1;

pin connected to GND 0 - 0.46VPV

GDEQ off; W11[2] = 0;

pin open-circuit 0.58VP-V

I2C-bus transceiver[30]

Address select; pin ADRSEL

VADRSEL voltage on pin ADRSEL

(DC) pin open-circuit - 0.5VP-V

for address select

MAD1; pin connected to

GND 0 - 0.04VPV

MAD3; pin connected to

GND via RADRSEL

0.20VP- 0.34VPV

MAD4; pin connected to

VP via RADRSEL

0.66VP- 0.80VPV

MAD2; pin connected to

0.96VP-V

Riinput resistance [3] -31-kΩ

RADRSEL resistance on pin ADRSEL 42.3 47 51.7 kΩ

I2C-bus voltage select; pin BVS

VBVS voltage on pin BVS (DC) pin open-circuit - 0.52VP-V

Isink(I) input sink current pin connected to VP-- 10µA

Isource(I) input source current pin connected to GND - - 60 µA

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 62 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] Values of video and sound parameters can be decreased at VP= 4.5 V.

[2] Condition for secure POR is a rise or fall time greater than 2 µs.

[3] This parameter is not tested during the production and is only given as application information for designing the receiver circuit.

[4] Level headroom for input level jumps during gain control setting.

VIinput voltage VCC(I2C-bus) = 5.0 V;

pin connected to VP

0.88VP-V

VCC(I2C-bus) = 3.3 V;

pin open-circuit 0.46VP- 0.58VPV

VCC(I2C-bus) = 2.5 V;

pin connected to GND 0 - 0.12VPV

I2C-bus transceiver; pins SCL and SDA[31]

VIH HIGH-level input voltage VCC(I2C-bus) = 5.0 V [32] 0.6VP-V

VCC(I2C-bus) = 3.3 V [33] 2.3 - VPV

VCC(I2C-bus) = 2.5 V [33] 1.75 - VPV

VIL LOW-level input voltage VCC(I2C-bus) = 5.0 V [32] −0.3 - +0.3VPV

VCC(I2C-bus) = 3.3 V [33] −0.3 - +1.0 V

VCC(I2C-bus) = 2.5 V [33] −0.3 - +0.75 V

IIH HIGH-level input current −10 - +10 µA

IIL LOW-level input current −10 - +10 µA

VOL LOW-level output voltage IOL = 3 mA; for data

transmission (SDA) - - 0.4 V

fSCL SCL clock frequency 0 - 400 kHz

Pins PORT1 or PORT2 or PORT3 operating as open-collector output port

VOL LOW-level output voltage I = 2 mA (sink) - - 0.4 V

Isink(o) output sink current PORT1

W7[3] = 0 - - 3 mA

W7[3] = 1 - - 10 µA

PORT2; W8[7] = 1

W8[1] = 0 - - 3 mA

W8[1] = 1 - - 10 µA

PORT3; W8[7] = 1

W8[2] = 0 - - 3 mA

W8[2] = 1 - - 10 µA

VOH HIGH-level output voltage - - VP+ 0.5 V

Table 53. Characteristics

…continued

=5V; T

amb

=25

C; see Table 24 for input frequencies; B/G standard is used for the speciﬁcation (f

= 38.375 MHz;

= 32.875 MHz; PC / SC = 13 dB; f

= 400 Hz); input level V

i(IF)

= 10 mV (RMS) (sync level for B/G; peak white level

for L); IF input from 50

Ω

via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for

B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;

internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 63 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[5] BLF(−3dB) = 100 kHz (damping factor d = 1.7; calculated with sync level within gain control range). Calculation of the VIF PLL ﬁlter by

using the following formulae:

, valid for d ≥1.2

with the following parameters:

KO= VCO steepness (Hz/V),

KD= phase detector steepness (A/rad),

R = loop ﬁlter serial resistor (Ω),

C = loop ﬁlter serial capacitor (F),

BLF(−3dB) =−3 dB LF bandwidth (Hz),

d = damping factor.

[6] The VCO frequency offset related to the PC frequency is set to 1 MHz with white picture video modulation.

[7] AC load; CL< 20 pF and RL>1kΩ. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound

carrier traps.

[8] Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps.

[9] Measurement using 200 kHz high-pass ﬁlter, 5 MHz low-pass ﬁlter and subcarrier notch ﬁlter (

“ITU-T J.64”

[10] Modulation VSB; sound carrier off; fvideo > 0.5 MHz.

[11] Sound carrier on; fvideo = 10 kHz to 10 MHz.

[12] The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 23. In this way the full composite video

spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p).

[13] Measurement condition: with transformer, transmitter pre-correction on; reference is at 1 MHz.

[14] The response time is valid for a VIF input level range from 200 µVto70mV.

[15] AGC response time increased if no AGC event occurs during two lines at minimum.

[16] AGC response time increased if video level falls below half of selected level.

[17] Load applied to output pin causes signal loss. The resulting gain can be calculated by using .

[18] See Figure 19 to smooth current pulses.

[19] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The

AFC steepness can be changed by different applications of resistors R1 and R2.

[20] The AFC value of the VIF and RIF frequency is generated by using digital counting methods. The used counter resolution is provided

with an uncertainty of ±1 bit corresponding to ±25 kHz. This uncertainty of ±25 kHz has to be added to the frequency accuracy

parameter.

[21] Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The audio signal processing stage

provides headroom of 6 dB with THD < 1.5 %. The I2C-bus bits W3[0] and W3[1] control the AF output signal amplitude from

0dBto−18 dB in steps of −6 dB. Reducing the audio gain for handling a frequency deviation of more than 55 kHz avoids AF output

signal clipping.

[22] Amplitude response depends on dimensioning of FM PLL loop ﬁlter.

[23] The lower AF cut-off frequency depends on the value of the capacitor at pin CAF. A value of CAF1 = 470 nF leads to f−3dB(AF)l ≈20 Hz

and CAF1 = 220 nF leads to f−3dB(AF)l ≈40 Hz.

[24] For all signal-to-noise measurements the used VIF modulator has to meet the following speciﬁcations:

a) Incidental phase modulation for black-to-white jump less than 0.5 degrees.

b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted signal-to-noise ratio) better than

60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation.

c) Picture-to-sound carrier ratio PC / SC1 = 13 dB (transmitter).

[25] The PC / SC ratio is calculated as the addition of TV transmitter PC / SC1 ratio and SAW ﬁlter PC / SC1 ratio. This PC / SC ratio is

necessary to achieve the weighted signal-to-noise values as noted. A different PC / SC ratio will change these values.

[26] Measurement condition is SC1 / SC2 ≥7dB.

[27] The differential QSS signal output on pins OUT1A and OUT1B is analyzed by a test demodulator TDA9820. The signal-to-noise ratio of

this device is better than 60 dB. The measurement is related to an FM deviation of ±27 kHz and in accordance with

“ITU-R BS.468-4”

BLF 3dB–()

KOKDR=

---R2πKOKDC=

Gv(load) Gv20 RL

RORL

--------------------





log+=

Product data sheet Rev. 04 — 25 May 2009 64 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[28] The tolerance of the reference frequency determines the accuracy of VIFAFC, RIFAFC, FM demodulator center frequency, maximum

FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.

[29] The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.

[30] The AC characteristics are in accordance with the I2C-bus speciﬁcation for fast mode (maximum clock frequency is 400 kHz).

Information about the I2C-bus can be found in the brochure

“The I2C-bus and how to use it”

(order number 9398 393 40011).

[31] The SDA and SCL lines will not be pulled down if VP is switched off.

[32] The threshold is dependent on VP.

[33] The threshold is independent of VP.

Table 54. Examples to the FM PLL ﬁlter

BLF(−3dB) (kHz) Cs (nF) Cpar (pF) Rs (kΩ) Comment

200 2.2 100 8.2 recommended for single-carrier-sound, FM narrow

410 2.2 47 5.6 recommended for single-carrier-sound, FM wide

110 2.2 470 5.6 recommended for two-carrier-sound, FM narrow

210 2.2 47 8.2 used for test circuit

Table 55. Input frequencies and carrier ratios (examples)

Symbol Parameter B/G standard M/N standard L standard L-accent standard Unit

fPC picture carrier frequency 38.375 38.375 38.375 33.625 MHz

fSC1 sound carrier frequency 1 32.825 33.825 31.825 40.125 MHz

fSC2 sound carrier frequency 2 32.583 - - - MHz

PC / SC1 picture to ﬁrst sound carrier ratio 13 7 10 10 dB

PC / SC2 picture to second sound carrier ratio 20 - - - dB

Fig 10. Typical video signal levels on output pin CVBS (sound carrier off)

1.20 V

1.80 V

3.20 V white level

3.41 V

1.5 V

2.72 V

2.6 V

1.83 V

zero carrier level

black level

sync level

001aaj651

trap bypass mode

normal mode 2.0 V

1.2 V

3.08 V

2.9 V

1.71 V

normal mode 1.7 V

Product data sheet Rev. 04 — 25 May 2009 65 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Fig 11. Ripple rejection condition

(1) VIF AGC.

(2) TAGC; W10 = 00h.

(3) TAGC; W10 = 10h.

(4) TAGC; W10 = 1Fh.

Fig 12. Typical VIF monitor and TAGC characteristic

001aae391

TDA9897

TDA9898

V = VP + Vripple

VP (V)

5.050

5.000

4.950

t (s)

001aaj590

Vi(VIF) (dBµV)

30 13011070 9050

VTAGC

(V)

(3)(2)(1) (4)

Vmonitor(VIFAGC)

(V)

Product data sheet Rev. 04 — 25 May 2009 66 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Fig 13. Typical tuner takeover point as a function of I2C-bus register W9 or W10

(1) IF based TAGC (TOP2).

Fig 14. Typical tuner takeover point as a function of resistor RTOP2

bit pattern W9[4:0] or W10[4:0]

001aaj591

100

Vi(IF)

(dBµV)

Integral TAGC (W9); step width: 1.255 dB typical.

IF based TAGC (W10).

RTOP2 (kΩ)

0252010 155

001aaj592

100

Vi(IF)

(dBµV)

(1)

Product data sheet Rev. 04 — 25 May 2009 67 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) AM.

(2) FM.

Fig 15. Typical FM AGC characteristic measured at

pin MPP Fig 16. Typical SIF AGC characteristic measured at

pin MPP

001aaj593

Vi(EXTFMI) (dBµV)

40 12010060 80

VAGC(FM)

(V)

001aaj594

Vi(SIF) (dBµV)

20 12010060 8040

VAGC(SIF)

(V)

(1) (2)

Product data sheet Rev. 04 — 25 May 2009 68 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) VIF AFC via I2C-bus; accuracy is ±1 digit.

(2) Bit AFCWIN via I2C-bus (VCO is in ±1.6 MHz window) for all standards except M/N standard.

(3) Bit AFCWIN via I2C-bus (VCO is in ±0.8 MHz window) for M/N standard.

(4) VIF AFC average current.

(5) Reading via I2C-bus.

(6) Average; RC network at pin MPP.

Fig 17. Typical analog and digital AFC characteristic for VIF

008aaa035

−50

−150

150

250

−250

−50

−150

150

250

IAFC(6)

(µA)

−250

fVIF (MHz)

36.375 40.37539.87537.875 38.87537.37536.875 38.375 39.375

bit AFCWIN (R1[7]) = 1

(1)

(4)

(2)

(3)

∆fAFC(VIF)(5)

(kHz)

Characteristics of digital and analog radio AFC is mirrored with respect to center frequency when lower sideband is used

(W2[3] = 0).

(1) RIF AFC via I2C-bus.

(2) FM carrier detection via I2C-bus.

(3) RIF AFC average current.

(4) Reading via I2C-bus.

(5) Average; RC network at pin MPP.

Fig 18. Typical analog and digital AFC characteristic for RIF

001aad443

0 0

−50

−150

150

250

IAFC(5)

(µA)

−250

fRIF (MHz)

5.0 6.05.85.4 5.65.2

AFC undefinedAFC undefined bit CARRDET (R1[5]) = 1

(1)

(3)

(2)

−50

−150

150

250

∆fAFC(RIF)(4)

(kHz)

−250

Product data sheet Rev. 04 — 25 May 2009 69 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Fig 19. RC network for measurement of analog AFC characteristic

(1) B/G standard; weighted video S/N; using 50 % grey picture.

(2) M/N standard; unweighted video S/N; using 50 IRE grey picture.

Fig 20. Typical signal-to-noise ratio as a function of VIF input voltage

008aaa152

100 nF

22 kΩ

MPP IAFC

TDA9897

TDA9898

Vi(VIF) (dBµV)

50 1009070 8060

001aaj595

S/N

(dB)

(1)

(2)

Product data sheet Rev. 04 — 25 May 2009 70 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Minimum requirements upper limit.

(2) Minimum requirements lower limit.

(3) Typical trap amplitude frequency response.

Fig 21. Typical amplitude frequency response for sound trap at M/N standard (including

Korea)

(1) Minimum requirements upper limit.

(2) Minimum requirements lower limit.

(3) Typical trap group delay response.

Fig 22. Typical group delay response for sound trap at M/N standard

001aaj556

f (MHz)

0135642

−25

−15

−35

−5

−10

αresp(f)

(dB)

−45

−20

−30

−40

(1)

(2) (3)

f (MHz)

0 621453

td(grp)

(ns)

−50

−100

−150

−200

150

100

250

200

−250

(1)

(2)

001aaj555

(3)

Product data sheet Rev. 04 — 25 May 2009 71 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Minimum requirements upper limit.

(2) Minimum requirements lower limit.

(3) Typical trap amplitude frequency response.

Fig 23. Typical amplitude frequency response for sound trap at B/G standard

(1) Minimum requirements upper limit (valid for GDEQ off).

(2) Minimum requirements lower limit (valid for GDEQ off).

(3) Typical trap group delay response; GDEQ off.

(4) Typical trap group delay response; GDEQ on.

(5) Typical group delay response of additional group delay equalizer (difference of curves 3 and 4).

Fig 24. Typical group delay response for sound trap at B/G standard

001aaj557

f (MHz)

0 86427531

−25

−15

−35

−5

αresp(f)

(dB)

−45

−20

−10

−30

−40

(1)

(3)

(2)

f (MHz)

0 621453

td(grp)

(ns)

−50

−100

−150

−200

150

100

250

200

−250

(1)

(5)

(4)

(3)

(2)

001aaj554

Product data sheet Rev. 04 — 25 May 2009 72 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Minimum requirements upper limit.

(2) Minimum requirements lower limit.

(3) Typical trap amplitude frequency response.

Fig 25. Typical amplitude frequency response for sound trap at I standard

(1) Minimum requirements upper limit.

(2) Minimum requirements lower limit.

(3) Typical trap group delay response.

Fig 26. Typical group delay response for sound trap at I standard

001aaj553

f (MHz)

0 86421753

−25

−15

−35

−5

αresp(f)

(dB)

−45

−20

−10

−30

−40

(1)

(2) (3)

f (MHz)

0 87621453

td(grp)

(ns)

−50

−100

−150

−200

150

100

250

200

−250

(1)

(3)

(2)

001aaj552

Product data sheet Rev. 04 — 25 May 2009 73 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Minimum requirements upper limit.

(2) Minimum requirements lower limit.

(3) Typical trap amplitude frequency response.

Fig 27. Typical amplitude frequency response for sound trap at D/K standard

(1) Minimum requirements upper limit.

(2) Minimum requirements lower limit.

(3) Typical trap group delay response.

Fig 28. Typical group delay response for sound trap at D/K standard

001aaj551

f (MHz)

0 86421753

−25

−15

−35

−5

αresp(f)

(dB)

−45

−20

−10

−30

−40

(1)

(2)

(3)

f (MHz)

0 87621453

td(grp)

(ns)

−50

−100

−150

−200

150

100

250

200

−250

(1)

(3)

(2)

001aaj550

Product data sheet Rev. 04 — 25 May 2009 74 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Minimum requirements upper limit.

(2) Minimum requirements lower limit.

(3) Typical trap amplitude frequency response.

Fig 29. Typical amplitude frequency response for sound trap at L standard

(1) Minimum requirements upper limit.

(2) Minimum requirements lower limit.

(3) Typical trap group delay response.

Fig 30. Typical group delay response for sound trap at L standard

001aaj549

f (MHz)

0 86421753

−25

−15

−35

−5

αresp(f)

(dB)

−45

−20

−10

−30

−40

(1)

(2) (3)

f (MHz)

0 87621453

td(grp)

(ns)

−50

−100

−150

−200

150

100

250

200

−250

(1)

(3)

(2)

001aaj548

Product data sheet Rev. 04 — 25 May 2009 75 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Center frequency.

(2) Minimum upper cut-off frequency.

(3) Minimum lower cut-off frequency.

(4) Maximum upper cut-off frequency.

(5) Maximum lower cut-off frequency.

(6) Minimum upper stop-band attenuation.

(7) Minimum lower stop-band attenuation.

Fig 31. Typical sound BP amplitude frequency response at TV mode, normalized to BP

center frequency

(1) FM; transmitter pre-correction off and receiver de-emphasis off; FM PLL ﬁlter: Rs= 5.6 kΩ and

Cpar =47pF.

(2) AM and AGC normal.

(3) AM and AGC fast.

Fig 32. Typical AM and FM audio frequency response

f − fc (MHz)

−3.0 3.01.0−1.0 2.00−2.0

001aaf579

−30

−10

−20

−40

αresp(f)

(dB)

−50

(7)

(5) (3) (2)

(1)

(4)

(6)

001aaj633

fAF (kHz)

10 105

104

102103

−10

−20

Vo(AF)

(dB)

−30

(2) (1)

(2) (3)

(1)

(3)

Product data sheet Rev. 04 — 25 May 2009 76 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Fig 33. Typical total harmonic distortion as a function of audio frequency at AM standard

Reference frequency input signal taken from external quartz circuit.

Fig 34. Unweighted FM audio S/N versus reference frequency input level using radio

mode

001aaj596

fAF (kHz)

10 105

104

102103

1.0

0.5

1.5

2.0

THD

(%)

001aaj597

Vi(FREF)(RMS) (mV)

0 20015050 100

(S/N)unw

(dB)

Product data sheet Rev. 04 — 25 May 2009 77 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Video signal related peak-to-peak levels are divided by factor 2√2 in order to conform with the RMS

value scale of the secondary y-axis, but disregarding the none sine wave signal content.

(1) Signal levels for −1 dB video output level using maximum RF gain and maximum IF gain.

(2) Signal levels for +1 dB video output level using minimum IF gain.

(3) Signal levels for TOP-adjusted tuner output level using maximum RF gain and adjustment-related

minimum IF gain.

(4) Signal levels for TOP-adjusted tuner output level using minimum RF gain and adjustment-related

minimum IF gain.

(5) TOP-adjusted tuner output level.

(6) TOP-adjusted VIF ampliﬁer input level.

(7) Minimum antenna input level at −1 dB video level.

Fig 35. Front-end level diagram

001aaf639

120

100

antenna

input

level

(dBµV)

video

amplifier

demodulatorVIF

amplifier

band-passtuner

IF demodulator, TDA989xX3450LTD1716

input

output

input

IF signal

RMS

values

(V)

10−1

10−2

10−3

10−4

10−5

10−6

(7)

(1)

(3)

(4) (2)

(5)

(6)

IF gain

control

range

gain

control

range

IF gain

control

range limited

by TOP

adjustment

Product data sheet Rev. 04 — 25 May 2009 78 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

12.2 Digital TV signal processing

Table 56. Characteristics

=5V

[1]

; T

amb

=25

C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for speciﬁcation;

i(IF)

= 10 mV (RMS); f

= 36 MHz for low IF output of 5 MHz; IF input from 50

Ω

via broadband transformer 1 : 1;

gain controlled ampliﬁer adjusted to typical speciﬁed output level; measurements taken in test circuit of Figure 51 with 4 MHz

crystal oscillator reference; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

IF ampliﬁer; IF1A and IF1B or IF2A and IF2B or pins IF3A and IF3B

VIinput voltage 1.8 1.93 2.2 V

Ri(dif) differential input

resistance [2] -2-kΩ

Ci(dif) differential input

capacitance [2] -3-pF

GIF(cr) control range IF gain [2] 60 66 - dB

DTV differential output; pins OUT1A, OUT1B, OUT2A and OUT2B

VOoutput voltage pin open-circuit 1.8 2.0 2.2 V

Ibias(int) internal bias current

(DC) for emitter-follower 2.0 2.5 - mA

Isink(o)(max) maximum output sink

current DC and AC; see Figure 36 [3] 1.4 1.7 - mA

Isource(o)(max) maximum output

source current DC and AC; see Figure 36 [3] 6.0 - - mA

ROoutput resistance differential; output active [2] --50Ω

output inactive; internal

resistance to GND [2] - 800 - Ω

Vi(IF)(RMS) RMS IF input voltage minimum input sine wave

level for nominal output level - 70 100 µV

maximum input sine wave

level for nominal output level 130 170 - mV

permissible overload [2] - - 320 mV

Direct IF; pins OUT2A and OUT2B

GIF(max) maximum IF gain output peak-to-peak level to

input RMS level ratio [2] -83-dB

Vo(dif)(p-p) peak-to-peak

differential output

voltage

between pin OUT2A and

pin OUT2B [4]

W4[7] = 0 - 1.0 1.1 V

W4[7] = 1 - 0.50 0.55 V

C/N carrier-to-noise ratio at fo= 33.4 MHz;

see Figure 37 [2][5][6]

Vi(IF) = 10 mV (RMS) 115 124 - dBc/Hz

Vi(IF) = 0.5 mV (RMS) 90 104 - dBc/Hz

αIM intermodulation

suppression input signals: fi= 47.0 MHz

and 57.5 MHz; output

signals: fo= 36.5 MHz or

68.0 MHz; see Figure 38

[2]

W4[7] = 0 40 - - dB

W4[7] = 1 40 - - dB

Product data sheet Rev. 04 — 25 May 2009 79 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

fIF(−1dB)l lower −1 dB IF cut-off

frequency [2] -7-MHz

f−3dB(IF)u upper IF cut-off

frequency W4[7] = 0 [4] 60 - - MHz

W4[7] = 1 [7] 60 - - MHz

PSRR power supply ripple

rejection residual spurious at nominal

differential output voltage

dependent on power supply

ripple

[2]

fripple =70Hz - 60 - dB

fripple = 20 kHz - 60 - dB

Low IF output signal; pins OUT1A and OUT1B; differential

GIF(max) maximum IF gain output peak-to-peak level to

input RMS level ratio [2] -89-dB

fsynth synthesizer frequency see Table 34 and Table 35 ---MHz

Vo(dif)(p-p) peak-to-peak

differential output

voltage

W4[7] = 0 [4] -2-V

W4[7] = 1 [4] -1-V

PSRR power supply ripple

rejection residual spurious at nominal

differential output voltage

dependent on power supply

ripple

[2]

fripple =70Hz - 50 - dB

fripple = 20 kHz - 30 - dB

αripple(pb)LIF low IF pass-band

ripple 6 MHz bandwidth - - 2.7 dB

7 MHz bandwidth - - 2.7 dB

8 MHz bandwidth - - 2.7 dB

B−3dB −3 dB bandwidth BP off [4] 11 15 - MHz

6 MHz bandwidth [4] - 7.8 - MHz

7 MHz bandwidth [4] - 8.8 - MHz

8 MHz bandwidth [4] - 9.8 - MHz

αstpb stop-band attenuation 6 MHz band; f = 11.75 MHz 30 40 - dB

6 MHz band; f = 20 MHz 28 35 - dB

7 MHz band; f = 13.75 MHz 30 40 - dB

7 MHz band; f = 20 MHz 28 35 - dB

8 MHz band; f = 15.75 MHz 30 40 - dB

8 MHz band; f = 20 MHz 28 35 - dB

Table 56. Characteristics

…continued

=5V

[1]

; T

amb

=25

C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for speciﬁcation;

i(IF)

= 10 mV (RMS); f

= 36 MHz for low IF output of 5 MHz; IF input from 50

Ω

via broadband transformer 1 : 1;

gain controlled ampliﬁer adjusted to typical speciﬁed output level; measurements taken in test circuit of Figure 51 with 4 MHz

crystal oscillator reference; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 80 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

∆td(grp) group delay time

variation from 1 MHz to 2 MHz [2] - 90 200 ns

from 2 MHz to end of band

with a bandwidth of [2]

6 MHz - 90 160 ns

7 MHz - 90 160 ns

8 MHz - 90 160 ns

αimage image rejection −10 MHz to 0 MHz

BP on 30 34 - dB

BP off 24 28 - dB

C/N carrier-to-noise ratio at fo= 4.9 MHz;

see Figure 37 [2][5][6]

Vi(IF) = 10 mV (RMS) 112 118 - dBc/Hz

Vi(IF) = 0.5 mV (RMS) 90 104 - dBc/Hz

αH(ib) in-band harmonics

suppression low IF = multiple of

1.31 MHz;

fi=f

synth + 1.31 MHz;

see Figure 40

[2]

W4[7] = 0 40 - - dB

W4[7] = 1 40 - - dB

αIM intermodulation

suppression input signals:

fi=f

synth + 4.7 MHz and

fsynth + 5.3 MHz; output

signals: fo= 4.1 MHz or

5.9 MHz; see Figure 39

[2]

W4[7] = 0 40 - - dB

W4[7] = 1 40 - - dB

αsp(ib) in-band spurious

suppression single-ended AC load;

RL=1kΩ; CL= 5 pF;

1 MHz to end of band;

BP on

[2] 50--dB

αsp(ob) out-band spurious

suppression single-ended AC load;

RL=1kΩ; CL= 5 pF; BP on [2] 50--dB

IF AGC control; pin AGCDIN

Isink(i)(max) maximum input sink

current [2] --2µA

Vi(max) maximum input

voltage [2] --V

VAGCDIN voltage on pin

AGCDIN [2] 0- 3V

∆GIF/∆VAGCDIN change of IF gain with

voltage on

pin AGCDIN

VAGCDIN = 0.8 V to 2.2 V - −45 - dB/V

Table 56. Characteristics

…continued

=5V

[1]

; T

amb

=25

C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for speciﬁcation;

i(IF)

= 10 mV (RMS); f

= 36 MHz for low IF output of 5 MHz; IF input from 50

Ω

via broadband transformer 1 : 1;

gain controlled ampliﬁer adjusted to typical speciﬁed output level; measurements taken in test circuit of Figure 51 with 4 MHz

crystal oscillator reference; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 81 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Tuner AGC; pin TAGC

TAGC integral loop mode (W6[7:6] = 10); TAGC is current output; unmodulated IF; see Table 44 and Figure 13

Vi(IF)(RMS) RMS IF input voltage at starting point of tuner

AGC takeover;

Isink(TAGC) = 100 µA

W9[4:0] = 0 0000 - 59.6 - dBµV

W9[4:0] = 1 0000 - 78.3 - dBµV

W9[4:0] = 1 1111 - 98.5 - dBµV

αacc(set)TOP TOP setting accuracy −2 - +2 dB

Isource source current TAGC charge current

normal mode; W9[5] = 0 0.20 0.33 0.45 µA

normal mode; W9[5] = 1 1.6 2.5 3.4 µA

fast mode activated by

internal level detector;

W9[5] = 0

71115µA

fast mode activated by

internal level detector;

W9[5] = 1

60 90 120 µA

Isink sink current TAGC discharge current;

VTAGC =1V 375 500 625 µA

∆αacc(set)TOP/∆T TOP setting accuracy

variation with

temperature

Isink(TAGC) = 100 µA;

W9[4:0] = 1 0000 [2] - 0.006 0.02 dB/K

RLload resistance [2] 50--MΩ

Vsat(u) upper saturation

voltage pin operating as current

output [2] VP−0.3 - - V

Vsat(l) lower saturation

voltage pin operating as current

output [2] - - 0.3 V

αth(fast)AGC AGC fast mode

threshold activated by internal fast

AGC detector; I2C-bus

setting corresponds to

W9[4:0] = 1 0000

[2] 6810dB

tddelay time before activating; Vi(IF)

below αth(fast)AGC

[2] 40 60 80 ms

Filter synthesizer PLL; pin LFSYN1

VLFSYN1 voltage on pin

LFSYN1 1.0 - 3.5 V

KOVCO steepness ∆fVCO /∆VLFSYN1 - 3.75 - MHz/V

KDphase detector

steepness ∆ILFSYN1 /∆ϕVCO -9-µA/rad

Isink(o)PD(max) maximum phase

detector output sink

current

--65µA

Table 56. Characteristics

…continued

=5V

[1]

; T

amb

=25

C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for speciﬁcation;

i(IF)

= 10 mV (RMS); f

= 36 MHz for low IF output of 5 MHz; IF input from 50

Ω

via broadband transformer 1 : 1;

gain controlled ampliﬁer adjusted to typical speciﬁed output level; measurements taken in test circuit of Figure 51 with 4 MHz

crystal oscillator reference; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 82 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Isource(o)PD(max) maximum phase

detector output

source current

--65µA

Conversion synthesizer PLL; pin LFSYN2

VLFSYN2 voltage on pin

LFSYN2 1- 3V

KOVCO steepness ∆fVCO /∆VLFSYN2 - 31 - MHz/V

KDphase detector

steepness ∆ILFSYN2 /∆ϕVCO;

see Table 57;

fVCO selection:

22 MHz to 29.5 MHz - 32 - µA/rad

30 MHz to 37.5 MHz - 38 - µA/rad

38 MHz to 45.5 MHz - 47 - µA/rad

46 MHz to 53.5 MHz - 61 - µA/rad

57 MHz - 61 - µA/rad

Io(PD) phase detector output

current sink or source;

fVCO selection:

22 MHz to 29.5 MHz - 200 - µA

30 MHz to 37.5 MHz - 238 - µA

38 MHz to 45.5 MHz - 294 - µA

46 MHz to 53.5 MHz - 384 - µA

57 MHz - 384 - µA

ϕn(synth) synthesizer phase

noise fsynth = 31 MHz;

fIF =36MHz

at 1 kHz [2] 89 99 - dBc/Hz

at 10 kHz [2] 89 99 - dBc/Hz

at 100 kHz [2] 98 102 - dBc/Hz

at 1.4 MHz [2] 115 119 - dBc/Hz

fsynth = 40 MHz;

fIF = 44 MHz; external

4 MHz reference signal of

265 mV (RMS) and phase

noise better than

120 dBc/Hz; see Figure 46

at 1 kHz [2] 89 96 - dBc/Hz

at 10 kHz [2] 89 100 - dBc/Hz

at 100 kHz [2] 96 100 - dBc/Hz

at 1.4 MHz [2] 115 118 - dBc/Hz

αsp spurious suppression multiple of ∆f = 500 kHz [2] 50 - - dBc

ILleakage current synthesizer spurious

performance > 50 dBc [2] --10nA

Table 56. Characteristics

…continued

=5V

[1]

; T

amb

=25

C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for speciﬁcation;

i(IF)

= 10 mV (RMS); f

= 36 MHz for low IF output of 5 MHz; IF input from 50

Ω

via broadband transformer 1 : 1;

gain controlled ampliﬁer adjusted to typical speciﬁed output level; measurements taken in test circuit of Figure 51 with 4 MHz

crystal oscillator reference; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 83 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Reference frequency

General

fref reference frequency [8] -4-MHz

Reference frequency generation with crystal; pin OPTXTAL

VOPTXTAL voltage on pin

OPTXTAL (DC) pin open-circuit 2.3 2.6 2.9 V

Riinput resistance [2] -2-kΩ

Rrsn(xtal) crystal resonance

resistance - - 200 Ω

Cpull pull capacitance [9] ---pF

Rswoff(OPTXTAL) switch-off resistance

on pin OPTXTAL to switch off crystal input by

external resistor wired

between pin OPTXTAL and

GND

0.22 - 4.7 kΩ

Iswoff switch-off current Rswoff(OPTXTAL) = 0.22 kΩ--5000µA

Rswoff(OPTXTAL) = 3.3 kΩ- 500 - µA

Reference frequency input from external source; pin OPTXTAL

VOPTXTAL voltage on pin

OPTXTAL (DC) pin open-circuit 2.3 2.6 2.9 V

Riinput resistance [2] -2-kΩ

Vref(RMS) RMS reference

voltage 80 - 400 mV

ROoutput resistance of external reference signal

source [2] - 2 4.7 kΩ

Cdec decoupling

capacitance to external reference signal

source [2] 22 100 - pF

Reference frequency input from external source; pin FREF

VFREF voltage on pin FREF

(DC) pin open-circuit 2.2 2.5 2.8 V

Riinput resistance [2] 50--kΩ

fref reference frequency [8] -4-MHz

Vref(RMS) RMS reference

voltage see Figure 46 15 150 500 mV

ROoutput resistance of external reference signal

source; AC-coupled - - 4.7 kΩ

Cdec decoupling

capacitance to external reference signal

source 22 100 - pF

Table 56. Characteristics

…continued

=5V

[1]

; T

amb

=25

C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for speciﬁcation;

i(IF)

= 10 mV (RMS); f

= 36 MHz for low IF output of 5 MHz; IF input from 50

Ω

via broadband transformer 1 : 1;

gain controlled ampliﬁer adjusted to typical speciﬁed output level; measurements taken in test circuit of Figure 51 with 4 MHz

crystal oscillator reference; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 04 — 25 May 2009 84 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

[1] Some parameters can be decreased at VP= 4.5 V.

[2] This parameter is not tested during production and is only given as application information.

[3] Output current can be increased by application of single-ended resistor from each output pin to GND. Recommended resistor value is

minimum 1 kΩ.

[4] With single-ended load for fIF < 45 MHz RL≥1kΩ and CL≤5 pF to ground and for fIF = 45 MHz to 60 MHz RL=1kΩ and CL≤3 pF to

ground.

[5] Noise level is measured without input signal but AGC adjusted corresponding to the given input level.

[6] Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off.

[7] With single-ended load RL≥1kΩ and CL≤5 pF to ground.

[8] The tolerance of the reference frequency determines the accuracy of VIFAFC, RIFAFC, FM demodulator center frequency, maximum

FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.

[9] The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.

[1] Calculation of the PLL loop ﬁlter by using the following formulae:

, valid for d ≥1.2

with the following parameters:

KO= VCO steepness (Hz/V),

N = divider ratio: ,

KD= phase detector steepness (A/rad),

RLFSYN2 = synthesizer loop ﬁlter serial resistor (Ω),

CLFSYN2 = synthesizer loop ﬁlter serial capacitor (F),

BLF(−3dB) =−3 dB LF bandwidth (Hz),

d = damping factor.

[2] If more than one frequency range is used in the application, then the smallest resistor value should be applied.

Rswoff(FREF) switch-off resistance

on pin FREF to switch off reference signal

input by external resistor

wired between pin FREF

and GND

3.9 - 27 kΩ

Iswoff switch-off current Rswoff(FREF) = 3.9 kΩ- - 100 µA

Rswoff(FREF) =22kΩ-25-µA

Table 56. Characteristics

…continued

=5V

[1]

; T

amb

=25

C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for speciﬁcation;

i(IF)

= 10 mV (RMS); f

= 36 MHz for low IF output of 5 MHz; IF input from 50

Ω

via broadband transformer 1 : 1;

gain controlled ampliﬁer adjusted to typical speciﬁed output level; measurements taken in test circuit of Figure 51 with 4 MHz

crystal oscillator reference; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Table 57. Conversion synthesizer PLL; loop ﬁlter dimensions[1]

fVCO (MHz) RLFSYN2 (kΩ)[2] CLFSYN2 (nF)

22 to 29.5 1.5 4.7

30 to 37.5 1.8 4.7

38 to 45.5 2.2 4.7

46 to 53.5 2.7 4.7

57 3.3 4.7

BLF 3dB–()

------- KDRLFSYN2

---RLFSYN2 2πKO

------- KDCLFSYN2

NfVCO

0.5 MHz

--------------------

Product data sheet Rev. 04 — 25 May 2009 85 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

W4[7] = 0; nominal output level

(1) Direct IF, fmax = 40 MHz, with single-ended resistors of 1 kΩ to GND.

(2) Low IF, fmax = 9 MHz.

Fig 36. Maximum differential load ﬁgures at OUT1/OUT2

(1) Direct IF.

(2) Low IF.

(3) Noise level of measurement setup.

Fig 37. Typical C/N ratio as a function of IF input voltage

008aaa153

RL(dif) (kΩ)

0321

CL(dif)

(pF)

(2)

(1)

001aaj598

Vi(IF)(RMS) (dBµV)

30 1109050 70

100

110

120

130

C/N

(dBc/Hz)

(2)

(3)

(1)

Product data sheet Rev. 04 — 25 May 2009 86 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) 0.25 V for W4[7] = 1.

Fig 38. Direct IF signal conditions for measurement of intermodulation at OUT2

(1) 0.25 V for W4[7] = 1.

Fig 39. Low IF signal conditions for measurement of intermodulation at OUT1

(1) 1.0 V for W4[7] = 1.

Fig 40. Low IF signal conditions for measurement of harmonics at OUT1

008aaa051

input signal output signal

0 47 57.5

αIM

(MHz) 47 57.506836.5 fo

(MHz)

0.5

(1)

Vi(IF)(RMS)

(dBµV) Vo(dif)(p-p)

(V)

008aaa053

input signal

fsynth output signal

36 40.7 41.3

αIM

(MHz) 4.7 5.30 5.94.1 fo

(MHz)

0.5

(1)

Vi(IF)(RMS)

(dBµV) Vo(dif)(p-p)

(V)

008aaa054

input signal

fsynth output signal

36 37.31

αH(ib)

(MHz) 1.31 5.240 6.55 7.862.62 3.93 fo

(MHz)

2.0

(1)

Vi(IF)(RMS)

(dBµV) Vo(dif)(p-p)

(V)

Product data sheet Rev. 04 — 25 May 2009 87 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Channel bandwidth = 6 MHz.

(2) Channel bandwidth = 7 MHz.

(3) Channel bandwidth = 8 MHz.

Fig 41. Detailed low IF amplitude and group delay pass-band tolerance scheme

(1) Channel bandwidth = 6 MHz.

(2) Channel bandwidth = 7 MHz.

(3) Channel bandwidth = 8 MHz.

Fig 42. Low IF amplitude stop-band tolerance scheme

001aaj605

−10

−8

−6

−200

−100

100

−4

−2

−9

−7

−5

−3

−1

0681024 12

f (MHz)

(1) (2) (3)

αresp(f)

(dB)

tolerance scheme:

td(grp)LIF

(ns)

(3)

(1)

(2)

(3)

(2)(1)

001aaj607

−70

−30 −25 −20 −15 −10 −50

−50

−10

−30

−60

−20

−40

f (MHz)

tolerance scheme: (1) (2) (3)

αresp(f)

(dB)

(1)

(2)

(3)

Product data sheet Rev. 04 — 25 May 2009 88 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Channel bandwidth = 6 MHz.

(2) Channel bandwidth = 7 MHz.

(3) Channel bandwidth = 8 MHz.

Fig 43. Low IF amplitude pass-band tolerance scheme

(1) 2.0 V (p-p) differential output voltage (LIF, W9[7] = 0, W4[7] = 0).

(2) 1.0 V (p-p) differential output voltage (LIF, W9[7] = 0, W4[7] = 1; DIF, W9[7] = 0, W4[7] = 0).

(3) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 0, W4[7] = 1).

(4) 2.0 V (p-p) differential output voltage (LIF, W9[7] = 1, W4[7] = 0).

(5) 1.0 V (p-p) differential output voltage (LIF, W9[7] = 1, W4[7] = 1; DIF, W9[7] = 1, W4[7] = 0).

(6) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 1, W4[7] = 1).

(7) Ratio of output peak-to-peak level to input RMS level.

Fig 44. Typical gain characteristic for AGCDIN control voltage

001aaj606

−700 5 10 15 20 25 30

−30

−50

−10

−40

−60

−20

f (MHz)

tolerance scheme: (1) (2) (3)

αresp(f)

(dB)

(3)

(2)

(1)

VAGCDIN (V)

0 3.53.02.00.5 2.51.51.0

001aaj599

100

G(7)

(dB)

(1)

(2)

(3)

(4)

(5)

(6)

Product data sheet Rev. 04 — 25 May 2009 89 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Fig 45. Typical synthesizer loop ﬁlter voltage as function of synthesizer frequency

fsynth = 40 MHz; fIF = 44 MHz; sound BP off

(1) ∆f = 100 kHz.

(2) ∆f = 10 kHz.

(3) ∆f = 1 kHz.

Fig 46. Typical synthesizer phase noise at carrier frequency plus ∆f on LIF output versus

input voltage on pin FREF

fsynth (MHz)

20 605030 40

001aaj601

1.5

2.0

2.5

VLFSYN2

(V)

1.0

Vi(FREF)(RMS) (mV)

0 500400200 300100

001aaj600

105

ϕn(synth)

(dBc/Hz)

(1)

(2)

(3)

Product data sheet Rev. 04 — 25 May 2009 90 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

13. Application information

(1) Optional single-ended IF input possible.

(2) Application depends on synthesizer frequency; see Table 57.

(3) Application of FM PLL loop ﬁlter; see Table 54.

(4) EMI suppression ﬁlter for DC, e.g. BLM21RK121SN1 (Murata).

(5) Capacitor connected only for TDA9898.

Fig 47. Application diagram of TDA9897 and TDA9898; ATV/DVB-T

001aai815

22 pF

synthesizer

downconverter

loop filter(2)

100 nF

470 Ω

3.3 kΩ

synthesizer

trap control

loop filter

1.5 nF

CAF

470 nF

148 45 42 3839

analog

ground

VP = 5 V

470 nF

100 nF

n.c.

44 4347

CTAGC

220 nF

tuner

AGC

output

470 nF

CIFAGC(5)

100 nF

CCTAGC

CFREF

100 pF

4 MHz

reference

input

41 40

TDA9897

TDA9898

AGC input for DIF

(from channel decoder)

BVS

2 V CVBS

output

AUD

1st DIF

digital LIF or

analog 2nd

sound IF

13 14 221815 16 17

VIF PLL

loop filter

digital

ground

ADRSEL

SDA

100 Ω

220 nF

100 Ω

20 23

SCL

100 Ω

RLFSYN2 CLFSYN2

external

FM input

4.7 nF

Cde-em

n.c.

7 MHz WINDOW

6 MHz WINDOW

SAW

X3450L

IF(1)

FM PLL loop filter(3)

Cpar Cs

L(4)

Product data sheet Rev. 04 — 25 May 2009 91 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Application depends on synthesizer frequency; see Table 57.

(2) Application of FM PLL loop ﬁlter; see Table 54.

(3) EMI suppression ﬁlter for DC, e.g. BLM21RK121SN1 (Murata).

(4) Capacitor connected only for TDA9898.

Fig 48. Application diagram of TDA9897 and TDA9898; ATV/DVB-T/DVB-C

4.7 kΩ4.7 kΩ

4.7 kΩ

001aai816

22 pF

synthesizer

downconverter

loop filter(1)

100 nF

470 Ω

3.3 kΩ

synthesizer

trap control

loop filter

1.5 nF

CAF

470 nF

148 45 42 3839

analog

ground

VP = 5 V

470 nF

100 nF

n.c.

44 4347

CTAGC

220 nF

tuner

AGC

output

470 nF

CIFAGC(4)

100 nF

CCTAGC

CFREF

100 pF

4 MHz

reference

input

41 40

TDA9897

TDA9898

AGC input for DIF

(from channel decoder)

BVS

PORT2

PORT1

PORT2

2 V CVBS

output

AUD

1st DIF

digital LIF or

analog 2nd

sound IF

13 14 221815 16 17

VIF PLL

loop filter

digital

ground

ADRSEL

SDA

100 Ω

BA277

220 nF

100 Ω

20 23

SCL

100 Ω

RLFSYN2 CLFSYN2

external

FM input

4.7 nF

Cde-em

n.c.

SOUND

2317

6 MHz or 8 MHz

WINDOW

SAW

X3751L

FM PLL loop filter(2)

Cpar Cs

L(3)

Product data sheet Rev. 04 — 25 May 2009 92 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Application depends on synthesizer frequency; see Table 57.

(2) Application of FM PLL loop ﬁlter; see Table 54.

(3) EMI suppression ﬁlter for DC, e.g. BLM21RK121SN1 (Murata).

(4) Optional.

(5) Value depends on application.

Fig 49. Application diagram of TDA9897 using SAW ﬁlter with Nyquist slope

001aai817

22 pF

synthesizer

downconverter

loop filter(1)

100 nF

470 Ω

3.3 kΩ

synthesizer

trap control

loop filter

1.5 nF

CAF

470 nF

148 45 42 3839

analog

ground

VP = 5 V

470 nF

100 nF

n.c.

44 4347

CTAGC

220 nF

tuner

AGC

output

100 nF

CCTAGC

IF 3

CFREF

100 pF L(3)

4 MHz

reference

input

41 40

TDA9897

PORT2

AGC input for DIF

(from channel decoder)

BVS

2 V CVBS

output

AUD

1st DIF

digital LIF or

analog 2nd

sound IF

13 14 221815 16 17

PORT1

VIF PLL

loop filter

digital

ground

ADRSEL

SDA

(5)

(4)

100 Ω

220 nF

100 Ω

20 23

SCL

100 Ω

RLFSYN2 CLFSYN2

external

FM input

4.7 nF

Cde-em

n.c.

SAW

SIF

X7550

SAW

VIF

M1980

NYQUIST SLOPE

FM PLL loop filter(2)

Cpar Cs

Product data sheet Rev. 04 — 25 May 2009 93 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

(1) Optional 4 MHz quartz crystal oscillator.

(2) Alternative buffered TAGC voltage output.

(3) Alternative VIF AGC voltage monitor output.

(4) Optional use of (a) PORT1, (b) PORT2 or (c) PORT3.

(5) Optional CVBS buffer at setting (a) W6[1] = 0, 2 V CVBS or (b) W6[1] = 1, 1.7 V CVBS.

(6) Optional analog AFC voltage output.

(7) Optional output current increase at output (a) 1st DIF respectively (b) digital LIF.

(8) Optional radio application with external BP.

Fig 50. Optional applications

001aai818

R ≥ 1 kΩ

43 Ω

560 Ω

220 Ω22 kΩ

560 Ω

22 kΩ

47 µF

digital LIF or

analog 2nd

sound IF

R ≥ 1 kΩ

1st DIF

1 V CVBS

into 75 Ω

VAGC voltage

monitor output

buff ered TAGC

control voltage

output

TDA9897

TDA9898

(4c)

TDA9897

TDA9898 16

(6)

TDA9897

TDA9898 35

(4b)

TDA9897

TDA9898

(7b)

TDA9897

TDA9898

(7a)

TDA9897

TDA9898 33

(5b)

TDA9897

TDA9898

(3)

PORT1 PORT2

PORT3

TDA9897

TDA9898

(4a)

22 kΩ

22 pF

100 nF

4 MHz

TDA9897

TDA9898

46 39

(1)

CTAGC

220 nF

TDA9897

TDA9898

47 42

(2)

TDA9897

TDA9898

15 17

(8)

VPVP

68 Ω

220 Ω

47 µF

1 V CVBS

into 75 Ω

TDA9897

TDA9898 33

(5a)

4.7 kΩ

AFC

voltage

output

Product data sheet Rev. 04 — 25 May 2009 94 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

14. Test information

(1) Switch-off resistor connected if external reference signal is not used.

(2) Switch-off resistor connected if crystal is not used.

(3) Use of crystal is optional.

(4) Application depends on synthesizer frequency; see Table 57.

(5) Application of FM PLL loop ﬁlter; see Table 54.

(6) Capacitor connected only for TDA9898.

(7) Pull-up resistor connected only for port function.

Fig 51. Test circuit of TDA9897 and TDA9898

22 kΩ

001aai819

22 pF

22 kΩ(1) 2.7 kΩ(7)

2.7 kΩ(7)

synthesizer

downconverter

loop filter(4)

100 nF

470 Ω

synthesizer

trap control

loop filter

1.5 nF

CAF

470 nF

148 45

i.c.

42 38

3.3 kΩ(2)

PORT3

PORT2

+5 V

n.c.

44 4347

CTAGC

100 nF

tuner

AGC

output

470 nF

CIFAGC(6)

100 nF

CCTAGC

CFREF

100 pF

4 MHz

reference

input

VP = 5 V

41 40

analog

ground

TDA9897

TDA9898

MPP

FM input

from sound BPF

output to

sound BPF

AGC input for DIF

(from channel decoder)

BVS

2 V CVBS

output

AUD

1st DIF

(b)

(a)

digital LIF or

analog 2nd

sound IF

(b)

(a)

TOP potentiometer for

RSSI and positive modulation

13 14 221815 16 17

VIF

loop filter

digital

ground

21 ADRSEL

SDA

100 Ω

220 nF

100 Ω

20 23

SCL

100 Ω

RLFSYN2 CLFSYN2

22 pF

4 MHz(3)

external

FM input

4.7 nF

Cde-em

n.c.

FM PLL

loop filter(5) Rs

Cpar Cs

2.7 kΩ(7)

+5 V

PORT1

51 Ω

SIF/DIF

1 : 1

51 Ω

VIF/SIF/DIF

1 : 1

51 Ω

VIF/SIF/DIF

1 : 1

Product data sheet Rev. 04 — 25 May 2009 95 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

15. Package outline

Fig 52. Package outline SOT313-2 (LQFP48)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 7.1

6.9 0.5 9.15

8.85 0.95

0.55 7

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Product data sheet Rev. 04 — 25 May 2009 96 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

Fig 53. Package outline SOT619-1 (HVQFN48)

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 7.1

6.9

5.25

4.95

7.1

6.9 5.25

4.95

5.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT619-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT619-1

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 24

48 37

01-08-08

02-10-18

terminal 1

index area

terminal 1

index area

1/2 e

1/2 e AC

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 04 — 25 May 2009 97 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 04 — 25 May 2009 98 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

16.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 54) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 58 and 59

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 54.

Table 58. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 59. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 04 — 25 May 2009 99 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

17. Soldering of through-hole mount packages

17.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.

Wave soldering is the preferred method for mounting of through-hole mount IC packages

on a printed-circuit board.

17.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder

pastes is increasing. Typical dwell time of the leads in the wave ranges from

3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb

or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (Tstg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

17.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

MSL: Moisture Sensitivity Level

Fig 54. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 04 — 25 May 2009 100 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

17.4 Package related soldering information

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit

board.

[2] For PMFP packages hot bar soldering or manual soldering is suitable.

18. Abbreviations

Table 60. Suitability of through-hole mount IC packages for dipping and wave soldering

Package Soldering method

Dipping Wave

CPGA, HCPGA - suitable

DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]

PMFP[2] - not suitable

Table 61. Abbreviations

Acronym Description

ADC Analog-to-Digital Converter

AFC Automatic Frequency Control

AGC Automatic Gain Control

ATV Analog TV

BP Band-Pass

CW Continuous Wave

DAC Digital-to-Analog Converter

DC Direct Current

DIF Digital Intermediate Frequency

DSP Digital Signal Processor

DTV Digital TV

DVB Digital Video Broadcasting

DVB-C Digital Video Broadcasting-Cable

DVB-T Digital Video Broadcasting-Terrestrial

EMI Electro-Magnetic Interference

ESD ElectroStatic Discharge

FPLL Frequency Phase-Locked Loop

I/O Input/Output

IC Integrated Circuit

IF Intermediate Frequency

LCD Liquid Crystal Display

LIF Low Intermediate Frequency

MAD Module Address

NB NarrowBand

NICAM Near Instantaneous Companded Audio Multiplex

PLL Phase-Locked Loop

POR Power-On Reset

QSS Quasi Split Sound

Product data sheet Rev. 04 — 25 May 2009 101 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

19. Revision history

RIF Radio Intermediate Frequency

RSSI Received Signal Strength Indication

SAW Surface Acoustic Wave

SC Sound Carrier

SIF Sound Intermediate Frequency

TAGC Tuner Automatic Gain Control

TOP TakeOver Point

VCO Voltage-Controlled Oscillator

VIF Vision Intermediate Frequency

VITS Vertical Interval Test Signal

Table 61. Abbreviations

…continued

Acronym Description

Table 62. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TDA9897_TDA9898_4 20090525 Product data sheet - TDA9897_TDA9898_3

Modiﬁcations: •Speciﬁcation of features for V3 version

TDA9897_TDA9898_3 20080111 Product data sheet - TDA9897_TDA9898_2

TDA9897_TDA9898_2 20070411 Product data sheet - TDA9897_TDA9898_1

TDA9897_TDA9898_1 20060922 Product data sheet - -

Product data sheet Rev. 04 — 25 May 2009 102 of 103

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

20.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors TDA9897; TDA9898

Multistandard hybrid IF processing

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 May 2009

Document identifier: TDA9897_TDA9898_4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

22. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Analog TV processing. . . . . . . . . . . . . . . . . . . . 1

2.3 Digital TV processing . . . . . . . . . . . . . . . . . . . . 2

2.4 FM radio mode . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3

5 Ordering information. . . . . . . . . . . . . . . . . . . . . 7

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7 Pinning information. . . . . . . . . . . . . . . . . . . . . 12

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 13

8 Functional description . . . . . . . . . . . . . . . . . . 15

8.1 IF input switch. . . . . . . . . . . . . . . . . . . . . . . . . 15

8.2 VIF demodulator. . . . . . . . . . . . . . . . . . . . . . . 15

8.3 VIF AGC and tuner AGC. . . . . . . . . . . . . . . . . 15

8.3.1 Mode selection of VIF AGC . . . . . . . . . . . . . . 15

8.3.2 VIF AGC monitor . . . . . . . . . . . . . . . . . . . . . . 15

8.3.3 Tuner AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.4 DIF/SIF FM and AM sound AGC . . . . . . . . . . 16

8.5 Frequency phase-locked loop for VIF. . . . . . . 16

8.6 DIF/SIF converter stage . . . . . . . . . . . . . . . . . 17

8.7 Mono sound demodulator. . . . . . . . . . . . . . . . 17

8.7.1 FM PLL narrowband demodulation. . . . . . . . . 17

8.7.2 AM sound demodulation. . . . . . . . . . . . . . . . . 17

8.8 Audio ampliﬁer . . . . . . . . . . . . . . . . . . . . . . . . 17

8.9 Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.10 I2C-bus transceiver and slave address. . . . . . 18

2C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 18

9.1 Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9.2 Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.2.1 Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.2.2 Description of data bytes . . . . . . . . . . . . . . . . 24

10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 39

11 Thermal characteristics. . . . . . . . . . . . . . . . . . 39

12 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 40

12.1 Analog TV signal processing . . . . . . . . . . . . . 40

12.2 Digital TV signal processing . . . . . . . . . . . . . . 78

13 Application information. . . . . . . . . . . . . . . . . . 90

14 Test information. . . . . . . . . . . . . . . . . . . . . . . . 94

15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 95

16 Soldering of SMD packages . . . . . . . . . . . . . . 97

16.1 Introduction to soldering . . . . . . . . . . . . . . . . . 97

16.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 97

16.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 97

16.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 98

17 Soldering of through-hole mount packages. 99

17.1 Introduction to soldering through-hole mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

17.2 Soldering by dipping or by solder wave . . . . . 99

17.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 99

17.4 Package related soldering information. . . . . 100

18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 100

19 Revision history . . . . . . . . . . . . . . . . . . . . . . 101

20 Legal information . . . . . . . . . . . . . . . . . . . . . 102

20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . 102

20.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . 102

20.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 102

20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 102

21 Contact information . . . . . . . . . . . . . . . . . . . 102

22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103