February 2005 i
© 2005 Actel Corporation See the Actel website for the latest version of the datasheet.
SX-A Family FPGAs
Leading-Edge Performance
250 MHz System Performance
350 MHz Internal Performance
Specifications
12,000 to 108,000 Available System Gates
Up to 360 User-Programmable I/O Pins
Up to 2,012 Dedicated Flip-Flops
0.22 µ / 0.25 µ CMOS Process Technology
Features
Hot-Swap Compliant I/Os
Power-Up/Down Friendly (No Sequencing Required
for Supply Voltages)
66 MHz PCI Compliant
Nonvolatile, Single-Chip Solution
Configurable I/O Support for 3.3 V / 5 V PCI, 5 V
TTL, 3.3 V LVTTL, 2.5 V LVCMOS2
2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with
5 V Input Tolerance and 5 V Drive Strength
Devices Support Multiple Temperature Grades
Configurable Weak-Resistor Pull-Up or Pull-Down
for I/O at Power-Up
Individual Output Slew Rate Control
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary-Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Actel Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and
Design Theft
Table 1 SX-A Product Profile
Device A54SX08A A54SX16A A54SX32A A54SX72A
Capacity
Typ ic al Ga te s
System Gates
8,000
12,000
16,000
24,000
32,000
48,000
72,000
108,000
Logic Modules
Combinatorial Cells
Dedicated Flip-Flops
Maximum Flip-Flops
768
512
256
512*
1,452
924
528
990
2,880
1,800
1,080
1,980
6,036
4,024
2,012
4,024
Maximum User I/Os 130 180 249 360
Global Clocks 3 3 3 3
Quadrant Clocks 0 0 0 4
Boundary Scan Testing Yes Yes Yes Yes
3.3 V / 5 V PCI Yes Yes Yes Yes
Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns
Speed Grades –F, Std, –1, –2 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3
Temperature Grades C, I, A, M C, I, A, M C, I, A, M C, I, A, M
Package (by pin count)
PQFP
TQFP
PBGA
FBGA
CQFP
208
100, 144
144
208
100, 144
144, 256
208
100, 144, 176
329
144, 256, 484
208, 256
208
256, 484
208, 256
Note: *A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers
v5.1
SX-A Family FPGAs
ii v5.1
Ordering Information
Device Resources
Note: *For more information about the CQFP package options, refer to the HiRel SX-A datasheet.
Package Lead Count
A54SX16A PQ 2082
Part Number
A54SX08A = 12,000 System Gates
A54SX16A = 24,000 System Gates
A54SX32A = 48,000 System Gates
A54SX72A = 108,000 S
y
stem Gates
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
Package Type
BG = 1.27 mm Plastic Ball Grid Array
FG = 1.0 mm Fine Pitch Ball Grid Array
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
CQ = Ceramic Quad Flat Pack*
Application (Temperature Range)
Blank = Commercial (0 to +70˚)
I = Industrial (-40 to +85˚C)
A = Automotive (-40 to +125˚C)
M = Military (-55 to +125˚C)
B = MIL-STD-883 Class B
User I/Os (Including Clock Buffers)
Device
208-Pin
PQFP
100-Pin
TQFP
144-Pin
TQFP
176-Pin
TQFP
329-Pin
PBGA
144-Pin
FBGA
256-Pin
FBGA
484-Pin
FBGA
A54SX08A 130 81 113 111
A54SX16A 175 81 113 111 180
A54SX32A 174 81 113 147 249 111 203 249
A54SX72A 171 203 360
Notes: Package Definitions: PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array,
FBGA = Fine Pitch Ball Grid Array
SX-A Family FPGAs
v5.1 iii
Temperature Grade Offering
Speed Grade and Temperature Grade Matrix
Contact your Actel Sales representative for more information on availability.
Package A54SX08A A54SX16A A54SX32A A54SX72A
PQ208 C,I,A,M C,I,A,M C,I,A,M C,I,A,M
TQ100 C,I,A,M C,I,A,M C,I,A,M
TQ144 C,I,A,M C,I,A,M C,I,A,M
TQ176 C,I,M
BG329 C,I,M
FG144 C,I,A,M C,I,A,M C,I,A,M
FG256 C,I,A,M C,I,A,M C,I,A,M
FG484 C,I,M C,I,A,M
CQ208 C,M,B C,M,B
CQ256 C,M,B C,M,B
Notes:
1. C = Commercial
2. I = Industrial
3. A = Automotive
4. M = Military
5. B = Mil-Std-883 Class B
6. For more information regarding automotive products, refer to the SX-A Automotive Family FPGAs datasheet.
7. For more information regarding Mil-Temp and ceramic packages, refer to the HiRel SX-A Family FPGAs datasheet.
F Std –1 –2 –3
Commercial ✓✓✓✓✓
Industrial ✓✓✓✓
Automotive
Military ✓✓
Mil-Std. 883B ✓✓
Notes:
1. For more information regarding automotive products, refer to the SX-A Automotive Family FPGAs datasheet.
2. For more information regarding Mil-Temp and ceramic packages, refer to the HiRel SX-A Family FPGAs datasheet.
iv v5.1
Table of Contents
SX-A Family FPGAs
General Description
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Detailed Specifications
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Typical SX-A Standby Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
PCI Compliance for the SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Sample Path Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Package Pin Assignments
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
329-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
v5.1 v
Table of Contents
SX-A Family FPGAs
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
International Traffic in Arms Regulations (ITAR) and Export Administration
Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
SX-A Family FPGAs
v5.1 1-1
General Description
Introduction
The Actel SX-A family of FPGAs offers a cost-effective,
single-chip solution for low-power, high-performance
designs. Fabricated on 0.22 µm / 0.25 µm CMOS
antifuse technology and with the support of 2.5 V,
3.3 V and 5 V I/Os, the SX-A is a versatile platform to
integrate designs while significantly reducing time-
to-market.
SX-A Family Architecture
The SX-A family’s device architecture provides a unique
approach to module organization and chip routing that
satisfies performance requirements and delivers the most
optimal register/logic mix for a wide variety of
applications.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements (Figure 1-1). The
antifuses are normally open circuit and, when
programmed, form a permanent low-impedance
connection.
Note: The A54SX72A device has four layers of metal with the antifuse between Metal 3 and Metal 4. The A54SX08A, A54SX16A, and
A54SX32A devices have three layers of metal with the antifuse between Metal 2 and Metal 3.
Figure 1-1 SX-A Family Interconnect Elements
Silicon Substrate
Metal 4
Metal 3
Metal 2
Metal 1
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
Tungsten Plug Contact
Routing Tracks
SX-A Family FPGAs
1-2 v5.1
Logic Module Design
The SX-A family architecture is described as a “sea-of-
modules” architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. The Actel SX-A family provides two types of
logic modules: the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable, using the S0 and S1
lines control signals (Figure 1-2). The R-cell registers feature
programmable clock polarity selectable on a register-by-
register basis. This provides additional flexibility while
allowing mapping of synthesized functions into the SX-A
FPGA. The clock source for the R-cell can be chosen from
either the hardwired clock, the routed clocks, or internal
logic.
The C-cell implements a range of combinatorial functions
of up to five inputs (Figure 1-3). Inclusion of the DB input
and its associated inverter function allows up to 4,000
different combinatorial functions to be implemented in a
single module. An example of the flexibility enabled by
the inversion capability is the ability to integrate a 3-input
exclusive-OR function into a single C-cell. This facilitates
construction of 9-bit parity-tree functions with 1.9 ns
propagation delays.
Module Organization
All C-cell and R-cell logic modules are arranged into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
Clusters are grouped together into SuperClusters
(Figure 1-4 on page 1-3). SuperCluster 1 is a two-wide
grouping of Type 1 Clusters. SuperCluster 2 is a two-wide
group containing one Type 1 Cluster and one Type 2
Cluster. SX-A devices feature more SuperCluster 1
modules than SuperCluster 2 modules because designers
typically require significantly more combinatorial logic
than flip-flops.
Figure 1-2 R-Cell
Figure 1-3 C-Cell
DQ
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS CKP
CLR
PRE
Y
Routed
Data Input
S0 S1
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
SX-A Family FPGAs
v5.1 1-3
Routing Resources
The routing and interconnect resources of SX-A devices
are in the top two metal layers above the logic modules
(Figure 1-1 on page 1-1), providing optimal use of silicon,
thus enabling the entire floor of the device to be
spanned with an uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using the Actel patented metal-to-metal programmable
antifuse interconnect elements. The antifuses are
normally open circuits and, when programmed, form a
permanent low-impedance connection.
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 1-5 on page 1-4 and
Figure 1-6 on page 1-4). This routing architecture also
dramatically reduces the number of antifuses required to
complete a circuit, ensuring the highest possible
performance, which is often required in applications such
as fast counters, state machines, and data path logic. The
interconnect elements (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring
R-Cell in a given SuperCluster. DirectConnect uses a
hardwired signal path requiring no programmable
interconnection to achieve its fast signal propagation
time of less than 0.1 ns.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster, and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect path, delivering a maximum pin-to-pin
propagation time of 0.3 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. The Actel segmented routing structure provides
a variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
100% automatic place-and-route software to minimize
signal propagation delays.
The general system of routing tracks allows any logic
module in the array to be connected to any other logic
or I/O module. Within this system, most connections
typically require three or fewer antifuses, resulting in
fast and predictable performance.
The unique local and general routing structure featured
in SX-A devices allows 100% pin-locking with full logic
utilization, enables concurrent printed circuit board
(PCB) development, reduces design time, and allows
designers to achieve performance goals with minimum
effort.
Figure 1-4 Cluster Organization
Type 1 SuperCluster Type 2 SuperCluster
Cluster 1 Cluster 1 Cluster 2 Cluster 1
R-Cell C-Cell
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS CKP
CLR
PRE
YDQ
Routed
Data Input
S0 S1
SX-A Family FPGAs
1-4 v5.1
Figure 1-5 DirectConnect and FastConnect for Type 1 SuperClusters
Figure 1-6 DirectConnect and FastConnect for Type 2 SuperClusters
DirectConnect
• No Antifuses
• 0.1 ns Maximum Routing Delay
FastConnect
• One Antifuse
• 0.3 ns Maximum Routing Delay
Routing Segments
• Typically Two Antifuses
• Max. Five Antifuses
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
FastConnect
• One antifuse
DirectConnect
• No antifuses for
smallest routing delay
SX-A Family FPGAs
v5.1 1-5
Clock Resources
Actel’s high-drive routing structure provides three clock
networks (Table 1-1). The first clock, called HCLK, is
hardwired from the HCLK buffer to the clock select
multiplexor (MUX) in each R-cell. HCLK cannot be
connected to combinatorial logic. This provides a fast
propagation path for the clock signal. If not used, this
pin must be set as Low or High on the board. It must not
be left floating. Figure 1-7 describes the clock circuit
used for the constant load HCLK and the macros
supported.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Design
software and the pin must be tied to GND on the board.
Two additional clocks (CLKA, CLKB) are global clocks that
can be sourced from external pins or from internal logic
signals within the SX-A device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB pins are not used or sourced from signals,
these pins must be set as Low or High on the board. They
must not be left floating. Figure 1-8 describes the CLKA
and CLKB circuit used and the macros supported in SX-A
devices with the exception of A54SX72A.
In addition, the A54SX72A device provides four
quadrant clocks (QCLKA, QCLKB, QCLKC, and QCLKD—
corresponding to bottom-left, bottom-right, top-left,
and top-right locations on the die, respectively), which
can be sourced from external pins or from internal logic
signals within the device. Each of these clocks can
individually drive up to an entire quadrant of the chip,
or they can be grouped together to drive multiple
quadrants (Figure 1-9 on page 1-6). QCLK pins can
function as user I/O pins. If not used, the QCLK pins
must be tied Low or High on the board and must not be
left floating.
For more information on how to use quadrant clocks in
the A54SX72A device, refer to the Global Clock Networks
in Actel’s Antifuse Devices and Using A54SX72A and
RT54SX72S Quadrant Clocks application notes.
The CLKA, CLKB, and QCLK circuits for A54SX72A as well
as the macros supported are shown in Figure 1-10 on
page 1-6. Note that bidirectional clock buffers are only
available in A54SX72A. For more information, refer to
the "Pin Description" section on page 1-14.
Table 1-1 SX-A Clock Resources
A54SX08A A54SX16A A54SX32A A54SX72A
Routed Clocks (CLKA, CLKB) 2 2 2 2
Hardwired Clocks (HCLK) 1 1 1 1
Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD) 0 0 0 4
Figure 1-7 SX-A HCLK Clock Buffer
Figure 1-8 SX-A Routed Clock Buffer
Constant Load
Clock Network
HCLKBUF
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
SX-A Family FPGAs
1-6 v5.1
Figure 1-9 SX-A QCLK Architecture
Figure 1-10 A54SX72A Routed Clock and QCLK Buffer
4
4
4 QCLKBUFS
5:1 5:1
5:1 5:1
Quadrant 2
Quadrant 0
Quadrant 3
Quadrant 1
QCLKINT (to arra
y
)
QCLKINT (to array)
QCLKINT (to arra
y
)
QCLKINT (to array)
Clock Network
From Internal Logic
From Internal Logic
OE
QCLKBUF
QCLKBUFI
QCLKINT
QCLKINTI
QCLKBIBUF
QCLKBIBUFI
CLKBUF
CLKBUFI
CLKINT
CLKINTI
CLKBIBUF
CLKBIBUFI
SX-A Family FPGAs
v5.1 1-7
Other Architectural Features
Technology
The Actel SX-A family is implemented on a high-voltage,
twin-well CMOS process using 0.22 µ/0.25µ design
rules. The metal-to-metal antifuse is comprised of a
combination of amorphous silicon and dielectric material
with barrier metals and has a programmed ('on' state)
resistance of 25 with capacitance of 1.0 fF for low
signal impedance.
Performance
The unique architectural features of the SX-A family
enable the devices to operate with internal clock
frequencies of 350 MHz, causing very fast execution of
even complex logic functions. The SX-A family is an
optimal platform upon which to integrate the
functionality previously contained in multiple complex
programmable logic devices (CPLDs). In addition, designs
that previously would have required a gate array to meet
performance goals can be integrated into an SX-A device
with dramatic improvements in cost and time-to-market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
User Security
Reverse engineering is virtually impossible in SX-A
devices because it is extremely difficult to distinguish
between programmed and unprogrammed antifuses. In
addition, since SX-A is a nonvolatile, single-chip solution,
there is no configuration bitstream to intercept at device
power-up.
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
where they cannot be accessed or bypassed without
destroying access to the rest of the device, making both
invasive and more-subtle noninvasive attacks ineffective
against Actel antifuse FPGAs.
Look for this symbol to ensure your valuable IP is secure
(Figure 1-11).
For more information, refer to Actel’s Implementation of
Security in Actel Antifuse FPGAs application note.
I/O Modules
For a simplified I/O schematic, refer to Figure 1 in the
application note, Actel eX, SX-A, and RTSX-S I/Os.
Each user I/O on an SX-A device can be configured as an
input, an output, a tristate output, or a bidirectional pin.
Mixed I/O standards can be set for individual pins,
though this is only allowed with the same voltage as the
input. These I/Os, combined with array registers, can
achieve clock-to-output-pad timing as fast as 3.8 ns, even
without the dedicated I/O registers. In most FPGAs, I/O
cells that have embedded latches and flip-flops,
requiring instantiation in HDL code; this is a design
complication not encountered in SX-A FPGAs. Fast pin-
to-pin timing ensures that the device is able to interface
with any other device in the system, which in turn
enables parallel design of system components and
reduces overall design time. All unused I/Os are
configured as tristate outputs by the Actel Designer
software, for maximum flexibility when designing new
boards or migrating existing designs.
SX-A I/Os should be driven by high-speed push-pull
devices with a low-resistance pull-up device when being
configured as tristate output buffers. If the I/O is driven
by a voltage level greater than VCCI and a fast push-pull
device is NOT used, the high-resistance pull-up of the
driver and the internal circuitry of the SX-A I/O may
create a voltage divider. This voltage divider could pull
the input voltage below specification for some devices
connected to the driver. A logic '1' may not be correctly
presented in this case. For example, if an open drain
driver is used with a pull-up resistor to 5 V to provide the
logic '1' input, and VCCI is set to 3.3 V on the SX-A device,
the input signal may be pulled down by the SX-A input.
Each I/O module has an available power-up resistor of
approximately 50 k that can configure the I/O in a
known state during power-up. For nominal pull-up and
pull-down resistor values, refer to Table 1-4 on page 1-8
of the application note Actel eX, SX-A, and RTSX-S I/Os.
Just slightly before VCCA reaches 2.5 V, the resistors are
disabled, so the I/Os will be controlled by user logic. See
Table 1-2 on page 1-8 and Table 1-3 on page 1-8 for
more information concerning available I/O features.
Figure 1-11 FuseLock
e
u
SX-A Family FPGAs
1-8 v5.1
Power-Up/Down and Hot Swapping
SX-A I/Os are configured to be hot-swappable, with the
exception of 3.3 V PCI. During power-up/down (or partial
up/down), all I/Os are tristated. VCCA and VCCI do not
have to be stable during power-up/down, and can be
powered up/down in any order. When the SX-A device is
plugged into an electrically active system, the device will
not degrade the reliability of or cause damage to the
host system. The device’s output pins are driven to a high
impedance state until normal chip operating conditions
are reached. Table 1-4 summarizes the VCCA voltage at
which the I/Os behave according to the user’s design for
an SX-A device at room temperature for various ramp-up
rates. The data reported assumes a linear ramp-up
profile to 2.5 V. For more information on power-up and
hot-swapping, refer to the application note, Actel SX-A
and RT54SX-S Devices in Hot-Swap and Cold-Sparing
Applications.
Table 1-2 I/O Features
Function Description
Input Buffer Threshold Selections 5 V: PCI, TTL
3.3 V: PCI, LVTTL
2.5 V: LVCMOS2 (commercial only)
Flexible Output Driver 5 V: PCI, TTL
3.3 V: PCI, LVTTL
2.5 V: LVCMOS2 (commercial only)
Output Buffer “Hot-Swap” Capability (3.3 V PCI is not hot swappable)
I/O on an unpowered device does not sink current
Can be used for “cold-sparing”
Selectable on an individual I/O basis
Individually selectable slew rate; high slew or low slew (The default is high slew rate).
The slew is only affected on the falling edge of an output. Rising edges of outputs are
not affected.
Power-Up Individually selectable pull-ups and pull-downs during power-up (default is to power-up
in tristate)
Enables deterministic power-up of device
VCCA and VCCI can be powered in any order
Table 1-3 I/O Characteristics for All I/O Configurations
Hot Swappable Slew Rate Control Power-Up Resistor
TTL, LVTTL, LVCMOS2 Yes Yes. Only affects falling edges of outputs Pull-up or pull-down
3.3 V PCI No No. High slew rate only Pull-up or pull-down
5 V PCI Yes No. High slew rate only Pull-up or pull-down
Table 1-4 Power-Up Time at which I/Os Become Active
Supply Ramp Rate 0.25 V/µs 0.025 V/µs 5 V/ms 2.5 V/ms 0.5 V/ms 0.25 V/ms 0.1 V/ms 0.025 V/ms
Units µsµsmsmsmsmsms ms
A54SX08A 10 96 0.34 0.65 2.7 5.4 12.9 50.8
A54SX16A 10 100 0.36 0.62 2.5 4.7 11.0 41.6
A54SX32A 10 100 0.46 0.74 2.8 5.2 12.1 47.2
A54SX72A 10 100 0.41 0.67 2.6 5.0 12.1 47.2
SX-A Family FPGAs
v5.1 1-9
Boundary-Scan Testing (BST)
All SX-A devices are IEEE 1149.1 compliant and offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
The BST function is controlled through the special JTAG
pins (TMS, TDI, TCK, TDO, and TRST). The functionality of
the JTAG pins is defined by two available modes:
Dedicated and Flexible. TMS cannot be employed as a
user I/O in either mode.
Dedicated Mode
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, the user must reserve the
JTAG pins in Actel’s Designer software. Reserve the JTAG
pins by checking the Reserve JTAG box in the Device
Selection Wizard (Figure 1-12).
The default for the software is Flexible mode; all boxes
are unchecked. Table 1-5 lists the definitions of the
options in the Device Selection Wizard.
Flexible Mode
In Flexible mode, TDI, TCK, and TDO may be employed as
either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are not present in
flexible JTAG mode.
To select the Flexible mode, uncheck the Reserve JTAG
box in the Device Selection Wizard dialog in the Actel
Designer software. In Flexible mode, TDI, TCK, and TDO
pins may function as user I/Os or BST pins. The
functionality is controlled by the BST Test Access Port
(TAP) controller. The TAP controller receives two control
inputs, TMS and TCK. Upon power-up, the TAP controller
enters the Test-Logic-Reset state. In this state, TDI, TCK,
and TDO function as user I/Os. The TDI, TCK, and TDO are
transformed from user I/Os into BST pins when a rising
edge on TCK is detected while TMS is at logic low. To
return to Test-Logic Reset state, TMS must be high for at
least five TCK cycles. An external 10 k pull-up resistor
to VCCI should be placed on the TMS pin to pull it
High by default.
Table 1-6 describes the different configuration
requirements of BST pins and their functionality in
different modes.
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan
Reset pin when the Reserve JTAG Test Reset option is
selected as shown in Figure 1-12. An internal pull-up
resistor is permanently enabled on the TRST pin in this
mode. Actel recommends connecting this pin to ground
in normal operation to keep the JTAG state controller in
the Test-Logic-Reset state. When JTAG is being used, it
can be left floating or can be driven high.
When the Reserve JTAG Test Reset option is not
selected, this pin will function as a regular I/O. If unused
as an I/O in the design, it will be configured as a tristated
output.
Figure 1-12 Device Selection Wizard
Table 1-5 Reserve Pin Definitions
Pin Function
Reserve JTAG Keeps pins from being used and
changes the behavior of JTAG pins (no
pull-up on TMS)
Reserve JTAG Test
Reset
Regular I/O or JTAG reset with an
internal pull-up
Reserve Probe Keeps pins from being used or regular
I/O
Table 1-6 Boundary-Scan Pin Configurations and
Functions
Mode
Designer
"Reserve JTAG"
Selection
TAP Controller
State
Dedicated (JTAG) Checked Any
Flexible (User I/O) Unchecked Test-Logic-Reset
Flexible (JTAG) Unchecked Any EXCEPT Test-
Logic-Reset
SX-A Family FPGAs
1-10 v5.1
JTAG Instructions
Table 1-7 lists the supported instructions with the corresponding IR codes for SX-A devices.
Table 1-8 lists the codes returned after executing the IDCODE instruction for SX-A devices. Note that bit 0 is always '1'.
Bits 11-1 are always '02F', which is the Actel manufacturer code.
Table 1-7 JTAG Instruction Code
Instructions (IR4:IR0) Binary Code
EXTEST 00000
SAMPLE/PRELOAD 00001
INTEST 00010
USERCODE 00011
IDCODE 00100
HighZ 01110
CLAMP 01111
Diagnostic 10000
BYPASS 11111
Reserved All others
Table 1-8 JTAG Instruction Code
Device Process Revision Bits 31-28 Bits 27-12
A54SX08A 0.22 µ 0 8, 9 40B4, 42B4
1 A, B 40B4, 42B4
A54SX16A 0.22 µ 0 9 40B8, 42B8
1 B 40B8, 42B8
0.25 µ 1 B 22B8
A54SX32A 0.2 2µ 0 9 40BD, 42BD
1 B 40BD, 42BD
0.25 µ 1 B 22BD
A54SX72A 0.22 µ 0 9 40B2, 42B2
1 B 40B2, 42B2
0.25 µ 1 B 22B2
SX-A Family FPGAs
v5.1 1-11
Probing Capabilities
SX-A devices also provide an internal probing capability
that is accessed with the JTAG pins. The Silicon Explorer II
diagnostic hardware is used to control the TDI, TCK, TMS,
and TDO pins to select the desired nets for debugging.
The user assigns the selected internal nets in Actel Silicon
Explorer II software to the PRA/PRB output pins for
observation. Silicon Explorer II automatically places the
device into JTAG mode. However, probing functionality is
only activated when the TRST pin is driven high or left
floating, allowing the internal pull-up resistor to pull
TRST High. If the TRST pin is held Low, the TAP controller
remains in the Test-Logic-Reset state so no probing can
be performed. However, the user must drive the TRST pin
High or allow the internal pull-up resistor to pull TRST
High.
When selecting the Reserve Probe Pin box as shown in
Figure 1-12 on page 1-9, direct the layout tool to reserve
the PRA and PRB pins as dedicated outputs for probing.
This Reserve option is merely a guideline. If the designer
assigns user I/Os to the PRA and PRB pins and selects the
Reserve Probe Pin option, Designer Layout will
override the Reserve Probe Pin option and place the
user I/Os on those pins.
To allow probing capabilities, the security fuse must not
be programmed. Programming the security fuse disables
the JTAG and probe circuitry. Table 1-9 summarizes the
possible device configurations for probing once the
device leaves the Test-Logic-Reset JTAG state.
Table 1-9 Device Configuration Options for Probe Capability (TRST Pin Reserved)
JTAG Mode TRST1Security Fuse Programmed PRA, PRB2TDI, TCK, TDO2
Dedicated Low No User I/O3JTAG Disabled
High No Probe Circuit Outputs JTAG I/O
Flexible Low No User I/O3User I/O3
High No Probe Circuit Outputs JTAG I/O
Yes Probe Circuit Secured Probe Circuit Secured
Notes:
1. If the TRST pin is not reserved, the device behaves according to TRST = High as described in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
the Designer software.
SX-A Family FPGAs
1-12 v5.1
SX-A Probe Circuit Control Pins
SX-A devices contain internal probing circuitry that
provides built-in access to every node in a design,
enabling 100% real-time observation and analysis of a
device's internal logic nodes without design iteration.
The probe circuitry is accessed by Silicon Explorer II, an
easy to use, integrated verification and logic analysis tool
that can sample data at 100 MHz (asynchronous) or
66 MHz (synchronous). Silicon Explorer II attaches to a
PC’s standard COM port, turning the PC into a fully
functional 18-channel logic analyzer. Silicon Explorer II
allows designers to complete the design verification
process at their desks and reduces verification time from
several hours per cycle to a few seconds.
The Silicon Explorer II tool uses the boundary-scan ports
(TDI, TCK, TMS, and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 1-13 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification.
Design Considerations
In order to preserve device probing capabilities, users
should avoid using the TDI, TCK, TDO, PRA, and PRB pins
as input or bidirectional ports. Since these pins are active
during probing, critical input signals through these pins
are not available. In addition, the security fuse must not
be programmed to preserve probing capabilities. Actel
recommends that you use a 70 series termination
resistor on every probe connector (TDI, TCK, TMS, TDO,
PRA, PRB). The 70 series termination is used to prevent
data transmission corruption during probing and
reading back the checksum.
Figure 1-13 Probe Setup
16
Additional
Channels
SX-A FPGA
70
70
70
70
70
70
TDI
TCK
TMS
TDO
PRA
PRB
Serial Connection Silicon Explorer II
SX-A Family FPGAs
v5.1 1-13
Design Environment
The SX-A family of FPGAs is fully supported by both Actel
Libero® Integrated Design Environment (IDE) and
Designer FPGA development software. Actel Libero IDE is
a design management environment, seamlessly
integrating design tools while guiding the user through
the design flow, managing all design and log files, and
passing necessary design data among tools. Additionally,
Libero IDE allows users to integrate both schematic and
HDL synthesis into a single flow and verify the entire
design in a single environment. Libero IDE includes
Synplify® for Actel from Synplicity®, ViewDraw® for
Actel from Mentor Graphics®, ModelSim® HDL Simulator
from Mentor Graphics, WaveFormer Lite™ from
SynaptiCAD™, and Designer software from Actel. Refer
to the Libero IDE flow diagram for more information
(located on the Actel website).
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven place-and-route, and a world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can select and lock
package pins while only minimally impacting the results
of place-and-route. Additionally, the back-annotation
flow is compatible with all the major simulators and the
simulation results can be cross-probed with Silicon
Explorer II, Actel’s integrated verification and logic
analysis tool. Another tool included in the Designer
software is the ACTgen macro builder, which easily
creates popular and commonly used logic functions for
implementation in your schematic or HDL design. Actel's
Designer software is compatible with the most popular
FPGA design entry and verification tools from companies
such as Mentor Graphics, Synplicity, Synopsys, and
Cadence Design Systems. The Designer software is
available for both the Windows and UNIX operating
systems.
Programming
Programming support is provided through Actel's Silicon
Sculptor II, a single-site programmer driven via a PC
based GUI. In addition, BP Microsystems offers multi-site
programmers that provide qualified support for Actel
devices. Factory programming is available for high
volume production needs.
For detail information on programming, visit:
http://www.actel.com/products/tools/prog.aspx .
Related Documents
Application Notes
Global Clock Networks in Actel’s Antifuse Devices
http://www.actel.com/documents/GlobalClk.pdf
Using A54SX72A and RT54SX72S Quadrant Clocks
http://www.actel.com/documents/QCLK.pdf
Implementation of Security in Actel Antifuse FPGAs
http://www.actel.com/documents/
AntifuseSecurityAN.pdf
Actel eX, SX-A, and RTSX-S I/Os
http://www.actel.com/documents/antifuseIOan.pdf
Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-
Sparing Applications
http://www.actel.com/documents/
HotSwapColdSparing.pdf
Datasheets
HiRel SX-A Family FPGAs
http://www.actel.com/documents/HRSXADS.pdf
SX-A Automotive Family FPGAs
http://www.actel.com/documents/SXAAutoDS.pdf
SX-A Family FPGAs
1-14 v5.1
Pin Description
CLKA/B, I/O Clock A and B
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL,
LVTTL, LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. The
clock input is buffered prior to clocking the R-cells. When
not used, this pin must be tied Low or High (NOT left
floating) on the board to avoid unwanted power
consumption.
For A54SX72A, these pins can also be configured as user
I/Os. When employed as user I/Os, these pins offer built-
in programmable pull-up or pull-down resistors active
during power-up only. When not used, these pins must
be tied Low or High (NOT left floating).
QCLKA/B/C/D, I/O Quadrant Clock A, B, C, and D
These four pins are the quadrant clock inputs and are
only used for A54SX72A with A, B, C, and D
corresponding to bottom-left, bottom-right, top-left,
and top-right quadrants, respectively. They are clock
inputs for clock distribution networks. Input levels are
compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V
PCI, or 5 V PCI specifications. Each of these clock inputs
can drive up to a quarter of the chip, or they can be
grouped together to drive multiple quadrants. The clock
input is buffered prior to clocking the R-cells. When not
used, these pins must be tied Low or High on the board
(NOT left floating).
These pins can also be configured as user I/Os. When
employed as user I/Os, these pins offer built-in
programmable pull-up or pull-down resistors active
during power-up only.
GND Ground
Low supply voltage.
HCLK Dedicated (Hardwired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL, LVTTL,
LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. This input is
directly wired to each R-cell and offers clock speeds
independent of the number of R-cells being driven.
When not used, HCLK must be tied Low or High on the
board (NOT left floating). When used, this pin should be
held Low or High during power-up to avoid unwanted
static power consumption.
I/O Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL, LVTTL, LVCMOS2, 3.3 V PCI or 5 V PCI specifications.
Unused I/O pins are automatically tristated by the
Designer software.
NC No Connection
This pin is not connected to circuitry within the device
and can be driven to any voltage or be left floating with
no effect on the operation of the device.
PRA/B, I/O Probe A/B
The Probe pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the other
probe pin to allow real-time diagnostic output of any
signal path within the device. The Probe pin can be used
as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be
permanently disabled to protect programmed design
confidentiality.
TCK, I/O Test Clock
Test clock input for diagnostic probe and device
programming. In Flexible mode, TCK becomes active
when the TMS pin is set Low (refer to Table 1-6 on
page 1-9). This pin functions as an I/O when the
boundary scan state machine reaches the "logic reset"
state.
TDI, I/O Test Data Input
Serial input for boundary scan testing and diagnostic
probe. In Flexible mode, TDI is active when the TMS pin is
set Low (refer to Table 1-6 on page 1-9). This pin
functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
TDO, I/O Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set Low (refer to
Table 1-6 on page 1-9). This pin functions as an I/O when
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer II is being used, TDO
will act as an output when the checksum command is
run. It will return to user /IO when checksum is complete.
TMS Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set Low, the TCK, TDI, and
TDO pins are boundary scan pins (refer to Table 1-6 on
page 1-9). Once the boundary scan pins are in test mode,
they will remain in that mode until the internal
boundary scan state machine reaches the logic reset
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The logic
reset state is reached five TCK cycles after the TMS pin is
set High. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
TRST, I/O Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the Reserve JTAG Reset Pin is
not selected in Designer.
VCCI Supply Voltage
Supply voltage for I/Os. See Table 2-2 on page 2-1. All
VCCI power pins in the device should be connected.
VCCA Supply Voltage
Supply voltage for array. See Table 2-2 on page 2-1. All
VCCA power pins in the device should be connected.
SX-A Family FPGAs
v5.1 2-1
Detailed Specifications
Operating Conditions
Typical SX-A Standby Current
Table 2-1 Absolute Maximum Ratings
Symbol Parameter Limits Units
VCCI DC Supply Voltage for I/Os –0.3 to +6.0 V
VCCA DC Supply Voltage for Arrays –0.3 to +3.0 V
VIInput Voltage –0.5 to +5.75 V
VOOutput Voltage –0.5 to +VCCI+0.5 V
TSTG Storage Temperature –65 to +150 °C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
"Recommended Operating Conditions".
Table 2-2 Recommended Operating Conditions
Parameter Commercial Industrial Units
Temperature Range 0 to +70 –40 to +85 °C
2.5 V Power Supply Range (VCCA and VCCI) 2.25 to 2.75 2.25 to 2.75 V
3.3 V Power Supply Range (VCCI) 3.0 to 3.6 3.0 to 3.6 V
5 V Power Supply Range (VCCI) 4.75 to 5.25 4.75 to 5.25 V
Table 2-3 Typical Standby Current for SX-A at 25°C with VCCA = 2.5 V
Product VCCI = 2.5 V VCCI = 3.3 V VCCI = 5 V
A54SX08A 0.8 mA 1.0 mA 2.9 mA
A54SX16A 0.8 mA 1.0 mA 2.9 mA
A54SX32A 0.9 mA 1.0 mA 3.0 mA
A54SX72A 3.6 mA 3.8 mA 4.5 mA
Table 2-4 Supply Voltages
VCCA VCCI* Maximum Input Tolerance Maximum Output Drive
2. 5 V 2.5 V 5.75 V 2.7 V
2.5 V 3.3 V 5.75 V 3.6 V
2.5 V 5 V 5.75 V 5.25 V
Note: *3.3 V PCI is not 5 V tolerant due to the clamp diode, but instead is 3.3 V tolerant.
SX-A Family FPGAs
2-2 v5.1
Electrical Specifications
Table 2-5 3.3 V LVTTL and 5 V TTL Electrical Specifications
Symbol Parameter
Commercial Industrial
Min. Max. Min. Max. Units
VOH VCCI = Minimum
VI = VIH or VIL
(IOH = –1 mA) 0.9 VCCI 0.9 VCCI V
VCCI = Minimum
VI = VIH or VIL
(IOH = –8 mA) 2.4 2.4 V
VOL VCCI = Minimum
VI = VIH or VIL
(IOL= 1 mA) 0.4 0.4 V
VCCI = Minimum
VI = VIH or VIL
(IOL= 12 mA) 0.4 0.4 V
VIL Input Low Voltage 0.8 0.8 V
VIH Input High Voltage 2.0 5.75 2.0 5.75 V
IIL/IIH Input Leakage Current, VIN = VCCI or GND –10 10 –10 10 µA
IOZ Tristate Output Leakage Current –10 10 –10 10 µA
tR, tFInput Transition Time tR, tF10 10 ns
CIO I/O Capacitance 10 10 pF
ICC Standby Current 10 20 mA
IV Curve* Can be derived from the IBIS model on the web.
Note: *The IBIS model can be found at http://www.actel.com/techdocs/models/ibis.html.
Table 2-6 2.5 V LVCMOS2 Electrical Specifications
Symbol Parameter
Commercial Industrial
Min. Max. Min. Max. Units
VOH VDD = MIN,
VI = VIH or VIL
(IOH = –100 µA) 2.1 2.1 V
VDD = MIN,
VI = VIH or VIL
(IOH = –1 mA) 2.0 2.0 V
VDD = MIN,
VI = VIH or VIL
(IOH =–-2 mA) 1.7 1.7 V
VOL VDD = MIN,
VI = VIH or VIL
(IOL= 100 µA) 0.2 0.2 V
VDD = MIN,
VI = VIH or VIL
(IOL= 1 mA) 0.4 0.4 V
VDD = MIN,
VI = VIH or VIL
(IOL= 2 mA) 0.7 0.7 V
VIL Input Low Voltage, VOUT VVOL(max) -0.3 0.7 -0.3 0.7 V
VIH Input High Voltage, VOUT VVOH(min) 1.75.751.75.75V
IIL/IIH Input Leakage Current, VIN = VCCI or GND –10 10 –10 10 µA
IOZ Tristate Output Leakage Current, VOUT = VCCI or GND –10 10 –10 10 µA
tR, tFInput Transition Time tR, tF10 10 ns
CIO I/O Capacitance 10 10 pF
ICC Standby Current 10 20 mA
IV Curve* Can be derived from the IBIS model on the web.
Note: *The IBIS model can be found at http://www.actel.com/techdocs/models/ibis.html.
SX-A Family FPGAs
v5.1 2-3
PCI Compliance for the SX-A Family
The SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
Table 2-7 DC Specifications (5 V PCI Operation)
Symbol Parameter Condition Min. Max. Units
VCCA Supply Voltage for Array 2.25 2.75 V
VCCI Supply Voltage for I/Os 4.75 5.25 V
VIH Input High Voltage 2.0 5.75 V
VIL Input Low Voltage –0.5 0.8 V
IIH Input High Leakage Current1VIN = 2.7 70 µA
IIL Input Low Leakage Current1VIN = 0.5 –70 µA
VOH Output High Voltage IOUT = –2 mA 2.4 V
VOL Output Low Voltage2IOUT = 3 mA, 6 mA 0.55 V
CIN Input Pin Capacitance3–10pF
CCLK CLK Pin Capacitance 5 12 pF
Notes:
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter includes
FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and
ACK64#.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
SX-A Family FPGAs
2-4 v5.1
Table 2-8 AC Specifications (5 V PCI Operation)
Symbol Parameter Condition Min. Max. Units
IOH(AC) Switching Current High 0 < VOUT 1.4 1–44 mA
1.4 VOUT < 2.4 1, 2 (–44 + (VOUT – 1.4)/0.024) mA
3.1 < VOUT < VCCI 1, 3 EQ 2-1 on
page 2-5
(Test Point) VOUT = 3.1 3––142mA
IOL(AC) Switching Current Low VOUT 2.2 195 mA
2.2 > VOUT > 0.55 1(VOUT/0.023) mA
0.71 > VOUT > 0 1, 3 EQ 2-2 on
page 2-5
(Test Point) VOUT = 0.71 3 206 mA
ICL Low Clamp Current –5 < VIN –1 –25 + (VIN + 1)/0.015 mA
slewROutput Rise Slew Rate 0.4 V to 2.4 V load 415V/ns
slewFOutput Fall Slew Rate 2.4 V to 0.4 V load 415V/ns
Notes:
1. Refer to the V/I curves in Figure 2-1 on page 2-5. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A
and B) are provided with the respective diagrams in Figure 2-1 on page 2-5. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not
required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge
rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and
should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.
Output
Buffer
1/2 in. max.
50 pF
Pin