REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Boilerplate update, part of 5 year review. ksr 06-11-08 Raymond Monnin
THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.
REV
SHEET
REV A A A A A A
SHEET 15 16 17 18 19 20
REV STATUS REV A A A A A A A A A A A A A A
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
James E. Jamison
DEFENSE SUPPLY CENTER COLUMBUS
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Charles Reusing
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
APPROVED BY
Michael A. Frye
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
90-09-17
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, PARALLEL 512 X 9 FIFO ,
MONOLITHIC SILICON
AMSC N/A
REVISION LEVEL
A SIZE
A CAGE CODE
67268
5962-89863
SHEET
1 OF
20
DSCC FORM 2233
APR 97 5962-E011-07
.
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A SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-89863 01 X A
Drawing number Device type
(see 1.2.1) Case outline
(see 1.2.2) Lead finish
(see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number 1/ Circuit function Acess time
01 512 X 9 FIFO 80 ns
02 512 X 9 FIFO 65 ns
03 512 X 9 FIFO 50 ns
04 512 X 9 FIFO 40 ns
05 512 X 9 FIFO 30 ns
06 512 X 9 FIFO 25 ns
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
X GDIP1-T28 or CDIP2-T28 28 dual-in-line package
Y CDIP3-T28 or GDIP4-T28 28 dual-in-line package
Z CQCC1-N32 32 rectangular chip carrier package
U GDFP2-F28 28 flat package
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
Supply voltage to ground potential ------------------------------ -0.5 V dc to +7.0 V dc
DC voltage applied to outputs in high Z state ---------------- -0.5 V dc to +7.0 V dc
DC input voltage ----------------------------------------------------- -0.3 V dc to +7.0 V dc
DC output current ---------------------------------------------------- 20 mA
Maximum power dissipation 2/ ----------------------------------- 1.0 W
Lead temperature (soldering, 10 seconds) -------------------- +260°C
Thermal resistance, junction-to-case (ΘJC) -------------------- See MIL-STD-1835
Junction temperature (TJ) 3/ ------------------------------------- +150°C
Storage temperature range --------------------------------------- -65°C to +150°C
Temperature under bias ------------------------------------------- -55°C to +125°C
1.4 Recommended operating conditions.
Supply voltage (VCC)------------------------------------------------- +4.5 V dc to +5.5 V dc
Ground voltage (GND)---------------------------------------------- 0 V dc
Input high voltage (VIH) -------------------------------------------- 2.2 V dc minimum
Input low voltage (VIL) ---------------------------------------------- 0.8 V dc maximum
Case operating temperature range (TC) ------------------------ -55°C to +125°C
1/ Generic numbers are listed on the Standardized Military Drawing Source Approval Bulletin at the end of this document and
will also be listed in MIL-HDBK-103.
2/ Must withstand the added PD due to short circuit test (e.g., IOS).
3/ Maximum junction temperature may be increased to +175°C during burn-in and steady-state life.
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APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-
PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying
activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan
may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.
These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-
PRF-38535 is required to identify when the QML flow option is used.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535, appendix A and herein.
3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.2 Truth table. The truth table shall be as specified on figure 2.
3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein.
3.2.4 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection
only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass
the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor
testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements
as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics
are as specified in table I and shall apply over the full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
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APR 97
TABLE I. Electrical performance characteristics.
Limits
Test
Symbol
Conditions 1/
-55°C TA +125°C
4.5 V VCC 5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Min
Max
Unit
Output high voltage
VOH
VCC = 4.5 V, IOH = -2.0 mA
VIN = VIH, VIL
1, 2, 3 All 2.4 V
Output low voltage
VOL
VCC = 4.5 V, IOH = 8.0 mA
VIN = VIH, VIL
1, 2, 3 All 0.4 V
Input high voltage
VIH 2/
1, 2, 3 All 2.2 V
Input low voltage
VIL 2/
1, 2, 3 All 0.8 V
Input leakage current
IIX
VIN = 5.5 V to GND 1, 2, 3 All -10 +10 µA
Output leakage
current
IOZ
VCC = 5.5 V,
VOUT = 5.5 V to GND
1, 2, 3 All -10 +10 µA
01, 02 115
03 130
04, 05 140
Operating supply
current
ICC1
VCC = 5.5 V, IOUT = 0 mA
f = 1/tRC
W, R, D0 - D8 pins are
toggling between 0 V and 3 V
FF, XO / HF = 0 mA
Q0 - Q8 = 0 mA
MR, FL /RT = 3.0 V
1, 2, 3
06 147
mA
Standby current
ICC2
VCC = 5.5 V, IOUT = 0 mA
All inputs = VIH
FF, XO / HF = 0 mA
Q0 - Q8 = 0 mA
1, 2, 3 All 30 mA
Power down current
ICC3
VCC = 5.5 V, IOUT = 0 mA
All inputs = VCC -0.2 V
FF, XO / HF = 0 mA
Q0 - Q8 = 0 mA
1, 2, 3 All 25 mA
Input capacitance
CIN 3/
VCC = 5.0 V
TA = +25°C, f = 1 MHz
See 4.3.1c
4 All 8 pF
Output capacitance
COUT 3/
VCC = 5.0 V
TA = +25°C, f = 1 MHz
See 4.3.1c
4 All 8 pF
Functional tests See 4.3.1d 7,8 All
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Conditions 1/
-55°C TA +125°C
4.5 V VCC 5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Min
Max
Unit
01 100
02 80
03 65
04 50
05 40
Read cycle time
tRC 9, 10, 11
06 35
ns
01 80
02 65
03 50
04 40
05 30
Access time
tA 9, 10, 11
06 25
ns
01 20
02
,
03 15
Read recovery time
tRR 9, 10, 11 04
,
05
,
06 10
ns
01 80
02 65
03 50
04 40
05 30
Read pulse width
tPR 9, 10, 11
06 25
ns
Read low to low Z
tLZR 3/ 4/ 9, 10, 11 All 3 ns
Read high to data
valid
tDVR 9, 10, 11 All 3 ns
01
,
02
,
03 30
04 25
05 20
Read high to high Z
tHZR 3/ 4/ 9, 10, 11
06 18
ns
01 100
02 80
03 65
04 50
05 40
Write cycle time
tWC
See figure 3
9, 10, 11
06 35
ns
01 80
02
65
03
50
04
40
05
30
Write pulse width
tPW
9, 10, 11
06
25
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Conditions 1/
-55°C TA +125°C
4.5 V VCC 5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Min
Max
Unit
Write high to low Z
tHWZ 3/ 4/
9, 10, 11
All
10
ns
01
20
02, 03
15
Write recovery time
tWR 9, 10, 11
04,05,06
10
ns
01
40
02,03
30
04
20
05
18
Data setup time
tSD 9, 10, 11
06
15
ns
01,02
10
03
5
Data hold time
tHD 9, 10, 11
04,05,06
0
ns
01
10
0
02
80
03
65
04
50
05
40
Master reset cycle
time
tMRSC 9, 10, 11
06
35
ns
01
80
02
65
03
50
04
40
05
30
Master reset pulse
width
tPMR 9, 10, 11
06
25
ns
01
20
02,03
15
Master reset
recovery time
tRMR 9, 10, 11
04,05,06
10
ns
01
80
02
65
03
50
04
40
05
30
Read high to master
reset high
tRPW 3/ 9, 10, 11
06
25
ns
01 80
02
65
03
50
04
40
05
30
Write high to master
reset high
tWPW 3/
See figure 3
9, 10, 11
06
25
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Conditions 1/
-55°C TA +125°C
4.5 V VCC 5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Min
Max
Unit
01
100
02
80
03
65
04
50
05
40
Retransmit cycle time
tRTC 9, 10, 11
06
35
ns
01
80
02
65
03
50
04
40
05
30
Retransmit pulse
width
tPRT 9, 10, 11
06
25
ns
01
20
02,03
15
Retransmit recovery
time
tRTR 9, 10, 11 04,05,06 10
ns
01
100
02
80
03
65
04
50
05
40
Master reset to empty
flag low
tEFL 9, 10, 11
06
35
ns
01
100
02
80
03
65
04
50
05
40
Master reset to half-
full flag high
tHFH 9, 10, 11
06
35
ns
01
100
02
80
03
65
04
50
05
40
Master reset to full
flag high
tFFH 9, 10, 11
06
35
ns
01,02
60
03
45
04
35
05
30
Read low to empty
flag low
tREF 9, 10, 11
06
25
ns
01,02
60
03
45
04
35
05
30
Read high to full flag
high
tRFF
See figure 3
9, 10, 11
06
25
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Conditions 1/
-55°C TA +125°C
4.5 V VCC 5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Min
Max
Unit
01
,
02 60
03
45
04
35
05
30
Write high to empty
flag high
tWEF 9, 10, 11
06
25
ns
01,02
60
03
45
04
35
05
30
Write low to full flag
low
tWFF 9, 10, 11
06
25
ns
01
100
02
80
03
65
04
50
05
40
Write low to half-full
flag low
tWHF 9, 10, 11
06
35
ns
01
100
02
80
03
65
04
50
05
40
Read high to half-full
flag high
tRHF 9, 10, 11
06
35
ns
01,02
60
03
45
04
35
05
30
Effective read from
write high
tRAE 3/ 9, 10, 11
06
25
ns
01
80
02
65
03
50
04
40
05
30
Effective read pulse
width after empty
flag high
tRPE 9, 10, 11
06
25
ns
01,02
60
03
45
04
35
05
3
0
Effective write from
read high
tWAF 3/ 9, 10, 11
06
25
ns
01
80
02
65
03
50
04
40
05
30
Effective write pulse
width after full
flag high
tWPF
See figure 3
9, 10, 11
06
25
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Conditions 1/
-55°C TA +125°C
4.5 V VCC 5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Min
Max
Unit
01 80
02 65
03 50
04 40
05 30
Expansion out low
delay from clock tXOL 9, 10, 11
06 25
ns
01 80
02 65
03 50
04 40
05 30
Expansion out high
delay from clock tXOH
See figure 3
9, 10, 11
06 25
ns
1/ AC tests are performed with input rise and fall times of 5ns or less, timing reference levels of 1.5 V, input pulse levels
of 0 V to 3.0 V, and the output load on figure 4.
2/ These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
3/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to
the limits specified in table1.
4/ Transition is measured at steady-state high level -500 mV or steady-state low level +500 mV on the output from the 1.5 V
level on the input.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN
listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD
PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in
compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification
mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-
38535, appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.
3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
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Device
types
All
Case
outlines
U, X, Y
Z
Terminal
number
Terminal
symbol
1
2
3
4
5
W
D8
D3
D2
D1
NC
W
D8
D3
D2
6
7
8
9
10
D0
XI
FF
Q0
Q1
D1
D0
XI
FF
Q
0
11
12
13
14
15
Q2
Q3
Q8
GND
R
Q1
NC
Q2
Q3
Q8
16
17
18
19
20
Q4
Q5
Q6
Q7
XO/HF
GND
NC
R
Q4
Q5
21
22
23
24
25
EF
MR
FL /RT
D7
D6
Q6
Q7
XO/HF
EF
MR
26
27
28
29
30
D5
D4
VCC
-
-
FL /RT
NC
D7
D6
D5
31
32
-
-
D4
VCC
FIGURE 1. Terminal connections.
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Reset and retransmit
Single device configuration/width expansion mode
Inputs Internal status Outputs
Mode MR RT XI Read pointer Write pointer EF FF HF
Reset
Retransmit
Read/Write
0
1
1
X
0
1
0
0
0
Location zero
Location zero
Increment 1/
Location zero
Unchanged
Increment 1/
0
X
X
1
X
X
1
X
X
1/ Pointer will increment if flag is high.
Reset and first load truth table
Depth expansion/compound expansion mode
Inputs Internal status Outputs
Mode MR FL XI Read pointer Write pointer EF FF
Reset first device
Reset all other devices
Read/Write
0
0
1
0
1
X
1/
1/
1/
Location zero
Location zero
X
Location zero
Location zero
X
0
0
X
1
1
X
1/ XI is connected to XO of previous device.
NOTE: MR = Reset input, FL /RT = First load/retransmit EF = Empty flag output,
FF = Full flag output, XI = Expansion input, and HF = Half-full flag output
FIGURE 2. Truth table.
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FIGURE 3. Timing waveforms.
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NOTES:
1. tRTC = tPRT + tRTR.
2. E_F_, H_F_, and F_F_ may change state during retransmit as a result of the
offset of the read write pointer, but flags will be valid at tRTC.
FIGURE 3. Timing waveforms - Continued.
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NOTES:
1. tMRSC = tPMR + tRMR.
2. W and R = VIH around the rising edge of MR
FIGURE 3. Timing waveforms - Continued.
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FIGURE 3. Timing waveforms - Continued.
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FIGURE 3. Timing waveforms - Continued.
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NOTE: Expansion Out of device 1 ( XO1) is connected to Expansion In of device 2 ( XI2).
FIGURE 3. Timing waveforms - Continued.
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AC test conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
GND to 3.0 V
5 ns
1.5 V
1,5 V
FIGURE 4. Output load circuit and test conditions.
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4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all
devices prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition D or E. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of
MIL-STD-883.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
tests prior to burn-in are optional at the discretion of the manufacturer.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-
STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroup 4 (CIN and COUT measurement) shall be measured only for the initial test and after process or design
changes which may affect capacitance. Sample size is fifteen devices with no failures and all input and output
terminals tested.
d. Subgroups 7 and 8 tests shall include verification of the truth table.
4.3.2 Groups C and D inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition D or E. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89863
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
A SHEET 20
DSCC FORM 2234
APR 97
TABLE II. Electrical test requirements. 1/ 2/ 3/
MIL-STD-883 test requirements Subgroups
(per method
5005, table I)
Interim electrical parameters
(method 5004)
---
Final electrical test parameters
(method 5004)
1*, 2, 3, 7*, 8A, 8B,
9, 10,11
Group A test requirements
(method 5005)
1, 2, 3, 4**, 7, 8A, 8B,
9, 10, 11
Groups C and D end-point electrical
parameters (method 5005)
2, 3, 7, 8A, 8B
1/ * indicates PDA applies to subgroups 1 and 7.
2/ ** see 4.3.1c.
3/ see 4.3.1d.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be
used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC
5962) should contact DSCC-VA, telephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-
HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted
by DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 06-11-08
Approved sources of supply for SMD 5962-89863 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor similar
PIN 2/
5962-8986301UA 0C7V7
3/
CY7C421-80KMB
IDT7201SA80XEB
5962-8986301XA 0C7V7
3/
CY7C420-80DMB
IDT7201SA80DB
5962-8986301YA 0C7V7
3/
3/
CY7C421-80DMB
IDT7201SA80TDB
MM1P-67201-55MB
5962-8986301ZA 0C7V7
3/
3/
CY7C421-80LMB
IDT7201SA80LB
MM4J-67201-55MB
5962-8986302UA 0C7V7
3/
CY7C421-65KMB
IDT7201SA65XEB
5962-8986302XA 0C7V7
3/
CY7C420-65DMB
IDT7201SA65DB
5962-8986302YA 0C7V7
3/
3/
CY7C421-65DMB
IDT7201SA65TDB
MM1P-67201-55MB
5962-8986302ZA 0C7V7
3/
3/
CY7C421-65LMB
IDT7201SA65LB
MM4J-67201-55MB
5962-8986303UA 0C7V7
3/
CY7C421-50KMB
IDT7201SA50XEB
5962-8986303XA 0C7V7
3/
CY7C420-50DMB
IDT7201SA50DB
5962-8986303YA 0C7V7
61772
3/
CY7C421-50DMB
IDT7201SA50TDB
MM1P-67201-45MB
5962-8986303ZA 0C7V7
3/
3/
CY7C421-50LMB
IDT7201SA50LB
MM4J-67201-45MB
5962-8986304UA 0C7V7
3/
CY7C421-40KMB
IDT7201SA40XEB
5962-8986304XA 0C7V7
3/
CY7C421-40DMB
IDT7201SA40DB
See footnotes at end of table.
Page 1 of 2
STANDARD MICROCIRCUIT DRAWING BULLETIN – Continued.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor similar
PIN 1/
5962-8986304YA 0C7V7
3/
3/
CY7C421-40DMB
IDT7201SA40TDB
MM1P-67201-35MB
5962-8986304ZA 0C7V7
3/
3/
CY7C421-40LMB
IDT7201SA40LB
MM4J-67201-35MB
5962-8986305UA 0C7V7
3/
CY7C421-30KMB
IDT7201SA30XEB
5962-8986305XA 0C7V7
3/
CY7C420-30DMB
IDT7201SA30DB
5962-8986305YA 0C7V7
61772
CY7C421-30DMB
IDT7201SA30TDB
5962-8986305ZA 0C7V7
3/
CY7C421-30LMB
IDT7201SA30LB
5962-8986306UA 0C7V7
CY7C421-25KMB
5962-8986306XA 0C7V7
CY7C420-25DMB
5962-8986306YA 0C7V7
CY7C421-25DMB
5962-8986306ZA 0C7V7
CY7C421-25LMB
1/ The lead finish shown for each PIN representing a hermetic package is the
most readily available from the manufacturer listed for that part. If the
desired lead finish is not listed, contact the Vendor to determine its
availability.
2/ Caution: Do not use this number for item acquisition. Items acquired to
this number may not satisfy the performance requirements of this drawing.
3/ Not available from an approved source.
Vendor CAGE Vendor name
number and address
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
61772 Integrated Device Technology, Inc.
2975 Stender Way
Santa Clara, CA 95054
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
Page 2 of 2