IDT70V7599S166BFI - Integrated Device Technology, Inc.

DECEMBER 2002

DSC 5626/4

Functional Block Diagram

Features:

◆128K x 36 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

–64 independent 2K x 36 banks

– 4 megabits of memory on chip

◆Bank access controlled via bank address pins

◆High-speed data access

– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

◆Selectable Pipelined or Flow-Through output mode

◆Counter enable and repeat features

◆Dual chip enables allow for depth expansion without

additional logic

◆Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆Separate byte controls for multiplexed bus and bus

matching compatibility

◆LVTTL- compatible, 3.3V (±150mV) power supply

for core

◆LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

◆Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

◆Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

Grid Array (BGA)

◆Supports JTAG features compliant with IEEE 1149.1

HIGH-SPEED 3.3V 128K x 36

SYNCHRONOUS

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70V7599S

2Kx36

MEMORY

ARRAY

(BANK 63)

MUX

PL/FTL

OPTL

CLKL

ADSL

CNTENL

REPEATL

R/WL

CE0L

CE1L

BE3L

BE2L

BE1L

BE0L

OEL

I/O0L-35L

A10L

A0L

JTAG

2Kx36

MEMORY

ARRAY

(BANK 1)

MUX

2Kx36

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

I/O0R-35R

A10R

A0R

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

5626 drw 01

BA5R

BA4R

BA3R

BA2R

BA1R

BA0R

BA5L

BA4L

BA3L

BA2L

BA1L

BA0L

PL/FTR

OPTR

CLKR

ADSR

CNTENR

REPEATR

R/WR

CE0R

CE1R

BE3R

BE2R

BE1R

BE0R

OER

TMS

TCK

TRST

TDI

TDO

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 19

for details.

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70V7599 is a high-speed 128Kx36 (4Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent

2Kx36 banks. The device has two independent ports with separate

control, address, and I/O pins for each port, allowing each port to access

any 2Kx36 memory block not already accessed by the other port.

Accesses by the ports into specific banks are controlled via the bank

address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup

and hold times. The timing latitude provided by this approach allows

systems to be designed with very short cycle times. With an input data

Pin Configuration(1,2,3,4)

NOTES:

1. All VDD pins must be connected to 3.3V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to VIL (0V).

3. All VSS pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

A17

VSS

B17

I/O15R

C17

VSS

D17

I/O14R

E16

VSS

E17

I/O13L

D16

I/O14L

C16

I/O15L

B16

I/O16L

A16

I/O17L

A15

OPTL

B15

VDDQR

C15

I/O16R

D15

VDDQL

E15

I/O13R

E14

I/O12L

D14

I/O17R

D13

VDD

C12

A6L C14

VDD

B14

VSS

A14

A0L

A12

CNTEN

B12

A5L

C11

R/WL

D12

A3L

D11

REPEAT

C10

VSS

B11

ADSL

A11

CLKL

BE0L

BE3L

BE1L

VDD

CE1L

CE0L

D10

OEL

A10L

BE2L

A8L

B13

A1L

A13

A4L

A10

VDD

A7L

A9L

BA1L

BA2L

BA3L

BA0L

C5NC

BA4L

TDO

TDI

PL/

I/O20L

VSS

I/O18R

VDDQR

I/O21L

VSS

I/O19R

VSS

IO18L

IO19L

I/O20R

VDDQL

I/O22L

I/O23L

I/O22R

VDDQR

I/O21R

VDDQL F2

I/O23R F3

I/O24L F4

VSS

I/O26L G2

VSS G3

I/O25L

I/O24R

VDD H2

I/O26R

VDDQR

I/O25R

VDDQL J2

VDD

J3VSS

J4VSS

I/O28R

VSS K3

I/O27R

VSS

I/O29R

I/O28L

VDDQR L4

I/O27L

VDDQL

I/O29L

I/O30R

VSS

I/O31L N2

VSS N3

I/O31R

I/O30L

I/O32R

I/O32L

VDDQR

I/O35R

VSS

I/O33L

I/O34R

TCK

I/O33R

I/O34L

VDDQL T4

TMS

VSS

I/O35L

PL/

TRST

BA0R

P12

CNTEN

A8R

U10

OER

BE1R

BE2R

BE3R

VDD

P10

VDD

T11

R/WR

BE0R

P11

CLKR

R12

A5R

T12

A6R

U12

A3R

P13

A4R

BA1R

R13

A1R

T13

A2R

U13

A0R

BA2R

T5NC

A7R U14

VDD

T14

VSS

R14

VSS

P14

I/O2L

P15

I/O3L

R15

VDDQL

T15

I/O0R

U15

OPTR

U16

I/O0L

U17

I/O1L

T16

VSS

T17

I/O2R

R17

VDDQR

R16

I/O1R

P17

I/O4L

P16

VSS

N17

I/O5L

N16

I/O4R

N15

VDDQL

N14

I/O3R

M17

VDDQR

M16

I/O5R

M15

I/O6L

M14

VSS

L17

I/O8L

L16

VSS

L15

I/O7L

L14

I/O6R

K17

VSS

K16

I/O8R

K15

VDDQL

K14

I/O7R

J17

VDDQR

J16

VSS

J15

VDD

J14

VSS

H17

I/O10R

H16

VSS

H15

IO9R

H14

VDD

G17

I/O11R

G16

I/O10L

G15

VDDQL

G14

I/O9L

F17

VDDQR

F16

I/O11L

F14

VSS

70V7599BF

BF-208(5)

208-Pin fpBGA

Top View(6)

F15

I/O12R

CE0R

R11

ADSR

BA3R

CE1R

BA5L

B10

VSS

C13

A2L

BA5R

R10

VSS

A9R

T10

VSS

A10R

BA4R

5626 drw 02c ,

11/08/01

unidirectional or bidirectional data flow in bursts. An automatic power down

feature, controlled by CE0 and CE1, permits the on-chip circuitry of each

port to enter a very low standby power mode. The dual chip enables also

facilitate depth expansion.

The 70V7599 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controllable by the OPT pins. The power supply for

the core of the device(VDD) remains at 3.3V. Please refer also to the

functional description on page 19.

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration(1,2,3,4) (con't.)

NOTES:

1. All VDD pins must be connected to 3.3V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to VIL (0V).

3. All VSS pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

70V7599BC

BC-256(5)

256-Pin BGA

Top View (6)

E16

I/O14R

D16

I/O16R

C16

I/O16L

B16

A16

A15

B15

I/O17L

C15

I/O17R

D15

I/O15L

E15

I/O14L

E14

I/O13L

D14

I/O15R

D13

VDD

C12

A6L C14

OPTL

B14

VDD

A14

A0L

A12

A5L

B12

A4L

C11

ADSL

D12

VDDQR

D11

VDDQR

C10

CLKL

B11

REPEAT

A11

CNTEN

VDDQR

BE1L

CE1L

VDDQL

BE0L

CE0L

D10

VDDQL

A7L

BE3L

BE2L

B13

A1L

A13

A2L

A10

OEL

VDDQR

A9L

A8L

BA1L

A10L

VDDQL

BA3L

BA4L

BA2L

VDDQL

BA5L

PL/FT

TDO

VSS

I/O20L

I/O19R

I/O19L

B2NC

TDI

I/O18L

I/O18R

I/O20R

I/O21R E2

I/O21L E3

I/O22L E4

VDDQL

I/O23L

I/O22R

I/O23R F4

VDDQL

I/O24R G2

I/O24L G3

I/O25L

VDDQR

I/O26L

I/O25R

I/O26R

VDDQR

I/O27L J2

I/O28R

I/O27R

VDDQL

I/O29R

I/O29L K3

I/O28L

VDDQL

I/O30L

I/O31R

I/O30R

VDDQR

I/O32R M2

I/O32L M3

I/O31L M4

VDDQR

I/O33L

I/O34R

I/O33R

PL/FT

I/O35R

I/O34L

TMS P4

BA5R

I/O35L R2NC R3

TRST

T1NC T2

TCK T3NC T4NC

BA2R

BA4R

P12

A6R

BE1R

BE0R

BE3R

BE2R

P10

CLKR

T11

CNTEN

P11

ADSR

R12

A4R

T12

A5R

P13

A3R

A7R

R13

A1R

T13

A2R

BA1R

BA3R T14

A0R

R14

OPTR

P14

I/O0L

P15

I/O0R

R15

T15

NC T16

R16

P16

I/O1L

N16

I/O2R

N15

I/O1R

N14

I/O2L

M16

I/O4L

M15

I/O3L

M14

I/O3R

L16

I/O5R

L15

I/O4R

L14

I/O5L

K16

I/O7L

K15

I/O6L

K14

I/O6R

J16

I/O8L

J15

I/O7R

J14

I/O8R

H16

I/O10R

H15

IO9L

H14

I/O9R

G16

I/O11R

G15

I/O11L

G14

I/O10L

F16

I/O12L

F14

I/O12R

F15

I/O13R

CE0R R11

REPEAT

BA0R

CE1R

BA0L

B10

R/WL

C13

A3L

A10R

R10

R/WR

A9R

T10

OER

A8R

VDD

VSS

E10

VSS

E11

VDD

E12

VDD

E13

VDDQR

VDD

VSS F8

VSS

F10

VSS F12

VDD

F13

VDDQR

VSS G6

VSS G7

VSS

VSS G10

VSS G11

VSS

G12

VSS

G13

VDDQL

VSS H6

VSS

H10

VSS

H11

VSS

H12

VSS H13

VDDQL

VSS J6VSS

J7VSS

VSS

VSS J10

VSS

J11

VSS

J12

VSS

J13

VDDQR

VSS

VSS K7

VSS

VDD L6VSS

L7VSS L8

VSS

VDD

VSS

VDDQR N6

VDDQR N7

VDDQL

VSS

K10

VSS K11

VSS

K12

VSS

VSS L10

VSS

L11

VSS L12

VDD

VSS

M10

VSS

M11

VDD

M12

VDD

VDDQR N10

VDDQR N11

VDDQL

N12

VDDQL

K13

VDDQR

L13

VDDQL

M13

VDDQL

N13

VDD

VSS F11

VSS

5626 drw 02d

11/08/01

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration(1,2,3,4) (con't.)

NOTES:

1. All VDD pins must be connected to 3.3V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).

3. All VSS pins must be connected to ground supply.

4. Package body is approximately 28mm x 28mm x 3.5mm.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

100

101

102

103

104

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

70V7599DR

DR-208(5)

208-Pin PQFP

Top View(6)

I/O19L

I/O19R

I/O20L

I/O20R

VDDQL

VSS

I/O21L

I/O21R

I/O22L

I/O22R

VDDQR

VSS

I/O23L

I/O23R

I/O24L

I/O24R

VDDQL

VSS

I/O25L

I/O25R

I/O26L

I/O26R

VDDQR

VSS

VDD

VSS

VDDQL

VSS

I/O27R

I/O27L

I/O28R

I/O28L

VDDQR

VSS

I/O29R

I/O29L

I/O30R

I/O30L

VDDQL

VSS

I/O31R

I/O31L

I/O32R

I/O32L

VDDQR

VSS

I/O33R

I/O33L

I/O34R

I/O34L

DDQL

I/O

35R

I/O

35L

PL/FT

TMS

TCK

TRST

10R

CLK

R/W

ADS

CNTEN

REPEAT

OPT

I/O

DDQL

I/O16L

I/O16R

I/O15L

I/O15R

VSS

VDDQL

I/O14L

I/O14R

I/O13L

I/O13R

VSS

VDDQR

I/O12L

I/O12R

I/O11L

I/O11R

VSS

VDDQL

I/O10L

I/O10R

I/O9L

I/O9R

VSS

VDDQR

VDD

VSS

VDDQL

I/O8R

I/O8L

I/O7R

I/O7L

VSS

VDDQR

I/O6R

I/O6L

I/O5R

I/O5L

VSS

VDDQL

I/O4R

I/O4L

I/O3R

I/O3L

VSS

VDDQR

I/O2R

I/O2L

I/O1R

I/O1L

DDQR

I/O

18R

I/O

18L

PL/FT

TDI

TDO

10L

CLK

R/W

ADS

CNTEN

REPEAT

OPT

I/O

17L

I/O

17R

DDQR

5626 drw 02a

11/08/01

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port Right Port Names

CE0L, CE1L CE0R, CE1R Chip Enables

R/WLR/WRRead /Wri te Enab le

OELOEROutput Enable

BA0L - BA5L BA0R - BA5R Bank Address

(4)

A0L - A10L A0R - A10R Address

I/O0L - I/ O35L I/O0R - I/ O35R Data Inp ut/ Ou tp ut

CLKLCLKRClock

PL/FTLPL/FTRPipeline/Flow-Through

ADSLADSRAddress Strobe Enable

CNTENLCNTENRCo unte r E nabl e

REPEATLREPEATRCo unte r Re p e at

(3)

BE0L - BE3L BE0R - BE3R Byte Enables (9-bit b ytes )

VDDQL VDDQR Powe r (I/O Bus) (3.3V or 2.5V)

(1)

OPTLOPTROptio n for se lecting VDDQX

(1,2)

VDD Power (3.3V)

(1)

VSS Ground (0V)

TDI Te s t Da ta In p u t

TDO Te s t Data Ou tp ut

TCK Te s t Lo g ic Clo c k (10MHz )

TMS Test Mode Select

TRST Re se t (Initialize TA P Controller)

5 626 t bl 01

NOTES:

1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and VDDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

3. When REPEATX is asserted, the counter will reset to the last valid address loaded

via ADSX.

4. Accesses by the ports into specific banks are controlled by the bank address

pins under the user's direct control: each port can access any bank of memory

with the shared array that is not currently being accessed by the opposite port

(i.e., BA0L - BA 5L ≠ BA0R - BA 5R). In the event that both ports try to access the

same bank at the same time, neither access will be valid, and data at the two

specific addresses targeted by the ports within that bank may be corrupted (in

the case that either or both ports are writing) or may result in invalid output (in

the case that both ports are trying to read).

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1 . "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, REPEAT are set as appropriate for address access. Refers to Truth Table II for details.

3. OE is an asynchronous input signal.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table IRead/Write and Enable Control(1,2,3,4)

OE3CLK CE0CE1BE3BE2BE1BE0R/WBy te 3

I/O27-35 By te 2

I/O18-26 By te 1

I/O9-17 By te 0

I/O0-8 MODE

X↑HXXXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down

X↑XL XXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down

X↑L HHHHHXHigh-ZHigh-ZHigh-ZHigh-ZAll Bytes Deselected

X↑L H H H H L L High-Z High-Z High-Z DIN Write to Byte 0 Only

X↑LHHHLHLHigh-ZHigh-Z D

IN Hig h-Z Write to By te 1 Only

X↑LHHLHHLHigh-Z D

IN Hi g h-Z Hi g h-Z Wr ite to B y te 2 On l y

X↑LHLHHHL D

IN Hi g h-Z Hi gh-Z Hi g h-Z Wr ite to B yte 3 O nl y

X↑L H H H L L L High-Z High-Z DIN DIN Write to Lower 2 Bytes Only

X↑LHLLHHL D

IN DIN High- Z High - Z Wr ite to Upper 2 bytes On ly

X↑LHLLLLL D

IN DIN DIN DIN Write to All Bytes

L↑L H H H H L H High-Z High-Z High-Z DOUT Re a d B y te 0 Only

L↑L H H H L H H High-Z High-Z DOUT Hig h-Z Rea d By te 1 Only

L↑LHHLHHHHigh-Z D

OUT High-Z Hi g h-Z Re ad B y te 2 Onl y

L↑LHLHHHHD

OUT High-Z High-Z Hi g h-Z Re ad B y te 3 Onl y

L↑L H H H L L H High-Z High-Z DOUT DOUT Read Lower 2 Bytes O nl y

L↑LHLLHHHD

OUT DOUT Hi gh-Z High- Z Rea d Upper 2 Bytes On ly

L↑LHLLLLHD

OUT DOUT DOUT DOUT Re ad All Bytes

HXXXXXXXXHigh-ZHigh-ZHigh-ZHigh-ZOutputs Disabled

5626 t bl 02

Truth Table IIAddress and Address Counter Control(1,2,7)

NOTES:

1 . "H" = VIH, "L" = VIL, "X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.

3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.

4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.

6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded

via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address

FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer

to Timing Waveform of Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA0L

- BA5L ≠ BA0R - BA5R), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details.

Address

Addr

Used

CLK

ADS CNTEN REPEAT

(6)

I/O

(3)

MODE

An X An ↑ L(4) XHD

I/O (n) External Address Used

XAnAn + 1

↑H L

(5) HD

I/O(n+1) Counter Enabled—Internal Address generation

X An + 1 An + 1 ↑HH HD

I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)

XXAn

↑XX L

(4) DI/O(0) Counter Set to last valid ADS load

5626 tbl 03

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage(1) Recommended DC Operating

Conditions with VDDQ at 2.5V

Absolute Maximum Ratings(1)

NOTES:

1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.

2. VTERM must not exceed VDDQ + 100mV.

3 . To select operation at 2.5V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied

as indicated above.

NOTES:

1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or

4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.

NOTE:

1. This is the parameter TA. This is the "instant on" case temperature.

Grade

Ambient

Temperature

GND

Commercial 0OC to + 70OC0V3.3V

+ 150m V

Industrial -40OC to +85OC0V3.3V

+ 150m V

5626 tbl 04

Symbol

Parameter

Min.

Typ.

Max.

Unit

VDD Co re Supply Voltage 3.15 3.3 3.45 V

VDDQ I/ O S up ply Vo l tag e (3) 2.4 2.5 2.6 V

VSS Ground 0 0 0 V

VIH Inp u t Hi g h Vo l tag e

(Ad d re ss & Co ntro l Inp uts ) 1.7 ____ VDDQ + 100mV (2) V

VIH Input High Voltage - I/O(3) 1.7 ____ VDDQ + 100mV(2) V

VIL Inp u t Lo w Vo lta g e -0. 3(1) ____ 0.7 V

5626 tb l 05a

Symbol

Rating

Commercial

& Industrial

Unit

VTERM(2) Terminal Vol tag e

with Res p e c t to

GND

-0. 5 t o + 4. 6 V

TBIAS Temperature

Under Bias -55 to +125 oC

TSTG Storage

Temperature -65 to +150 oC

IOUT DC O utp ut Curre nt 5 0 mA

5626 tbl 06

Recommended DC Operating

Conditions with VDDQ at 3.3V

NOTES:

1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.

2. VTERM must not exceed VDDQ + 150mV.

3 . To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be

supplied as indicated above.

Symbol Parameter Min. Typ. Max. Unit

VDD Co re Su pp ly Vo ltag e 3. 15 3. 3 3. 45 V

VDDQ I/O Sup p ly Vo l tag e

(3)

3.15 3.3 3.45 V

VSS Ground 0 0 0 V

VIH Inp u t High Vo l tag e

(Add re ss & Co ntro l Inp uts )

(3)

2.0 ____ VDDQ + 150mV

(2)

VIH Input High Voltage - I/O

(3)

2.0 ____ VDDQ + 150mV

(2)

VIL Inp u t Lo w Vo l tag e -0. 3

(1)

____ 0.8 V

5626 tbl 05b

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)

NOTES:

1. At VDD < 2.0V leakages are undefined.

2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.

Symbol

Parameter

Test Conditions

70V7599S

Unit

Min.

Max.

|ILI| Input Leakage Curre nt(1) VDDQ = Max., VIN = 0V to VDDQ ___ 10 µA

|ILO| Outp ut Le ak ag e Curre nt(1) CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ ___ 10 µA

VOL (3.3V) Output Low Voltag e(2) IOL = +4mA, VDDQ = Min. ___ 0.4 V

VOH (3.3V) Output High Voltage(2) IOH = -4mA, VDDQ = M in. 2.4 ___ V

VOL (2.5V) Output Low Voltag e(2) IOL = +2mA, VDDQ = Min. ___ 0.4 V

VOH (2.5V) Output High Voltage(2) IOH = -2mA, VDDQ = M in. 2.0 ___ V

5626 t bl 08

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. COUT also references CI/O.

Capacitance(1)

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance V

= 3dV 8 pF

OUT

(3) Output Capacitance V

OUT

= 3dV 10.5 pF

5626 tbl 07

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(5) (VDD = 3.3V ± 150mV)

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V

CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V

"X" represents "L" for left port or "R" for right port.

70V7599S200

(7)

Com'l Only

70V7599S166

(6)

Com'l

& Ind

70V7599S133

Com'l

& Ind

Symbol

Parameter

Test Condition

Version

Typ.

(4)

Max.

Typ.

(4)

Max.

Typ.

(4)

Max.

Unit

Dynamic Operating

Curre nt (Bo th

Ports Active)

and

= V

Outputs Disabled,

f = f

MAX

(1)

COM'L

815

950

675

790

550

645

IND

____

675

830

550

675

SB1

Standby Current

(Bo th P o rts - TTL

Lev e l Inp uts )

= V

f = f

MAX

(1)

COM'L

340

410

275

340

250

295

IND

____

275

355

250

310

SB2

Standby Current

(One Po rt - TTL

Lev e l Inp uts )

"A"

= V

and

"B"

= V

(3)

Ac tiv e P o rt Outp uts D isab le d ,

f=f

MAX

(1)

COM'L

690

770

515

640

460

520

IND

____

515

660

460

545

SB3

Full Standby Current

(Bo th P o rts - CM OS

Lev e l Inp uts )

Both Ports

and

- 0.2V, V

- 0.2V

or V

0.2 V, f = 0

(2)

COM'L

IND

____

SB4

Full Standby Current

(One Po rt - CM OS

Lev e l Inp uts )

"A"

0.2V and

"B"

- 0.2V

(3)

- 0.2V or V

0.2V

A ctive Port, Ou tpu ts Dis a ble d, f = f

MAX

(1)

COM'L

690

770

515

640

460

520

IND

____

515

660

460

545

5626 tb l 0 9

6. 166MHz Industrial Temperature not available in BF-208 package.

7. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC-256 package only.

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions (VDDQ - 3.3V/2.5V)

Figure 1. AC Output Test load.

Figure 2. Output Test Load

(For tCKLZ, tCKHZ, tOLZ, and tOHZ).

*Including scope and jig.

Figure 3. Typical Output Derating (Lumped Capacitive Load).

In p ut P ul s e Lev e l s (A d dre s s & Control s )

Input Pulse Levels (I/Os)

Inp ut Ris e/ Fal l Ti me s

In p ut Ti mi ng Re fere n ce Le ve l s

Outp ut Re fe re nc e Le ve ls

Output Load

GND to 3

0V/ GND to 2. 4V

GND to 3.0V/GND to 2.4V

2ns

1.5V/1.25V

Fi gure s 1 and 2

5626 tbl 10

1.5V/1.25

50Ω

5626 drw 03

10pF

(Tester)

DATAOUT

5626 drw 04

590Ω

5pF*

435Ω

3.3V

DATAOUT

833Ω

5pF*

770Ω

2.5V

DATAOUT

-1

20.5 30 50 80 100 200

10.5pF is the I/O capacitance of this

device, and 10pF is the AC Test Load

Capacitance.

Capacitance (pF)

∆tCD

(Typical, ns)

5626 drw 05

•

••

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing)(2) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)

NOTES:

1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when

FT/PIPEX = VIL for that port.

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a

DC signal, i.e. steady state during operation.

3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.

70V7599S200

(5)

Com'l Only

70V7599S166

(3,4)

Com'l

& Ind

70V7599S133

(3)

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CYC1

Clock Cycle Time (Flow-Through)

(1)

____

CYC2

Clock Cycle Time (Pipelined)

(1)

____

7.5

____

CH1

Clock High Time (Flow-Through)

(1)

____

CL1

Clock Low Tim e (Flow-Through)

(1)

____

CH2

Clock High Time (Pipelined)

(2)

2.0

____

2.1

____

2.6

____

CL2

Clock Low Time (Pipelined)

(1)

2.0

____

2.1

____

2.6

____

Clock Rise Time

____

1.5

____

1.5

____

1.5 ns

Clock Fall Time

____

1.5

____

1.5

____

1.5 ns

Address Setup Time 1.5

____

1.7

____

1.8

____

Address Hold Time 0.5

____

0.5

____

0.5

____

Chip E nab le S e tup Tim e 1.5

____

1.7

____

1.8

____

Chip E nab le Ho ld Tim e 0.5

____

0.5

____

0.5

____

R/W Setup Time 1.5

____

1.7

____

1.8

____

R/W Hold Time 0.5

____

0.5

____

0.5

____

Inp ut D ata S e tup Tim e 1.5

____

1.7

____

1.8

____

Input Data Ho ld Tim e 0.5

____

0.5

____

0.5

____

SAD

ADS

Setup Time 1.5

____

1.7

____

1.8

____

HAD

ADS

Hold Time 0.5

____

0.5

____

0.5

____

SCN

CNTEN

Setup Time 1.5

____

1.7

____

1.8

____

HCN

CNTEN

Hold Time 0.5

____

0.5

____

0.5

____

SRPT

REPEAT

Setup Time 1.5

____

1.7

____

1.8

____

HRPT

REPEAT

Hold Time 0.5

____

0.5

____

0.5

____

Output Enable to Data Valid

____

4.0

____

4.0

____

4.2 ns

OLZ

Output Enable to Output Low-Z 0.5

____

0.5

____

0.5

____

OHZ

Output Enable to Output High-Z 1 3.4 1 3.6 1 4.2 ns

CD1

Clock to Data Valid (Flow-Through)

(1)

____

15 ns

CD2

Clock to Data Valid (Pipelined)

(1)

____

3.4

____

3.6

____

4.2 ns

Data Output Hold After Clock High 1

____

CKHZ

Clock High to Output High-Z 13.4 13.6 14.2ns

CKLZ

Clock High to Output Low-Z 0.5

____

0.5

____

0.5

____

Port-to-Port Delay

Clock-to-Clock Offset 5.0

____

6.0

____

7.5

____

5626 tbl 11

4. 166MHz Industrial Temperature not available in BF-208 package.

5. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC-256 package only.

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

An An + 1 An + 2 An + 3

tCYC2

tCH2 tCL2

R/W

ADDRESS

CE0

CLK

CE1

BEn

(3)

DATAOUT

tCD2

tCKLZ

Qn Qn + 1 Qn + 2

tOHZ tOLZ

tOE

5626 drw 06

(1)

tSC tHC

tSB tHB

tSW tHW

tSA tHA

tDC

tSC tHC

tSB tHB

(4)

(1 Latency)

(5)

Timing Waveform of Read Cycle for Pipelined Operation

(ADS Operation) (FT/PIPE'X' = VIH)(2)

NOTES:

1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

2. ADS = VIL, CNTEN and REPEAT = VIH.

3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).

6. "x" denotes Left or Right port. The diagram is with respect to that port.

Timing Waveform of Read Cycle for Flow-through Output

(FT/PIPE"X" = VIL)(2,6)

An An + 1 An + 2 An + 3

tCYC1

tCH1 tCL1

R/W

ADDRESS

DATAOUT

CE0

CLK

tSC tHC

tCD1

tCKLZ

Qn Qn + 1 Qn + 2

tOHZ tOLZ

tOE

tCKHZ

5626 drw 07

(5)

(1)

CE1

BEn

(3)

tSB tHB

tSW tHW

tSA tHA

tDC

(4)

tSC tHC

tSB tHB

(5)

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

tSC tHC

CE0(B1)

ADDRESS(B1) A0A1A2A3A4A5

tSA tHA

CLK

Q0Q1Q3

DATAOUT(B1)

tCH2 tCL2

tCYC2

ADDRESS(B2) A0A1A2A3A4A5

tSA tHA

CE0(B2)

DATAOUT(B2) Q2Q4

tCD2 tCD2 tCKHZ tCD2

tCKLZ

tDC tCKHZ

tCD2

tCKLZ

tSC tHC

tCKHZ

tCKLZ

tCD2

tDC

tSC tHC

5626 drw 08

Timing Waveform of a Multi-Device Pipelined Read(1,2)

NOTES:

1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V7599 for this waveform,

and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.

2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.

Timing Waveform of a Multi-Device Flow-Through Read(1,2)

tSC tHC

CE0(B1)

ADDRESS(B1) A0A1A2A3A4A5

tSA tHA

CLK

5626 drw 09

D0D3

tCD1

tCKLZ tCKHZ

(1) (1)

DATAOUT(B1)

tCH1 tCL1

tCYC1

(1)

ADDRESS(B2) A0A1A2A3A4A5

tSA tHA

CE0(B2)

DATAOUT(B2) D2D4

tCD1 tCD1 tCKHZ

tDC

tCD1

tCKLZ

tSC tHC

(1)

tCKHZ(1)

tCKLZ(1)

tCD1

tDC

tSC tHC

tCD1

tCKLZ(1)

tCKHZ (1)

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

CLK

"A"

R/W

"A"

BANK ADDRESS

AND ADDRESS

"A"

DATA

IN"A"

CLK

"B"

R/W

"B"

BANK ADDRESS

AND ADDRESS

"B"

DATA

OUT"B"

CD2

5626 drw 10

(3)

Timing Waveform of Port A Write to Pipelined Port B Read(1,2,4)

Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)

DATA

IN "A"

CLK

"B"

R/W

"B"

BANK ADDRESS

AND ADDRESS

"A"

R/W

"A"

CLK

"A"

BANK ADDRESS

AND ADDRESS

"B"

DATA

OUT "B"

5626 drw 11

CD1

(3)

NOTES:

1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.

3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle

(ie, time from write to valid read on opposite port will be tCO + tCYC2 + tCD2).

4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"

NOTES:

1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle

(i.e., time from write to valid read on opposite port will be tCO + tCD1).

4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

R/W

ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4

DATAIN Dn + 2

CE0

CLK

5626 drw 12

Qn Qn + 3

DATAOUT

CE1

BEn

tCD2 tCKHZ tCKLZ tCD2

tSC tHC

tSB tHB

tSW tHW

tSA tHA

tCH2 tCL2

tCYC2

READ NOP READ

tSD tHD

(3)

(1)

tSW tHW

WRITE

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = VIL)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

R/W

ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5

DATAIN Dn + 3Dn + 2

CE0

CLK

5626 drw 13

DATAOUT Qn Qn + 4

CE1

BEn

tCH2 tCL2

tCYC2

tCKLZ tCD2

tOHZ

tCD2

tSD tHD

READ WRITE READ

tSC tHC

tSB tHB

tSW tHW

tSA tHA

(3)

(1)

tSW tHW

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

R/W

ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4

DATAIN Dn + 2

CE0

CLK

5626 drw 14

DATAOUT

CE1

BEn

tCD1

Qn + 1

tCH1 tCL1

tCYC1

tSD tHD

tCD1 tCD1

tDC tCKHZ

Qn + 3

tCD1

tDC

tSC tHC

tSB tHB

tSW tHW

tSA tHA

READ NOP READ

tCKLZ

(3)

(1)

tSW tHW

WRITE

(4)

R/W

ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5

(3)

DATAIN Dn + 2

CE0

CLK

5626 drw 15

DATAOUT

CE1

BEn

tCD1

tCH1 tCL1

tCYC1

tSD tHD

tCD1 tDC

Qn + 4

tCD1

tDC

tSC tHC

tSB tHB

tSW tHW

tSA tHA

READ WRITE READ

tCKLZ

(1)

Dn + 3

tOHZ

tSW tHW

tOE

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

ADDRESS An

CLK

DATAOUT Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3

ADS

CNTEN

tCYC2

tCH2 tCL2

5626 drw 16

tSA tHA

tSAD tHAD

tCD2

tDC

READ

EXTERNAL

ADDRESS READ WITH COUNTER COUNTER

HOLD

tSAD tHAD

tSCN tHCN

READ

WITH

COUNTER

Qn + 1

Timing Waveform of Pipelined Read with Address Counter Advance(1)

NOTES:

1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH.

2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then

the data output remains constant for subsequent clocks.

Timing Waveform of Flow-Through Read with Address Counter Advance(1)

ADDRESS An

CLK

DATAOUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4

ADS

CNTEN

tCYC1

tCH1 tCL1

5626 drw 17

tSA tHA

tSAD tHAD

READ

EXTERNAL

ADDRESS

READ WITH COUNTER COUNTER

HOLD

tCD1

tDC

tSAD tHAD

tSCN tHCN

READ

WITH

COUNTER

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

(Flow-through or Pipelined Inputs)(1,6)

NOTES:

1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.

2. CE0, BEn = VIL; CE1 = VIH.

3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid

ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.

5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address

FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0.

7. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.

ADDRESS An

CLK

DATAIN Dn Dn + 1 Dn + 1 Dn + 2

ADS

CNTEN

tCH2 tCL2

tCYC2

5626 drw 18

INTERNAL(3)

ADDRESS An(5) An + 1 An + 2 An + 3 An + 4

Dn + 3 Dn + 4

tSA tHA

tSAD tHAD

WRITE

COUNTER HOLD WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS WRITE

WITH COUNTER

tSD tHD

tSCN tHCN

Timing Waveform of Counter Repeat for Flow Through Mode(2,6,7)

ADDRESS An

tCYC2

CLK

DATAIN

R/W

REPEAT

5626 drw 19

INTERNAL(3)

ADDRESS

ADS

CNTEN

WRITE TO

ADS

ADDRESS

ADVANCE

COUNTER

WRITE TO

An+1

ADVANCE

COUNTER

WRITE TO

An+2

HOLD

COUNTER

WRITE TO

An+2

REPEAT

READ LAST

ADS

ADDRESS

DATAOUT

tSA tHA

tSAD tHAD

tSW tHW

tSCN tHCN

tSRPT tHRPT

tSD tHD

tCD1

An+1 An+2 An+2 An An+1 An+2 An+2

D0D1D2D3

An An+1 An+2 An+2

ADVANCE

COUNTER

READ

An+1

ADVANCE

COUNTER

READ

An+2

HOLD

COUNTER

READ

An+2

(4)

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70V7599 is a high-speed 128Kx36 (4 Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent

2Kx36 banks. Based on a standard SRAM core instead of a traditional true

dual-port memory core, this bank-switchable device offers the benefits of

increased density and lower cost-per-bit while retaining many of the

features of true dual-ports. These features include simultaneous, random

access to the shared array, separate clocks per port, 166 MHz operating

speed, full-boundary counters, and pinouts compatible with the IDT70V3599

(128Kx36) dual-port family.

The two ports are permitted independent, simultaneous access into

separate banks within the shared array. Access by the ports into specific

banks are controlled by the bank address pins under the user's direct

control: each port can access any bank of memory with the shared array

that is not currently being accessed by the opposite port (i.e., BA0L - BA5L

≠ BA0R - BA5R). In the event that both ports try to access the same bank

at the same time, neither access will be valid, and data at the two specific

addresses targeted by the ports within that bank may be corrupted (in the

case that either or both ports are writing) or may result in invalid output (in

the case that both ports are trying to read).

The IDT70V7599 provides a true synchronous Dual-Port Static RAM

5626 drw 20

IDT70V7599 CE0

CE1

CE0

CE1

BA6(1)

CE1

CE0

VDD VDD

IDT70V7599

Control Inputs

Control Inputs BE,

R/W,

OE,

CLK,

ADS,

REPEAT,

CNTEN

Figure 4. Depth and Width Expansion with IDT70V7599

interface. Registered inputs provide minimal setup and hold times on

address, data and all critical control inputs.

An asynchronous output enable is provided to ease asynchronous

bus interfacing. Counter enable inputs are also provided to stall the

operation of the address counters for fast interleaved memory applications.

A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down

the internal circuitry on each port (individually controlled) to reduce static

power consumption. Dual chip enables allow easier banking of multiple

IDT70V7599S for depth expansion configurations. Two cycles are

required with CE0 LOW and CE1 HIGH to read valid data on the outputs.

Depth and Width Expansion

The IDT70V7599 features dual chip enables (refer to Truth

Table I) in order to facilitate rapid and simple depth expansion with no

requirements for external logic. Figure 4 illustrates how to control the

various chip enables in order to expand two devices in depth.

The IDT70V7599 can also be used in applications requiring expanded

width, as indicated in Figure 4. Through combining the control signals, the

devices can be grouped as necessary to accommodate applications

needing 72-bits or wider.

NOTE:

1. In the case of depth expansion, the additional address pin logically serves as an extension of the bank address. Accesses by the ports into specific banks are

controlled by the bank address pins under the user's direct control: each port can access any bank of memory within the shared array that is not currently

being accessed by the opposite port (i.e., BA0L - BA6L ≠ BA0R - BA6R). In the event that both ports try to access the same bank at the same time, neither

access will be valid, and data at the two specific addresses targeted by the parts within that bank may be corrupted (in the case that either or both parts are

writing) or may result in invalid output (in the case that both ports are trying to read).

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

JTAG AC Electrical

Characteristics(1,2,3,4)

70V7599

Symbol

Parameter

Min.

Max.

Units

tJCYC JTAG Clock Input Period 100 ____ ns

tJCH JTAG Clock HIGH 40 ____ ns

tJCL JTAG Clock Low 40 ____ ns

tJR JTAG Clock Rise Time ____ 3(1) ns

tJF JTAG Clo ck Fall Time ____ 3(1) ns

tJRST JTAG Reset 50 ____ ns

tJRSR JTAG Reset Reco very 50 ____ ns

tJCD JTA G Data Outp ut ____ 25 ns

tJDC JTA G Data Outp ut Ho ld 0 ____ ns

tJS JTAG Setup 15 ____ ns

tJH JTAG Hold 15 ____ ns

5626 tbl 12

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

JTAG Timing Specifications

TCK

Device Inputs(1)/

TDI/TMS

Device Outputs(2)/

TDO

TRST

tJCD

tJDC

tJRST

tJS tJH

tJCYC

tJRSR

tJF tJCLtJR tJCH

5626 drw 21

Figure 5. Standard JTAG Timing

NOTES:

1. Device inputs = All device inputs except TDI, TMS, TRST, and TCK.

2. Device outputs = All device outputs except TDO.

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Field

Value

Description

Revisio n Numb er (31:28) 0x0 Reserve d for v ersion numb er

IDT Device ID (27:12) 0x308 Defines IDT p art numb er

IDT JEDEC ID (11:1) 0x33 Allo ws unique ide ntification o f d ev ice v endo r as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

5626 tbl 13

Scan Register Sizes

Bit S ize

Instruction (IR) 4

Bypass (BYR) 1

Id e ntific atio n (IDR) 32

Boundary Scan (BSR) Note (3)

5626 tbl 14

System Interface Parameters

Instruction

Code

Description

EXTES T 0000 Fo rce s co nte nts of the b o undary sc an c ells onto the d ev ic e outp uts (1).

Places the boundary scan register (BSR) between TDI and TDO.

B Y P A S S 1111 Pl a c es th e bypa s s regis t er ( B YR) be t ween TD I a nd TD O .

IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the

HIGHZ 0100 Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

CLAMP 0011 Uses BYR. Forces contents of the bound ary scan cells onto the device

outputs. Places the bypass registe r (BYR) between TDI and TDO.

SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs(2) and o utputs (1) to be captured

in the b ound ary sc an c e lls and shifte d se rially thro ug h TDO. P RE LOAD

allows data to be input serially into the b oundary scan cells via the TDI.

RESERVED All other codes Several combinations are reserved. Do not use codes other than those

identified above.

5626 tbl 15

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, TRST, and TCK.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

Power 999

Speed A

Package A

Process/

Temperature

Range

Blank

ICommercial (0°C to +70°C)

Industrial (-40°C to +85°C)

208-pin fpBGA (BF-208)

208-pin PQFP (DR-208)

256-pin BGA (BC-256)

200

166

133

XXXXX

Device

Type

IDT

Speed in Megahertz

5626 drw 22

S Standard Power

70V7599 4Mbit (128K x 36-Bit) Synchronous Bank-Switchable Dual-Port RAM

Commercial Only(1)

Commercial & Industrial(2)

Commercial & Industrial

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-5166 831-754-4613

Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com

www.idt.com

Datasheet Document History:

1/5/00: Initial Public Offering

10/19/01: Page 2, 3 & 4 Added date revision for pin configurations

Page 9 Changed ISB3 values for commercial and industrial DC Electrical Characteristics

Page 11 Changed tOE value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05

Page 20 Increased tJCD from 20ns to 25ns, please refer to Errata #SMEN-01-04

Page 1 & 22 Replaced TM logo with ® logo

03/18/02: Page 1, 9, 11 & 22 Added 200MHz specification

Page 9 Tightened power numbers in DC Electrical Characteristics

Page 14 Changed waveforms to show INVALID operation if tCO < minimum specified

Page 1 - 22 Removed "Preliminary" status

12/4/02: Page 9, 11 & 22 Designated 200 Mhz speed grade available in BC-256 package only.

NOTES:

1. Available in BC-256 package only.

2. Industrial Temperature at 166Mhz not available in BF-208 package.