FEATURES
DEIGHT ADDRESSES
DDIGITAL OUTPUT: Two-Wire Serial Interface
DRESOLUTION: 9- to 12-Bits, User-Selectable
DACCURACY:
±0.5°C (max) from −20°C to +100°C
DLOW QUIESCENT CURRENT:
50µA, 0.1µA Standby
DWIDE SUPPLY RANGE: 2.7V to 5.5V
DSMALL MSOP-8 AND SO-8 PACKAGES
DNO POWER-UP SEQUENCE REQUIRED;
TWO-WIRE BUS PULL-UPS CAN BE
ENABLED BEFORE V+
APPLICATIONS
DPOWER-SUPPLY TEMPERATURE
MONITORING
DCOMPUTER PERIPHERAL THERMAL
PROTECTION
DNOTEBOOK COMPUTERS
DCELL PHONES
DBATTERY MANAGEMENT
DOFFICE MACHINES
DTHERMOSTAT CONTROLS
DENVIRONMENTAL MONITORING AND HVAC
DELECTROMECHANICAL DEVICE
TEMPERATURE
−0.50
−0.40
−0.30
−0.20
−0.10
0.00
0.10
0.20
0.30
0.40
0.50
Temperature Error (_C)
Population
TEMPERATURE ERROR AT 25_C
DESCRIPTION
The TMP275 is a 0.5°C accurate, Two-Wire, serial output
temperature sensor available in an MSOP-8 or an SO-8
package. The TMP 275 is capable of reading temperatures
with a resolution of 0.0625°C.
The TMP275 is SMBus-compatible and allows up to eight
devices on one bus. It is ideal for extended temperature
measurement in a variety of communication, computer,
consumer, environmental, industrial, and instrumentation
applications.
The TMP275 is specified for operation over a temperature
range of −40°C to +125°C.
Diode
Temp.
Sensor
∆Σ
A/D
Converter
OSC
Control
Logic
Serial
Interface
Config.
andTemp.
Register
TMP275
Temperature
ALERT
SDA 1
3
4
8
6
5
GND
V+
A1
SCL 27
A0
A2
TEMPERATURE ERROR vs TEMPERATURE
Temperature (_C)
Temperature Error (_C)
−55 −35 −15 5 25 45 65 85 105 125 130
0.500
0.375
0.250
0.125
0
−0.125
−0.250
−0.375
−0.500
TMP275
SBOS363D − JUNE 2006 − REVISED AUGUST 2007
0.5°C Digital Out Temperature Sensor
! !
www.ti.com
Copyright 2006−2007, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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2
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply, V+ 7.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage(2) −0.5V to 7.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Current 10mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range −55 °C to +127°C. . . . . . . . . . . . . . .
Storage Temperature Range −60 °C to +130°C. . . . . . . . . . . . . . . . .
Junction Temperature (TJ max) +150°C. . . . . . . . . . . . . . . . . . . . . .
ESD Rating:
Human Body Model (HBM) 4000V. . . . . . . . . . . . . . . . . . . . . . .
Charged Device Model (CDM) 1000V. . . . . . . . . . . . . . . . . . . .
Machine Model (MM) 300V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(1) Stresses above these ratings may cause permanent damage.
Exposure t o absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, an d
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Input voltage rating applies to all TMP275 input voltages.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
TMP275 MSOP-8 DGK T275
TMP275 SO-8 D TMP275
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
PIN ASSIGNMENTS
Top View
NOTE: Pin 1 is determined by orienting the package as indicated in the diagram.
SDA
SCL
ALERT
GND
V+
A0
A1
A2
1
2
3
4
8
7
6
5
MSOP−8, SO−8
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ELECTRICAL CHARACTERISTICS
At TA = −40°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted.
PARAMETER
CONDITION
TMP275
UNITS
PARAMETER
CONDITION
MIN TYP MAX
UNITS
TEMPERATURE INPUT
Range −40 +125 °C
Accuracy (Temperature Error) −20°C to +100°C, V+ = 3.3V ±0.0625 ±0.5 °C
0°C to +100°C, V+ = 3.0V to 3.6V ±0.0625 ±0.75 °C
−40°C to +125°C, V+ = 3.0V to 3.6V ±0.0625 ±1°C
+25°C to +100°C, V+ = 3.3V to 5.5V 0.2 ±1.5 °C
Resolution(1) Selectable +0.0625 °C
DIGITAL INPUT/OUTPUT
Input Capacitance 3 pF
Input Logic Levels:
VIH 0.7(V+) 6.0 V
VIL −0.5 0.3(V+) V
Leakage Input Current, IIN 0V ≤ VIN ≤ 6V 1µA
Input Voltage Hysteresis SCL and SDA Pins 500 mV
Output Logic Levels:
VOL SDA IOL = 3mA 0 0.15 0.4 V
VOL ALERT IOL = 4mA 0 0.15 0.4 V
Resolution Selectable 9 to 12 Bits
Conversion Time 9-Bit 27.5 37.5 ms
10-Bit 55 75 ms
11-Bit 110 150 ms
12-Bit 220 300 ms
Timeout Time 25 54 74 ms
POWER SUPPLY
Operating Range 2.7 5.5 V
Quiescent Current IQSerial Bus Inactive 50 85 µA
Serial Bus Active, SCL Freq = 400kHz 100 µA
Serial Bus Active, SCL Freq = 3.4MHz 410 µA
Shutdown Current ISD Serial Bus Inactive 0.1 3 µA
Serial Bus Active, SCL Freq = 400kHz 60 µA
Serial Bus Active, SCL Freq = 3.4MHz 380 µA
TEMPERATURE RANGE
Specified Range −40 +125 °C
Operating Range −55 +127 °C
Thermal Resistance qJA
MSOP-8 250 °C/W
SO-8 150 °C/W
(1) Specified for 12-bit resolution.
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TYPICAL CHARACTERISTICS
At TA = +25°C and V+ = 5.0V, unless otherwise noted.
85
75
65
55
45
35
25
QUIESCENT CURRENT vs TEMPERATURE
Temperature (_C)
−55 −35 −15 5 25 45 65 85 105 125 130
IQ(µA)
Serial Bus Inactive
V+=5V
V+ = 2.7V
300
250
200
150
100
CONVERSION TIME vs TEMPERATURE
Temperature (_C)
Conversion Time (ms)
12−bit resolution.
−55 −35 −15 5 25 45 65 85 105 125 130
V+=5V
V+ = 2.7V
500
450
400
350
300
250
200
150
100
50
0
QUIESCENT CURRENT WITH
BUS ACTIVITY vs TEMPERATURE
Frequency (Hz)
1k 10k 100k 1M 10M
IQ(µA)
125_C
25_C
−55_C
Hs MODE
FAST MODE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
SHUTDOWN CURRENT vs TEMPERATURE
Temperature (_C)
ISD (µA)
−55 −35 −15 5 25 45 65 85 105 125 130
TEMPERATURE ERROR vs TEMPERATURE
Temperature (_C)
Temperature Error (_C)
−55 −35 −155 25456585105125130
0.500
0.375
0.250
0.125
0
−0.125
−0.250
−0.375
−0.500
40
−0.50
−0.
−0.30
−0.20
−0.10
0.00
0.10
0.20
0.30
0.40
0.50
Temperature Error (_C)
Population
TEMPERATURE ERROR AT 25_C
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APPLICATIONS INFORMATION
The TMP275 is a digital temperature sensor that is optimal
for thermal management and thermal protection
applications. The TMP275 is Two-Wire and SMBus
interface-compatible, and is specified over a temperature
range of −40°C to +125°C.
The TMP275 requires no external components for
operation except for pull-up resistors on SCL, SDA, and
ALERT, although a 0.1µF bypass capacitor is
recommended, as shown in Figure 1.
TMP275
0.1µF
V+
GND
4
3
7
8
ALERT
(Output)
A0
6A1
5A2
2
1
SCL
SDA
To
Two−Wire
Controller
NOTE:SCL,SDA,andALERT
pins require pull−up resistors.
Figure 1. Typical Connections of the TMP275
The sensing device of the TMP275 is the chip itself.
Thermal paths run through the package leads as well as
the plastic package. The lower thermal resistance of metal
causes the leads to provide the primary thermal path.
To maintain accuracy in applications requiring air or
surface temperature measurement, care should be taken
to isolate the package and leads from ambient air
temperature. A thermally-conductive adhesive will assist
in achieving accurate surface temperature measurement.
POINTER REGISTER
Figure 2 shows the internal register structure of the
TMP275. The 8-bit Pointer Register of the devices is used
to address a given data register. The Pointer Register uses
the two LSBs to identify which of the data registers should
respond to a read or write command. Table 1 identifies the
bits of the Pointer Register byte. Table 2 describes the
pointer address of the registers available in the TMP275.
Power-up reset value of P1/P0 is 00.
P7 P6 P5 P4 P3 P2 P1 P0
000000Register Bits
Table 1. Pointer Register Byte
I/O
Control
Interface
SCL
SDA
Temperature
Register
Configuration
Register
TLOW
Register
THIGH
Register
Pointer
Register
Figure 2. Internal Register Structure of the
TMP275
P1 P0 REGISTER
0 0 Temperature Register (READ Only)
0 1 Configuration Register (READ/WRITE)
1 0 TLOW Register (READ/WRITE)
1 1 THIGH Register (READ/WRITE)
Table 2. Pointer Addresses of the TMP275
TEMPERATURE REGISTER
The Temperature Register of the TMP275 is a 12-bit,
read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data, and are
described in Table 3 and Table 4. Note that byte 1 is the
most significant byte, followed by byte 2, the least
significant byte. The first 12 bits are used to indicate
temperature, with all remaining bits equal to zero. The
least significant byte does not have to be read if that
information is not needed. Data format for temperature is
summarized in Table 5. Following power-up or reset, the
Temperature Register will read 0°C until the first
conversion is complete.
D7 D6 D5 D4 D3 D2 D1 D0
T11 T10 T9 T8 T7 T6 T5 T4
Table 3. Byte 1 of Temperature Register
D7 D6 D5 D4 D3 D2 D1 D0
T3 T2 T1 T0 0 0 0 0
Table 4. Byte 2 of Temperature Register
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TEMPERATURE
(°C) DIGITAL OUTPUT
(BINARY) HEX
128 0111 1111 1111 7FF
127.9375 0111 1111 1111 7FF
100 0110 0100 0000 640
80 0101 0000 0000 500
75 0100 1011 0000 4B0
50 0011 0010 0000 320
25 0001 1001 0000 190
0.25 0000 0000 0100 004
00000 0000 0000 000
−0.25 1111 1111 1100 FFC
−25 1110 0111 0000 E70
−55 1100 1001 0000 C90
Table 5. Temperature Data Format
The user can obtain 9, 10, 11, or 12 bits of resolution by
addressing the Configuration Register and setting the
resolution bits accordingly. For 9-, 10-, or 11-bit resolution,
the most significant bits in the Temperature Register are
used with the unused LSBs set to zero.
CONFIGURATION REGISTER
The Configuration Register is an 8-bit read/write register
used to store bits that control the operational modes of the
temperature sensor. Read/write operations are performed
MSB first. The format of the Configuration Register for the
TMP275 is shown in Table 6, followed by a breakdown of
the register bits. The power-up/reset value of the
Configuration Register is all bits equal to 0.
BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 OS R1 R0 F1 F0 POL TM SD
Table 6. Configuration Register Format
SHUTDOWN MODE (SD)
The Shutdown Mode of the TMP275 allows the user to
save maximum power by shutting down all device circuitry
other than the serial interface, which reduces current
consumption to typically less than 0 .1µA. Shutdown Mode
is enabled when the SD bit is 1; the device will shut down
once the current conversion is completed. When SD is
equal to 0, the device will maintain a continuous
conversion state.
THERMOSTAT MODE (TM)
The Thermostat Mode bit of the TMP275 indicates to the
device whether to operate in Comparator Mode (TM = 0)
or Interrupt Mode (TM = 1). For more information on
comparator and interrupt modes, see the High and Low
Limit Registers section.
POLARITY (POL)
The Polarity Bit of the TMP275 allows the user to adjust the
polarity of the ALERT pin output. If POL = 0, the ALER T pin
will be active LOW, as shown in Figure 3. For POL = 1, the
ALERT pin will be active HIGH, and the state of the ALER T
pin is inverted.
Measured
Temperature
THIGH
TLOW
TMP275 ALERT PIN
(Comparator Mode)
POL = 0
TMP275 ALERT PIN
(Interrupt Mode)
POL = 0
TMP275 ALERT PIN
(Comparator Mode)
POL = 1
TMP275 ALERT PIN
(Interrupt Mode)
POL = 1
Read Read
Time
Read
Figure 3. Output Transfer Function Diagrams
FAULT QUEUE (F1/F0)
A fault condition is defined as when the measured
temperature exceeds the user-defined limits set in the
THIGH and TLOW Registers. Additionally, the number of
fault conditions required to generate an alert may be
programmed using the fault queue. The fault queue is
provided to prevent a false alert as a result of
environmental noise. The fault queue requires
consecutive fault measurements in order to trigger the
alert function. Table 7 defines the number of measured
faults that may be programmed to trigger an alert condition
in the device. For THIGH and TLOW register format and byte
order, see section High and Low Limit Registers.
F1 F0 CONSECUTIVE FAULTS
0 0 1
0 1 2
1 0 4
1 1 6
Table 7. Fault Settings of the TMP275
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CONVERTER RESOLUTION (R1/R0)
The Converter Resolution Bits control the resolution of th e
internal Analog-to-Digital (A/D) converter. This control
allows the user to maximize efficiency by programming for
higher resolution or faster conversion time. Table 8
identifies the Resolution Bits and the relationship between
resolution and conversion time.
R1 R0 RESOLUTION CONVERSION TIME
(typical)
0 0 9 Bits (0.5°C) 27.5ms
0 1 10 Bits (0.25°C) 55ms
1 0 11 Bits (0.125°C) 110ms
1 1 12 Bits (0.0625°C) 220ms
Table 8. Resolution of the TMP275
ONE-SHOT (OS)
The TMP275 features a One-Shot Temperature
Measurement Mode. When the device is in Shutdown
Mode, writing a ‘1’ to the OS bit starts a single temperature
conversion. The device returns to the shutdown state at
the completion of the single conversion. This mode is
useful for reducing power consumption in the TMP275
when continuous temperature monitoring is not required.
When the configuration register is read, the OS always
reads zero.
HIGH AND LOW LIMIT REGISTERS
In Comparator Mode (TM = 0), the ALERT pin of the
TMP275 becomes active when the temperature equals or
exceeds the value in THIGH and generates a consecutive
number of faults according to fault bits F1 and F0. The
ALERT pin remains active until the temperature falls below
the indicated TLOW value for the same number of faults.
In Interrupt Mode (TM = 1), the ALERT pin becomes active
when the temperature equals or exceeds THIGH for a
consecutive number of fault conditions. The ALERT pin
remains active until a read operation of any register
occurs, or the device successfully responds to the SMBus
Alert Response Address. The ALERT pin is also cleared
if the device is placed in Shutdown Mode. Once the ALERT
pin is cleared, it only becomes active again by the
temperature falling below TLOW. When the temperature
falls below TLOW, the ALERT pin becomes active and
remain active until cleared by a read operation of any
register or a successful response to the SMBus Alert
Response Address. Once the ALERT pin is cleared, the
above cycle repeats, with the ALERT pin becoming active
when the temperature equals or exceeds THIGH. The
ALERT pin can also be cleared by resetting the device with
the General Call Reset command. This command also
clears the state of the internal registers in the device,
returning the device to Comparator Mode (TM = 0).
Both operational modes are represented in Figure 3.
Table 9 and Table 10 describe the format for the THIGH and
TLOW registers. Note that the most significant byte is sent
first, followed by the least significant byte. Power-up reset
values for THIGH and TLOW are:
THIGH = 80°C and TLOW = 75°C
The format of the data for THIGH and TLOW is the same as
for the Temperature Register.
BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 H11 H10 H9 H8 H7 H6 H5 H4
BYTE D7 D6 D5 D4 D3 D2 D1 D0
2 H3 H2 H1 H0 0 0 0 0
Table 9. Bytes 1 and 2 of THIGH Register
BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 L11 L10 L9 L8 L7 L6 L5 L4
BYTE D7 D6 D5 D4 D3 D2 D1 D0
2 L3 L2 L1 L0 0 0 0 0
Table 10. Bytes 1 and 2 of TLOW Register
All 12 bits for the Temperature, THIGH, and TLOW registers
are used in the comparisons for the ALERT function for all
converter resolutions. The three LSBs in THIGH and TLOW
can affect the ALERT output even if the converter is
configured for 9-bit resolution.
SERIAL INTERFACE
The TMP275 operates only as a slave device on the
Two-Wire bus and SMBus. Connections to the bus are
made via the open-drain I/O lines SDA and SCL. The SDA
and SCL pins feature integrated spike suppression filters
and Schmitt triggers to minimize the effects o f input spikes
and bus noise. The TMP275 supports the transmission
protocol for fast (1kHz to 400kHz) and high-speed (1kHz
to 3.4MHz) modes. All data bytes are transmitted MSB
first.
SERIAL BUS ADDRESS
To communicate with the TMP275, the master must first
address slave devices via a slave address byte. The slave
address byte consists of seven address bits, and a
direction bit indicating the intent of executing a read or
write operation.
The TMP275 features three address pins allowing up to
eight devices to be connected per bus. Pin logic levels are
described i n Table 11. The address pins of the TMP275 are
read after reset, at start of communication, or in response
to a Two-Wire address acquire request. Following reading
the state of the pins the address is latched to minimize
power dissipation associated with detection.
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A2 A1 A0 SLAVE ADDRESS
0 0 0 1001000
0 0 1 1001001
0 1 0 1001010
0 1 1 1001011
1 0 0 1001100
1 0 1 1001101
1 1 0 1001110
1 1 1 1001111
Table 11. Address Pins and Slave Addresses for
the TMP275
BUS OVERVIEW
The device that initiates the transfer is called a master, and
the devices controlled by the master are slaves. The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions.
To address a specific device, a START condition is
initiated, indicated by pulling the data-line (SDA) from a
HIGH to LOW logic level while SCL is HIGH. All slaves on
the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended.
During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge
and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock
pulses followed by an Acknowledge Bit. During data
transfer SDA must remain stable while SCL is HIGH, as
any change in SDA while SCL is HIGH is interpreted as a
control signal.
Once all data has been transferred, the master generates
a STOP condition indicated by pulling SDA from LOW to
HIGH, while SCL is HIGH.
WRITING/READING TO THE TMP275
Accessing a particular register on the TMP275 is
accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is the
first byte transferred after the slave address byte with the
R/W bit LOW. Every write operation to the TMP275
requires a value for the Pointer Register. (Refer to
Figure 5.)
When reading from the TMP275, the last value stored in
the Pointer Register by a write operation is used to
determine which register is read by a read operation. To
change the register pointer for a read operation, a new
value must be written to the Pointer Register. This is
accomplished by issuing a slave address byte with the
R/W bit LOW, followed by the Pointer Register Byte. No
additional data is required. The master can then generate
a START condition and send the slave address byte with
the R/W bit HIGH to initiate the read command. See
Figure 6 for details of this sequence. If repeated reads
from the same register are desired, it is not necessary to
continually send the Pointer Register bytes, as the
TMP275 remembers the Pointer Register value until it is
changed by the next write operation.
Note that register bytes are sent most-significant byte first,
followed by the least significant byte.
SLAVE MODE OPERATIONS
The TMP275 can operate as a slave receiver or slave
transmitter.
Slave Receiver Mode:
The first byte transmitted by the master is the slave
address, with the R/W bit LOW. The TMP275 then
acknowledges reception of a valid address. The next byte
transmitted by the master is the Pointer Register. The
TMP275 then acknowledges reception of the Pointer
Register byte. The next byte or bytes are written to the
register addressed by the Pointer Register. The TMP275
acknowledges reception of each data byte. The master
may terminate data transfer by generating a START or
STOP condition.
Slave Transmitter Mode:
The first byte is transmitted by the master and is the slave
address, with the R/W bit HIGH. The slave acknowledges
reception of a valid slave address. The next byte is
transmitted by the slave and is the most significant byte of
the register indicated by the Pointer Register. The master
acknowledges reception of the data byte. The next byte
transmitted by the slave is the least significant byte. The
master acknowledges reception of the data byte. The
master may terminate data transfer by generating a
Not-Acknowledge on reception of any data byte, or
generating a START or STOP condition.
SMBus ALERT FUNCTION
The TMP275 supports the SMBus Alert function. When
the TMP275 is operating in Interrupt Mode (TM = 1), the
ALERT pin of the TMP275 may be connected as an
SMBus Alert signal. When a master senses that an ALER T
condition is present on the ALERT line, the master sends
an SMBus Alert command (00011001) on the bus. If the
ALERT pin of the TMP275 is active, the device
acknowledges the SMBus Alert command and responds
by returning its slave address on the SDA line. The eighth
bit (LSB) of the slave address byte indicates if the
temperature exceeding THIGH or falling below TLOW
caused the ALERT condition. This bit will be HIGH if the
temperature is greater than or equal to T HIGH. This bit will
be LOW if the temperature is less than TLOW. Refer to
Figure 7 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert
command, arbitration during the slave address portion of
the SMBus Alert command determines which device will
clear its ALER T status. If the TMP275 wins the arbitration,
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its ALERT pin will become inactive at the completion of the
SMBus Alert command. If the TMP275 loses the
arbitration, its ALERT pin will remain active.
GENERAL CALL
The TMP275 responds to a Two-Wire General Call
address (0000000) if the eighth bit is 0. The device
acknowledges the General Call address and responds to
commands in the second byte. If the second byte is
00000100, the TMP275 latches the status of the address
pins, but does not reset. If the second byte is 00000110,
the TMP275 latches the status of the address pins and
resets the internal registers to the power-up values.
HIGH-SPEED MODE
In order for the Two-Wire bus to operate at frequencies
above 400kHz, the master device must issue an Hs-mode
master code (00001XXX) as the first byte after a START
condition to switch the bus to high-speed operation. The
TMP275 will not acknowledge this byte, but will switch its
input filters on SDA and SCL and its output filters on SDA
to operate in Hs-mode, allowing transfers at up to 3.4MHz.
After the Hs-mode master code has been issued, the
master transmits a Two-Wire slave address to initiate a
data transfer operation. The bus continues to operate in
Hs-mode until a STOP condition occurs on the bus. Upon
receiving the STOP condition, the TMP275 switches the
input and output filters back to fast-mode operation.
TIMEOUT FUNCTION
The TMP275 resets the serial interface if either SCL or
SDA is held LOW for 54ms (typ) between a START and
STOP condition. The TMP275 releases the bus if it is
pulled LOW and waits for a START condition. To avoid
activating the timeout function, it is necessary to maintain
a communication speed of at least 1kHz for SCL operating
frequency.
TIMING DIAGRAMS
The TMP275 is Two-Wire and SMBus-compatible.
Figure 4 to Figure 7 describe the various operations on the
TMP275. Bus definitions are given below. Parameters for
Figure 4 are defined in Table 12.
Bus Idle: Both SDA and SCL lines remain HIGH.
Start Data Transfer: A change in the state of the SDA line,
from HIGH to LOW, while the SCL line is HIGH, defines a
START condition. Each data transfer is initiated with a
START condition.
Stop Da t a Transfer: A change in the state of the SDA line
from LOW to HIGH while the SCL line is HIGH defines a
STOP condition. Each data transfer is terminated with a
repeated START or STOP condition.
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not limited and
is determined by the master device. The receiver
acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an Acknowledge bit. A device that
acknowledges must pull down the SDA line during the
Acknowledge clock pulse in such a way that the SDA line
is stable LOW during the HIGH period of the Acknowledge
clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data
transfer can be signaled by the master generating a
Not-Acknowledge on the last byte that has been
transmitted by the slave.
PARAMETER
FAST MODE HIGH-SPEED MODE
UNITS
PARAMETER
MIN MAX MIN MAX
UNITS
SCL Operating Frequency f(SCL) 0.001 0.4 0.001 3.4 MHz
Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns
Hold time after repeated START condition.
After this period, the first clock is generated. t(HDSTA) 100 100 ns
Repeated STAR T Condition Setup Time t(SUSTA) 100 100 ns
STOP Condition Setup Time t(SUSTO) 100 100 ns
Data Hold Time t(HDDAT) 0 0 ns
Data Setup Time t(SUDAT) 100 10 ns
SCL Clock LOW Period t(LOW) 1300 160 ns
SCL Clock HIGH Period t(HIGH) 600 60 ns
Clock/Data Fall Time tF300 160 ns
Clock/Data Rise Time tR300 160 ns
for SCLK ≤ 100kHz tR1000 ns
Table 12. Timing Diagram Definitions for the TMP275
"#$%
SBOS363D − JUNE 2006 − REVISED AUGUST 2007
www.ti.com
10
TWO-WIRE TIMING DIAGRAMS
SCL
SDA
t(LOW) tRtFt(HDSTA)
t(HDSTA) t(HDDAT)
t(BUF)
t(SUDAT)
t(HIGH) t(SUSTA) t(SUSTO)
PS SP
Figure 4. Two-Wire Timing Diagram
Frame 1 Two−Wire Slave Address Byte Frame 2 Pointer Register Byte
Frame 4 Data Byte 2
1
Start By
Master ACK By
TMP275 ACK By
TMP275
ACK By
TMP275 Stop By
Master
191
1
D7 D6 D5 D4 D3 D2 D1 D0
9
Frame 3 Data Byte 1
ACK By
TMP275
1
D7
SDA
(Continued)
SCL
(Continued)
D6 D5 D4 D3 D2 D1 D0
9
9
SDA
SCL
0 0 1 A2A1A0R/W 0 0 0 0 0 0 P1 P0 …
…
Figure 5. Two-Wire Timing Diagram for TMP275 Write Word Format
"#$%
SBOS363D − JUNE 2006 − REVISED AUGUST 2007
www.ti.com
11
Frame 1 Two−Wire Slave Address Byte Frame 2 Pointer Register Byte
1
Start By
Master ACK By
TMP275 ACK By
TMP275
Frame3Two−WireSlaveAddressByte Frame4DataByte1ReadRegister
Start By
Master ACK By
TMP275 ACK By
Master
From
TMP275
1919
1919
SDA
SCL
001 R/W 000000P1P0 …
…
…
…
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1001
000
000
R/W D7 D6 D5 D4 D3 D2 D1 D0
Frame 5 Data Byte 2 Read Register NOTE: Address Pins A0, A1, A2 = 0
Stop By
Master
ACK By
Master
From
TMP275
19
D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. Two-Wire Timing Diagram for Read Word Format
Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte
Start By
Master ACK By
TMP275 From
TMP275 NACK By
Master Stop By
Master
1919
SDA
SCL
ALERT
0001100R/W 1001000
Status
NOTE: Address Pins A0, A1, A2 = 0
Figure 7. Timing Diagram for SMBus ALERT
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMP275AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TMP275AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TMP275AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
TMP275AIDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
TMP275AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
TMP275AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
TMP275AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TMP275AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TMP275AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TMP275AIDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TMP275AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMP275AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
TMP275AIDGKT VSSOP DGK 8 250 366.0 364.0 50.0
TMP275AIDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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