MP1474
High-Efficiency, 2A, 16V, 500kHz
Synchronous, Step-Down Converter
MP1474 Rev. 1.0 www.MonolithicPower.com 1
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
The Future of Analog IC Technology
DESCRIPTION
The MP1474 is a high-frequency, synchronous,
rectified, step-down, switch-mode converter
with built-in power MOSFETs. It offers a very
compact solution to achieve a 2A continuous
output current with excellent load and line
regulation over a wide input supply range. The
MP1474 has synchronous mode operation for
higher efficiency over the output current load
range.
Current-mode operation provides fast transient
response and eases loop stabilization.
Full protection features include over-current
protection and thermal shut down.
The MP1474 requires a minimal number of
readily-available standard external components,
and is available in a space-saving 8-pin
TSOT23 package.
FEATURES
Wide 4.5V-to-16V Operating Input Range
100m/40m Low RDS(ON) Internal Power
MOSFETs
High-Efficiency Synchronous Mode
Operation
Fixed 500kHz Switching Frequency
Synchronizes from a 200kHz-to-2MHz
External Clock
Power-Save Mode at Light Load
Internal Soft-Start
Power Good Indicator
OCP Protection and Hiccup
Thermal Shutdown
Output Adjustable from 0.8V
Available in an 8-pin TSOT-23 Package
APPLICATIONS
Notebook Systems and I/O Power
Digital Set-Top Boxes
Flat-Panel Television and Monitors
Distributed Power Systems
A
ll MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithi
c
Power Systems, Inc.
TYPICAL APPLICATION
MP1474
IN
EN/SYNC
VCC
PG GND
FB
SW
BSTVIN
EN/
SYNC
C5
0.1
R1
40.2k
R2
13k
R5
100k
L1
C2
47
C4C1
4.5V-16V
3.3V/2A
22
2
6
7
1
5
3
8
4
R6
16k
R3
20
OUTPUT CURRENT (A)
Efficiency vs.
Output Current
VOUT=3.3V, IOUT=0.01A-2A
50
55
60
65
70
75
80
85
90
95
100
0.0 0.4 0.8 1.2 1.6 2.0
VIN=16V
VIN=12V
VIN=5V
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 2
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking
MP1474DJ TSOT-23-8 ADK
* For Tape & Reel, add suffix –Z (e.g. MP1474DJ–Z);
For RoHS Compliant Packaging, add suffix –LF (e.g. MP1474DJ–LF–Z)
PACKAGE REFERENCE
PG
IN
SW
GND
FB
VCC
EN/SYNC
BST
1
2
3
4
8
7
6
5
TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
VIN .................................................. -0.3V to 17V
VSW ......................................................................
-0.3V (-5V for <10ns) to 17V (19V for <10ns)
VBST ........................................................ VSW+6V
All Other Pins ................................ -0.3V to 6V (2)
Continuous Power Dissipation (TA = +25°C) (3)
........................................................... 1.25W
Junction Temperature ............................... 150°C
Lead Temperature .................................... 260°C
Storage Temperature ................. -65°C to 150°C
Recommended Operating Conditions (4)
Supply Voltage VIN ........................... 4.5V to 16V
Output Voltage VOUT ..................... 0.8V to VIN-3V
Operating Junction Temp. (TJ). -40°C to +125°C
Thermal Resistance (5) θJA θJC
TSOT-23-8 ............................. 100 ..... 55 ... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) About the details of EN pin’s ABS MAX rating, please refer to
Page 9, Enable/SYNC control section.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance JA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/JA. Exceeding the maximum allowable powe
r
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 3
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS (6)
VIN = 12V, TA = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Supply Current (Shutdown) IIN V
EN = 0V 7 A
Supply Current (Quiescent) I
q
V
EN = 2V, VFB = 1V 0.6 1 mA
HS Switch-On Resistance HSRDS-ON V
BST-SW=5V 100 m
LS Switch-On Resistance LSRDS-ON V
CC =5V 40 m
Switch Leakage SWLKG V
EN = 0V, VSW =12V 1 A
Current Limit
(
6
)
I
LIMIT Under 40% Duty Cycle 3 A
Oscillator Frequency fSW V
FB=0.75V 430 500 570 kHz
Fold-Back Frequency fFB V
FB<400mV 0.25 fSW
Maximum Duty Cycle DMAX V
FB=700mV 90 95 %
Minimum On Time
(6)
τON MIN 40 ns
Sync Frequency Range fSYNC 0.2 2 MHz
Feedback Voltage VFB TA =25°C 791 807 823 mV
-40°C<TA<85°C
(7)
787 807 827
Feedback Current IFB V
FB=820mV 10 50 nA
EN Rising Threshold VEN RISING 1.2 1.4 1.6 V
EN Falling Threshold VEN FALLING 1.1 1.25 1.4 V
EN Input Current IEN VEN=2V 2 A
VEN=0 0 A
EN Turn-Off Delay ENtd-off 5 s
Power-Good Rising Threshold PGvth-Hi 0.9 VFB
Power-Good Falling Threshold PGvth-Lo 0.85 VFB
Power-Good Delay PGTd 0.4 ms
Power-Good Sink Current
Capability VPG Sink 4mA 0.4 V
Power-Good Leakage Current IPG-LEAK 1 A
VIN Under-Voltage Lockout
Threshold—Rising INUVVth 3.7 3.9 4.1 V
VIN Under-Voltage Lockout
Threshold—Hysteresis INUVHYS 650 mV
VCC Regulator VCC 5 V
VCC Load Regulation ICC=5mA 3 %
Soft-Start Period τSS 1.2 ms
Thermal Shutdown
(
6
)
150 °C
Thermal Hysteresis
(
6
)
20 °C
Notes:
6) Guaranteed by design.
7) Not tested in production and guaranteed by over-temperature correlation.
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 4
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
TYPICAL CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
4 6 8 10 12 14 16 18
INPUT VOLTAGE(V)
2.5
2.8
3.1
3.4
3.7
4
4.3
25 30 35 40 45 50 55 60 65 70 75
Load Regulation
VIN=5-16V, IOUT=0-2A
Peak Current
vs. Duty Cycle
Disabled Supply Current
vs. Input Voltage
VEN=0V
Enabled Supply Current
vs. Input Voltage
VFB=1V
Line Regulation
VIN=5V-16V
OUTPUT CURRENT (A) INPUT VOLTAGE(V)
PEAK CURRENT (A)
INPUT VOLTAGE(V)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 0.4 0.8 1.2 1.6 2
VIN=12V
VIN=16V
VIN=5V
-0.5
-0.3
-0.1
0.1
0.3
0.5
5678910111213141516
IOUT=0A
IOUT=1A
IOUT=2A
-10
-7
-4
-1
2
5
8
11
14
17
20
0 5 10 15 20 400
450
500
550
600
650
700
750
800
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 5
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
OUTPUT CURRENT (A)OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Short Recovery
IOUT=0A
Startup through Enable
IOUT=0A
Short Entry
IOUT=0A
OUTPUT CURRENT (A)OUTPUT CURRENT (A)
0
3
6
9
12
15
18
00.511.52
OUTPUT CURRENT (A)
Case Temperature Rise
vs. Output Current
IOUT=0A-2A
50
55
60
65
70
75
80
85
90
95
100
0.0 0.4 0.8 1.2 1.6 2.0
VIN=5V
VIN=12V
VIN=16V
50
55
60
65
70
75
80
85
90
95
100
0.0 0.4 0.8 1.2 1.6 2.0
VIN=5V
VIN=12V
VIN=16V
50
55
60
65
70
75
80
85
90
95
100
0.0 0.4 0.8 1.2 1.6 2.0
VIN=5V
VIN=12V
VIN=16V
50
55
60
65
70
75
80
85
90
95
100
0.0 0.4 0.8 1.2 1.6 2.0
VIN=16V
VIN=12V
50
55
60
65
70
75
80
85
90
95
100
0.0 0.4 0.8 1.2 1.6 2.0
VIN=7V
VIN=12V
VIN=16V
V
OUT
2V/div.
VPG
5V/div.
VSW
10V/div.
VIN
10V/div.
IINDUCTOR
5A/div.
VOUT
2V/div.
VPG
5V/div.
VSW
10V/div.
VIN
10V/div.
IINDUCTOR
5A/div.
VOUT
2V/div.
VPG
5V/div.
VSW
10V/div.
VEN
5V/div.
IINDUCTOR
2A/div.
VIN=5V
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 6
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
Startup through Enable
I
OUT
=2A
Shutdown through
Enable
I
OUT
=0A
Shutdown through
Enable
I
OUT
=2A
Startup through Input
Voltage
I
OUT
=0A
Startup through Input
Voltage
I
OUT
=2A
Shutdown through
Input Voltage
I
OUT
=0A
Shutdown through
Input Voltage
I
OUT
=2A
Input / Output Ripple
I
OUT
=2A
VSW
10V/div.
IOUT
1A/div.
VIN/AC
200mV/div.
VOUT/AC
20mV/div.
VOUT/AC
50mV/div.
IL
2A/div.
VEN
5V/div.
VSW
10V/div.
VOUT
2V/div.
VPG
5V/div.
IINDUCTOR
2A/div.
VIN
5V/div.
VSW
5V/div.
VOUT
2V/div.
VPG
5V/div.
IINDUCTOR
2A/div.
VIN
5V/div.
VSW
5V/div.
VOUT
2V/div.
VPG
5V/div.
IINDUCTOR
2A/div.
VIN
5V/div.
VSW
5V/div.
VOUT
2V/div.
VPG
5V/div.
IINDUCTOR
2A/div.
VIN
5V/div.
VSW
5V/div.
VOUT
2V/div.
VPG
5V/div.
IINDUCTOR
2A/div.
VEN
5V/div.
VSW
10V/div.
VOUT
2V/div.
VPG
5V/div.
IINDUCTOR
2A/div.
VEN
5V/div.
VSW
10V/div.
VOUT
2V/div.
VPG
5V/div.
IINDUCTOR
2A/div.
Load Transient Reponse
I
OUT
=1A-2A
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 7
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
PIN FUNCTIONS
Package
Pin # Name Description
1 PG
Power Good Output. The output of this pin is an open drain that goes high if the output
voltage exceeds 90% of the normal voltage. There is a 0.4ms delay between when
FB90% to when the PG pin goes high.
2 IN
Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The
MP1474 operates from a +4.5V to +16V input rail. Requires a low-ESR, and low-
inductance capacitor (C1) to decouple the input rail. Place the input capacitor very close to
this pin and connect it with wide PCB traces and multiple vias.
3 SW
Switch Output. Connect to the inductor and bootstrap capacitor. This pin is driven up to VIN
by the high-side switch during the PWM duty cycle ON time. The inductor current drives
the SW pin negative during the OFF time. The ON resistance of the low-side switch and
the internal body diode fixes the negative voltage. Connect using wide PCB traces and
multiple vias.
4 GND
System Ground. Reference ground of the regulated output voltage. PCB layout Requires
extra care. For best results, connect to GND with copper and vias.
5 BST
Bootstrap. Requires a capacitor connected between SW and BST pins to form a floating
supply across the high-side switch driver.
6 EN/SYNC
Enable. EN=high to enable the MP1474. Apply an external clock change the switching
frequency. For automatic start-up, connect EN pin to VIN with a 100k resistor.
7 VCC
Internal 5V LDO output. Powers the driver and control circuits. Decouple with 0.1F-to-
0.22F capacitor. Do not use a capacitor 0.22F.
8 FB
Feedback. Connect to the tap of an external resistor divider from the output to GND to set
the output voltage. The frequency fold-back comparator lowers the oscillator frequency
when the FB voltage is below 400mV to prevent current limit runaway during a short circuit
fault. Place the resistor divider as close to the FB pin as possible. Avoid placing vias on
the FB traces.
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 8
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
FUNCTIONAL BLOCK DIAGRAM
50pF
1MEG
6.5V
BST
RSEN
IN
Oscillator
VCC
Regulator
Bootstrap
Regulator
VCC
Currrent Sense
Amplifer
VCC
Current Limit
Comparator
Error Amplifier
Ref
Reference
EN/SYNC
FB
+
+
+
-
-
+
-
+
-
PG
SW
GND
LS
Driver
HS
Driver
Comparator
On Time Control
Logic Control
1pF
400k
Figure 1: Functional Block Diagram
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 9
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
OPERATION
The MP1474 is a high-frequency, synchronous,
rectified, step-down, switch-mode converter
with built-in power MOSFETs. It offers a very
compact solution that achieves a 2A continuous
output current with excellent load and line
regulation over a wide input supply range.
The MP1474 operates in a fixed-frequency,
peak-current–control mode to regulate the
output voltage. An internal clock initiates a
PWM cycle. The integrated high-side power
MOSFET turns on and remains on until the
current reaches the value set by the COMP
voltage. When the power switch is off, it
remains off until the next clock cycle starts. If,
within 95% of one PWM period, the current in
the power MOSFET does not reach the value
set by the COMP value, the power MOSFET is
forced off.
Internal Regulator
A 5V internal regulator powers most of the
internal circuitries. This regulator takes VIN and
operates in the full VIN range. When VIN
exceeds 5.0V, the output of the regulator is in
full regulation. When VIN is less than 5.0V, the
output decreases, and the part requires a 0.1µF
ceramic decoupling capacitor.
Error Amplifier
The error amplifier compares the FB pin voltage
to the internal 0.807V reference (VREF) and
outputs a current proportional to the difference
between the two. This output current then
charges or discharges the internal
compensation network to form the COMP
voltage, which controls the power MOSFET
current. The optimized internal compensation
network minimizes the external component
counts and simplifies the control loop design.
Enable/SYNC Control
EN/SYNC is a digital control pin that turns the
regulator on and off. Drive EN high to turn on
the regulator; drive it low to turn it off. An
internal 1M resistor from EN/SYNC to GND
allows EN/SYNC to be floated to shut down the
chip.
The EN pin is clamped internally using a 6.5V
series-Zener-diode as shown in Figure 2.
Connecting the EN input pin through a pullup
resistor to the voltage on the IN pin limits the
EN input current to less than 100µA.
For example, with 12V connected to IN, RPULLUP
(12V – 6.5V) ÷ 100µA = 55k.
Connecting the EN pin is directly to a voltage
source without any pullup resistor requires
limiting the amplitude of the voltage source to
6V to prevent damage to the Zener diode.
Figure 2: 6.5V Zener Diode Connection
For external clock synchronization, connect a
clock with a frequency range between 200kHz
and 2MHz 2ms after the output voltage is set:
The internal clock rising edge will synchronize
with the external clock rising edge. Select an
external clock signal with a pulse width less
than 1.7s.
Under-Voltage Lockout (UVLO)
The MP1474 has under-voltage lock-out
protection (UVLO). When the VCC voltage
exceeds the UVLO rising threshold voltage, the
MP1474 powers up. It shuts off when the VCC
voltage drops below the UVLO falling threshold
voltage. This is non-latch protection.
The MP1474 is disabled when the input voltage
falls below 3.25V. If an application requires a
higher under-voltage lockout (UVLO) threshold,
use the EN pin as shown in Figure 3 to adjust
the input voltage UVLO by using two external
resistors. For best results, set the UVLO falling
threshold (VSTOP) above 4.5V using the
enable resistors. Set the rising threshold
(VSTART) to provide enough hysteresis to
allow for any input supply variations.
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 10
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
Figure 3: Adjustable UVLO
Internal Soft-Start
The soft-start prevents the converter output
voltage from overshooting during startup. When
the chip starts, the internal circuitry generates a
soft-start voltage (VSS) that ramps up from 0V to
1.2V. When VSS is less than VREF, the error
amplifier uses VSS as the reference. When VSS
exceeds VREF, the error amplifier uses VREF as
the reference. The SS time is internally set to
1.2ms.
Power Good Indicator
MP1474 has an open drain pin as the power-
good indicator (PG). Pull this up to VCC or
another external source through a 100k
resistor. When VFB exceeds 90% of VREF, PG
switches goes high with 0.4ms delay time. If VFB
goes below 85% of VREF, an internal MOSFET
pulls the PG pin down to ground.
The internal circuit keeps the PG low once the
input supply exceeds 1.2V.
Over-Current-Protection and Hiccup
The MP1474 has a cycle-by-cycle over-current
limit when the inductor current peak value
exceeds the set current limit threshold.
Meanwhile, the output voltage drops until VFB is
below the Under-Voltage (UV) threshold—
typically 50% below the reference. Once UV is
triggered, the MP1474 enters hiccup mode to
periodically restart the part. This protection
mode is especially useful when the output is
dead-shorted to ground, and greatly reduces
the average short circuit current to alleviate
thermal issues and protect the regulator. The
MP1474 exits the hiccup mode once the over-
current condition is removed.
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the silicon die reaches temperatures that
exceed 150°C, it shuts down the whole chip.
When the temperature drops below its lower
threshold, typically 130°C, the chip is enabled
again.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. This floating
driver has its own UVLO protection. This
UVLO’s rising threshold is 2.2V with a
hysteresis of 150mV. The bootstrap capacitor
voltage is regulated internally by VIN through
D1, M1, R3, C4, L1 and C2 (Figure 4). If (VIN-
VSW) exceeds 5V, U1 will regulate M1 to
maintain a 5V BST voltage across C4. A 20
resistor placed between SW and BST cap. is
strongly recommended to reduce SW spike
voltage.
V
IN
D1
5V
M1
U1
BST
C4
SW L1
V
OUT
C2
R3
Figure 4: Internal Bootstrap Charging Circuit
Startup and Shutdown
If both VIN and VEN exceed their respective
thresholds, the chip starts. The reference block
starts first, generating stable reference voltage
and currents, and then the internal regulator is
enabled. The regulator provides a stable supply
for the remaining circuitries.
Three events can shut down the chip: VEN low,
VIN low, and thermal shutdown. During the
shutdown procedure, the signaling path is first
blocked to avoid any fault triggering. The
COMP voltage and the internal supply rail are
then pulled down. The floating driver is not
subject to this shutdown command.
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 11
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider sets the output
voltage (see Typical Application on page 1). The
feedback resistor R1 also sets the feedback loop
bandwidth with the internal compensation
capacitor (see Typical Application on page 1).
Choose R1 around 40k. R2 is then given by:
OUT
R1
R2 V1
0.807V
The T-type network—as shown in Figure 5—is
highly recommended when VOUT is low.
Rt
FB 8
R2
R1
Cf
VOUT
Figure 5: T-Type Network
Table 1 lists the recommended T-type resistors
value for common output voltages.
Table 1: Resistor Selection for Common Output
Voltages
VOUT
(V) R1 (kΩ) R2 (kΩ) Rt (kΩ) Cf(pF) L(μH)
1.0 20.5 84.5 82 15 2.2
1.2 30.1 61.9 82 15 2.2
1.8 40.2 32.4 33 15 4.7
2.5 40.2 19.1 33 15 4.7
3.3 40.2 13 16 15 5.5
5 40.2 7.68 16 15 5.5
Selecting the Inductor
Use a1µH-to-10µH inductor with a DC current
rating of at least 25% percent higher than the
maximum load current for most applications. For
highest efficiency, use an inductor with a DC
resistance less than 15m. For most designs,
the inductance value can be derived from the
following equation.
OUT IN OUT
1
IN L OSC
V(VV)
LVIf
Where IL is the inductor ripple current.
Choose the inductor ripple current to be
approximately 30% of the maximum load current.
The maximum inductor peak current is:
2
I
II L
LOAD)MAX(L
Use a larger inductor for improved efficiency
under light-load conditions—below 100mA.
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous, therefore requires a capacitor is to
supply the AC current to the step-down converter
while maintaining the DC input voltage. Use low
ESR capacitors for the best performance. Use
ceramic capacitors with X5R or X7R dielectrics
for best results because of their low ESR and
small temperature coefficients. For most
applications, use a 22µF capacitor.
Since C1 absorbs the input switching current, it
requires an adequate ripple current rating. The
RMS current in the input capacitor can be
estimated by:
IN
OUT
IN
OUT
LOAD1C V
V
1
V
V
II
The worse case condition occurs at VIN = 2VOUT,
where:
2
I
ILOAD
1C
For simplification, choose an input capacitor with
an RMS current rating greater than half of the
maximum load current.
The input capacitor can be electrolytic, tantalum
or ceramic. When using electrolytic or tantalum
capacitors, add a small, high quality ceramic
capacitor (e.g. 0.1F) placed as close to the IC
as possible. When using ceramic capacitors,
make sure that they have enough capacitance to
provide sufficient charge to prevent excessive
voltage ripple at input. The input voltage ripple
caused by capacitance can be estimated as:
LOAD OUT OUT
IN IN
SIN
IV V
V1
fC1V V
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 12
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
Selecting the Output Capacitor
The output capacitor (C2) maintains the DC
output voltage. Use ceramic, tantalum, or low-
ESR electrolytic capacitors. For best results,
use low ESR capacitors to keep the output
voltage ripple low. The output voltage ripple can
be estimated as:
OUT OUT
OUT ESR
S1 IN S
VV 1
V1R
fL V 8fC2
Where L1 is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and the capacitance causes the
majority of the output voltage ripple. For
simplification, the output voltage ripple can be
estimated as:
OUT OUT
OUT 2
IN
S1
VV
V1
V
8f L C2
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated as:
OUT OUT
OUT ESR
IN
S1
VV
V1R
fL V
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP1474 can be optimized for a wide range of
capacitance and ESR values.
External Bootstrap Diode
An external bootstrap diode can enhance the
efficiency of the regulator given the following
conditions:
VOUT is 5V or 3.3V; and
Duty cycle is high: D=
IN
OUT
V
V>65%
In these cases, add an external BST diode from
the VCC pin to BST pin, as shown in Figure 6.
SW
BST
MP1474 C
L
BST
COUT
External BST Diode
VCC
IN4148
Figure 6: Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is
IN4148, and the BST capacitor value is 0.1µF
to 1F.
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 13
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
PC Board Layout (8)
PCB layout is very important to achieve stable
operation especially for VCC capacitor and
input capacitor placement. For best results,
follow these guidelines:
1. Use large ground plane directly connect to
GND pin. Add vias near the GND pin if
bottom layer is ground plane.
2. Place the VCC capacitor to VCC pin and
GND pin as close as possible. Make the
trace length of VCC pin-VCC capacitor
anode-VCC capacitor cathode-chip GND
pin as short as possible.
3. Place the ceramic input capacitor close to
IN and GND pins. Keep the connection of
input capacitor and IN pin as short and
wide as possible.
4. Route SW, BST away from sensitive
analog areas such as FB. It’s not
recommended to route SW, BST trace
under chip’s bottom side.
5. Place the T-type feedback resistor R6 close
to chip to ensure the trace which connects
to FB pin as short as possible
Notes:
8) The recommended layout is based on the Figure 7 Typical
Application circuit on the next page.
Design Example
Below is a design example following the
application guidelines for the specifications:
Table 2: Design Example
VIN 12V
VOUT 3.3V
Io 2A
The detailed application schematic is shown in
Figure 8. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
Evaluation Board Datasheets.
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 14
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
TYPICAL APPLICATION CIRCUITS
VCC
25V
C1A
22uF 0.1uF
C1
25V
0.1uF
C5
GND GND
GND
GND
GND
PG
EN/SYNC
VOUT
100k
R5
VIN
100k
R4
20
R3
0.1uF
C4
22uF
C2A
22uF
C2
15pF
C3
5.5uH
L1
40.2k
R1
7.68k
R2
GND
GND
16k
R6
5V/2A
MP1474
2
7
1
6
5
3
8
4
BST
SW
EN/SYNC
VCC
IN
GND
FB
PG
Figure 7: 12VIN, 5V/2A Output
VCC
25V
C1A
22uF 0.1uF
C1
25V
0.1uF
C5
GND GND
GND
GND
GND
PG
EN/SYNC
VOUT
100k
R5
VIN
100k
R4
20
R3
0.1uF
C4
22uF
C2A
22uF
C2
15pF
C3
5.5uH
L1
40.2k
R1
13k
R2
GND
GND
16k
R6
3.3V/2A
MP1474
2
7
1
6
5
3
8
4
BST
SW
EN/SYNC
VCC
IN
GND
FB
PG
Figure 8: 12VIN, 3.3V/2A Output
VCC
25V
C1A
22uF 0.1uF
C1
25V
0.1uF
C5
GND GND
GND
GND
GND
PG
EN/SYNC
VOUT
100k
R5
VIN
100k
R4
20
R3
0.1uF
C4
22uF
C2A
22uF
C2
15pF
C3
4.7uH
L1
40.2k
R1
19.1k
R2
GND
GND
33k
R6
2.5V/2A
MP1474
2
7
1
6
5
3
8
4
BST
SW
EN/SYNC
VCC
IN
GND
FB
PG
Figure 9: 12VIN, 2.5V/2A Output
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1474 Rev. 1.0 www.MonolithicPower.com 15
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
VCC
25V
C1A
22uF 0.1uF
C1
25V
0.1uF
C5
GND GND
GND
GND
GND
PG
EN/SYNC
VOUT
100k
R5
VIN
100k
R4
20
R3
0.1uF
C4
22uF
C2A
22uF
C2
15pF
C3
4.7uH
L1
40.2k
R1
32.4k
R2
GND
GND
33k
R6
1.8V/2A
MP1474
2
7
1
6
5
3
8
4
BST
SW
EN/SYNC
VCC
IN
GND
FB
PG
Figure 10: 12VIN, 1.8V/2A Output
VCC
25V
C1A
22uF 0.1uF
C1
25V
0.1uF
C5
GND GND
GND
GND
GND
PG
EN/SYNC
VOUT
100k
R5
VIN
100k
R4
20
R3
0.1uF
C4
22uF
C2A
22uF
C2
15pF
C3
2.2uH
L1
30.1k
R1
61.9k
R2
GND
GND
82k
R6
1.2V/2A
MP1474
2
7
1
6
5
3
8
4
BST
SW
EN/SYNC
VCC
IN
GND
FB
PG
Figure 11: 12VIN, 1.2V/2A Output
VCC
25V
C1A
22uF 0.1uF
C1
25V
0.1uF
C5
GND GND
GND
GND
GND
PG
EN/SYNC
VOUT
100k
R5
VIN
100k
R4
20
R3
0.1uF
C4
22uF
C2A
22uF
C2
15pF
C3
2.2uH
L1
20.5k
R1
84.5k
R2
GND
GND
82k
R6
1V/2A
MP1474
2
7
1
6
5
3
8
4
BST
SW
EN/SYNC
VCC
IN
GND
FB
PG
Figure 12: 12VIN, 1V/2A Output
MP1474 – SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP1474 Rev. 1.0 www.MonolithicPower.com 16
9/26/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
PACKAGE INFORMATION
TSOT23-8
