LM5118MH/NOPB - Texas Instruments

VIN VCC

VOUT

GND

CSG

RAMP

VOUT

COMP

LM5118

010 20 30 40 50 60

VIN (V)

100

EFFICIENCY (%)

1 AMP

2 AMP

3 AMP

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5118

SNVS566J –APRIL 2008–REVISED JUNE 2017

LM5118 Wide Voltage Range Buck-Boost Controller

1 Features

1• Ultra-Wide Input Voltage Range From 3 V to 75 V

• Emulated Peak Current Mode Control

• Smooth Transition Between Step-Down and Step-

Up Modes

• Switching Frequency Programmable to 500 KHz

• Oscillator Synchronization Capability

• Internal High Voltage Bias Regulator

• Integrated High and Low-Side Gate Drivers

• Programmable Soft-Start Time

• Ultra-Low Shutdown Current

• Enable Input Wide Bandwidth Error Amplifier

• 1.5% Feedback Reference Accuracy

• Thermal Shutdown

• Package: 20-Pin HTSSOP (Exposed Pad)

• Create a Custom Design Using the LM5118 With

the WEBENCH®Power Designer

2 Applications

Industrial Buck-Boost Supplies

3 Description

The LM5118 wide voltage range Buck-Boost

switching regulator controller features all of the

functions necessary to implement a high-

performance, cost-efficient Buck-Boost regulator

using a minimum of external components. The Buck-

Boost topology maintains output voltage regulation

when the input voltage is either less than or greater

than the output voltage, making it especially suitable

for automotive applications. The LM5118 operates as

a buck regulator while the input voltage is sufficiently

greater than the regulated output voltage and

gradually transitions to the buck-boost mode as the

input voltage approaches the output. This dual-mode

approach maintains regulation over a wide range of

input voltages with optimal conversion efficiency in

the buck mode and a glitch-free output during mode

transitions. This easy-to-use controller includes

drivers for the high-side buck MOSFET and the low-

side boost MOSFET. The regulators control method

is based upon current mode control using an

emulated current ramp. Emulated current mode

control reduces noise sensitivity of the pulse-width

modulation circuit, allowing reliable control of the very

small duty cycles necessary in high input voltage

applications. Additional protection features include

current limit, thermal shutdown and an enable input.

The device is available in a power-enhanced, 20-pin

HTSSOP package featuring an exposed die attach

pad to aid thermal dissipation.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM5118 HTSSOP (20) 6.50 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic Efficiency vs VIN and IOUT, VOUT = 12 V

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 4

6 Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Typical Characteristics............................................ 10

7 Detailed Description............................................ 12

7.1 Overview................................................................. 12

7.2 Functional Block Diagram....................................... 12

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 20

8 Application and Implementation ........................ 23

8.1 Application Information............................................ 23

8.2 Typical Application ................................................. 23

9 Power Supply Recommendations...................... 35

9.1 Thermal Considerations.......................................... 35

9.2 Bias Power Dissipation Reduction.......................... 36

10 Layout................................................................... 38

10.1 Layout Guidelines ................................................. 38

10.2 Layout Example .................................................... 38

11 Device and Documentation Support................. 39

11.1 Device Support...................................................... 39

11.2 Trademarks........................................................... 39

11.3 Electrostatic Discharge Caution............................ 39

11.4 Glossary................................................................ 39

12 Mechanical, Packaging, and Orderable

Information........................................................... 39

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision I (August 2014) to Revision J Page

• Moved the automotive device to a standalone data sheet (SNVSAX9) ................................................................................ 1

• Moved the storage temp parameters to the Absolute Maximum Ratings .............................................................................. 6

• Changed junction temperature range from: ±150°C max to: –40°C to 150°C....................................................................... 6

• Changed Handling Ratings table to ESD Ratings.................................................................................................................. 6

• Moved the junction temperature ranges to the condition statement ...................................................................................... 7

• Removed the VOLL minimum value......................................................................................................................................... 8

• Removed the VOLH minimum value......................................................................................................................................... 8

Changes from Revision H (October 2013) to Revision I Page

• Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Application

and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical,

Packaging, and Ordering Information .................................................................................................................................... 1

• Deleted footnote "These pins must not be raised above VIN." .............................................................................................. 6

Changes from Revision G (February, 2013) to Revision H Page

• Deleted VIN Range on Functional Block Diagram................................................................................................................. 12

• Changed Figure 19............................................................................................................................................................... 24

• Changed Inductor Selection, L1 Text................................................................................................................................... 27

• Changed Equation 15........................................................................................................................................................... 27

• Changed Equation 16 .......................................................................................................................................................... 27

• Added Efficiency Parameter................................................................................................................................................. 27

• Changed II(PEAK) Value.......................................................................................................................................................... 28

• Changed I2(PEAK) Value.......................................................................................................................................................... 28

• Changed R13 = RSENSEText ................................................................................................................................................ 28

• Added Equation 19 .............................................................................................................................................................. 28

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• Added Equation 20 .............................................................................................................................................................. 28

• Changed Equation 21 .......................................................................................................................................................... 28

• Changed Equation 22 .......................................................................................................................................................... 28

• Changed R13(BUCK) Value..................................................................................................................................................... 28

• Changed R13(BUCK-BOOST) Value............................................................................................................................................ 28

• Added Inductor Current Limit Calculation Section................................................................................................................ 29

• Added Equation 24 .............................................................................................................................................................. 29

• Added Equation 26 .............................................................................................................................................................. 29

• Changed Equation 29 .......................................................................................................................................................... 29

• Changed ESRMAX Value ....................................................................................................................................................... 29

• Deleted Previous Equation 17.............................................................................................................................................. 30

• Deleted Previous Equation 18.............................................................................................................................................. 30

• Changed C1 - C5 = Input Capacitor Text............................................................................................................................. 30

• Changed R8, R9 Text........................................................................................................................................................... 31

• Changed Equation 38 .......................................................................................................................................................... 31

• Changed R1, R3, C21 Text.................................................................................................................................................. 31

• Changed Equation 40 .......................................................................................................................................................... 32

• Changed DMIN to DMAX .......................................................................................................................................................... 32

• Changed DMAX Value............................................................................................................................................................ 32

• Changed DC Gain(MOD) Value............................................................................................................................................... 32

• Changed ESRZERO Value...................................................................................................................................................... 32

• Changed R4, C18, C17 Text................................................................................................................................................ 33

• Changed Figure 21............................................................................................................................................................... 34

• Changed Figure 22............................................................................................................................................................... 34

• Changed Figure 23............................................................................................................................................................... 34

• Added Figure 24................................................................................................................................................................... 34

• Added Figure 25................................................................................................................................................................... 34

• Added Figure 26................................................................................................................................................................... 34

Changes from Revision F (February 2013) to Revision G Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 24

UVLO

RAMP

AGND

VIN

COMP

VOUT

PGND

CSG

SYNC

VCC

VCCX

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(1) G = Ground, I = Input, O = Output, P = Power

5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP

(Top View)

Pin Descriptions

PIN TYPE(1) DESCRIPTION

NO. NAME

1 VIN P/I Input supply voltage.

2 UVLO I If the UVLO pin is below 1.23 V, the regulator will be in standby mode (VCC regulator running, switching

regulator disabled). When the UVLO pin exceeds 1.23 V, the regulator enters the normal operating mode.

An external voltage divider can be used to set an undervoltage shutdown threshold. A fixed 5-µA current is

sourced out of the UVLO pin. If a current limit condition exists for 256 consecutive switching cycles, an

internal switch pulls the UVLO pin to ground and then releases.

3 RT I The internal oscillator frequency is set with a single resistor between this pin and the AGND pin. The

recommended frequency range is 50 kHz to 500 kHz.

4 EN I If the EN pin is below 0.5 V, the regulator will be in a low power state drawing less than 10 µA from VIN. EN

must be raised above 3 V for normal operation.

5 RAMP I Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp

slope used for emulated current mode control.

6 AGND G Analog ground.

7 SS I Soft Start. An external capacitor and an internal 10-µA current source set the rise time of the error amp

reference. The SS pin is held low when VCC is less than the VCC undervoltage threshold (< 3.7 V), when

the UVLO pin is low (< 1.23 V), when EN is low (< 0.5 V) or when thermal shutdown is active.

8 FB I Feedback signal from the regulated output. Connect to the inverting input of the internal error amplifier.

9 COMP O Output of the internal error amplifier. The loop compensation network should be connected between COMP

and the FB pin.

10 VOUT I Output voltage monitor for emulated current mode control. Connect this pin directly to the regulated output.

11 SYNC I Sync input for switching regulator synchronization to an external clock.

12 CS I Current sense input. Connect to the diode side of the current sense resistor.

13 CSG I Current sense ground input. Connect to the ground side of the current sense resistor.

14 PGND G Power Ground.

15 LO O Boost MOSFET gate drive output. Connect to the gate of the external boost MOSFET.

16 VCC P/I/O Output of the bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as close to

the controller as possible.

17 VCCX P/I Optional input for an externally supplied bias supply. If the voltage at the VCCX pin is greater than 3.9 V, the

internal VCC regulator is disabled and the VCC pin is internally connected to VCCX pin supply. If VCCX is

not used, connect to AGND.

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Pin Descriptions (continued)

PIN TYPE(1) DESCRIPTION

NO. NAME

18 HB I High-side gate driver supply used in bootstrap operation. The bootstrap capacitor supplies current to charge

the high-side MOSFET gate. This capacitor should be placed as close to the controller as possible and

connected between HB and HS.

19 HO O Buck MOSFET gate drive output. Connect to the gate of the high-side buck MOSFET through a short, low

inductance path.

20 HS I Buck MOSFET source pin. Connect to the source terminal of the high-side buck MOSFET and the bootstrap

capacitor.

— EP — Solder to the ground plane under the IC to aid in heat dissipation.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VIN, EN, VOUT to GND –0.3 76 V

VCC, LO, VCCX, UVLO to GND –0.3 15 V

HB to HS –0.3 15 V

HO to HS –0.3 HB + 0.3 V

HS to GND –4 76 V

CSG, CS to GND –0.3 0.3 V

RAMP, SS, COMP, FB, SYNC, RT to GND –0.3 7 V

Junction temperature –40 150 °C

Storage temperature, Tstg –55 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

(1) The Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but does not ensure

specific performance limits. For specifications and test conditions see Electrical Characteristics.

(2) 5-V VIN is required to initially start the controller.

6.3 Recommended Operating Conditions

over operating free air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VIN (2) 3 75 V

VCC, VCCX 4.75 14 V

Junction temperature –40 +125 °C

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) LM5118

UNITPWP (HTSSOP)

20 PINS

RθJA Junction-to-ambient thermal resistance 40 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 4 °C/W

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(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through

correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

6.5 Electrical Characteristics

Unless otherwise specified, the following conditions apply: VIN = 48 V, VCCX = 0 V, EN = 5 V, RT = 29.11 kΩ, No load on

LO and HO. Typical values apply for TJ= 25°C; minimum and maximum values apply over the full junction temperature range

for operation, −40°C to +125°C.(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN SUPPLY

IBIAS VIN operating current VCCX = 0 V 4.5 5.5 mA

IBIASX VIN operating current VCCX = 5 V 1 1.85 mA

ISTDBY VIN shutdown current EN = 0 V 1 10 µA

VCC REGULATOR

VCC(REG) VCC regulation VCCX = 0 V 6.8 7 7.2 V

VCC(REG) VCC regulation VCCX = 0 V, VIN = 6 V 5 5.25 5.5 V

VCC sourcing current limit VCC = 0 21 35 mA

VCCX switch threshold VCCX rising 3.68 3.85 4.02 V

VCCX switch hysteresis 0.2 V

VCCX switch RDS(ON) ICCX = 10 mA 5 12 Ω

VCCX switch leakage VCCX = 0 V 0.5 1 µA

VCCCX pulldown resistance VCCX = 3 V 70 kΩ

VCC undervoltage lockout voltage VCC rising 3.52 3.7 3.86 V

VCC undervoltage hysteresis 0.21 V

HB DC bias current HB-HS = 15 V 205 260 µA

VC LDO mode turnoff 10 V

EN INPUT

VIL max EN input low threshold 0.5 V

VIH min EN input high threshold 3 V

EN input bias current VEN = 3 V –1 1 µA

EN input bias current VEN = 0.5 V –1 1 µA

EN input bias current VEN = 75 V 50 µA

UVLO THRESHOLDS

UVLO standby threshold UVLO rising 1.191 1.231 1.271 V

UVLO threshold hysteresis 0.105 V

UVLO pullup current source UVLO = 0 V 5 µA

UVLO pulldown RDS(ON) 100 200 Ω

SOFT START

SS current source SS = 0V 7.5 10.5 13.5 µA

SS to FB offset FB = 1.23 V 150 mV

SS output low voltage Sinking 100 µA, UVLO = 0 V 7 mV

ERROR AMPLIFIER

VREF FB reference voltage Measured at FB pin,

FB = COMP 1.212 1.23 1.248 V

FB input bias current FB = 2 V 20 200 nA

COMP sink/source current 3 mA

AOL DC gain 80 dB

fBW Unity bain bandwidth 3 MHz

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Electrical Characteristics (continued)

Unless otherwise specified, the following conditions apply: VIN = 48 V, VCCX = 0 V, EN = 5 V, RT = 29.11 kΩ, No load on

LO and HO. Typical values apply for TJ= 25°C; minimum and maximum values apply over the full junction temperature range

for operation, −40°C to +125°C.(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PWM COMPARATORS

tHO(OFF) Forced HO off-time 305 400 495 ns

TON(MIN) Minimum HO on-time 70 ns

COMP to comparator offset 200 mV

OSCILLATOR (RT PIN)

fSW1 Frequency 1 RT = 29.11 kΩ178 200 224 kHz

fSW2 Frequency 2 RT = 9.525 kΩ450 515 575 kHz

SYNC

Sync threshold falling 1.3 V

CURRENT LIMIT

VCS(TH) Cycle-by-cycle sense voltage

threshold (CS-CSG) RAMP = 0 buck mode –103 –125 –147 mV

VCS(THX) Cycle-by-cycle sense voltage

threshold (CS-CSG) RAMP = 0 buck-boost mode –218 –255 –300 mV

CS bias current CS = 0 V 45 60 µA

CSG bias current CSG = 0 V 45 60 µA

Current limit fault timer 256 cycles

RAMP GENERATOR

IR1 RAMP current 1 VIN = 60 V, VOUT = 10 V 245 305 365 µA

IR2 RAMP current 2 VIN = 12 V, VOUT = 12 V 95 115 135 µA

IR3 RAMP current 3 VIN = 5 V, VOUT = 12 V 65 80 95 µA

VOUT bias current VOUT = 48 V 245 µA

LOW-SIDE (LO) GATE DRIVER

VOLL LO low-state output voltage ILO = 100 mA 0.14 0.23 V

VOHL LO high-state output voltage ILO = -100 mA

VOHL = VCC-VLO 0.25 V

LO rise time C-load = 1 nF, VCC = 8 V 16 ns

LO fall time C-load = 1 nF, VCC = 8 V 14 ns

IOHL Peak LO source current VLO = 0 V, VCC = 8 V 2.2 A

IOLL Peak LO sink current VLO = VCC = 8 V 2.7 A

HIGH-SIDE (HO) GATE DRIVER

VOLH HO low-state output voltage IHO = 100 mA 0.135 0.21 V

VOHH HO high-state output voltage IHO = -100 mA,

VOHH = VHB-VOH 0.25 V

HO rise time C-load = 1 nF, VCC = 8 V 14 ns

HO fall time C-load = 1 nF, VCC = 8 V 12 ns

IOHH Peak HO source current VHO = 0V, VCC = 8 V 2.2 A

IOLH Peak HO sink current VHO = VCC = 8 V 3.5 A

HB-HS undervoltage lockout 3 V

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Electrical Characteristics (continued)

Unless otherwise specified, the following conditions apply: VIN = 48 V, VCCX = 0 V, EN = 5 V, RT = 29.11 kΩ, No load on

LO and HO. Typical values apply for TJ= 25°C; minimum and maximum values apply over the full junction temperature range

for operation, −40°C to +125°C.(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) When the duty cycle exceeds 75%, the LM5118 controller gradually phases into the Buck-Boost mode.

BUCK-BOOST CHARACTERISTICS

Buck-boost mode Buck duty cycle (2) 69% 75% 80%

THERMAL

TSD Thermal shutdown temperature 165 °C

Thermal shutdown hysteresis 25 °C

0 1 2 3 4 5 6 7 8

OUTPUT VOLTAGE (V)

0.5

1.5

2.5

3.5

CURRENT (A)

LO Source

LO Sink

HO Sink

HO Source

1E+04 1E+05 1E+06 1E+07

FREQUENCY (Hz)

-10

GAIN (dB)

-30

150

120

PHASE (°)

0 10 20 30 40 50

VCC (V)

IVCC (mA)

02 4 6 8 10 12

VIN (V)

VCC (V)

65 110

-275

-100

CURRENT LIMIT THRESHOLD (mV)

VOUT/VIN DC (%)

70 75 80 85 90 95 100 105

-250

-225

-200

-175

-150

-125

010 20 30 40 50 60

VIN (V)

100

EFFICIENCY (%)

1 AMP

2 AMP

3 AMP

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6.6 Typical Characteristics

Figure 1. Efficiency vs VIN and IOUT, VOUT = 12 V Figure 2. Current Limit Threshold vs VOUT/VIN

VOUT = 12 V

Figure 3. VCC vs VIN Figure 4. VCC vs IVCC

Figure 5. Error Amplifier Gain/Phase Figure 6. LO and HO Peak Gate Current vs Output Voltage

VCC = 8 V

020 40 60 80 100 120 140 160

RT (k:)

100

200

300

400

500

600

FOSC (kHz)

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Typical Characteristics (continued)

Figure 7. Oscillator Frequency vs RT

VOUT

VIN VCC

REGULATOR

Vin

LEVEL

SHIFT

THERMAL

SHUTDOWN

LM5118

VCC UVLO

HB UVLO

ERROR

AMP

COMP

TRACK

and

HOLD

CLK

OSCILLATOR

AGND

CLK

CSG

CLK

RAMP GENERATOR

= 5µA x Vin +

SHUTDOWN

AND

STANDBY

MODE

CONTROL

PWM

I-LIMIT

RAMP

Vin

10 µA

Vin

IRAMP BUCK-BOOST

MODE CONTROL

PGND

VOUT

514

3.9V

HICCUP MODE

FAULT TIMER

UVLO

VIN

VCCX

SYNC

A=10

C12

1.23V

C13

DISABLE

1.23V

IRAMP (buck-boost)

50 µA

5 µA

IRAMP (buck) = (5µA x (Vin -Vout)) + 50 µA

Vth(buck) = 1.25V

(buck-boost) = 2.50V

Vth

10 Rs V/A

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7 Detailed Description

7.1 Overview

The LM5118 high voltage switching regulator features all of the functions necessary to implement an efficient

high voltage buck or buck-boost regulator using a minimum of external components. The regulator switches

smoothly from buck to buck-boost operation as the input voltage approaches the output voltage, allowing

operation with the input greater than or less than the output voltage. This easy to use regulator integrates high-

side and low-side MOSFET drivers capable of supplying peak currents of 2 A. The regulator control method is

based on current mode control using an emulated current ramp. Peak current mode control provides inherent line

feed-forward, cycle-by-cycle current limiting and ease of loop compensation. The use of an emulated control

ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing of very small

duty cycles necessary in high input voltage applications. The operating frequency is user programmable from 50

kHz to 500 kHz. An oscillator synchronization pin allows multiple LM5118 regulators to self synchronize or be

synchronized to an external clock. Fault protection features include current limiting, thermal shutdown, and

remote shutdown capability. An undervoltage lockout input allows regulator shutdown when the input voltage is

below a user selected threshold, and a low state at the enable pin will put the regulator into an extremely low

current shutdown state. The device is available in the HTSSOP-20EP package featuring an exposed pad to aid

in thermal dissipation.

7.2 Functional Block Diagram

VOUT

CSG

LM5118

VIN

Q2 (OFF)

Buck Switch

Current

Diode Current

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7.3 Feature Description

A buck-boost regulator can maintain regulation for input voltages either higher or lower than the output voltage.

The challenge is that buck-boost power converters are not as efficient as buck regulators. The LM5118 has been

designed as a dual-mode controller whereby the power converter acts as a buck regulator while the input voltage

is above the output. As the input voltage approaches the output voltage, a gradual transition to the buck-boost

mode occurs. The dual-mode approach maintains regulation over a wide range of input voltages, while

maintaining the optimal conversion efficiency in the normal buck mode. The gradual transition between modes

eliminates disturbances at the output during transitions. Figure 8 shows the basic operation of the LM5118

regulator in the buck mode. In buck mode, transistor Q1 is active and Q2 is disabled. The inductor current ramps

in proportion to the VIN – VOUT voltage difference when Q1 is active and ramps down through the recirculating

diode D1 when Q1 is off. The first order buck mode transfer function is VOUT/VIN = D, where D is the duty cycle

of the buck switch, Q1.

Figure 8. Buck Mode Operation

18 17 16 15 14 13 12 0

100

DUTY CYCLE (%)

VIN (V)

VOUT

CSG

LM5118 D1

Buck Switch

Current

Diode Current

VIN

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Feature Description (continued)

Figure 9 shows the basic operation of buck-boost mode. In buck-boost mode both Q1 and Q2 are active for the

same time interval each cycle. The inductor current ramps up (proportional to VIN) when Q1 and Q2 are active

and ramps down through the recirculating diode during the off time. The first order buck-boost transfer function is

VOUT/VIN = D/(1-D), where D is the duty cycle of Q1 and Q2.

Figure 9. Buck-Boost Mode Operation

Figure 10. Mode Dependence on Duty Cycle (VOUT = 12 V)

7.3.1 UVLO

An undervoltage lockout pin is provided to disable the regulator when the input is below the desired operating

range. If the UVLO pin is below 1.13 V, the regulator enters a standby mode with the outputs disabled, but with

VCC regulator operating. If the UVLO input exceeds 1.23 V, the regulator will resume normal operation. A

voltage divider from the input to ground can be used to set a VIN threshold to disable the regulator in brownout

conditions or for low input faults.

SYNC

LM5118

SYNC

LM5118

UP TO FIVE

LM5118 DEVICES

RT = 6.4 x 109

f- 3.02 x 103

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Feature Description (continued)

If a current limit fault exists for more than 256 clock cycles, the regulator will enter a hiccup mode of current

limiting and the UVLO pin will be pulled low by an internal switch. This switch turns off when the UVLO pin

approaches ground potential allowing the UVLO pin to rise. A capacitor connected to the UVLO pin will delay the

return to a normal operating level and thereby set the off-time of the hiccup mode fault protection. An internal 5-

µA pullup current pulls the UVLO pin to a high state to ensure normal operation when the VIN UVLO function is

not required and the pin is left floating.

7.3.2 Oscillator and Sync Capability

The LM5118 oscillator frequency is set by a single external resistor connected between the RT pin and the

AGND pin. The RTresistor should be located very close to the device and connected directly to the pins of the

IC. To set a desired oscillator frequency (f), the necessary value for the RTresistor can be calculated from

Equation 1:

(1)

The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be

of higher frequency than the free-running frequency set by the RTresistor. A clock circuit with an open-drain

output is the recommended interface from the external clock to the SYNC pin. The clock pulse duration should

be greater than 15 ns.

Multiple LM5118 devices can be synchronized together simply by connecting the SYNC pins together as in

Figure 11. In this configuration, all of the devices are synchronized to the highest frequency device. Figure 12

shows the SYNC input and output features of the LM5118. The internal oscillator circuit drives the SYNC pin with

a strong pull down or weak pullup inverter. When the SYNC pin is pulled low, either by the internal oscillator or

an external clock, the ramp cycle of the oscillator is terminated and forced 400 ns off-time is initiated before a

new oscillator cycle begins. If the SYNC pins of several LM5118 IC’s are connected together, the IC with the

highest internal clock frequency will pull all the connected SYNC pins low and terminate the oscillator ramp

cycles of the other ICs. The LM5118 with the highest programmed clock frequency will serve as the master and

control the switching frequency of all the devices with lower oscillator frequencies.

Figure 11. Sync From Multiple Devices

Emulated

Ramp

Ton

Buck:

Buck - Boost:

Pedestal Level = (volts/amp)

Rsx10

Cramp

ton

50+)- VoutVin(x

Cramp

ton

50+Vinx

SYNC

100 PA

DEADTIME

ONE - SHOT

1.23V

I 1/RT

LM5118

SNVS566J –APRIL 2008–REVISED JUNE 2017

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Product Folder Links: LM5118

Feature Description (continued)

Figure 12. Simplified Oscillator and Block Diagram With Sync I/O Circuit

7.3.3 Error Amplifier and PWM Comparator

The internal high gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference (1.23 V). The output of the error amplifier is

connected to the COMP pin. Loop compensation components, typically a type II network shown in are connected

between the COMP and FB pins. This network creates a low frequency pole, a zero, and a noise reducing high

frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to

the error amplifier output voltage at the COMP pin. The same error amplifier is used for operation in buck and

buck-boost mode.

Figure 13. Composition of Emulated Current Signal

gm x L

CRAMP

RS x A =

gm x L

CRAMP =A x RS

5 PA

Vx VIN + 50 PA

IRAMP (buck - boost) =

5 PA

Vx (VIN - VOUT) + 50 PA

IRAMP (buck) =

LM5118

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Product Folder Links: LM5118

Feature Description (continued)

7.3.4 Ramp Generator

The ramp signal of a pulse-width modulator with current mode control is typically derived directly from the buck

switch drain current. This switch current corresponds to the positive slope portion of the inductor current signal.

Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and

provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current

signal for PWM control is the large leading edge spike due to circuit parasitics. The leading edge spike must be

filtered or blanked to avoid early termination of the PWM pulse. Also, the current measurement may introduce

significant propagation delays. The filtering, blanking time and propagation delay limit the minimal achievable

pulse width. In applications where the input voltage may be relatively large in comparison to the output voltage,

controlling a small pulse width is necessary for regulation. The LM5118 uses a unique ramp generator which

does not actually measure the buck switch current but instead creates a signal representing or emulating the

inductor current. The emulated ramp provides signal to the PWM comparator that is free of leading edge spikes

and measurement or filtering delays. The current reconstruction is comprised of two elements, a sample-and-

hold pedestal level and a ramp capacitor which is charged by a controlled current source. Refer to Figure 13 for

details.

The sample-and-hold pedestal level is derived from a measurement of the recirculating current through a current

sense resistor in series with the recirculating diode of the buck regulator stage. A small value current sensing

resistor is required between the recirculating diode anode and ground. The CS and CSG pins should be Kelvin

connected directly to the sense resistor. The voltage level across the sense resistor is sampled and held just

prior to the onset of the next conduction interval of the buck switch. The current sensing and sample-and-hold

provide the DC level of the reconstructed current signal. The sample and hold of the recirculating diode current is

valid for both buck and buck-boost modes. The positive slope inductor current ramp is emulated by an external

capacitor connected from the RAMP pin to the AGND and an internal voltage controlled current source. In buck

mode, the ramp current source that emulates the inductor current is a function of the VIN and VOUT voltages per

Equation 2:

(2)

In buck-boost mode, the ramp current source is a function of the input voltage VIN, per Equation 3:

(3)

Proper selection of the RAMP capacitor (CRAMP) depends upon the value of the output inductor (L) and the

current sense resistor (RS). For proper current emulation, the sample and hold pedestal value and the ramp

amplitude must have the same relative relationship to the actual inductor current. That is:

where

• gmis the ramp generator transconductance (5 µA/V)

• A is the current sense amplifier gain (10V/V) (4)

The ramp capacitor should be located very close to the device and connected directly to the RAMP and AGND

pins.

1 +VOUT

Iout x VIN

A = 10k

1k + RG

LM5118

SNVS566J –APRIL 2008–REVISED JUNE 2017

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Product Folder Links: LM5118

Feature Description (continued)

The relationship between the average inductor current and the pedestal value of the sampled inductor current

can cause instability in certain operating conditions. This instability is known as sub-harmonic oscillation, which

occurs when the inductor ripple current does not return to its initial value by the start of the next switching cycle.

Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch

node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this

oscillation. The 50 µA of offset current provided from the emulated current source adds enough slope

compensation to the ramp signal for output voltages less than or equal to 12 V. For higher output voltages,

additional slope compensation may be required. In such applications, the ramp capacitor can be decreased from

the nominal calculated value to increase the ramp slope compensation.

The pedestal current sample is obtained from the current sense resistor (Rs) connected to the CS and CSG pins.

It is sometimes helpful to adjust the internal current sense amplifier gain (A) to a lower value in order to obtain

the higher current limit threshold. Adding a pair of external resistors RG in a series with CS and CSG as in

Figure 14 reduces the current sense amplifier gain A according to Equation 5:

(5)

7.3.5 Current Limit

In the buck mode the average inductor current is equal to the output current (IOUT). In buck-boost mode the

average inductor current is approximately equal to:

(6)

Consequently, the inductor current in buck-boost mode is much larger especially when VOUT is large relative to

VIN. The LM5118 provides a current monitoring scheme to protect the circuit from possible over-current

conditions. When set correctly, the emulated current sense signal is proportional to the buck switch current with a

scale factor determined by the current sense resistor. The emulated ramp signal is applied to the current limit

comparator. If the peak of the emulated ramp signal exceeds 1.25 V when operating in the buck mode, the PWM

cycle is immediately terminated (cycle-by-cycle current limiting). In buck-boost mode the current limit threshold is

increased to 2.50 V to allow higher peak inductor current. To further protect the external switches during

prolonged overload conditions, an internal counter detects consecutive cycles of current limiting. If the counter

detects 256 consecutive current limited PWM cycles, the LM5118 enters a low power dissipation hiccup mode. In

the hiccup mode, the output drivers are disabled, the UVLO pin is momentarily pulled low, and the soft-start

capacitor is discharged. The regulator is restarted with a normal soft-start sequence once the UVLO pin charges

back to 1.23 V. The hiccup mode off-time can be programmed by an external capacitor connected from UVLO

pin to ground. This hiccup cycle will repeat until the output overload condition is removed.

In applications with low output inductance and high input voltage, the switch current may overshoot due to the

propagation delay of the current limit comparator and control circuitry. If an overshoot should occur, the sample-

and-hold circuit will detect the excess recirculating diode current. If the sample-and-hold pedestal level exceeds

the internal current limit threshold, the buck switch will be disabled and will skip PWM cycles until the inductor

current has decayed below the current limit threshold. This approach prevents current runaway conditions due to

propagation delays or inductor saturation since the inductor current is forced to decay before the buck switch is

turned on again.

Vout

D = Vin + Vout

0100 200 300 400 500 600

FREQUENCY (kHz)

0.75

0.8

0.85

0.9

0.95

MAX DUTY CYCLE

CSG

TRACK

and HOLD

RAMP

1k RG

10k

0.2V

RAMP

RESET

Vth

CRAMP

CURRENT LIMIT

COMPARATOR

IRAMP

CURRENT SENSE

AMPLIFIER

LM5118

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Product Folder Links: LM5118

Feature Description (continued)

Figure 14. Current Limit and Ramp Circuit

7.3.6 Maximum Duty Cycle

Each conduction cycle of the buck switch is followed by a forced minimum off-time of 400 ns to allow sufficient

time for the recirculating diode current to be sampled. This forced off-time limits the maximum duty cycle of the

controller. The actual maximum duty cycle will vary with the operating frequency as follows:

DMAX = 1 - f × 400 × 10–9

where

• f is the oscillator frequency in Hz (7)

Figure 15. Maximum Duty Cycle vs Frequency

Limiting the maximum duty cycle will limit the maximum boost ratio (VOUT/VIN) while operating in buck-boost

mode. For example, from Figure 15, at an operating frequency of 500 kHz, DMAX is 80%. Using the buck-boost

transfer function.

(8)

With D = 80%, solving for VOUT results in:

VOUT = 4 × VIN (9)

LM5118

SNVS566J –APRIL 2008–REVISED JUNE 2017

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Product Folder Links: LM5118

Feature Description (continued)

With a minimum input voltage of 5 V, the maximum possible output voltage is 20 V at f = 500 kHz. The buck-

boost step-up ratio can be increased by reducing the operating frequency which increases the maximum duty

cycle.

7.3.7 Soft Start

The soft-start feature allows the regulator to gradually reach the initial steady-state operating point, thus reducing

start-up stresses and surges. The internal 10-µA soft-start current source gradually charges an external soft-start

capacitor connected to the SS pin. The SS pin is connected to the positive input of the internal error amplifier.

The error amplifier controls the pulse-width modulator such that the FB pin approximately equals the SS pin as

the SS capacitor is charged. Once the SS pin voltage exceeds the internal 1.23-V reference voltage, the error

amp is controlled by the reference instead of the SS pin. The SS pin voltage is clamped by an internal amplifier

at a level of 150 mV above the FB pin voltage. This feature provides a soft-start controlled recovery in the event

a severe overload pulls the output voltage (and FB pin) well below normal regulation but does not persist for 256

clock cycles.

Various sequencing and tracking schemes can be implemented using external circuits that limit or clamp the

voltage level of the SS pin. The SS pin acts as a non-inverting input to the error amplifier anytime SS voltage is

less than the 1.23-V reference. In the event a fault is detected (overtemperature, VCC undervoltage, hiccup

current limit), the soft-start capacitor will be discharged. When the fault condition is no longer present, a new soft-

start sequence will begin.

7.3.8 HO Output

The LM5118 contains a high-side, high-current gate driver and associated high voltage level shift. This gate

driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.1-µF ceramic

capacitor, connected with short traces between the HB pin and HS pin is recommended for most circuit

configurations. The size of the bootstrap capacitor depends on the gate charge of the external FET. During the

off time of the buck switch, the HS pin voltage is approximately –0.5 V and the bootstrap capacitor is charged

from VCC through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck switch will

be forced off each cycle for 400 ns to ensure that the bootstrap capacitor is recharged.

7.3.9 Thermal Protection

Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction

temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power reset state,

disabling the output driver and the bias regulator. This protection is provided to prevent catastrophic failures from

accidental device overheating.

7.4 Device Functional Modes

Figure 10 shows how duty cycle effects the operational mode and is useful for reference in the following

discussions. Initially, only the buck switch is active and the buck duty cycle increases to maintain output

regulation as VIN decreases. When VIN is approximately equal to 15.5 V, the boost switch begins to operate with

a low duty cycle. If VIN continues to fall, the boost switch duty cycle increases and the buck switch duty cycle

decreases until they become equal at VIN = 13.2 V.

7.4.1 Buck Mode Operation: VIN > VOUT

The LM5118 buck-boost regulator operates as a conventional buck regulator with emulated current mode control

while VIN is greater than VOUT and the buck mode duty cycle is less than 75%. In buck mode, the LO gate drive

output to the boost switch remains low.