IRF634BFP001 - FAIRCHILD SEMICONDUCTOR

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HUFA75307T3ST

2.6A, 55 V, 0 .090 Ohm, N-Channel Ult raFET

Power MOSFET

This N- Channel pow er MOSF ET is

manufactured using the innovative

UltraFET® process. This advanced

process technology achieves the

lowest possib le on-resistance per silicon area, resul ting in

outstandi ng performance. This device is capable of

withstanding high energy in the avalan che mode and the

diode exhibits very low re verse recovery time and stor ed

charge. It was designed for use in applications where power

efficiency is important, such as switching regulators,

switching converters, motor drivers, relay drivers, low-

v oltage bus switc hes, and power management in portable

and battery-operated products.

Formerly developmental ty pe TA75307.

Features

•2.6A, 55V

• Ultra Low On-Resistance, rDS(ON) = 0.090Ω

• Diode Exh ibi ts Both H igh Spe ed and Soft Recovery

• Tempera ture Compensating PSPICE® Model

• Thermal Imped anc e SP ICE Mo de l

• Peak Current vs Pu lse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guid eli ne s for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

SOT-223

This p roduct has b een de si gned t o meet the ext reme te st c ondit i ons and envir onm ent de manded by t he aut omot ive i ndu str y. Fo r a copy

of the requirements, see AEC Q101 at : http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 an d QS9000 quality systems c e rtification.

Ordering Information

PART NUMBER PACKAGE BRAND

HUFA75307T3ST SOT-223 5307

NOT E: HUFA75307T3ST is available only in tape and reel.

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

Data Sheet December 2001

Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 55 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 55 V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20V V

Drain Current

Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 2.6

Figure 5 A

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS F igures 6, 14, 15

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1

9.09 W

mW/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: Str esses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess onl y rating and operation o f the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. TJ = 25oC to 125oC.

Electrical Specifications TA = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V

Zero Gate Vo ltage Drain C urrent IDSS VDS = 50V, VGS = 0V - - 1 µA

VDS = 45V, VGS = 0V, TA = 150oC - - 250 µA

Gate to Source Leakage Current IGSS VGS = ±20V - - 100 nA

Drain to Source On Resist ance rDS(ON) ID = 2.6A, VGS = 10V) (Figure 9) - 0.070 0.090 Ω

Turn-On Time tON VDD = 30V, ID ≅ 2.6A,

RL = 11.5Ω, VGS = 10V,

RGS = 25Ω

- - 55 ns

Turn-On De lay Time td(ON) -5-ns

Rise Time tr-30-ns

Turn-Off De lay Time td(OFF) -35-ns

Fall Time tf-25-ns

Turn-Off T ime tOFF - - 90 ns

Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 30V,

ID ≅ 2.6A,

RL = 11.5Ω

Ig(REF) = 1.0mA

(Figure 13)

-1417nC

Gate Charge at 10V Qg(10) VGS = 0V to 10V - 8.3 10 nC

Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 0.6 0.8 nC

Gate to Source Gate Charge Qgs - 1.00 - nC

Gate to Drain “Miller” Charge Qgd - 4.00 - nC

Input Capacitance CISS VDS = 25V, VGS = 0V,

f = 1MHz

(Figure 12)

- 250 - pF

Output Capacitance COSS - 115 - pF

Reverse Transfer Capacitance CRSS -30-pF

Thermal Resistance Junction to Ambient RθJA Pad Area = 0.171 in2 (see note 2) - - 110 oC/W

Pad Area = 0.068 in2 - - 128 oC/W

Pad Area = 0.026 in2- - 147 oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to D rain Diode Volt age VSD ISD = 2.6A - - 1.25 V

Reverse Recovery Time trr ISD = 2.6A, dISD/dt = 100A/µs--40ns

Reverse Recovered Charge QRR ISD = 2.6A, dISD/dt = 100A/µs--50nC

NOTE:

2. 110 oC/W measured using FR-4 board with 0.171in2 footprint for 1000s.

HUFA75307T3ST

Typical Performance Curves

FIGURE 1. NORMALIZED PO WER DISSIPA TION vs AMBIENT

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AM BIENT TEMPERATURE

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

0 50 100 150

TA, AMBIENT TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

0.2

0.4

0.6

0.8

1.0

1.2

ID, DRAIN CURRENT (A)

TA, AMBIENT TEMPERATURE (oC)

1.0

1.5

2.0

2.5

3.0

25 50 75 100 125 15

0.5

RθJA = 110oC/W

0.001

0.01

0.1

10-5 10-4 10-3 10-2 10-1 100101102103

ZθJA, NORMALIZED

THERMAL IMPEDANCE

SINGLE PULSE NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJA x RθJA + TA

PDM

t1t2

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.01

0.02

t, RECTANGULAR PULSE DURATION (s)

RθJA = 110oC/W

0.01

0.1

100

110100

VDS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

TJ = MAX RATED

TA = 25oC

100µs

10ms

1ms

VDSS(MAX) = 55V

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

RθJA = 110oC/W

103

102

101

100

10-1

10-2

10-3

t, PULSE WIDTH (s)

IDM, PEAK CURRENT ( A)

I = I25 150 - TA

125

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

TA = 25oC

RθJA = 110oC/W

HUFA75307T3ST

NOT E: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAM PE D INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

FIGURE 10. NORMALIZED GATE THRESHOLD V OLTA GE vs

JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN T O SOURCE BREAKDO WN

VOLTAGE vs JUNCTION TEMPERATURE

Typical Performance Curves (Continued)

0.01 0.1 1 10

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVAL ANCHE (ms)

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

STARTING TJ = 25oC

STARTING TJ = 150oC

01234

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 6V

VGS = 10V

VGS = 20V

PULSE DURATION = 80µs

TA = 25oC

VGS = 5V

VGS = 7V

DUTY CYCLE = 0.5% MAX

0 1.5 3.0 4.5 6.0 7.

ID, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15V

150oC

25oC

-55oC

0.5

1.0

1.5

2.0

2.5

-80 -40 0 40 80 120 16

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

PULSE DURATION = 8 0µs

VGS = 10V, ID = 2.6A

DUTY CYCLE = 0.5% MAX

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

THRESHOLD VO LTAGE

0.4

0.6

0.8

1.0

1.2

-80 -40 0 40 80 120 16

VGS = VDS, ID = 250µA

BREAKDOWN VOLTAGE

0.8

0.9

1.0

1.1

1.2

-80 -40 0 40 80 120 16

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

ID = 250µA

HUFA75307T3ST

FIGURE 12. CAPACI TANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE W A VEFORMS FOR CONSTANT

GATE CURRENT

Typical Performance Curves (Continued)

100

200

300

400

500

0 10203040506

C, CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

CISS

COSS

CRSS

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS = CDS + CGD

0246

VGS, GATE TO SOURCE VOLTAGE (V)

VDD = 30V

Qg, GATE CHARGE ( nC)

ID = 2.6A

ID = 1.5A

ID = 0.5A

WAVEFORMS IN

DESCENDING ORDER:

Test C ircuits and W aveforms

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PE AK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 2V

Qg(10)

VGS = 10V

Qg(TOT)

VGS = 20

VDS

VGS

g(REF)

HUFA75307T3ST

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJ(MAX), and the

thermal resistance of the heat dissipating path determines

the maxi mum allowable device power dissipation, PD(MAX),

in an application. Therefore the application’s ambient

temperature, TA (oC), and thermal resistance RθJA (oC/W)

must be re vie wed to ensure that TJ(MAX) is ne v er exce eded.

Equat ion 1 math em atically represents the rela tionship and

serves as the basis for estab l is hing the rating of the part.

In usin g surface mount devices such as the SOT-223

package, the environment in which it is applied will have a

signifi ca nt i nfl uen ce on the part’s current and m axi m u m

power dissipation ratings. Pr ecise determination of the

PD(MAX) is complex and influenced b y many factors:

1. Mounting pad area onto which the device is attached and

whet her there is coppe r on one side or both sides of the

board.

2. The number o f copp er la y e rs and the th ic knes s of t he

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non st eady state ap plication s, the pul se width, the

duty cy cle and the transien t thermal respons e of the part,

the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’ s preliminary application evaluation. Figure 20

defines the RθJA for the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board wi th 1oz co pper after 1000 seco nd s

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse applications

can be evaluated using the Fairchild device Spice thermal

model or manually utilizing the normalized maxi m um

tran si ent the rmal impeda nc e curve.

Displayed on the curve are the three RθJA values listed in

the Electrical Specifications table. The three poin ts were

chosen to depict the compromise between the copper board

area, the thermal resistance and ultimately the power

dissipation, PD(MAX). Th ermal re si stances correspondi ng to

other component side copper areas can be obtained from

Figure 20 or by calculation using Equation 2. The area, in

square inches is the top copper area including the gate and

source pad s .

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

Test C ircuits and W aveforms (Continued)

VGS

RGS DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

(EQ.

PDMAX()

TJMAX()

–()

RθJA

--------------------------------------------=

FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD

AREA

100

150

200

0.01 0.1 1.

147oC/W - 0.026 in2

RθJA = 75.9 -19.3 ln(AREA)

AREA, TOP COPPER AREA (in2)

RθJA (oC/W)

128oC/W - 0.068in2

110oC/W - 0.171 in2

(EQ.

RθJA 75.9 19.3 Area()ln×–=

HUFA75307T3ST

PSPICE Ele ctrical Model

.SUBCKT HU FA75307T3ST 2 1 3 ; rev 7/ 25/97

CA 12 8 3.5e -10

CB 15 14 3.7e-10

CIN 6 8 2.26e-10

DBODY 7 5 DBODYMOD

DBRE AK 5 11 DB REAK MOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 57.4

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTH R ES 6 21 19 8 1

EVTEMP 20 6 18 22 1

IT 8 17 1

LDRA IN 2 5 1e- 9

LGATE 1 9 1.4e-9

LSOURCE 3 7 3.1e-10

K1 LGATE LSOURCE 0.131

MMED 16 6 8 8 MMEDMOD

MSTRO 16 6 8 8 MSTROMOD

MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 7.0e-3

RGATE 9 20 1.9

RLDRAIN 2 5 10

RLGATE 1 9 14

RLSOURCE 3 7 3

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

RSOURCE 8 7 RSOURCEMOD 5.6e-2

RVTHRES 22 8 RVTHRESMOD 1

RVTE M P 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BMOD

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S2BMOD

VBAT 22 1 9 DC 1

ESL C 51 50 VALUE={(V(5,5 1)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))}

.MODEL DBOD YMOD D (IS = 2.6e -13 RS = 2.34e-2 IKF = 5.5 N = 0.9 95 TRS1 = 2.8e-3 TRS2 = 1.1e-5 CJO = 3.7e-10 TT = 3.5e-8 M = 0.46

+ XTI = 5.5)

.MODEL DBREAKMOD D (RS = 0. 5IKF = 0.1 N = 1 TRS1 = 3e- 3TRS2 = -5e-5)

.MODEL DPLCAPMOD D (CJO = 5.6e-1 0IS = 1e-3 0N = 10 M = 0.92)

.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.8 IS = 1e-30 N = 1 0 T OX = 1 L = 1u W = 1u RG = 1.9)

.MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19 RS = 0.1)

.MODEL RBREAK MOD R ES (TC1 = 1.08e - 3TC2 = 5e-7)

.MODEL RDRAINMOD RES (TC1 = 1.7e-2 TC2 = 1e-4)

.MODEL RSLCMOD RES (TC1 = 1e-9 TC2 = 1e-4)

.MODEL RSOURCEM OD RES (TC1 = 3.3e-3 TC2 = 1e-9)

.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4e-6)

.MODEL RVTEMPMO D RES (TC1 = -2.9e- 3TC2 = 2.2e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.1 VOFF= -4)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -7.1)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.01 VOFF= 1.9)

.MODEL S2BMOD VSWITCH (RON = 1 e-5 RO F F = 0.1 VON = 1.9 VOFF= 0.01)

.ENDS

NOTE: For further discussi on of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MO SFET Feat u ring Gl obal

Temperature Options; IEEE Power Electroni cs Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

HUFA75307T3ST

SPICE Thermal Model

REV 15 Nov 97

HUFA75307T3ST

CTHERM1 7 6 7 .5e-5

CTHERM2 6 5 3 .5e-4

CTHERM3 5 4 1 .2e-3

CTHERM4 4 3 1 .5e-2

CTHERM5 3 2 6 .9e-2

CTHERM6 2 1 4 .5e-1

RTHERM1 7 6 7 .5e-2

RTHERM2 6 5 2 .0e-1

RTHERM3 5 4 1.2

RTHERM4 4 3 3.3

RTHERM5 3 2 28

RTHERM6 2 1 90

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

7JUNCTION

CASE

HUFA75307T3ST

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Formative or

In Design

First Production

Full Production

Not In Production

OPTOLOGIC™

OPTOPLANAR™

PACMAN™

POP™

Power247™

PowerTrench

QFET™

QS™

QT Optoelectronics™

Quiet Series™

SILENT SWITCHER

FAST

FASTr™

FRFET™

GlobalOptoisolator™

GTO™

HiSeC™

ISOPLANAR™

LittleFET™

MicroFET™

MicroPak™

MICROWIRE™

Rev. H4



ACEx™

Bottomless™

CoolFET™

CROSSVOLT™

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

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