74HC/HCT4511 MSI BCD TO 7-SEGMENT LATCH/DECODER/DRIVER FEATURES Latch storage of BCD inputs @ Blanking input @ Lamp test input @ Driving common cathode LED disptays @ Guaranteed 10 mA drive capability per output Output capability: non-standard \c category: MSI GENERAL DESCRIPTION The 74HC/HCT4511 are high-speed Si-gate CMOS devices and are pin compatible with "4511" of the 40008 series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4511 are BCD to 7-segment latch/decoder/drivers with four address inputs (Dy to Oq), an active LOW latch enable input (LE), an active LOW rippie blanking input (BI), an active LOW lamp test input (LT}, and seven active HIGH segment outputs (Qg to Qg). When LE is LOW, the state of the segment outputs {Qg to Qg) is determined by the data on Dj to Dq. When LE goes HIGH, the last data present on Dy to Og are stored in the latches and the segment outputs remain stable. When LT is LOW, ail the segment outputs f TYPICAL | SYMBOL PARAMETER CONDITIONS UNIT i | Hc HCT i i propagation delay | | | DB, 0 24 24 ns | tPHL! Ze to Qn CL = 15 pF | 23 24 ns _'PLH Bi toQn Vee=8V jf 19 | 20 | ns | UT to Oy | 12 | 13 | ns t Cc input capacitance | 35) 3.5 pF i power dissipation | ceo capacitance per latch notes 1 and 2 64 | pF | GND =0 V; Tamb = 25 C; ty = te = 6 ns Notes 1. Cpp is used to determine the dynamic power dissipation (Pp in wW): Pp =Cpp x Vcc? x fi +5 (CL x VCC? x fo} where: fi = input frequency in MHz fo = output frequency in MHz Z (CL x Vec? x fg) = sum of outputs CL = vec 2. For HC the condition is Vj = GND to Vcc For HCT the condition is V| = GND to Vcc - 1.5 V PACKAGE OUTLINES SEE PACKAGE INFORMATION SECTION PIN DESCRIPTION output load capacitance in pF supply voltage in V are HIGH independent of all other input_ PIN NO. SYMBOL NAME AND FUNCTION conditions. With LT HIGH, a LOW on BI forces all segment outputs LOW. The 3 CT lamp test input {active LOW) inputs LT and 8! do not affect the latch 4 aT ripple blanking input (active LOW) 5 TE latch enable input (active LOW) APPLICATIONS 7,1, 2,6 Dy to Dg BCD address inputs @ Driving LED displays B GND ground (0 V) Driving incandescent displays 13,1211, 10 @ Driving fluorescent displays 9 15 ve "| Qa to Qg segments outputs Driving LCD displays a : itive iy valtage @ Driving gas discharge displays 16 Voc Positive Supply s U a1 acos7sEG > C Pe] vec ths wl 32] [is] 2 3 vittuT] =< a 152 bp 2 SJorote ata PE oG fi3] 9, 24d, o10.11 L2 ai[a | 3} 60, Og 10 SSI co 10.11 ph _ 4511 7 0 ce (5 | 12] Oy 34 a9 90.1 310,11 Rt o fe] ii] o, i arts 24 90,2 s10.11 LR . ea ha] 2 slie a,}-14 + op.4 #10,11 LAS ' 4 Tyaeea Si s08 tort PS ono (a | [3 ]% 7293604 7293692 Fig. 1 Pin configuration. Fig. 2 Lagic symbol. Fig. 3 1EC logic symbo}. December 1990 103774HC/HCT4511 MS! 7 1 2 6 Dy 9, [04 Oa LATCHES DRIVERS g [Fr [Qe [Ox (0, 1a |1S [9 [10 fat [12 413 7293805 Fig. 4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS DISPLAY TE] BF} TT) Og] Dg] D2] By] Qa | Qy ) Ag] Ag | Gy | Q, xX |X tL YX |X |X |X JH TH |H JH JH JH JH] 8 xX }L IH |X |X |X y_Rye Joe Pe Fu fe Fu |e | blank LT HH {Le ft {hk | H TH JH JH [H JHGL | O LJHIH | Pe Fe |H Je TH JH Poe |e Pe Yb} L}HJH |e PL JH PL |H FH |L JH | H TL JH | 2 L}JAH}JH |]. } Le JH JH JH JH JH PH Je Jk |H 43 L {HH | L | HPL Pe ye JH JH YL |e |H|H |] 4 L}HIH ft |H |} PH PH Tk JH JH | lk |AH YH] S L{}HJH PL YH JH PL | L JL |RH JH |H |H |H | 6 L |HJH}L YH JH TH} RYH TH FL Fe Jk yu) 7 CTH H |H | UPL YL |H TH JH TH [HH [TH /H |] 8 L |HJH}|H |L]L JH |H PH TH ITL TL JH THY] Y LJHIJH|H JTL] H Fe JL Ye Te Fe [kL YL | el | blank LyH/H |H |L PH FH FTL TE Fe fe Tue Je |e | blank L}HJH |H JH e PR Ye Pk Ju ye Fle |b | et | blank C}HIJR JH I]H JTL PH PR Fe Ge Fe Je TL | Ll | btank L}HIH | HHH PE Te Je ye |e |e Fu | Ll | blank L | H/}H}|H}H|H PH Jue _e Fe Pu Ju |e {el | blank H H|H |X |X ]X |x . . * Depends upon the BCD-code applied during the LOW-to-HIGH transition of CE. H = HIGH voltage level L = LOW voltage level X = don't care 1038 January 1986BCD to 7-segment latch/decoder/driver 74HC/HCT4511 Or a, Qy a, a, a 72793706 Fig. 5 Logic diagram. 7293266 Fig. 6 Segment designation. 7z22405 Fig. 7 Display. March 1988 103974HC/HCT4511 MSI DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard, excepting VQ} which is given beiow loc category: MSI Non-standard DC characteristics for 74HC Voltages are referenced to GND {ground = 0 V) T Tamb (C) TEST CONDITIONS 74HC SYMBOL PARAMETER UNIT | Veco | VI -lo | +25 40 to +85 | -40 to +125 Vv mA min. | typ. | max.| min. | max.) min. | max, VOH _ HIGH fevel output voltage 338 3ae 370 v 45 vid or oo 5.60 5.45 5.35 Vigor | 22 VOoH HIGH level output voltage | 5.48 5.34 5.20 v 6.0 yi 10.0 | 4.80 4.50 4.20 tL 15.0 AC CHARACTERISTICS FOR 74HC GND = OV; ty = ty = 6 ns; CL = 60 pF , Tamb (C) TEST CONDITIONS 76HC SYMBOL PARAMETER | UNIT | Voc | WAVEFORMS +25 | 40 to +85 | -40 to +125 iv | i min. | typ. | max. min. | max. | min. | max, | 7 | HL! ronan clay zim) fas) feo] oe, TPLH Dn to Qn 22! 51 | {ea | 7 6.0 | ; - | / 74127 LH | LE to. Qn 22:46 | 58 69 | 6.0 1 I | 61 | 22 TPHL/ + rgpagaiion delay 32 faa | os oe | ons | a8 Fig. 10 1PLH BI to : ' la . n 118, 37 | 47 | 56 ' 6.0 lar | | 'PHL/ propagation delay fis (a0) ge! fae | ns 148 | Fig t LT t0.Q |: see PLH n 12 | 26 33 | 38 6.0 : cru) | 119 75 95 110 | 2.0 wit i output transition time 7 15 19 22 ns | 4.5 | Figs 8,9 and 10 TLH 6 (13 16 19 6.0 , go 111 : 100 1120 2.0 | tw awe pulse width 16/4 20 24 ns 4.5 | Fig 9 14.13 ) Ws 20 6.0 | I : | ee a 60 | 14 75 $0 2.0 | tsu | O voce 12/5 15 18 ns; 45 | Fig. 11 | On 10 | 4 13 15 6.0 | o |-1 0 0 2.0 th | hold time_ 0 |-4 0 0 ns | 45 | Fig.11 __DntoLle 0 j-3 0 Q 6.0 1040 January 1986BCD to 7-segment latch/decoder/driver 74HC/HCT4511 MSI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard, excepting VQH which is given below (cc category: MSI Non-standard DC characteristics for 74HCT Voltages are referenced to GND (ground = 0 V) | Tamb (C) | TEST CONDITIONS | 74HCT | SYMBOL PARAMETER UNIT | Veco : Vi -lo +25 40 to +85 | 40 to +125 Vv mA | min. | typ. | max.) min. | max.| min, | max. | 3.98 | 3.84 3.70 vinor | 7.5 VOH | HIGH level output voltage |/ 3 6g 3.35 340 Vv 45 ViL 70.0 Note to HCT types The value of additional quiescent supply current (Alc) for a unit load of 1 is given in the family specifications. To determine Alec per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD INPUT COEFFICIENT LT, CE 1.50 Br, Dy 0.30 AC CHARACTERISTICS FOR 74HCT GND =O V; t, = t = 6 ns; Cy = 50 pF | Tamb (C) i | TEST CONDITIONS ' ' T ; | 74HCT | SYMBOL PARAMETER UNIT ; Vec | WAVEFORMS ! +25 40 to +85 | ~40 to +125 , Vv | i imin, | typ.| max. | min. | max. | min. | max. t = 1 A | tPHL/ propagation delay | | | Fa | tPLH Dp to On 28 60 | 75 | : 90 ; 45 | Fig. 8 | ; 1 tPHL/ propagation delay : i | : i le. tLH . TE t0Q, | 27 | 54 68 | 81 ns | 4.5 | Fig. 9 I { I | 1 , tPHLS propagation detay 23 | 44 55 -66 | ns 145 | Fig. 10 | tPLH Bl to Q, | | | ! i jo | : T t ; H . ' i | tPHL/ propagation delay | on | . -tPLH CT to Qn 16 | 30 38 | 45 ns 45 Fig. 8 | | } | | i , | rH output transition time (7145 19 | | 22 | ns . 4.5 | Figs 8,9 and 10 | ' ' ! i : . i : i tw a aoe pulsewidth Ng 5 | 20 24 ns 4.8 | Fig. 9 r set-up time i | : i | tsu | Dpto LE 12 5 15 18 ns 45 Fig, 11 i i | ! ! hold time _ ! : th + Dp to LE 0 4 0 0 ns | 45 | Fig. 11 January 1986 104174HC/HCT4511 MSI AC WAVEFORMS [ 0, CF INPUT CE iNpuT Q, OUTPUT Q, OUTPUT 7291699 7Z91697 Fig. 8 Waveforms showing the input (Dp, Fig. 9 Waveforms showing the input (CE} LT) to output (Q,_) propagation delays and to output (Q,) propagation delays and the the output transition times. latch enable pulse width. ai WNPUT D, (NPUT a, OUTPUT CE iweut 7293006 7293808 Fig. 10 Waveforms showing the input (Bi) Fig. 11 Waveforms showing the data set-up and to output (Qp_) propagation delays. hoid times for Dy input to LE input. Note to AC waveforms {1) HC : Vag = 50%; V) = GND to Voc. HCT: Vi = 1.3V; Vy =GND to 3 V. Note to Fig. 11 The shaded areas indicate when the input is permitted to change for predictable output performance. 1042 January 1986BCD to 7-segment latch/decoder/driver 74HC/HCT4511 MSI APPLICATION DIAGRAMS common cathode LED 7203705 Fig. 12 Connection to common cathode LED display readout. common anode 14 4 7293700 Fig. 13 Connection to common anode LED display readout. GNO 7z93701 (1) A filament pre-warm resistor to reduce thermal shock and to increase effective cold resistance of the filament is recommended. Fig. 14 Connection to incandescent display readout. direct {law arightness | 10 filament supply GNO 7293703 Fig. 15 Connection to fluorescent display readout. appropriate z OND 7293702 Fig. 16 Connection to gas discharge display readout. excitation (square wave ; | GNO to Veg! Yq HCs HCTEB 7293704 Fig. 17 Connection to LCD display readout. (Direct DC drive is not recommended as it can shorten the life of LCD dispiays). January 1986 1043