74F139SJ - Fairchild Semiconductor

April 1988

Revised September 2000

74F139 Dual 1-of-4 Decoder/Demultiplexer

74F139

Dual 1-of-4 Decoder/Demultiplexer

General Description

The F139 is a high-speed, dual 1-of-4 decoder/demulti-

plexer. The device has two independent decoders, each

accepting tw o inputs and pr oviding four m utually exclu sive

active LOW outputs. Each decoder has an active LOW

Enable input which can be used as a data input for a

4-output d emultiple xer. Each ha lf of the F139 can be used

as a function generator providing all four minterms of two

variables.

Features

■Multifunction capability

■Two completely independent 1-of-4 decoders

■Active LOW mutually exclusive outputs

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Truth Table

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Order Number Package Number Package Description

74F139SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

74F139SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F139PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

EA0A1O0O1O2O3

HXXHHHH

LLLLHHH

LHLHLHH

LLHHHLH

LHHHHHL

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74F139

Unit Loading/Fan Out

Functional Description

The F139 is a high-speed dual 1-of-4 decoder/demulti-

plexe r. The devic e has two indep enden t decoder s, each of

which accepts two binary weighted inputs (A0–A1) and pro-

vides four mutually exclusive active LOW Outputs (O0–O3).

Each decoder has an active LOW enable (E). When E is

HIGH al l out p ut s ar e f or c ed HIG H. Th e en a ble ca n be u s ed

as the data input for a 4-output demultiplexer application.

Each half of the F139 generates all four minterms of two

varia bles. The se fo ur mi nte rms are use ful i n so me a pplic a -

tions, replacing multiple gate functions as shown in

Figure 1, and thereby reducing the number of packages

required in a logic network.

FIGURE 1. Gate Functions (each half)

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagatio n delays.

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

A0, A1Address Inputs 1.0/1.0 20 µA/−0.6 mA

EEnable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA

O0–O3Outputs (A ctive LOW) 50/33. 3 −1 mA/20 mA

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74F139

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: Eith er v oltage lim it or c urrent limit is sufficie nt to protect inputs.

DC Electrical Characteristics

AC Electrical Characteristics

Storage Temperature −65°C to +150°C

Ambient Temper atu re und er Bia s −55°C to +125°C

Junction Temperature under Bias −55°C to +150°C

VCC Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 2) −0.5V to +7.0V

Input Current (Note 2) −30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State (with VCC = 0V)

Standard Output −0.5V to VCC

3 STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambient Temperature 0°C to +70°C

Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units VCC Conditions

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

VOH Output HIGH Voltage 10% VCC 2.5 VMin

IOH = −1 mA

5% VCC 2.7 IOH = −1 mA

VOL Output LOW Voltage 10% VCC 0.5 V Min IOL = 20 mA

IIH Input HIGH Current 5.0 µAMaxV

IN = 2.7 V

IBVI Input HIGH Current Breakdown Test 7.0 µAMaxV

IN = 7.0 V

ICEX Output HIGH Leakage Current 50 µAMaxV

OUT = VCC

VID Input Leakage Te st 4.75 V 0.0 IID = 1.9 µA

All Other Pins Grounded

IOD Output Leakage Circuit Current 3.75 µA0.0

VIOD = 150 mV

All Other Pins Grounded

IIL Input LOW Current −0.6 mA Max VIN = 0.5V

IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V

ICC Power Supply Current 13 20 mA Max

Symbol Parameter

TA = +25°CT

A = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

tPLH Propagation Delay 3.5 5.3 7.5 3.0 8.5 ns

tPHL A0 or A1 to On4.06.18.04.09.0

tPLH Propagation Delay 3.5 5.4 7.0 3.5 8.0 ns

tPHL E1 to On3.04.76.53.07.5

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74F139

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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74F139

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F139 Dual 1-of-4 Decoder/Demultiplexer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

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user.

2. A critical compon ent i n any compon ent of a lif e supp ort

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