CS4341-CZZ - Cirrus Logic, Inc. - Datasheet.Directory

http://www.cirrus.com

24-Bit, 96 kHz Stereo DAC with Volume Control

Features

!101 dB Dynamic Range

!-91 dB THD+N

!+3.0 V or +5.0 V Power Supply

!Low Clock-Jitter Sensitivity

!Filtered Line-Level Outputs

!On-Chip Digital De-Emphasis for 32, 44.1

and 48 kHz

!ATAPI Mixing

!Digital Volume Control with Soft Ramp

– 94 dB Attenuation

– 1 dB Step Size

– Zero Crossing Click-Free Transitions

!Popguard® Technology for Control of Clicks

and Pops

!33 mW with 3.0 V Supply

Description

The CS4341 is a complete stereo digital-to-analog sys-

tem including digital interpolation, fourth-order Delta-

Sigma digital-to-a nalog conversion, digital de-emphasis

and switched capacitor analog filtering. The advantages

of this architecture include: ideal differential linearity, no

distortion mechanisms due to resistor matching errors,

no linearity drift over time and temperature and a high

tolerance to clock jitter.

The CS4341 accepts data at audio sample rates from

4 kHz to 100 kHz, consumes very little power, and oper-

ates over a wide power supply range. The features of

the CS4341 are ideal for DVD players, CD players, set-

top box and automotive systems.

ORDERING INFORMATION

CS4341-K S 16-pin SOIC , -1 0 to 70 °C

CS4341-CZZ, Lead Free 16-pin TSSOP, -10 to 70 °C

CDB4341 Evaluation Board

Volume Contro lInterpolation Filter

∆Σ

DAC Anal og Filter

Control Port

Volume Contro lInterpolati on Fi lter Analog Filter

Serial Port

SCL/CCLK MUTECAD0/CS

AOUTA

AOUTB

RST

LRCK

SDATA

MCLK

SDA/CDIN

∆Σ

DAC

External

Mute Control

SCLK

Mixer

÷2

DECEMBER '05

DS298F5

CS4341

CS4341
2DS298F5
TABLE OF CONTENTS
 CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4
SPECIFIED OPERATING CONDITIONS.............................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................................4
ANALOG CHARACTERISTICS (CS4341-KS/CZZ)............................................................................... 5
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................................ 7
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................................ 10
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK..................................................... 11
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C®) ..................................... 12
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™) ................................... 13
DC ELECTRICAL CHARA CTERISTIC S.............. ... ... .... ... ... ... .................... ... ... ... .... ... ... ... ................... 14
DIGITAL INPUT CHARACTERISTICS................................................................................................ 14
DIGITAL INTERFACE SPECIFICATIONS........................................................................................... 14
 PIN DESCRIPTION  ............................................................................................................................. 15
 TYPICAL CONNECTION DIAGRAM   ................................................................................................. 16
 APPLICATIONS ................................................................................................................................... 17
1 Sample Rate Range/Operational Mode ........................................................................................ 17
2 System Clocking ........... ... ... ................... .................... ................... ... .................... ......................... 17
2.1 Internal Serial Clock Mode ...............................................................................................17
2.2 External Serial Clock Mode .............................................................................................. 18
3 Digital Interface Format ................................................................................................................. 18
4 De-Emphasis  ................ ... ... ... .... ... ... ... ... .................... ... ................... .... ... ................... ................... 19
5  Power-Up Sequence .... ... ... ................... .... ... ... ... .................... ... ... ... .................... ... ... ... ................ 19
6 Popguard® Transient Control ..... ... ... ................... .... ... ... ... .... ... ... ................... .... ... ... ... ... .... ............ 19
6.1 Power-Up ............... ................... .................................................... ................................... 19
6.2 Power-Down ........... ... .... ................... ................... .................... ... ................... ................... 20
6.3 Discharge Time ................... ... ... .... ... ................... .................... ................... ... ................... 20
7 Mute Control  .... ... ................... .................... ................... ... .................... ................... ...................... 20
8 Grounding and Power Supply Arrangements ............................................................................... 20
9 Control Port Interface .................................................................................................................... 20
9.1 Rise Time for Control Port Clock ...................................................................................... 21
9.2 Memory Address Pointer (MAP) ...................................................................................... 21
9.2a INCR (Auto Map Increment) .............................................................................. 21
9.2b MAP0-3 (Memory Address Pointer)  .................................................................. 21
9.3 I²C Mode  ... ... .... ................... ... .................... ................... ................... .... ............................ 21
9.3a I²C Write ............................................................................................................ 22
9.3b I²C Read ............................................................................................................ 22
9.4 SPI Mode  ..... .... ... ... ... .... ................... ................... .................... ... ................... ................... 23
9.4a SPI Write ........................................................................................................... 23
 REGISTER QUICK REFERENCE  ....................................................................................................... 24
 REGISTER DESCRIPTION  ................................................................................................................. 25
1 MCLK Control (address 00h)......... ... ... ... .... ... ... ... .... ................... ... .................... ... ... ...................... 25
2 Mode Control (address 01h)... .... ... ... ... ... .... ... ... ... .... ................... ... ... .... ... ... ... .... ............................ 25
3 Transition and Mixing Control (address 02h).................................................................................27
4 Channel A Volume Control (address 03h)..................................................................................... 29
5 Channel B Volume Control (address 04h)..................................................................................... 29
 PARAMETER DEFINITIONS ............................................................................................................... 31
 PACKAGE DIMENSIONS .................................................................................................................... 32

CS4341
DS298F5 3
8.1 SOIC ................ ... ... ... .... ... ... ................... .................................... ....................................................32
8.2 TSSOP  ......................................... ................................................... ..............................................33
9.  PACKAGE THERMAL RESISTANCE  .................................................................................................33
10.  REFERENCES ......... ... ... .... ... ... ... .... ................... ... .................... ... ... ................... .... ... ..........................34
11.  REVISION HISTORY ..........................................................................................................................34
LIST OF FIGURES
Figure 1. Output Test Load .........................................................................................................................6
Figure 2. Maximum Loading ........................................................................................................................6
Figure 3. Single-Speed Stopband Rejection ...............................................................................................8
Figure 4. Single-Speed Transition Band .....................................................................................................8
Figure 5. Single-Speed Transition Band (Detail) .........................................................................................8
Figure 6. Single-Speed Passband Ripple ...................................................................................................8
Figure 7. Double-Speed Stopband Rejection ..............................................................................................8
Figure 8. Double-Speed Transition Band ....................................................................................................8
Figure 9. Double-Speed Transition Band (Detail) .......................................................................................9
Figure 10. Double-Speed Passband Ripple ..................................................................................................9
Figure 11. Serial Input Timing (Ex ternal SCLK) ...................... ................... ... .................... ... ... ....................10
Figure 12. Internal Serial Mode Input Timing .......... ... ... ... .... ... ................... ... .... ... ... ................... .... .............11
Figure 13. Internal Serial Clock Generation ................................................................................................11
Figure 14. Control Port Timing - I²C Mode ..................................................................................................12
Figure 15. Control Port Timing - SPI Mode .................................................................................................13
Figure 16. Typical Connection Diagram ......................................................................................................16
Figure 17. CS4341 Formats 0-1 - I²S up to 24-Bit Data ..............................................................................18
Figure 18. CS4341 Format 2 - Left Justified up to 24-Bit Data ...................................................................18
Figure 19. CS4341 Formats 3-6 - Right Justified ........................................................................................18
Figure 20. De-Emphasis Curve ...................................................................................................................19
Figure 21. I²C Buffer Example .....................................................................................................................21
Figure 22. I²C Write .....................................................................................................................................22
Figure 23. I²C Read .....................................................................................................................................23
Figure 24. Control Port Timing, SPI Mode ..................................................................................................23
Figure 25. ATAPI Block Diagram ................................................................................................................29
LIST OF TABLES
Table 1. CS4341 Speed Modes.....................................................................................................................17
Table 2. Single-Speed Mode Standard Frequencies ....... ... .... ... ... ... .... ... ... ... ... .... ... ................... ... .... ... ... .......17
Table 3. Double-Speed Mode Standard Frequencies....................................................................................17
Table 4. Internal SCLK/LRCK Ratio...............................................................................................................18
Table 5. Digital Interface Format....................................................................................................................26
Table 6. ATAPI Decode.... ... ... ... .... ................... ... .................... ... ... ................... .... ... .......................................28
Table 7. Example Digital Volume Settings .....................................................................................................30

CS4341

4DS298F5

1. CHARACTERISTICS AND SPECIFICATIONS

(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.

Typical performance characteristics are derived from measurements taken at TA = 25°C.)

SPECIFIED OPERATING CONDITIONS (All voltages with respect to AGND = 0 V.)

ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation beyond

these limits may result in permanen t damage to the device. Normal operation is n ot guaranteed at these extremes.)

Notes: 1. Any pin except supplies.

Parameters Symbol Min Nom Max Units

DC Power Supply Nominal 3.3 V

Nominal 5.0 V VA

VA 2.7

4.75 3.3

5.0 3.6

5.5 V

Specified Operating Temperatur e -KS/CZZ

(Power Applied) TA-10 - +70 °C

Parameters Symbol Min Max Units

DC Power Supply VA -0.3 6.0 V

Input Current (Note 1) Iin -±10mA

Digital Input Voltage VIND -0.3 VA+0.4 V

Ambient Operating Temperature (power applied) TA-55 125 °C

Storage Temperature Tstg -65 150 °C

CS4341

DS298F5 5

ANALOG CHARACTERISTICS (CS4341-KS/CZZ) (Test conditions (unless otherwise specified): Input

test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL=10kΩ, CL

= 10 pF (see Figure 1).)

Parameter

VA = 5.0 V VA = 3.0 V

Min Typ Max Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range (Note 2)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

101

Total Harmonic Distortion + Noise (Note 2)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-91

-78

-38

-90

-72

-32

-86

-94

-74

-34

-91

-72

-32

-89

Double-Speed Mode Fs = 96 kHz

Dynamic Range (Note 2)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

101

Total Harmonic Distortion + Noise (Note 2)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-91

-78

-38

-90

-72

-32

-86

-94

-74

-34

-91

-72

-32

-89

CS4341

6DS298F5

ANALOG CHARACTERISTICS (CS4341-KS/CZZ) (Continued)

Notes: 2. One-half LSB of triangular PDF dither is added to data.

3. Refer to Figure 2.

Parameters Symbol Min Typ Max Units

Dynamic Performance for All Modes

Interchannel Isolation (1 kHz) - 100 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Drift - ±100 - ppm/°C

Analog Output Characteristics and Specifications

Full-Scale Output Voltage 0.6•VA 0.7•VA 0.8•VA Vpp

Output Impedance - 100 - Ω

Minimum AC-Load Resistance (Note 3) RL-3-kΩ

Maximum Load Capacitance (Note 3) CL- 100 - pF

AOUTx

AGND

3.3 µF

Vout

RLCL

Figure 1. Output Test Load

100

2.5

51015

Safe Operating

Region

Capaciti ve Load -- C (pF)

Resistive Load -- R (k

Ω

)

125

320

Figure 2. Maximum Loading

CS4341

DS298F5 7

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteris-

tics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the

desired sample rate by multiplying the given characteristic by Fs.)

Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.

For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

5. De-emphasis is only ava ilable in Single-Speed Mode.

Parameter Min Typ Max Unit

Single-Speed Mode - (4 kHz to 50 kHz sample rates)

Passband to -0.05 dB corner

to -3 dB corner 0

-0.4535

0.4998 Fs

Frequency Response 10 Hz to 20 kHz -0.02 - +0.08 dB

StopBand 0.5465 - - Fs

StopBand Attenuation (Note 4) 50 - - dB

Group Delay - 9/Fs - s

Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s

De-emphasis Error (Relative to 1 kHz) Fs = 32 kHz

(Note 5) Fs = 44.1 kHz

Fs = 48 kHz

+0.2/-0.1

+0.05/-0.14

+0/-0.22

Double-Speed Mode - (50 kHz to 100 kHz sample rates)

Passband to -0.1 dB corner

to -3 dB corner 0

-0.4621

0.4982 Fs

Frequency Resp onse 10 Hz to 20 kHz -0.06 - +0.2 dB

StopBand 0.577 - - Fs

StopBand Attenuation (Note 4) 55 - - dB

Group Delay - 4/Fs - s

Passband Group Delay Deviation 0 - 40 kHz

0 - 20 kHz -

-±1.39/Fs

±0.23/Fs -

-s

CS4341

8DS298F5

Figure 3. Single-Speed Stopband Rejection Figure 4. Single-Speed Transition Band

Figure 5. Single-Speed Transition Band (Detail) Figure 6. Single-Speed Passband Ripp le

Figure 7. Double-Speed Stopband Rejection Figure 8. Double-Speed Transition Band

CS4341

DS298F5 9

Figure 9. Double-Speed Transition Band (Detail) Figure 10. Double-Speed Passband Ripple

CS4341

10 DS298F5

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Parameters Symbol Min Max Units

MCLK Frequency 1.024 51.2 MHz

MCLK Duty Cycle 45 55 %

Input Sample Rate Single-Speed Mode

Double-Speed Mode Fs

Fs 4

50 50

100 kHz

kHz

LRCK Duty Cycle 40 60 %

SCLK Pulse Width Low tsclkl 20 - ns

SCLK Pulse Width High tsclkh 20 - ns

SCLK Frequency Single-Speed Mode

Double-Speed Mode -

-128xFs

64xFs Hz

SCLK rising to LRCK edge delay tslrd 20 - ns

SCLK rising to LRCK edge setup time tslrs 20 - ns

SDIN valid to SCLK rising setup time tsdlrs 20 - ns

SCLK rising to SDIN hold time tsdh 20 - ns

sclkh

slrs

slrd

sdlrs

tsdh

sclkl

SDATA

SCLK

LRCK

Figure 11. Serial Input Timing (External SCLK)

CS4341

DS298F5 11

SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK

Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.

7. See section 4.2.1 for derived internal frequencies.

Parameters Symbol Min Typ Max Units

MCLK Frequency 1.024 - 51.2 MHz

MCLK Duty Cycle 45 - 55 %

Input Sample Rate Single-Speed Mode

Double-Speed Mode Fs

Fs 4

50 -

-50

100 kHz

kHz

LRCK Duty Cycle (Note 6) %

SCLK Period (Note 7) tsclkw --s

SCLK rising to LRCK edge tsclkr --s

SDATA valid to SCLK rising setup time tsdlrs --ns

SCLK rising to SDATA hold time

MCLK / LRCK = 512, 256 or 128 tsdh --ns

SCLK rising to SDATA hold time

MCLK / LRCK = 384 or 192 tsdh --ns

SCLK

----------------

tsclkw

--------------

512()Fs

----------------------10+

512()Fs

----------------------15+

384()Fs

----------------------15+

SDATA

*INTERNAL SCLK

LRCK

sclkw

sdlrs

sdh

sclkr

Figure 12. Internal Serial Mode Input Timing

*The SCLK pulses shown are internal to the CS4341.

SDATA

LRCK

MCLK

*INTERNAL SCLK

Figure 13. Internal Serial Clock Generation

* The SCLK pulses shown are internal to the CS4341. N equals MCLK divided by SCLK

CS4341

12 DS298F5

SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C®)

Notes: 8. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

9. See “Rise Time for Control Port Clock” on page 21 for a recommended circuit to meet rise time

specification.

Parameter Symbol Min Max Unit

I²C Mode

SCL Clock Frequency fscl - 100 kHz

RST Rising Edge to Start tirs 500 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated S tart Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 8) thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise Time of SCL (Note 9) trc -25ns

Fall Time of SCL tfc -25ns

Rise Time SDA trd -1µs

Fall Time of SDA tfd -300ns

Setup Time for Stop Condition tsusp 4.7 - µs

buf thdst

hdst

low

hdd

thigh

sud

sust

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

irs

RST

Figure 14. Control Port Timing - I²C Mode

CS4341

DS298F5 13

SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™)

Notes: 10. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

11. Data must be held for sufficient time to bridg e th e tra n sitio n tim e of CCLK.

12. For fsclk < 1 MHz.

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency fsclk -6MHz

RST Rising Edge to CS Falling tsrs 500 - ns

CCLK Edge to CS Falling (Note 10) tspi 500 - ns

CS High Time Between Transmissions tcsh 1.0 - µs

CS Falling to CCLK Edge tcss 20 - ns

CCLK Low Time tscl -ns

CCLK High Time tsch -ns

CDIN to CCLK Rising Setup Time tdsu 40 - ns

CCLK Rising to DATA Hold Time (Note 11) tdh 15 - ns

Rise Time of CCLK and CDIN (Note 12) tr2 -100ns

Fall Time of CCLK and CDIN (Note 12) tf2 -100ns

MCLK

-----------------

MCLK

-----------------

tr2 tf2

tdsu t

sch

tscl

CCLK

CDIN

tcss t

csh

tspi

tsrs

RST

Figure 15. Control Port Timing - SPI Mode

CS4341

14 DS298F5

DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)

Notes: 13. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for

each speed mode, and open outputs, unless otherwise specified.

14. Power Down Mode is defined as RST = LO with all clocks and data lines held static.

15. Valid with the recommen ded capacito r values on FILT + and VQ as shown in Fig ure 16. In creasin g the

capacitance will also increase the PSRR.

DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)

DIGITAL INTERFACE SPECIFICATIONS (AGND = 0 V; all voltages with respect to AGND.)

Parameters Symbol Min Typ Max Units

Normal Operation (Note 13)

Power Supply Current VA = 5.0 V

VA = 3.0 V IA

-15

11 18

14 mA

Power Dissipation VA = 5.0 V

VA = 3.0 V -

-75

33 90

42 mW

Power-down Mode (Note 14)

Power Supply Current VA = 5.0 V

VA = 3.0 V IA-

-60

30 -

-µA

µA

Power Dissipation VA = 5.0 V

VA = 3.0 V -

-0.3

0.09 -

-mW

All Modes of Operation

Power Supply Rejection Ratio (Note 15) 1 kHz

60 Hz PSRR -

-60

40 -

-dB

VQ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

0.45•VA

250

0.01

kΩ

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

250

0.01

kΩ

MUTEC Low-Level Output Voltage - 0 - V

MUTEC High-Level Output Voltage - VA - V

Maximum MUTEC Drive Current - 3 - mA

Parameters Symbol Min Typ Max Units

Input Leakage Current Iin --±10µA

Input Capacitance - 8 - pF

Parameters Symbol Min Max Units

3.3 V Logic (3.0 V to 3.6 V DC Supply)

High-Level Input Voltage VIH 2.0 -V

Low-Level Input Voltage VIL -0.8V

5.0 V Logic (4.75 V to 5.25 V DC Supply)

High-Level Input Voltage VIH 2.0 - V

Low-Level Input Voltage VIL -0.8V

CS4341

DS298F5 15

2. PIN DESCRIPTION

Pin Name #Pin Description

RST 1Reset (Input) - Powers down device and resets registers to their default settings.

SDATA 2Serial Audio Data (Input) - Input for two’s complement serial audio data.

SCLK 3Serial Clock (Input) -Serial clock for the serial audio in terface.

LRCK 4Lef t Righ t Cloc k (Input) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

MCLK 5Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

SCL/CCLK 6Serial Control Port Clock (Input) - Serial clock for the control port interface.

SDA/CDIN 7Seria l Control Data I/O (Input/Output) - Input/Output for I²C da ta. Input for SPI data.

AD0/CS 8Address Bit / Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select

the chip in SPI mode.

FILT+ 9Positive Voltage Reference (Output) - Positive voltage reference for the internal

sampling circuits.

VQ 10 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.

REF_GND 11 Reference Ground (Input) - Ground reference for the internal sampling circuits.

AOUTB

AOUTA 12

15 Analog Outputs (Output) - The full-scale analog output level is specified in the

Analog Characteristics table.

AGND 13 Analog Ground (Input)

VA 14 Power (Input) - Positive power for the analog, digital, an d serial audio interface sections.

MUTEC 16 Mute Control (Output) - Control signal for an optional mute circuit.

152143134

161

116

107

125

RST MUTEC

SDATA AOUTA

SCLK VA

LRCK AGND

MCLK AOUTB

SCL/CCLK REF_GND

SDA/CDIN VQ

AD0/CS FILT+

CS4341

16 DS298F5

3. TYPICAL CONNECTION DIAGRAM

Serial Audio

Data

Processor

External Clock MCLK

AGND

AOUTB

CS4341

SDATA

LRCK

AOUTA

14 0.1 µF +1µF

+3 .0 V or + 5.0 V

3.3 µF

10 kΩC

560 Ω

Micro-Controlled

Configuration 8

SCLK

SCL/CCLK

SDA/CDIN

AD0/CS

RST

MUTEC 16 OPTIONAL

MUTE

CIRCUIT

1µF 0.1 µF

Audio

Output A

Audio

Output B

10 kΩ

.1 µF 1µF

REF_GND

FILT+

C= 4πFs(R 560)

R560

L+

Figure 16. Typical Connection Diag ram

CS4341

DS298F5 17

4. APPLICATIONS

4.1 Sample Rate Range/Operational Mode

The device operates in one of two operational modes determined by the Maste r Clock to Left/Right Clock

ratio (see section 4.2). Sample rates outside the specified range for each mode are not supported.

4.2 System Clocking

The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device

also requires external generation of the serial clock (SCLK) if the internal serial clock is not used. The

LRCK, defined also as the input sample rate Fs, must be synchronously derived from MCLK according to

specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates

and the required MCLK frequency, are illustrated in Tables 2 and 3.

*Requires MCLKDIV bit = 1 in the MCLK Control (address 00h) register.

4.2.1 Internal Serial Clock Mode

The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on

the SCLK pin for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and

synchronous with MCLK and LRCK. The SCL K/LRCK ratio is either 32 , 48, or 64 dep ending upon

the MCLK/LRCK ratio and the Digital Interface Format selection (see Table 4).

Operation in the Internal Serial Clock mode is identical to operation with an external SCLK syn-

chronized with LRCK; however, External SCLK mode is recommended for system clocking appli-

cations.

Input Sample Rate (Fs) MODE

4 kHz - 50 kHz Single-Speed Mo de

50 kHz - 100 kHz Double-Speed Mode

Table 1. CS4341 Speed Modes

Sample Rate

(kHz) MCLK (MHz)

256x 384x 512x 768x* 1024x*

32 8.1920 12.2880 16.3840 24.5760 32.768

44.1 11.2896 16.9344 22.5792 33.8688 45.1584

48 12.2880 18.4320 24.5760 36.8640 49.1520

Table 2. Single-Speed Mode Standard Frequencies

Sample Rate

(kHz) MCLK (MHz)

128x 192x 256x* 384x*

64 8.1920 12.2880 16.3840 24.5760

88.2 11.2896 16.9344 22.5792 33.8688

96 12.2880 18.4320 24.5760 36.8640

Table 3. Double-Speed Mode Standard Frequencies

CS4341

18 DS298F5

4.2.2 External Serial Clock Mode

The device will enter the External Serial Clock Mode whenever 16 low to high transitions are de-

tected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal

Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive pe-

riods of LRCK.

4.3 Digital Interface Format

The device will accept audio samples in several digital interface formats. The desired format is selected

via the DIF0, DIF1 and DIF2 bits in the Mode Con trol register (see section 6.2.2). For an illustration of the

required relationship between LRCK, SCLK and SDATA, see Figures 17 through 19.

Input Digital Interface Format Selection Internal

MCLK/LRCK

Ratio I2S up to 16 or

24 Bits Left Justified 24

Bits Right Justified

18, 20 or 24 Bits Right Justified

16 Bits SCLK/LRCK

Ratio

512, 256, 128 (Format 1) - - X 32

384, 192 XX X X48

512, 256, 128 (Format 0) X X - 64

Table 4. Internal SCLK/LRCK Ratio

LRCK

SCLK

Left Channel Right Channel

SDATA +3 +2 +1+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

LSB MSB LSB

Figure 17. CS4341 Formats 0-1 - I²S up to 24-Bit Data

LRCK

SCLK

Left Channel Right Channel

SDATA +3 +2 +1+5 +4

MSB-1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

LSB MSB LSB

Figure 18. CS4341 Format 2 - Left Justified up to 24-Bit Data

LRCK

SCLK

Left Channel

SDATA +6 +5 +4 +3 +2+1+7

-1 -2 -3 -4 -5

LSB

Right Channel

MSB LSB +6 +5 +4 +3 +2+1+7

-1 -2 -3 -4 -5

MSB LSB

Figure 19. CS4341 Formats 3-6 - Right Justified

CS4341

DS298F5 19

4.4 De-Emphasis

The device includes on-chip digital de-emphasis. The Mode Control (address 01h) bits select either the

32, 44.1 or 48 kHz de-emphasis filter. Figure 20 shows the de-emphasis curve for Fs equal to 44.1 kHz.

The frequency response of the de-emphasis curve will scale proportionally with changes in sample

rate, Fs. Please see section 6.2.3 for the desired de-emphasis control.

De-emphasis is only available in Single-Speed Mode.

4.5 Power-Up Sequence

1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the

appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default

settings and VQ will remain low.

2) Bring RST high. The device will remain in a low power state with VQ low.

3) Load the desired register settings while keeping the PDN bit set to 1.

4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when

the POR bit is set to 0. If the POR bit is set to 1, see section 4.6 for a complete description of power-

up timing.

4.6 Popguard® Transient Control

The CS4341 uses Popguard® technology to minimize the effects of output transients during power-up and

power-down. This technology, when used with external DC-blocking capacitors in series with the audio

outputs, minimizes the audio transient s commonly p roduced by single-ended single-su pply conve rters. It

is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside

from choosing the appropriate DC-blocking capacitors.

4.6.1 Power-Up

When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to

AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp to-

ward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and

audio output begins. This gradual voltag e ramping allows time for the external DC-blocking capac-

itors to charge to the quiescent voltage, minimizing the power-up transient.

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 20. De-Emphasis Curve

CS4341

20 DS298F5

4.6.2 Power-Down

To prevent transients at power-down, the device must first enter its po wer-down state by ena bling

RST or setting the PDN bit. When this occu rs, audio ou tput cea ses and the internal ou tput buffers

are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted

which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the

power to the device may be turned off and the system is ready for the next power-on.

4.6.3 Discharge Time

To prevent an audio t ransient at t he next power-on, it is n ecessary t o ensure that the DC-blocking

capacitors have fully discharged before turning on the power or exiting the power-down state. If

not, a transient will occur when the audio outputs are in itially clamped to AGND. The time that the

device must remain in the power-down state is related to the value of the DC-blocking capacitance.

For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately

0.4 seconds.

4.7 Mute Control

The Mute Control pin goes high during power-u p initialization, reset, mu ting (see section 6.2.1 and 6.5.1)

or if the MCLK to LRCK ratio is incorrect. This pin is intended to be used as a control for an external mute

circuit to prevent the clicks and pops that can occur in any single-ended single supply system.

Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute

minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system

designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute

circuit. See the CDB4341 data sheet for a suggested mute circuit.

4.8 Grounding and Power Supply Arrangements

As with any high resolution converter, the CS4341 requires careful atte ntion to power supply and ground-

ing arrangements if its potential performance is to be realized. Figure 16 shows the re commended power

arrangements, with VA connected to a clean supply. If the ground planes are split between digital groun d

and analog ground, REF_GND & AGND should be connected to the analog ground plane.

Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor

being the closest. To further minimize impedance, these capacitors should be located on the same layer

as the DAC.

All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted

coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µ F, must be

positioned to minimize the electrical path from FILT+ and REF_ GND (as well as VQ and REF_GND), and

should also be located on the same layer as the DAC. Th e CDB4341 evaluation b oard demon strates the

optimum layout and power supply arrangements.

4.9 Control Port Interface

The control port is used to load all the internal register settings (see section 6). The operation of the control

port may be completely asynchronous with the audio sample rate. However, to avoid potential interfer-

ence problems, the control port pins should remain static if no operation is required.

The control port operates in one of two modes: I²C or SPI.

Notes: MCLK must be applied during all I²C communication.

CS4341

DS298F5 21

4.9.1 Rise Time for Control Port Clock

When excess capacitive loading is present on the I²C clock line, pin 6 (SCL/CCLK) may not have

sufficient hysteresis to meet the standard I²C rise time spe cification. This prevents the use o f com-

mon I²C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt Trig-

ger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341. This will not affect the

operation of the I²C bus as pin 6 is an input only.

4.9.2 Memory Address Pointer (MAP)

The MAP byte precedes the contro l port regist er byte during a writ e operation and is not available

again until after a start condition is initiate d. During a read o peration the byte tran smitted after t he

ACK will contain the data of the register pointed to by the MAP (see section 4.9.3 for write/read

details).

4.9.2a INCR (Auto Map Increment)

The device has a MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP.

If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR

is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of suc-

cessive registers.

Default = ‘0’

0 - Disabled

1 - Enabled

4.9.2b MAP0-3 (Memory Address Pointer)

Default = ‘0000’

4.9.3 I²C Mode

In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by

the serial control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip

address (001000[AD0][R/W]) and should be tied to VA or AGND as required, before powering up

the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up,

SPI mode will be selected.

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

Pin 6

SCL

Figure 21. I²C Buffer Example

CS4341

22 DS298F5

4.9.3a I²C Write

To write to the device, follow the procedure below while adhering to the control port Switching

Specifications in section 6.

1) Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must

be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0.

The eighth bit of the address byte is the R/W bit.

2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP.

This byte points to the register to be written.

3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register point-

ed to by the MAP.

4) If the INCR bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired

registers are written, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to

repeat the procedure detailed from step 1. If no further writes to other registers are desired,

initiate a STOP condition to the bus.

4.9.3b I²C Read

To read from the device, follow the procedure below while adhering to the control port Switching

Specifications. During this operation it is first necessary to write to the device, specifying the ap-

propriate register through the MAP.

1) After writing to the MAP (see section 4.9.3a), initiate a repeated START condition to the I²C

bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must

match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte

is the R/W bit.

2) Signal the end of the address byte by not issuing an acknowledge. The device will then trans-

mit the contents of the reg ister pointed to by the MAP. The MAP will contain the address of the

last register written to the MAP.

3) If the INCR bit is set to 1, the device w ill continue to transmit the contents of successive reg-

isters. Continue providing a clock but do not issue an ACK on the bytes clocked out of the de-

vice. After all the desired registers are read, initiate a STOP condition to the bus.

4) If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary

to repeat the procedure detailed from step 1. If no further reads from other registers are de-

sired, initiate a STOP condition to the bus.

SDA

SCL

001000 AD0 W

Start

ACK MAP

1-8 ACK DATA

1-8 ACK

Stop

Figure 22. I²C Write

CS4341

DS298F5 23

4.9.4 SPI Mode

In SPI mode, data is clocked in to the serial control data line, CDIN, by the serial control port clock,

CCLK (see Figure 24 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip

select signal and is used to control SPI writes to the control port. When the device detects a high

to low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs

and data is clocked in on the rising edge of CCLK.

4.9.4a SPI Write

To write to the device, follow the procedure below while adhering to the control port Switching

Specifications in section 1.

1) Bring CS low.

2) The address byte on the CDIN pin must then be 00100000.

3) Write to the memory address pointer, MAP. This byte points to the register to be written.

4) Write the desired data to the register pointed to by the MAP.

5) If the INCR bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired

registers are written, then bring CS high.

6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary

to bring CS high, and repeat the procedure detailed from step 1. If no further writes to other

registers are desired, bring CS high.

SDA

SCL

001000 AD0 W

Start

ACK MAP

1-8 ACK 001000 AD0 R

Repeated START

Aborted WRITE

ACK Data 1-8

(pointed to by MAP) Data 1-8

(pointed to by MAP)

ACK

Stop

Figure 23. I²C Read

MAP

MSB

LSB

DATA

byte 1 byte n

R/W

MAP = Memo ry A ddress Point er

ADDRESS

CHIP

CDIN

CCLK

0010000

Figure 24. Control Port Timing, SPI Mode

CS4341

24 DS298F5

5. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

0h MCLK Control Reserved Reserved Reserved Reserved Reserved Reserved MCLKDIV Reserved

DEFAULT 00000000

1h Mode Control 2 AMUTE DIF2 DIF1 DIF0 DEM1 DEM1 POR PDN

DEFAULT 10000011

2h Transition and Mixing

Control A = B SCZ1 SCZ0 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

DEFAULT 00000000

3h Channel A Volume

Control MUTEA VOLA6 VOLA5 VOLA4 VOLA3 VOLA2 VOLA1 VOLA0

DEFAULT 00000000

4h Channel B Volume

Control MUTEB VOLB6 VOLB5 VOLB4 VOLB3 VOLB2 VOLB1 VOLB0

DEFAULT 00000000

CS4341

DS298F5 25

6. REGISTER DESCRIPTION

NOTE: All registers are read/write in I²C Mode and write only in SPI mode, unless otherwi se stated.

6.1 MCLK CONTROL (ADDRESS 00H)

6.1.1 MCLK DIVIDE-BY-2 (MCLKDIV) BIT 1

Default = 0

0 - Disabled

1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.

6.2 MODE CONTROL (ADDRESS 01H)

6.2.1 AUTO-MUTE (AMUTE) BIT 7

Default = 1

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio

samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting

is done independently for each channel. The quiescent voltage on the output will be retained and the

Mute Control pin will go active during the mute period. The muting function is affected, similar to vol-

ume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address

02h) register.

76543210

Reserved Reserved Reserved Reserved Reserved Reserved MCLKDIV Reserved

00000000

76543210

AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 POR PDN

10000011

CS4341
26 DS298F5
6.2.2  DIGITAL INTERFACE FORMAT (DIF) BIT 4-6 
Default = 000 - Format 0 (I²S, up to 24-bit data, 64 x Fs Internal SCLK)
Function:
The required relationship  between the Left/Right clock, serial clock and serial data is defined by the 
Digital Interface Format and the options ar e detailed in Figures 17 through 19.   
6.2.3  DE-EMPHASIS CONTROL (DEM) BIT 2-3 
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Implementation of the standar d 15µs/50µs digital d e-emphasis filter response, Figure 20,  requires re-
configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample 
rates. 
NOTE: De-emphasis is only available in Single-Speed Mode.
6.2.4  POPGUARD® TRANSIENT CONTROL (POR) BIT 1 
Default = 1
0 - Disabled
1 - Enabled
Function:
The Popguard® Transient Control allows the quiescent volta ge to sl owly ra mp to and fr om 0 volts to 
the quiescent voltage during power-on or  power-down. Please refer to section 4.6 for implementation 
details.
6.2.5  POWER DOWN (PDN) BIT 0 
Default = 1
0 - Disabled
1 - Enabled
Function:
The device will enter a low-power state when this function is enabled. The power-down bit defaults to 
‘enabled’ on  power- up and m ust be  disabled b efore normal op eration can occu r. The contents of the 
control registers are retained in this mode. 
DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE
0 0 0 I²S, up to 24-bit data, 64Fs Internal SCLK 0 17
0 0 1 I²S, up to 16-bit data, 32Fs Internal SCLK 1 17
0 1 0 Left Justi fi ed, up to  24-bit data, 2 18
0 1 1 Right Justified, 24-bit data 3 19
1 0 0 Right Justified, 20-bit data 4 19
1 0 1 Right Justified, 16-bit data 5 19
1 1 0 Right Justified, 18-bit data 6 19
1 1 1 Identical to Format 1 1 17
Table 5. Digital Interface Format

CS4341

DS298F5 27

6.3 TRANSITION AND MIXING CONTROL (ADDRESS 02H)

6.3.1 CHANNEL A VOLUME = CHANNEL B VOLUME (A = B) BIT 7

Default = 0

0 - Disabled

1 - Enabled

Function:

The AOUTA and AOUTB volume levels are independ ently controlled by the A an d the B Channel Vol-

ume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are de-

termined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function

is enabled.

6.3.2 SOFT RAMP AND ZERO CROSS CONTROL (SZCX) BIT 5-6

Default = 10

00 - Immediate Changes

01 - Changes On Zero Crossings

10 - Soft Ramped Changes

11 - Soft Ramped Changes On Zero Crossings

Function:

Immediate Ch an ge s

When Immediate Changes is selected all level changes will take effect immediately in one step.

Changes On Zero Crossings

Changes on Zero Cro ssings dictates that signal le vel changes, either by attenuation chan ges or mut-

ing, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will

occur after a timeout period between 512 and 1024 sample perio ds (10.7 ms to 21.3 ms at 48 kHz

sample rate) if the signal d oes not encounter a zero crossing. T he zero cross function is independen t-

ly monitored and implemented for each channel.

Soft Ramped Changes

Soft Ramped Changes allows level changes, both muting and attenuation, to be impl emented by in-

crementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8

left/right clock periods.

Soft Ramped Changes on Zero Crossings

Soft Ramped Changes On Zero Crossings dictates that signal level changes, either by attenuation

changes or muting, will occur in 1/8 dB steps implemented on a signal zero crossing. The 1/8 dB level

change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms

at 48 kHz sample rate) if the signal does not encounter a zero crossing. The ze ro cross function is

independently monitored and implemented for each channel.

76543210

A = B SZC1 SZC0 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

01001001

CS4341

28 DS298F5

6.3.3 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 0-4

Default = 01001 - AOUTA = Left Channel, AOUTB = Right Channel (Stereo)

Function:

The CS4341 implements the channel mixing functions of the ATAPI CD-ROM specificati on. Refer to

Table 6 and Figure 25 for additional information.

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB

00000 MUTE MUTE

00001 MUTE bR

00010 MUTE bL

00011 MUTE b[(L+R)/2]

00100 aR MUTE

00101 aR bR

00110 aR bL

00111 aR b[(L+R)/2]

01000 aL MUTE

01001 aL bR

01010 aL bL

01011 aL b[(L+R)/2]

0 1 1 0 0 a[(L+R)/2] MUTE

0 1 1 0 1 a[(L+R)/2] bR

0 1 1 1 0 a[(L+R)/2] bL

0 1 1 1 1 a[(L+R)/2] b[(L+R)/2]

10000 MUTE MUTE

10001 MUTE bR

10010 MUTE bL

10011 MUTE bL/2

10100 aR MUTE

10101 aR bR

10110 aR bL

10111 aR [(aR+bL)/2]

11000 aL MUTE

11001 aL bR

11010 aL bL

1 1 0 1 1 aL [(aL+bR)/2]

11100 aL/2 MUTE

1 1 1 0 1 [(aL+bR)/2] bR

1 1 1 1 0 [(bL+aR)/2] bL

1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2]

Table 6. ATAPI Decode

CS4341

DS298F5 29

6.4 CHANNEL A VOLUME CONTROL (ADDRESS 03H)

Same as CHANNEL B Volume Control.

6.5 CHANNEL B VOLUME CONTROL (ADDRESS 04H)

6.5.1 MUTE (MUTE) BIT 7

Default = 0

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output

will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero

Cross bits in the Transition and Mixing Control (address 02h) register. The MUTEC will go active dur-

ing the mute period if the Mute function is enabled for both channels.

76543210

MUTEx VOLx6 VOLx5 VOLx4 VOLx3 VOLx2 VOLx1 VOLx0

00000000

ΣΣ

A Channel

Volume

Control AoutA

AoutB

Left Channel

Audio Dat a

Right Channel

Audio Dat a

B Channel

Volume

Control

MUTE

Figure 25. ATAPI Block Diagram

CS4341

30 DS298F5

6.5.2 VOLUME (VOLx) BIT 0-6

Default = 0 dB (No Attenuation)

Function:

The digital volume co ntrol allows the user to attenuate the signal in 1 dB increments from 0 to -90 dB.

Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated

by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. All volume

settings less than - 94 dB are equivalent to enablin g the Mute bit.

Binary Code Decimal Value Volume Setting

0000000 0 0 dB

0010100 20 -20 dB

0101000 40 -40 dB

0111100 60 -6 0 dB

1011010 90 -90 dB

Table 7. Example Digital Volume Settings

CS4341

DS298F5 31

7. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms valu e of the signal to the rms sum of all other spectral components o ver the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full-sca le rms value of the signal to the rms sum of all othe r spectral components over the

specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth

made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement

to full scale. This technique ensures that the distortion components are below the noise level and do not

affect the measurement. This measurement technique has been accepted by the Audio Engineering

Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s

output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decib els.

Gain Error

The deviation from the nominal full-scale analog output for a full-scal e digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

CS4341

32 DS298F5

8. PACKAGE DIMENSIONS

8.1 SOIC

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A 0.053 0.064 0.069 1.35 1.63 1.75

A1 0.004 0.006 0.010 0.10 0.15 0.25

b 0.013 0.016 0.020 0.33 0.41 0.51

C 0.0075 0.008 0.010 0.19 0.20 0.25

D 0.386 0.390 0.394 9.80 9.91 10.00

E 0.150 0.154 0.157 3.80 3.90 4.00

e 0.040 0.050 0.060 1.02 1.27 1.52

H 0.228 0.236 0.244 5.80 6.0 6.20

L 0.016 0.025 0.050 0.40 0.64 1.27

∝0° 4° 8° 0° 4° 8°

JEDEC #: MS-012

Controling Dimension is Millimeters

16L SOIC (150 MIL BODY) PACKAGE DRAWING

∝

SEATING

PLANE

CS4341

DS298F5 33

8.2 TSSOP

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting li ne, mold flash or protrusions shall not exceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intr usion. Allowable dambar protrusion sh all be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not

reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

9. PACKAGE THERMAL RESISTANCE

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10

A1 0.002 0.004 0.006 0.05 -- 0.15

A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.193 0.1969 0.201 4.90 5.00 5.10 1

E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

∝0° 4° 8° 0° 4° 8°

JEDEC #: MO-153

Controlling Dimension is Millimeters

Package Symbol Min Typ Max Units

SOIC (for multi-layer boards)

TSSOP (for multi-layer boards) θJA

θJA

-74

89 -

-°C/Watt

°C/Watt

16L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

CS4341

34 DS298F5

10.REFERENCES

CDB4341 Evaluation Board Datasheet

11.REVISION HISTORY

Revision Changes

F4 Added lead-free packaging information

F5 Corrected Dimension e in TSSOP Package Drawing value for NOM Millimeters from 0.065 to 0.6 5

Contacting Cirrus Logic Support

For all product questions and inq uiries, contact a Cirrus Logic Sales Representative.

To find the one nearest to you, go to www.cirrus.com/corporate/contacts/sales.cfm

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