©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
Document No. 70-0165-03 www. psemi.com
RX1
RX2
RX3
RX4
TX1
TX2
CMOS
Control/Driver
and ESD
V1 V2 V3
Fig ur e 2. Pa ck ag e Typ e
20-lead 4x4 mm QFN
The PE4268 SP6T RF UltraCMOS™ Switch addresses the
specific design needs of the Quad-Band GSM Handset
Antenna Switch M odu le Mark et. Broadband per formance als o
makes it a versatile solution in other IF and RF applications.
The switch includes two high power paths with low insertion
loss and four low power paths with high isolation. On-chip
CMOS decod e logic facilitates three-pin low voltage CMOS
control. Hi g h ESD tol erance of 1500 V at all por ts an d no
blocking capacitor requirements make this the ultimate in
integration and ruggedness.
The PE4268 UltraCMOS™ RF Switch is manufactured in
Pe reg rine’s paten ted Ultra Thin Silicon (UTSi® ) CMOS
proc es s , off er i ng th e per formance of GaAs wit h the econ om y
and integration of conventional CMOS.
Pro duct Specification
SP6T UltraCMOS™ 2. 6 V Switch
100 – 3000 MHz
Product Description
Figure 1. Functional Diagram
PE4268
Features
• Three pin CMOS logic control with
integral decoder/driver
• Low TX insertion loss: 0.55 dB at 900
MHz, 0.7 dB at 1900 MHz
• TX – RX Isolation of 48 dB at 900 MHz,
40 dB at 1900 MHz
• Low har m o ni cs : 2fo = -84 dBc and
3fo = -70 dBc at +35 dBm input power
• 1500 V HBM ESD toleranc e
• RX SAW over voltage protection circuit
• Harmo nics immune to RX VSWR
• No blocking capacitors required
• 20-lead 4x4 mm QFN package
Product Specification
PE4268
Page 2 of 11
©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0165-03 UltraCM OS™ RFIC Solutions
Table 1. Electrical Specifications @ +25 °C, V DD = 2.6 V (ZS = ZL = 50 )
Parameter Condition Min Typ Max Unit
Operational Frequency 100 3000 MHz
Insertion Loss
ANT - TX - 850 / 900 MHz
AN T - TX - 1800 / 1900 MHz
ANT - RX - 850 / 900 MHz
ANT - RX - 1800 / 1900 MHz
0.6
0.8
0.9
1.1
0.75
0.95
1.15
1.35
dB
dB
dB
dB
Isolation
TX - RX - 850 / 900 MHz
TX - RX - 1800 / 1900 MHz
TX1 - TX2 - 850 / 900 MHz
TX1 - TX2 - 1800 / 1900 MHz
46
38
28
22
50
42
30
24
dB
dB
dB
dB
Return Loss 850 / 900 MHz
1800 / 19 00 MH z 17
15 20
18 dB
dB
2nd Harmonic1 35 dBm TX Input - 850 / 900 MHz
33 dBm TX Input - 1800 / 1900 MHz -84
-80 -78
-77 dBc
dBc
3rd Harmonic1 35 dBm TX Input - 850 / 900 MHz
33 dBm TX Input - 1800 / 1900 MHz -70
-66 -68
-63
IP3 RX Input 40 dBm
1dB Compression RX Input 20 dBm
Switching time (10-90%) (90-10%) RF 2 3 µs
dBc
dBc
Note : 1. Harm onics are characterized with a source that is 50 at the fundamental and reflective at the harmonics.
Contact Applications Support at help@psemi.com for more information.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Product Specification
PE4268
Page 3 of 11
Document No. 70-0165-03 www. psemi.com
Table 2 . Pin Descriptions
Table 4. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitiv e de vices . A lthou gh th is device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latc h-Up Avoidance
Unlike conven tional CMOS devices, Ultra CMOS™
devices are immune to latch-up.
Note 1: ANT port rated higher per applications section, see page 4.
Table 3. DC Electrical Specifications
Table 5. Truth Table
Pin No. Pin Name Description
11 TX1 RF I/O - TX1
2 GND Ground
31 TX2 RF I/O – TX2
4 GND Ground
5 GND Ground
6 VDD Supply
7 V3 Sw itch control input, CMOS logi c level
8 V2 Sw itch control input, CMOS logi c level
9 V1 Sw itch control input, CMOS logi c level
10 GND Ground
111 RX4 RF I/O - RX4
121 RX3 RF I/O - RX3
13 GND Ground
141 RX2 RF I/O - RX2
151 RX1 RF I/O - RX1
16 GND Ground
17 GND Ground
18 GND Ground
191 ANT RF Common – Antenna Input
20 GND Ground
Note 1: Blocking capacitors needed only when connected to an
external non-zero DC voltage.
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any input -0.3 VDD+
0.3 V
TST Storage temperature range -65 +150 °C
TOP Operating temperature range -40 +85 °C
PIN TX input power (50 ) +38 dBm
RX input power (50 ) +23
VESD1
ESD Voltage (HBM,
MI L_S T D 883 Met h od
3015.7) 1500 V
ESD Vol tage (MM, JEDEC,
JESD22-A114-B) 100 V
ESD Voltage (CDM, JEDE C,
JESD22-C101-A) 2000 V
Parameter Min Typ Max Units
VDD Su pp ly Volt a g e 2.4 2.6 2.8 V
IDD Power Supply Curre nt
(VDD = 2.6V ) 13 20 µA
Control Voltage High 0.7 x VDD V
Control Voltage Low 0.3 x VDD V
Path V3 V2 V1
ANT – RX1 0 0 0
ANT – RX2 0 0 1
ANT – RX3 0 1 0
ANT – RX4 0 1 1
ANT - TX1 1 0 x
ANT - TX2 1 1 x
Figure 3. Pin Configuration (Top View)
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause per manent de vice damage.
Functional operation should be restricted to the
limits in the DC Ele c t rical Specifications table.
Exposure to absolute max i mum ratings for
exten de d perio ds may affect device reliability.
V
DD
V3
V2
V1
GND
1
20
19
18
17
16
15
14
13
12
11
6
7
8
9
10
2
3
4
5
TX1
GND
TX2
GND
GND RX4
RX3
GND
RX2
RX1
GND
GND
GND
ANT
GND
20-lead QFN
4x4mm
Exposed Solder Pad
Product Specification
PE4268
Page 4 of 11
©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0165-03 UltraCM OS™ RFIC Solutions
Evaluation Kit
The SP6T Evaluation Kit board was designed to
ease customer evaluation of the PE4268 RF switch.
The PE4268 has two high power TX ports and four
high isolation RX ports. The TX ports are symmetric
and are designed as paths for the 850, 900, 1800, or
1900 MHz bands. The RX ports are also symmetric
and can be assigned to any of these frequency
bands.
The ANT port connects through a 50 transmission
line to the top SMA connector, J1. The RX and TX
ports connect through 50 transmission lines to
SMA connectors J2 – J7. A through 50
transmission line between SMA connectors J9 and
J10 allows estimation of the PCB losses over
environmental conditions. An open transmission line
connected to J11 is also provided.
J8 supplies DC power to the pin marked VDD and the
bottom row of pins, which is GND. 1 M pull-up
resistors are connected from VDD to each of the three
control logic inputs: V1, V2, and V3. These pull-up
resistors are provided for ease of evaluation on this
board and are not required for the PE4268 to
operate.
Adding a jumper between a control pin and the
adjacent GND pin on th e bottom row of J8 will set a
logic-0 on that control pin. Re moving th e jumper will
set a logic-1. To evaluate the PE4268, add or
remove jumpers according to the truth table in
Table 5.
Figure 4. Evaluation Board Layout
ANT RX1
RX2
RX3
RX4
TX1
TX2
Open Line
Through-Line
Figure 5. Evaluation Board Schematic
Peregr ine S pec ification 101/ 0205
Peregr ine S pec ification 102/ 0267
©2005 Peregrine Semiconductor Corp. All rights reserved.
Product Specification
PE4268
Page 5 of 11
Document No. 70-0165-03 www. psemi.com
-90
-70
-50
-30
-10
0 1000 2000 3000 4000
Frequency (MHz)
Insertion Loss (dB)
TX1-TX2
TX1-RX4
TX2-RX4
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0 1000 2000 3000 4000
Frequency (MHz)
Insertion Loss (dB)
RX1
RX2
RX3
RX4
TX1
TX2
-2.5
-2
-1.5
-1
-0.5
0
0 1000 2000 3000 4000
Frequency (MHz)
Insertion Loss (dB)
2.4 V
2.6 V
2.8 V
-2.5
-2
-1.5
-1
-0.5
0
0 1000 2000 3000 4000
Frequency (MHz)
Insertion Loss (dB)
-40°C
+25°C
+85°C
Typical Performan ce D ata @ VDD = 2.6 V, 25 °C (Unless otherwise noted)
Figure 7. Insertion Loss: TX Over VDD
Figure 9. Isolation: Worst Case Paths Figure 8. Insertion Loss: TX Over Temp
Figure 6. Insertion Loss: All Ports
Product Specification
PE4268
Page 6 of 11
©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0165-03 UltraCM OS™ RFIC Solutions
-75
-65
-55
-45
-35
-25
28 30 32 34 36 38
Input Power (dBm)
Harmonic Output Power (dBm)
-40°C 2fo
+25°C 2fo
+85°C 2fo
-40°C 3fo
+25°C 3fo
+85°C 3fo
-65
-55
-45
-35
-25
28 30 32 34 36 38
Input Power (dBm)
Harmonic Output Power (dBm)
2.4 V 2fo
2.6 V 2fo
2.8 V 2fo
2.4 V 3fo
2.6 V 3fo
2.8 V 3fo
-75
-65
-55
-45
-35
-25
28 30 32 34 36 38
Input Power (dBm)
Harmonic Output Power (dBm)
2.4 V 2fo
2.6 V 2fo
2.8 V 2fo
2.4 V 3fo
2.6 V 3fo
2.8 V 3 fo
-40
-30
-20
-10
0
0 1000 2000 3000 4000
Frequency (MHz)
Return Loss (dB)
ANT, RX1
RX1
TX1
Typical Performan ce D ata @ VDD = 2.6 V, 25 °C (Unless otherwise noted)°
Figure 11. TX Harmonics 915 MHz
Figure 13. TX Harmonics 1900MHz Figure 12. TX Harmonics 915 MHz
Figure 10. Return Loss: Worse Case Paths Over VDD
Over VDD Over Temp
©2005 Peregrine Semiconductor Corp. All rights reserved.
Product Specification
PE4268
Page 7 of 11
Document No. 70-0165-03 www. psemi.com
-65
-55
-45
-35
-25
28 30 32 34 36 38
Input Power (dBm)
Harmonic Output Power (dBm)
-40°C 2fo
+2 5°C 2 f o
+8 5°C 2 f o
-40°C 3fo
+2 5°C 3 f o
+8 5°C 3 f o
Typical Performan ce D ata @ VDD = 2.6 V, 25 °C (Unless otherwise noted)
Figure 14. TX Harmonics 1900MHz
Over Temp
Product Specification
PE4268
Page 8 of 11
©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0165-03 UltraCM OS™ RFIC Solutions
Figure 15. Package Drawing (mm)
1.00
1.00
2.00
2.00
0.23
0.10 C A B
EXPOSED PAD
4.00
DETAIL A
16
15
115
1
6
20
10
0.50
TYP
2.00
TYP
0.55
2
1
DETAIL A
0.18
0.18
0.435
0.435
SEATING
PLANE
0.08 C
0.10 C
0.020
0.20 REF
EXPOSED PAD &
TERMINAL PADS
0.80
- C -
2.00 X 2.00
2.00
2.00
4.00
4.00
- B -
- A -
INDEX AREA
0.25 C
2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL
1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED
AS THE TERMINALS.
BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP.
20-lead 4x4 mm QFN
©2005 Peregrine Semiconductor Corp. All rights reserved.
Product Specification
PE4268
Page 9 of 11
Document No. 70-0165-03 www. psemi.com
Figure 16. Marking Specification
Figure 17. Tape and Reel Drawing
4268
YYWW
ZZZZZ
YYWW = Date Code (Year, Work Week)
ZZZZZ = Last five digits of PSC Lot Number
Product Specification
PE4268
Page 10 of 11
©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0165-03 UltraCM OS™ RFIC Solutions
Table 7. Ordering Information
ES D Protection Circuit
Handset products must tolerate large ESD surges
at the an tenna interface without damage. The IEC
61000-4-2 standard specifies both 8 kV contact
and 16 kV air discharges that typical handsets
must survive. By itself, the PE4268 offers
protection to 1.5 kV but with the addition of two
inexpensive passive components, the switch can
meet the levels as specified in the IEC spec.
Figure 18 is the suggested solution for compliance
with the IEC standards.
Figure 18. ESD Protecti on Circuit
Table 6 . PE4268 Antenna Application Test Results
(C=150 pF, R=330 Ω, IEC 61000-4-2 Standard)
L = 27 nH (muRata: LQG1127NJ00),
C = 33 pF (muRata: GRM33C0G330J50)
Test Condition Results
+8 kV contact discharge, 10 times with 1s intervals Pass
-8 kV contact discharge, 10 times with 1s intervals Pass
+16 kV air discharge, 10 times with 1s intervals Pass
-16 kV air discharge, 10 times with 1s intervals Pass
Order Co de Part Mar ki ng Description Packa ge Shipping Method
4268-01 42 68 PE4 268-2 0Q FN 4x4m m- 7 5A 20- le ad 4x 4 m m QFN 75 units / Tu be
4268-02 42 68 PE 4 26 8- 2 0Q FN 4x 4 m m-3000C 20- le ad 4x 4 m m QFN 30 00 un it s / T&R
4268-00 PE4268-EK PE4268-20QFN 4x4mm-EK Evaluation Kit 1 / Box
4268-51 4268 PE4268G-20QFN 4x4mm-75A Green 20-lead 4x4mm QFN 75 units / Tube
4268-52 4268 PE4268G-20QFN 4x4mm-3000C Green 20-lead 4x4mm QFN 3000 units / T&R
PE4268
ESD Protection
©2005 Peregrine Semiconductor Corp. All rights reserved.
Product Specification
PE4268
Page 11 of 11
Document No. 70-0165-03 www. psemi.com
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Tel: +82-31-728-4300
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Tel: +33-1-47-41-91-73
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For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design st age. The data
sheet contains design target specificat ions for product
development. Specif ications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains pr eliminary data. Additional data
may be added at a later date. Peregrine reserves t he right
to change specifications at any time without notice in order
to supply t he best possible product.
Product Specification
The data sheet contains final data . In the event Peregrine
dec ide s to cha nge the spe c ific a tions, Peregr in e will notify
cust omers of the intended changes by iss u ing a DCN
(Document Change Not ice).
The information in this data sheet is believed t o be reliable.
Howeve r, Pere grin e assume s no liabilit y for t he use of this
information. Use shall be entirely at the user ’s own risk.
No patent rights or licenses to any circuits descr ibed in t his
data sheet are implied or granted to any third party.
Peregrine’s pr oducts are not designed or int ended for use in
devices or systems intended for surgical implant, or in other
applications intended t o support or sustain life, or in any
application in which the failure of t he Per egrine product could
create a situation in which personal injury or death m ight occur.
Peregr ine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregr ine nam e, logo, and UTSi are registered t r ademarks
and UltraCMOS and HaRP are tr ademarks of Peregrine
Semiconductor Cor p.
South As ia Pa cific
Peregrine Semiconductor, China
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
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