MK22FN256VLL12 - NXP SEMICONDUCTORS

Kinetis K22F 256 KB Flash

120 MHz ARM® Cortex®-M4-Based Microcontroller with FPU

The Kinetis K22 product family members are optimized for cost-

sensitive applications requiring low-power, USB connectivity,

high peripheral integration and processing efficiency with floating

point unit. These devices share the comprehensive enablement

and scalability of the Kinetis family.

This product offers:

• Run power consumption down to 153 µA/MHz and static

power consumption down to 2.6 µA with full state retention

and 6 µs wakeup. Lowest static mode down to 120 nA

• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO

voltage regulator. USB FS device crystal-less functionality.

Performance

• 120 MHz ARM Cortex-M4 core with DSP instructions

delivering 1.25 Dhrystone MIPS per MHz

Memories and memory interfaces

• 256 KB of embedded flash and 48 KB of RAM

• Serial programming interface (EzPort)

• Preprogrammed Kinetis flashloader for one-time, in-

system factory programming

System peripherals

• Flexible low-power modes, multiple wake up sources

• 16-channel DMA controller

• Independent external and software watchdog monitor

Clocks

• Two crystal oscillators: 32 kHz (RTC) and 32-40 kHz or

3-32 MHz

• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz

• Multi-purpose clock generator with PLL and FLL

Security and integrity modules

• Hardware CRC module

• 128-bit unique identification (ID) number per chip

• Hardware random-number generator

• Flash access control to protect proprietary software

Human-machine interface

• Up to 70 general-purpose I/O (GPIO)

Analog modules

• Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode)

• One 12-bit DAC

• Two analog comparators (CMP) with 6- bit DAC

• Accurate internal voltage reference

Communication interfaces

• USB LS/FS OTG 2.0 with on-chip transceiver and

USB LDO voltage regulator

• USB full-speed device crystal-less operation

• Two SPI modules

• Three UART modules and one low-power UART

• Two I2C modules: Support for up to 1 Mbps

operation

• I2S module

Timers

• One 8-channel general purpose/ PWM timer

• Two 2-channel general purpose timers with

quadrature decoder functionality

• Periodic interrupt timers

• 16-bit low-power timer

• Real-time clock with independent power domain

• Programmable delay block

Operating Characteristics

• Voltage range (including flash writes): 1.71 to 3.6 V

• Temperature range (ambient): -40 to 105°C

MK22FN256VDC12

MK22FN256VLL12

MK22FN256VMP12

MK22FN256VLH12

121 XFBGA (DC)

8 x 8 x 0.5 Pitch 0.65

100 LQFP (LL)

14 x 14 x 1.4 Pitch 0.5

64 MAPBGA (MP)

5 x 5 x 1.2 Pitch 0.5

64 LQFP (LH)

10 x 10 x 1.4 Pitch 0.5

NXP Semiconductors K22P121M120SF8

Data Sheet: Technical Data Rev. 7, 08/2016

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Ordering Information

Part Number Memory Number of GPIOs

Flash (KB) SRAM (KB)

MK22FN256VDC12 256 48 70

MK22FN256VLL12 256 48 66

MK22FN256VMP12 256 48 40

MK22FN256VLH12 256 48 40

Device Revision Number

Device Mask Set Number SIM_SDID[REVID] JTAG ID Register[PRN]

0N51M 0001 0001

Related Resources

Type Description Resource

Selector

Guide

The NXP Solution Advisor is a web-based tool that features interactive

application wizards and a dynamic product selector

KINETISKMCUSELGD

Product Brief The Product Brief contains concise overview/summary information to

enable quick evaluation of a device for design suitability.

K22FPB

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

K22P121M120SF8RM

Data Sheet The Data Sheet is this document. It includes electrical characteristics

and signal connections.

K22P121M120SF8

Chip Errata The chip mask set Errata provides additional or corrective information for

a particular device mask set.

KINETIS_K_xN51M 1

Package

drawing

Package dimensions are provided by part number:

• MK22FN256VDC12

• MK22FN256VLL12

• MK22FN256VMP12

• MK22FN256VLH12

Package drawing:

•98ASA00595D

•98ASS23308W

•98ASA00420D

•98ASS23234W

1. To find the associated resource, go to nxp.com and perform a search using this term with the x replaced by the revision

of the device you are using.

Figure 1 shows the functional modules in the chip.

2Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

Memories and Memory Interfaces

Program

(256 KB)

RAM

CRC

Programmable

Analog Timers Communication InterfacesSecurity

and Integrity

Clocks

Frequency-

Core

Debug

interfaces DSP

Interrupt

controller

Comparator

16-bit

timer

Human-Machine

Interface (HMI)

Up to

System

DMA (16ch)

Low-leakage

wakeup locked loop

Serial

programming

interface

(EzPort)

reference

Internal

clocks

delay block

timers

interrupt

Periodic

real-time

Independent

clock

oscillators

Low/high

frequency

UART

Cortex™-M4ARM

FPU

voltage ref

Phase-

locked loop

USB voltage

regulator

USB OTG

LS/FS

USB LS/FS

transceiver

Timers

x1 (8ch)

ADC x2

SPI

LPUART

High

performance low-power

70 GPIOs

(48 KB)

flash

Internal

watchdogs

and external

with 6-bit DAC

12-bit DAC

x2 (2ch)

16-bit

Random-

number

generator

Flash access

control

Figure 1. Functional block diagram

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NXP Semiconductors

Table of Contents

1 Ratings....................................................................................5

1.1 Thermal handling ratings................................................. 5

1.2 Moisture handling ratings................................................ 5

1.3 ESD handling ratings.......................................................5

1.4 Voltage and current operating ratings............................. 5

2 General................................................................................... 6

2.1 AC electrical characteristics.............................................6

2.2 Nonswitching electrical specifications..............................6

2.2.1 Voltage and current operating requirements....... 6

2.2.2 LVD and POR operating requirements................7

2.2.3 Voltage and current operating behaviors.............8

2.2.4 Power mode transition operating behaviors........ 9

2.2.5 Power consumption operating behaviors............ 10

2.2.6 EMC radiated emissions operating behaviors.....17

2.2.7 Designing with radiated emissions in mind..........18

2.2.8 Capacitance attributes.........................................18

2.3 Switching specifications...................................................18

2.3.1 Device clock specifications..................................18

2.3.2 General switching specifications......................... 19

2.4 Thermal specifications.....................................................20

2.4.1 Thermal operating requirements......................... 20

2.4.2 Thermal attributes................................................20

3 Peripheral operating requirements and behaviors.................. 21

3.1 Core modules.................................................................. 21

3.1.1 SWD electricals .................................................. 21

3.1.2 JTAG electricals.................................................. 22

3.2 System modules.............................................................. 25

3.3 Clock modules................................................................. 25

3.3.1 MCG specifications..............................................25

3.3.2 IRC48M specifications.........................................28

3.3.3 Oscillator electrical specifications........................28

3.3.4 32 kHz oscillator electrical characteristics...........31

3.4 Memories and memory interfaces................................... 31

3.4.1 Flash electrical specifications..............................31

3.4.2 EzPort switching specifications........................... 33

3.5 Security and integrity modules........................................ 34

3.6 Analog............................................................................. 34

3.6.1 ADC electrical specifications............................... 34

3.6.2 CMP and 6-bit DAC electrical specifications....... 38

3.6.3 12-bit DAC electrical characteristics....................41

3.6.4 Voltage reference electrical specifications.......... 44

3.7 Timers..............................................................................45

3.8 Communication interfaces............................................... 45

3.8.1 USB electrical specifications............................... 46

3.8.2 USB VREG electrical specifications.................... 46

3.8.3 DSPI switching specifications (limited voltage

range).................................................................. 47

3.8.4 DSPI switching specifications (full voltage

range).................................................................. 49

3.8.5 Inter-Integrated Circuit Interface (I2C) timing...... 50

3.8.6 UART switching specifications............................ 52

3.8.7 I2S/SAI switching specifications..........................52

4 Dimensions............................................................................. 58

4.1 Obtaining package dimensions....................................... 58

5 Pinout......................................................................................59

5.1 K22F Signal Multiplexing and Pin Assignments.............. 59

5.2 Recommended connection for unused analog and

digital pins........................................................................64

5.3 K22F Pinouts................................................................... 65

6 Part identification.....................................................................69

6.1 Description.......................................................................69

6.2 Format............................................................................. 69

6.3 Fields............................................................................... 70

6.4 Example...........................................................................70

6.5 121-pin XFBGA part marking.......................................... 71

6.6 64-pin MAPBGA part marking......................................... 71

7 Terminology and guidelines.................................................... 71

7.1 Definitions........................................................................71

7.2 Examples.........................................................................72

7.3 Typical-value conditions.................................................. 72

7.4 Relationship between ratings and operating

requirements....................................................................73

7.5 Guidelines for ratings and operating requirements..........73

8 Revision History...................................................................... 73

4Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

1 Ratings

1.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes

TSTG Storage temperature –55 150 °C 1

TSDR Solder temperature, lead-free — 260 °C 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes

MSL Moisture sensitivity level — 3 — 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes

VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1

VCDM Electrostatic discharge voltage, charged-device

model

-500 +500 V 2

ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Ratings

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Symbol Description Min. Max. Unit

VDD Digital supply voltage –0.3 3.8 V

IDD Digital supply current — 158 mA

VDIO Digital input voltage –0.3 VDD + 0.3 V

VAIO Analog1–0.3 VDD + 0.3 V

IDMaximum current single pin limit (applies to all digital pins) –25 25 mA

VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V

VUSB0_DP USB0_DP input voltage –0.3 3.63 V

VUSB0_DM USB0_DM input voltage –0.3 3.63 V

VREGIN USB regulator input –0.3 6.0 V

VBAT RTC battery supply voltage –0.3 3.8 V

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2 General

2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

80%

20%

50%

VIL

Input Signal

VIH

Fall Time

High

Low

Rise Time

Midpoint1

The midpoint is VIL + (VIH - VIL) / 2

Figure 2. Input signal measurement reference

2.2 Nonswitching electrical specifications

General

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2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol Description Min. Max. Unit Notes

VDD Supply voltage 1.71 3.6 V

VDDA Analog supply voltage 1.71 3.6 V

VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V

VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V

VBAT RTC battery supply voltage 1.71 3.6 V

VIH Input high voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.7 V ≤ VDD ≤ 2.7 V

0.7 × VDD

0.75 × VDD

—

VIL Input low voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.7 V ≤ VDD ≤ 2.7 V

—

0.35 × VDD

0.3 × VDD

VHYS Input hysteresis 0.06 × VDD — V

IICIO Analog and I/O pin DC injection current — single pin

• VIN < VSS-0.3V (Negative current injection) -3 — mA

IICcont Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents or sum of

positive injection currents of 16 contiguous pins

• Negative current injection -25 — mA

VODPU Open drain pullup voltage level VDD VDD V2

VRAM VDD voltage required to retain RAM 1.2 — V

VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V

1. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or

greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is

calculated as R=(VIO_MIN-VIN)/|IICIO|.

2. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 2. VDD supply LVD and POR operating requirements

Symbol Description Min. Typ. Max. Unit Notes

VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V

VLVDH Falling low-voltage detect threshold — high

range (LVDV=01)

2.48 2.56 2.64 V

VLVW1H

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV=00)

2.62

2.70

2.78

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Table 2. VDD supply LVD and POR operating requirements (continued)

Symbol Description Min. Typ. Max. Unit Notes

VLVW2H

VLVW3H

VLVW4H

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

2.72

2.82

2.92

2.80

2.90

3.00

2.88

2.98

3.08

VHYSH Low-voltage inhibit reset/recover hysteresis —

high range

— 80 — mV

VLVDL Falling low-voltage detect threshold — low

range (LVDV=00)

1.54 1.60 1.66 V

VLVW1L

VLVW2L

VLVW3L

VLVW4L

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

VHYSL Low-voltage inhibit reset/recover hysteresis —

low range

— 60 — mV

VBG Bandgap voltage reference 0.97 1.00 1.03 V

tLPO Internal low power oscillator period — factory

trimmed

900 1000 1100 μs

1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 3. VBAT power operating requirements

Symbol Description Min. Typ. Max. Unit Notes

VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

VOH Output high voltage — Normal drive pad except

RESET_B

2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA VDD – 0.5 — — V 1

1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA VDD – 0.5 — — V

VOH Output high voltage — High drive pad except

RESET_B

2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA VDD – 0.5 — — V 1

1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 — — V

IOHT Output high current total for all ports — — 100 mA

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8Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

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Table 4. Voltage and current operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

VOL Output low voltage — Normal drive pad except

RESET_B

2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — — 0.5 V 1

1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA — — 0.5 V

VOL Output low voltage — High drive pad except

RESET_B

2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA — — 0.5 V 1

1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA — — 0.5 V

VOL Output low voltage — RESET_B

2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA — — 0.5 V

1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA — — 0.5 V

IOLT Output low current total for all ports — — 100 mA

IIN Input leakage current (per pin) for full

temperature range

All pins other than high drive port pins — 0.002 0.5 μA 1, 2

High drive port pins — 0.004 0.5 μA

IIN Input leakage current (total all pins) for full

temperature range

— — 1.0 μA 2

RPU Internal pullup resistors 20 — 50 kΩ 3

RPD Internal pulldown resistors 20 — 50 kΩ 4

1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability

selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

2. Measured at VDD=3.6V

3. Measured at VDD supply voltage = VDD min and Vinput = VSS

4. Measured at VDD supply voltage = VDD min and Vinput = VDD

2.2.4 Power mode transition operating behaviors

All specifications except tPOR, and VLLSx→RUN recovery times in the following

table assume this clock configuration:

• CPU and system clocks = 80 MHz

• Bus clock = 40 MHz

• Flash clock = 20 MHz

• MCG mode: FEI

Table 5. Power mode transition operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

tPOR After a POR event, amount of time from the

point VDD reaches 1.71 V to execution of the

— — 300 μs 1

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Table 5. Power mode transition operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

first instruction across the operating

temperature range of the chip.

• VLLS0 → RUN

—

140

μs

• VLLS1 → RUN

—

140

μs

• VLLS2 → RUN

—

μs

• VLLS3 → RUN

—

μs

• LLS2 → RUN

—

μs

• LLS3 → RUN

—

μs

• VLPS → RUN

—

5.7

μs

• STOP → RUN

—

5.7

μs

1. Normal boot (FTFA_OPT[LPBOOT]=1)

2.2.5 Power consumption operating behaviors

The current parameters in the table below are derived from code executing a while(1)

loop from flash, unless otherwise noted.

The IDD typical values represent the statistical mean at 25°C, and the IDD maximum

values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction

temperature unless otherwise noted. The maximum values represent characterized

results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).

Table 6. Power consumption operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

IDDA Analog supply current — — See note mA 1

IDD_HSRUN High Speed Run mode current - all peripheral

clocks disabled, CoreMark benchmark code

executing from flash

@ 1.8V — 25.66 26.35 mA 2, 3, 4

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Table 6. Power consumption operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

@ 3.0V — 25.75 26.44 mA

IDD_HSRUN High Speed Run mode current - all peripheral

clocks disabled, code executing from flash

@ 1.8V — 23.6 24.29 mA 2

@ 3.0V — 23.7 24.39 mA

IDD_HSRUN High Speed Run mode current — all peripheral

clocks enabled, code executing from flash

@ 1.8V — 31.9 32.59 mA 5

@ 3.0V — 32.0 32.69 mA

IDD_RUN Run mode current in Compute operation —

CoreMark benchmark code executing from flash

@ 1.8V — 15.8 16.49 mA 3, 4, 6

@ 3.0V — 15.8 16.49 mA

IDD_RUN Run mode current in Compute operation —

code executing from flash

@ 1.8V — 14.00 15.50 mA 6

@ 3.0V — 14.00 15.69 mA

IDD_RUN Run mode current — all peripheral clocks

disabled, code executing from flash

@ 1.8V — 15.3 15.99 mA 7

@ 3.0V — 15.4 16.09 mA

IDD_RUN Run mode current — all peripheral clocks

enabled, code executing from flash

@ 1.8V — 20.4 21.09 mA 8

@ 3.0V

• @ 25°C — 20.5 21.19 mA

• @ 70°C — 20.5 21.19 mA

• @ 85°C — 20.5 21.19 mA

• @ 105°C — 21.4 22.09 mA

IDD_RUN Run mode current — Compute operation, code

executing from flash

@ 1.8V — 14.0 14.69 mA 9

@ 3.0V

• @ 25°C — 14.0 14.69 mA

• @ 70°C — 14.0 14.69 mA

• @ 85°C — 14.0 14.69 mA

• @ 105°C — 15.0 15.69 mA

IDD_WAIT Wait mode high frequency current at 3.0 V — all

peripheral clocks disabled

— 8.1 8.79 mA 7

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Table 6. Power consumption operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

IDD_WAIT Wait mode reduced frequency current at 3.0 V

— all peripheral clocks disabled

— 4.4 5.09 mA 10

IDD_VLPR Very-low-power run mode current in Compute

operation — CoreMark benchmark code

executing from flash

@ 1.8V — 0.70 0.88 mA 3, 4, 11

@ 3.0V — 0.70 0.88 mA

IDD_VLPR Very-low-power run mode current in Compute

operation, code executing from flash

0.61 0.79

@ 1.8V — mA 11

@ 3.0V — 0.61 0.79 mA

IDD_VLPR Very-low-power run mode current at 3.0 V — all

peripheral clocks disabled

— 0.68 0.87 mA 12

IDD_VLPR Very-low-power run mode current at 3.0 V — all

peripheral clocks enabled

— 1.10 1.28 mA 13

IDD_VLPW Very-low-power wait mode current at 3.0 V — all

peripheral clocks disabled

— 0.38 0.57 mA 14

IDD_STOP Stop mode current at 3.0 V

@ -40°C to 25°C — 0.27 0.35 mA

@ 70°C — 0.32 0.47 mA

@ 85°C — 0.32 0.51 mA

@ 105°C — 0.45 0.77 mA

IDD_VLPS Very-low-power stop mode current at 3.0 V

@ -40°C to 25°C — 4.5 12.00 µA

@ 70°C — 16.8 42.40 µA

@ 85°C — 28.9 73.45 µA

@ 105°C — 60.8 141.90 µA

IDD_LLS3 Low leakage stop mode 3 current at 3.0 V

@ -40°C to 25°C — 2.6 3.75 µA

@ 70°C — 6.6 12.00 µA

@ 85°C — 10.5 17.25 µA

@ 105°C — 21.0 40.70 µA

IDD_LLS2 Low leakage stop mode 2 current at 3.0 V

@ -40°C to 25°C — 2.4 3.40 µA

@ 70°C — 5.3 8.90 µA

@ 85°C — 5.1 10.05 µA

@ 105°C — 15.9 28.85 µA

IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V

@ -40°C to 25°C — 1.9 2.30 µA

@ 70°C — 4.8 8.10 µA

@ 85°C — 7.6 11.30 µA

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12 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

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Table 6. Power consumption operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

@ 105°C — 15.3 27.65 µA

IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V

@ -40°C to 25°C — 1.7 2.10 µA

@ 70°C — 3.4 4.85 µA

@ 85°C — 5.1 8.80 µA

@ 105°C — 9.8 15.70 µA

IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V

@ -40°C to 25°C — 0.71 0.96 µA

@ 70°C — 1.79 2.10 µA

@ 85°C — 2.9 4.70 µA

@ 105°C — 5.7 8.10 µA

IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit enabled

@ -40°C to 25°C — 0.40 0.56 µA

@ 70°C — 1.39 1.70 µA

@ 85°C — 2.5 4.25 µA

@ 105°C — 5.3 7.50 µA

IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit disabled

@ -40°C to 25°C — 0.12 0.38 µA

@ 70°C — 1.05 1.38 µA

@ 85°C — 2.20 3.95 µA

@ 105°C — 4.9 7.10 µA

IDD_VBAT Average current with RTC and 32kHz disabled

at 3.0 V

@ -40°C to 25°C — 0.18 0.21 µA

@ 70°C — 0.66 0.86 µA

@ 85°C — 1.52 2.24 µA

@ 105°C — 2.92 4.30 µA

IDD_VBAT Average current when CPU is not accessing

RTC registers

@ 1.8V

• @ -40°C to 25°C — 0.59 0.70 µA 15

• @ 70°C — 1.00 1.3 µA

• @ 85°C — 1.76 2.59 µA

• @ 105°C — 3.00 4.42 µA

@ 3.0V

• @ -40°C to 25°C — 0.71 0.84 µA

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NXP Semiconductors

Table 6. Power consumption operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

• @ 70°C — 1.22 1.59 µA

• @ 85°C — 2.08 3.06 µA

• @ 105°C — 3.50 5.15 µA

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

2. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All

peripheral clocks disabled.

3. Cache on and prefetch on, low compiler optimization.

4. Coremark benchmark compiled using IAR 7.2 with optimization level low.

5. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All

peripheral clocks enabled.

6. 80 MHz core and system clock, 40 MHz bus clock, and 26.67 MHz flash clock. MCG configured for PEE mode. Compute

operation.

7. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All

peripheral clocks disabled.

8. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All

peripheral clocks enabled.

9. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. Compute

operation.

10. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode.

11. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute operation. Code

executing from flash.

12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

disabled. Code executing from flash.

13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

enabled but peripherals are not in active operation. Code executing from flash.

14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

disabled.

15. Includes 32kHz oscillator current and RTC operation.

Table 7. Low power mode peripheral adders—typical value

Symbol Description Temperature (°C) Unit

-40 25 50 70 85 105

IIREFSTEN4MHz 4 MHz internal reference clock (IRC)

adder. Measured by entering STOP or

VLPS mode with 4 MHz IRC enabled.

56 56 56 56 56 56 µA

IIREFSTEN32KHz 32 kHz internal reference clock (IRC)

adder. Measured by entering STOP

mode with the 32 kHz IRC enabled.

52 52 52 52 52 52 µA

IEREFSTEN4MHz External 4 MHz crystal clock adder.

Measured by entering STOP or VLPS

mode with the crystal enabled.

206 228 237 245 251 258 uA

IEREFSTEN32KHz External 32 kHz crystal clock adder by

means of the OSC0_CR[EREFSTEN

and EREFSTEN] bits. Measured by

Table continues on the next page...

General

14 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

Table 7. Low power mode peripheral adders—typical value (continued)

Symbol Description Temperature (°C) Unit

-40 25 50 70 85 105

entering all modes with the crystal

enabled.

VLLS1

VLLS3

LLS

VLPS

STOP

440

490

510

490

560

540

560

570

610

580

680

I48MIRC 48 Mhz internal reference clock 350 350 350 350 350 350 µA

ICMP CMP peripheral adder measured by

placing the device in VLLS1 mode with

CMP enabled using the 6-bit DAC and a

single external input for compare.

Includes 6-bit DAC power consumption.

22 22 22 22 22 22 µA

IRTC RTC peripheral adder measured by

placing the device in VLLS1 mode with

external 32 kHz crystal enabled by

means of the RTC_CR[OSCE] bit and

the RTC ALARM set for 1 minute.

Includes ERCLK32K (32 kHz external

crystal) power consumption.

432 357 388 475 532 810 nA

IUART UART peripheral adder measured by

placing the device in STOP or VLPS

mode with selected clock source waiting

for RX data at 115200 baud rate.

Includes selected clock source power

consumption.

MCGIRCLK (4 MHz internal reference

clock)

>OSCERCLK (4 MHz external crystal)

214

237

246

254

260

268

µA

IBG Bandgap adder when BGEN bit is set

and device is placed in VLPx, LLS, or

VLLSx mode.

45 45 45 45 45 45 µA

IADC ADC peripheral adder combining the

measured values at VDD and VDDA by

placing the device in STOP or VLPS

mode. ADC is configured for low power

mode using the internal clock and

continuous conversions.

42 42 42 42 42 42 µA

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

General

Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 15

NXP Semiconductors

• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at

frequencies between 50 MHz and 100MHz. MCG in PEE mode at frequencies

greater than 100 MHz.

• USB regulator disabled

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

Figure 3. Run mode supply current vs. core frequency

General

16 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 8. EMC radiated emissions operating behaviors for 64 LQFP package

Parame

ter

Conditions Clocks Frequency range Level

(Typ.)

Unit Notes

VEME Device configuration,

test conditions and EM

testing per standard IEC

61967-2.

Supply voltages:

• VREGIN (USB) =

5.0 V

• VDD = 3.3 V

Temp = 25°C

FSYS = 120 MHz

FBUS = 60 MHz

External crystal = 8 MHz

150 kHz–50 MHz 14 dBuV 1, 2, 3

50 MHz–150 MHz 23

150 MHz–500 MHz 23

500 MHz–1000 MHz 9

IEC level L 4

1. Measurements were made per IEC 61967-2 while the device was running typical application code.

2. Measurements were performed on the 64LQFP device, MK22FN512VLH12 .

General

Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 17

NXP Semiconductors

3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,

from among the measured orientations in each frequency range.

4. IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .

2.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

• Go to nxp.com

• Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 9. Capacitance attributes

Symbol Description Min. Max. Unit

CIN_A Input capacitance: analog pins — 7 pF

CIN_D Input capacitance: digital pins — 7 pF

2.3 Switching specifications

2.3.1 Device clock specifications

Table 10. Device clock specifications

Symbol Description Min. Max. Unit Notes

High Speed run mode

fSYS System and core clock — 120 MHz

fBUS Bus clock — 60 MHz

Normal run mode (and High Speed run mode unless otherwise specified above)

fSYS System and core clock — 80 MHz

fSYS_USB System and core clock when Full Speed USB in

operation

20 — MHz

fBUS Bus clock — 50 MHz

fFLASH Flash clock — 26.67 MHz

fLPTMR LPTMR clock — 25 MHz

VLPR mode1

fSYS System and core clock — 4 MHz

Table continues on the next page...

General

18 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

Table 10. Device clock specifications (continued)

Symbol Description Min. Max. Unit Notes

fBUS Bus clock — 4 MHz

fFLASH Flash clock — 1 MHz

fERCLK External reference clock — 16 MHz

fLPTMR_pin LPTMR clock — 25 MHz

fLPTMR_ERCLK LPTMR external reference clock — 16 MHz

fI2S_MCLK I2S master clock — 12.5 MHz

fI2S_BCLK I2S bit clock — 4 MHz

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

any other module.

2.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and timers.

Table 11. General switching specifications

Symbol Description Min. Max. Unit Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5 — Bus clock

cycles

1, 2

External RESET and NMI pin interrupt pulse width —

Asynchronous path

100 — ns 3

GPIO pin interrupt pulse width (digital glitch filter

disabled, passive filter disabled) — Asynchronous

path

50 — ns 4

Mode select (EZP_CS) hold time after reset

deassertion

2 — Bus clock

cycles

Port rise and fall time

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

—

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses

may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter

pulses can be recognized in that case.

2. The greater of synchronous and asynchronous timing must be met.

3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be

recognized.

General

Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 19

NXP Semiconductors

4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be

recognized.

5. 25 pF load

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 12. Thermal operating requirements

Symbol Description Min. Max. Unit Notes

TJDie junction temperature –40 125 °C

TAAmbient temperature –40 105 °C 1

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

determine TJ is: TJ = TA + RΘJA × chip power dissipation.

2.4.2 Thermal attributes

Board

type Symbol Descripti

on 121

XFBGA 100 LQFP 64 LQFP 64

MAPBGA Unit Notes

Single-layer

(1s)

RθJA Thermal

resistance,

junction to

ambient

(natural

convection)

44.4 61 67 47.3 °C/W 1

Four-layer

(2s2p)

RθJA Thermal

resistance,

junction to

ambient

(natural

convection)

27.0 48 48 38.9 °C/W 2

Single-layer

(1s)

RθJMA Thermal

resistance,

junction to

ambient

(200 ft./min.

air speed)

37.2 51 55 40.1 °C/W 3

Four-layer

(2s2p)

RθJMA Thermal

resistance,

junction to

ambient

(200 ft./min.

air speed)

23.7 42 42 35.3 °C/W 3

Table continues on the next page...

General

20 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

Board

type Symbol Descripti

on 121

XFBGA 100 LQFP 64 LQFP 64

MAPBGA Unit Notes

— RθJB Thermal

resistance,

junction to

board

23.5 34 31 35.4 °C/W 4

— RθJC Thermal

resistance,

junction to

case

17.4 16 16 29.2 °C/W 5

—ΨJT Thermal

characteriz

ation

parameter,

junction to

package

top outside

center

(natural

convection)

0.2 3 3 0.4 °C/W 6

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification.

2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental

Conditions—Forced Convection (Moving Air) with the board horizontal.

4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 SWD electricals

Table 13. SWD full voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 1.71 3.6 V

S1 SWD_CLK frequency of operation

• Serial wire debug

MHz

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Peripheral operating requirements and behaviors

Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 21

NXP Semiconductors

Table 13. SWD full voltage range electricals (continued)

Symbol Description Min. Max. Unit

S2 SWD_CLK cycle period 1/S1 — ns

S3 SWD_CLK clock pulse width

• Serial wire debug

—

S4 SWD_CLK rise and fall times — 3 ns

S9 SWD_DIO input data setup time to SWD_CLK rise 8 — ns

S10 SWD_DIO input data hold time after SWD_CLK rise 1.4 — ns

S11 SWD_CLK high to SWD_DIO data valid — 25 ns

S12 SWD_CLK high to SWD_DIO high-Z 5 — ns

S3 S3

S4 S4

SWD_CLK (input)

Figure 5. Serial wire clock input timing

S11

S12

S11

S9 S10

Input data valid

Output data valid

SWD_CLK

SWD_DIO

Figure 6. Serial wire data timing

Peripheral operating requirements and behaviors

22 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

3.1.2 JTAG electricals

Table 14. JTAG limited voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 2.7 3.6 V

J1 TCLK frequency of operation

• Boundary Scan

• JTAG and CJTAG

MHz

J2 TCLK cycle period 1/J1 — ns

J3 TCLK clock pulse width

• Boundary Scan

• JTAG and CJTAG

—

J4 TCLK rise and fall times — 3 ns

J5 Boundary scan input data setup time to TCLK rise 20 — ns

J6 Boundary scan input data hold time after TCLK rise 1 — ns

J7 TCLK low to boundary scan output data valid — 25 ns

J8 TCLK low to boundary scan output high-Z — 25 ns

J9 TMS, TDI input data setup time to TCLK rise 8 — ns

J10 TMS, TDI input data hold time after TCLK rise 1 — ns

J11 TCLK low to TDO data valid — 19 ns

J12 TCLK low to TDO high-Z — 19 ns

J13 TRST assert time 100 — ns

J14 TRST setup time (negation) to TCLK high 8 — ns

Table 15. JTAG full voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 1.71 3.6 V

J1 TCLK frequency of operation

• Boundary Scan

• JTAG and CJTAG

MHz

J2 TCLK cycle period 1/J1 — ns

J3 TCLK clock pulse width

• Boundary Scan

• JTAG and CJTAG

—

J4 TCLK rise and fall times — 3 ns

J5 Boundary scan input data setup time to TCLK rise 20 — ns

J6 Boundary scan input data hold time after TCLK rise 1.4 — ns

J7 TCLK low to boundary scan output data valid — 27 ns

Table continues on the next page...

Peripheral operating requirements and behaviors

Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 23

NXP Semiconductors

Table 15. JTAG full voltage range electricals (continued)

Symbol Description Min. Max. Unit

J8 TCLK low to boundary scan output high-Z — 27 ns

J9 TMS, TDI input data setup time to TCLK rise 8 — ns

J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns

J11 TCLK low to TDO data valid — 26.2 ns

J12 TCLK low to TDO high-Z — 26.2 ns

J13 TRST assert time 100 — ns

J14 TRST setup time (negation) to TCLK high 8 — ns

J3 J3

J4 J4

TCLK (input)

Figure 7. Test clock input timing

J5 J6

Input data valid

Output data valid

TCLK

Data inputs

Data outputs

Figure 8. Boundary scan (JTAG) timing

Peripheral operating requirements and behaviors

24 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

J11

J12

J11

J9 J10

Input data valid

Output data valid

TCLK

TDI/TMS

TDO

Figure 9. Test Access Port timing

J14

J13

TCLK

TRST

Figure 10. TRST timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

Peripheral operating requirements and behaviors

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NXP Semiconductors

3.3.1 MCG specifications

Table 16. MCG specifications

Symbol Description Min. Typ. Max. Unit Notes

fints_ft Internal reference frequency (slow clock) —

factory trimmed at nominal VDD and 25 °C

— 32.768 — kHz

Δfints_t Total deviation of internal reference frequency

(slow clock) over voltage and temperature

— +0.5/-0.7 ± 2 %

fints_t Internal reference frequency (slow clock) —

user trimmed

31.25 — 39.0625 kHz

Δfdco_res_t Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM and SCFTRIM

— ± 0.3 ± 0.6 %fdco 1

Δfdco_t Total deviation of trimmed average DCO output

frequency over voltage and temperature

— +0.5/-0.7 ± 2 %fdco 1, 2

Δfdco_t Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70°C

— ± 0.3 ± 1.5 %fdco 1

fintf_ft Internal reference frequency (fast clock) —

factory trimmed at nominal VDD and 25°C

— 4 — MHz

Δfintf_ft Frequency deviation of internal reference clock

(fast clock) over temperature and voltage —

factory trimmed at nominal VDD and 25 °C

— +1/-2 ± 5 %fintf_ft

fintf_t Internal reference frequency (fast clock) — user

trimmed at nominal VDD and 25 °C

3 — 5 MHz

floc_low Loss of external clock minimum frequency —

RANGE = 00

(3/5) x

fints_t

— — kHz

floc_high Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

fints_t

— — kHz

FLL

ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz

fdco DCO output

frequency range

Low range (DRS=00)

640 × ffll_ref

20 20.97 25 MHz 3, 4

Mid range (DRS=01)

1280 × ffll_ref

40 41.94 50 MHz

Mid-high range (DRS=10)

1920 × ffll_ref

60 62.91 75 MHz

High range (DRS=11)

2560 × ffll_ref

80 83.89 100 MHz

fdco_t_DMX3

DCO output

frequency

Low range (DRS=00)

732 × ffll_ref

— 23.99 — MHz 5, 6

Mid range (DRS=01)

1464 × ffll_ref

— 47.97 — MHz

Mid-high range (DRS=10) — 71.99 — MHz

Table continues on the next page...

Peripheral operating requirements and behaviors

26 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

Table 16. MCG specifications (continued)

Symbol Description Min. Typ. Max. Unit Notes

2197 × ffll_ref

High range (DRS=11)

2929 × ffll_ref

— 95.98 — MHz

Jcyc_fll FLL period jitter

• fVCO = 48 MHz

• fVCO = 98 MHz

—

180

150

—

tfll_acquire FLL target frequency acquisition time — — 1 ms 7

PLL

fvco VCO operating frequency 48.0 — 120 MHz

Ipll PLL operating current

• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 48)

— 1060 — µA 8

Ipll PLL operating current

• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 24)

— 600 — µA 8

fpll_ref PLL reference frequency range 2.0 — 4.0 MHz

Jcyc_pll PLL period jitter (RMS)

• fvco = 48 MHz

• fvco = 100 MHz

—

120

—

Jacc_pll PLL accumulated jitter over 1µs (RMS)

• fvco = 48 MHz

• fvco = 100 MHz

—

1350

600

—

Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 %

Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 %

tpll_lock Lock detector detection time — — 150 × 10-6

+ 1075(1/

fpll_ref)

s10

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. 2.0 V <= VDD <= 3.6 V.

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency

deviation (Δfdco_t) over voltage and temperature should be considered.

5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

8. Excludes any oscillator currents that are also consuming power while PLL is in operation.

9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL

disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this

specification assumes it is already running.

Peripheral operating requirements and behaviors

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NXP Semiconductors

3.3.2 IRC48M specifications

Table 17. IRC48M specifications

Symbol Description Min. Typ. Max. Unit Notes

VDD Supply voltage 1.71 — 3.6 V

IDD48M Supply current — 400 500 μA

firc48m Internal reference frequency — 48 — MHz

Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at

high voltage (VDD=1.89V-3.6V) over 0°C to 70°C

—

Regulator enable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)

— ± 0.2 ± 0.5 %firc48m 1

Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at

high voltage (VDD=1.89V-3.6V) over full temperature

Regulator enable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)

— ± 0.4 ± 1.0 %firc48m 1

Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at low

voltage (VDD=1.71V-1.89V) over full temperature

Regulator disable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)

— ± 0.4 ± 1.0 %firc48m

Regulator enable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)

— ± 0.5 ± 1.5

Δfirc48m_cl Closed loop total deviation of IRC48M frequency over

voltage and temperature

— — ± 0.1 %fhost 2

Jcyc_irc48m Period Jitter (RMS) — 35 150 ps

tirc48mst Startup time — 2 3 μs 3

1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard

deviation (mean ± 3 sigma).

2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It

is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover

function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).

3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the

clock by one of the following settings:

• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 or

• MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or

• SIM_SOPT2[PLLFLLSEL]=11

3.3.3 Oscillator electrical specifications

Peripheral operating requirements and behaviors

28 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016

NXP Semiconductors

3.3.3.1 Oscillator DC electrical specifications

Table 18. Oscillator DC electrical specifications

Symbol Description Min. Typ. Max. Unit Notes

VDD Supply voltage 1.71 — 3.6 V

IDDOSC Supply current — low-power mode (HGO=0)

• 32 kHz

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

—

500

200

300

950

1.2

1.5

—

μA

IDDOSC Supply current — high-gain mode (HGO=1)

• 32 kHz

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

—

400

500

2.5

—

μA

CxEXTAL load capacitance — — — 2, 3

CyXTAL load capacitance — — — 2, 3

RFFeedback resistor — low-frequency, low-power

mode (HGO=0)

— — — MΩ 2, 4

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

— 10 — MΩ

Feedback resistor — high-frequency, low-

power mode (HGO=0)

— — — MΩ

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

— 1 — MΩ

RSSeries resistor — low-frequency, low-power

mode (HGO=0)

— — — kΩ

Series resistor — low-frequency, high-gain

mode (HGO=1)

— 200 — kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

— — — kΩ

Series resistor — high-frequency, high-gain

mode (HGO=1)

—

kΩ

Vpp5Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

— 0.6 — V

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Peripheral operating requirements and behaviors

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NXP Semiconductors

Table 18. Oscillator DC electrical specifications (continued)

Symbol Description Min. Typ. Max. Unit Notes

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

— VDD — V

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

— 0.6 — V

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

— VDD — V

1. VDD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

3. Cx and Cy can be provided by using either integrated capacitors or external components.

4. When low-power mode is selected, RF is integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

any other device.

3.3.3.2 Oscillator frequency specifications

Table 19. Oscillator frequency specifications

Symbol Description Min. Typ. Max. Unit Notes

fosc_lo Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

32 — 40 kHz

fosc_hi_1 Oscillator crystal or resonator frequency — high-

frequency mode (low range)

(MCG_C2[RANGE]=01)

3 — 8 MHz

fosc_hi_2 Oscillator crystal or resonator frequency — high

frequency mode (high range)

(MCG_C2[RANGE]=1x)

8 — 32 MHz

fec_extal Input clock frequency (external clock mode) — — 50 MHz 1, 2

tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %

tcst Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

— 750 — ms 3, 4

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

— 250 — ms

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

— 0.6 — ms

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

— 1 — ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

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4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

3.3.4 32 kHz oscillator electrical characteristics

3.3.4.1 32 kHz oscillator DC electrical specifications

Table 20. 32kHz oscillator DC electrical specifications

Symbol Description Min. Typ. Max. Unit

VBAT Supply voltage 1.71 — 3.6 V

RFInternal feedback resistor — 100 — MΩ

Cpara Parasitical capacitance of EXTAL32 and

XTAL32

— 5 7 pF

Vpp1Peak-to-peak amplitude of oscillation — 0.6 — V

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices.

3.3.4.2 32 kHz oscillator frequency specifications

Table 21. 32 kHz oscillator frequency specifications

Symbol Description Min. Typ. Max. Unit Notes

fosc_lo Oscillator crystal — 32.768 — kHz

tstart Crystal start-up time — 1000 — ms 1

fec_extal32 Externally provided input clock frequency — 32.768 — kHz 2

vec_extal32 Externally provided input clock amplitude 700 — VBAT mV 2, 3

1. Proper PC board layout procedures must be followed to achieve specifications.

2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.

The oscillator remains enabled and XTAL32 must be left unconnected.

3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the

applied clock must be within the range of VSS to VBAT.

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

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3.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are

active and do not include command overhead.

Table 22. NVM program/erase timing specifications

Symbol Description Min. Typ. Max. Unit Notes

thvpgm4 Longword Program high-voltage time — 7.5 18 μs —

thversscr Sector Erase high-voltage time — 13 113 ms 1

thversall Erase All high-voltage time — 104 904 ms 1

1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 23. Flash command timing specifications

Symbol Description Min. Typ. Max. Unit Notes

trd1sec2k Read 1s Section execution time (flash sector) — — 60 μs 1

tpgmchk Program Check execution time — — 45 μs 1

trdrsrc Read Resource execution time — — 30 μs 1

tpgm4 Program Longword execution time — 65 145 μs —

tersscr Erase Flash Sector execution time — 14 114 ms 2

trd1all Read 1s All Blocks execution time — — 1.8 ms 1

trdonce Read Once execution time — — 30 μs 1

tpgmonce Program Once execution time — 100 — μs —

tersall Erase All Blocks execution time — 175 1300 ms 2

tvfykey Verify Backdoor Access Key execution time — — 30 μs 1

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3.4.1.3 Flash high voltage current behaviors

Table 24. Flash high voltage current behaviors

Symbol Description Min. Typ. Max. Unit

IDD_PGM Average current adder during high voltage

flash programming operation

— 2.5 6.0 mA

IDD_ERS Average current adder during high voltage

flash erase operation

— 1.5 4.0 mA

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3.4.1.4 Reliability specifications

Table 25. NVM reliability specifications

Symbol Description Min. Typ.1Max. Unit Notes

Program Flash

tnvmretp10k Data retention after up to 10 K cycles 5 50 — years —

tnvmretp1k Data retention after up to 1 K cycles 20 100 — years —

nnvmcycp Cycling endurance 10 K 50 K — cycles 2

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a

constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in

Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.

3.4.2 EzPort switching specifications

Table 26. EzPort switching specifications

Num Description Min. Max. Unit

Operating voltage 1.71 3.6 V

EP1 EZP_CK frequency of operation (all commands except

READ)

— fSYS/2 MHz

EP1a EZP_CK frequency of operation (READ command) — fSYS/8 MHz

EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK — ns

EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns

EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns

EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns

EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns

EP7 EZP_CK low to EZP_Q output valid — 25 ns

EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns

EP9 EZP_CS negation to EZP_Q tri-state — 12 ns

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EP2

EP3 EP4

EP5 EP6

EP7 EP8

EP9

EZP_CK

EZP_CS

EZP_Q (output)

EZP_D (input)

Figure 11. EzPort Timing Diagram

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the

differential pins ADCx_DPx, ADCx_DMx.

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy

specifications.

3.6.1.1 16-bit ADC operating conditions

Table 27. 16-bit ADC operating conditions

Symbol Description Conditions Min. Typ.1Max. Unit Notes

VDDA Supply voltage Absolute 1.71 — 3.6 V

ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2

Table continues on the next page...

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Table 27. 16-bit ADC operating conditions (continued)

Symbol Description Conditions Min. Typ.1Max. Unit Notes

ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2

VREFH ADC reference

voltage high

1.13 VDDA VDDA V

VREFL ADC reference

voltage low

VSSA VSSA VSSA V

VADIN Input voltage • 16-bit differential mode

• All other modes

VREFL

—

31/32 *

VREFH

CADIN Input

capacitance

• 16-bit mode

• 8-bit / 10-bit / 12-bit

modes

—

RADIN Input series

resistance

— 2 5 kΩ

RAS Analog source

resistance

(external)

13-bit / 12-bit modes

fADCK < 4 MHz

—

kΩ

fADCK ADC conversion

clock frequency

≤ 13-bit mode 1.0 — 24.0 MHz 4

fADCK ADC conversion

clock frequency

16-bit mode 2.0 — 12.0 MHz 4

Crate ADC conversion

rate

≤ 13-bit modes

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

—

1200

Ksps

Crate ADC conversion

rate

16-bit mode

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

—

461

Ksps

1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The

RAS/CAS time constant should be kept to < 1 ns.

4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

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RAS

VAS CAS

ZAS

VADIN

ZADIN

RADIN

CADIN

Pad

leakage

due to

input

protection

INPUT PIN

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

ADC SAR

ENGINE

Figure 12. ADC input impedance equivalency diagram

3.6.1.2 16-bit ADC electrical characteristics

Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)

Symbol Description Conditions1Min. Typ.2Max. Unit Notes

IDDA_ADC Supply current 0.215 — 1.7 mA 3

fADACK

ADC asynchronous

clock source

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

1.2

2.4

3.0

4.4

2.4

4.0

5.2

6.2

3.9

6.1

7.3

9.5

MHz

tADACK = 1/

fADACK

Sample Time See Reference Manual chapter for sample times

TUE Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

±4

±1.4

±6.8

±2.1

LSB45

DNL Differential non-

linearity

• 12-bit modes

• <12-bit modes

—

±0.7

±0.2

–1.1 to

+1.9

–0.3 to

0.5

LSB45

INL Integral non-linearity • 12-bit modes — ±1.0 –2.7 to

+1.9

LSB45

Table continues on the next page...

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Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)

Symbol Description Conditions1Min. Typ.2Max. Unit Notes

• <12-bit modes — ±0.5 –0.7 to

+0.5

EFS Full-scale error • 12-bit modes

• <12-bit modes

—

–4

–1.4

–5.4

–1.8

LSB4VADIN = VDDA5

EQQuantization error • 16-bit modes

• ≤13-bit modes

—

–1 to 0

—

±0.5

LSB4

ENOB Effective number of

bits

16-bit differential mode

• Avg = 32

• Avg = 4

16-bit single-ended mode

• Avg = 32

• Avg = 4

12.8

11.9

12.2

11.4

14.5

13.8

13.9

13.1

—

bits

SINAD Signal-to-noise plus

distortion

See ENOB 6.02 × ENOB + 1.76 dB

THD Total harmonic

distortion

16-bit differential mode

• Avg = 32

16-bit single-ended mode

• Avg = 32

—

-94

-85

—

SFDR Spurious free

dynamic range

16-bit differential mode

• Avg = 32

16-bit single-ended mode

• Avg = 32

—

EIL Input leakage error IIn × RAS mV IIn = leakage

current

(refer to the

MCU's voltage

and current

operating

ratings)

Temp sensor slope Across the full temperature

range of the device

1.55 1.62 1.69 mV/°C 8

VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8

1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA

2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with

1 MHz ADC conversion clock speed.

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4. 1 LSB = (VREFH - VREFL)/2N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

ENOB

ADC Clock Frequency (MHz)

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

12.30

12.00

1 2 3 4 5 6 7 8 9 10 1211

Hardware Averaging Disabled

Averaging of 4 samples

Averaging of 8 samples

Averaging of 32 samples

Figure 13. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

ENOB

ADC Clock Frequency (MHz)

14.00

13.75

13.25

13.00

12.75

12.50

12.00

11.75

11.50

11.25

11.00

1 2 3 4 5 6 7 8 9 10 1211

Averaging of 4 samples

Averaging of 32 samples

13.50

12.25

Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

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3.6.2 CMP and 6-bit DAC electrical specifications

Table 29. Comparator and 6-bit DAC electrical specifications

Symbol Description Min. Typ. Max. Unit

VDD Supply voltage 1.71 — 3.6 V

IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA

IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA

VAIN Analog input voltage VSS – 0.3 — VDD V

VAIO Analog input offset voltage — — 20 mV

VHAnalog comparator hysteresis1

• CR0[HYSTCTR] = 00

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

—

VCMPOh Output high VDD – 0.5 — — V

VCMPOl Output low — — 0.5 V

tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns

tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns

Analog comparator initialization delay2— — 40 μs

IDAC6b 6-bit DAC current adder (enabled) — 7 — μA

INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3

DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB

1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = Vreference/64

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HYSTCTR

Setting

0.1

Vin level (V)

CMP Hystereris (V)

3.12.82.5

2.2

1.91.61.3

0.70.4

0.05

0.01

0.02

0.03

0.08

0.07

0.06

0.04

Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

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HYSTCTR

Setting

0.1 3.12.82.5

2.2

1.91.61.3

0.70.4

0.1

0.02

0.04

0.06

0.18

0.14

0.12

0.08

0.16

Vin level (V)

CMP Hysteresis (V)

Figure 16. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

3.6.3 12-bit DAC electrical characteristics

3.6.3.1 12-bit DAC operating requirements

Table 30. 12-bit DAC operating requirements

Symbol Desciption Min. Max. Unit Notes

VDDA Supply voltage 1.71 3.6 V

VDACR Reference voltage 1.13 3.6 V 1

CLOutput load capacitance — 100 pF 2

ILOutput load current — 1 mA

1. The DAC reference can be selected to be VDDA or VREFH.

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

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3.6.3.2 12-bit DAC operating behaviors

Table 31. 12-bit DAC operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

IDDA_DACL

Supply current — low-power mode — — 330 μA

IDDA_DACH

Supply current — high-speed mode — — 1200 μA

tDACLP Full-scale settling time (0x080 to 0xF7F) —

low-power mode

— 100 200 μs 1

tDACHP Full-scale settling time (0x080 to 0xF7F) —

high-power mode

— 15 30 μs 1

tCCDACLP Code-to-code settling time (0xBF8 to

0xC08) — low-power mode and high-speed

mode

— 0.7 1 μs 1

Vdacoutl DAC output voltage range low — high-

speed mode, no load, DAC set to 0x000

— — 100 mV

Vdacouth DAC output voltage range high — high-

speed mode, no load, DAC set to 0xFFF

VDACR

−100

— VDACR mV

INL Integral non-linearity error — high speed

mode

— — ±8 LSB 2

DNL Differential non-linearity error — VDACR > 2

— — ±1 LSB 3

DNL Differential non-linearity error — VDACR =

VREF_OUT

— — ±1 LSB 4

VOFFSET Offset error — ±0.4 ±0.8 %FSR 5

EGGain error — ±0.1 ±0.6 %FSR 5

PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB

TCO Temperature coefficient offset voltage — 3.7 — μV/C 6

TGE Temperature coefficient gain error — 0.000421 — %FSR/C

Rop Output resistance (load = 3 kΩ) — — 250 Ω

SR Slew rate -80h→ F7Fh→ 80h

• High power (SPHP)

• Low power (SPLP)

1.2

0.05

1.7

0.12

—

V/μs

BW 3dB bandwidth

• High power (SPHP)

• Low power (SPLP)

550

—

kHz

1. Settling within ±1 LSB

2. The INL is measured for 0 + 100 mV to VDACR −100 mV

3. The DNL is measured for 0 + 100 mV to VDACR −100 mV

4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V

5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV

6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set

to 0x800, temperature range is across the full range of the device

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Digital Code

DAC12 INL (LSB)

500 1000 1500 2000 2500 3000 3500 4000

-2

-4

-6

-8

Figure 17. Typical INL error vs. digital code

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Temperature °C

DAC12 Mid Level Code Voltage

25 55 85 105 125

1.499

-40

1.4985

1.498

1.4975

1.497

1.4965

1.496

Figure 18. Offset at half scale vs. temperature

3.6.4 Voltage reference electrical specifications

Table 32. VREF full-range operating requirements

Symbol Description Min. Max. Unit Notes

VDDA Supply voltage 1.71 3.6 V

TATemperature Operating temperature

range of the device

°C

CLOutput load capacitance 100 nF 1, 2

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external

reference.

2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range

of the device.

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