NXP Semiconductors Data Sheet: Technical Data K22P121M120SF8 Rev. 7, 08/2016 Kinetis K22F 256 KB Flash 120 MHz ARM(R) Cortex(R)-M4-Based Microcontroller with FPU The Kinetis K22 product family members are optimized for costsensitive applications requiring low-power, USB connectivity, high peripheral integration and processing efficiency with floating point unit. These devices share the comprehensive enablement and scalability of the Kinetis family. This product offers: * Run power consumption down to 153 A/MHz and static power consumption down to 2.6 A with full state retention and 6 s wakeup. Lowest static mode down to 120 nA * USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO voltage regulator. USB FS device crystal-less functionality. Performance * 120 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz Memories and memory interfaces * 256 KB of embedded flash and 48 KB of RAM * Serial programming interface (EzPort) * Preprogrammed Kinetis flashloader for one-time, insystem factory programming System peripherals * Flexible low-power modes, multiple wake up sources * 16-channel DMA controller * Independent external and software watchdog monitor MK22FN256VDC12 MK22FN256VLL12 MK22FN256VMP12 MK22FN256VLH12 121 XFBGA (DC) 8 x 8 x 0.5 Pitch 0.65 mm 100 LQFP (LL) 14 x 14 x 1.4 Pitch 0.5 mm 64 MAPBGA (MP) 5 x 5 x 1.2 Pitch 0.5 mm 64 LQFP (LH) 10 x 10 x 1.4 Pitch 0.5 mm Analog modules * Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode) * One 12-bit DAC * Two analog comparators (CMP) with 6- bit DAC * Accurate internal voltage reference Communication interfaces * USB LS/FS OTG 2.0 with on-chip transceiver and USB LDO voltage regulator * USB full-speed device crystal-less operation * Two SPI modules * Three UART modules and one low-power UART * Two I2C modules: Support for up to 1 Mbps operation * I2S module Clocks * Two crystal oscillators: 32 kHz (RTC) and 32-40 kHz or Timers 3-32 MHz * One 8-channel general purpose/ PWM timer * Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz * Two 2-channel general purpose timers with * Multi-purpose clock generator with PLL and FLL quadrature decoder functionality * Periodic interrupt timers Security and integrity modules * 16-bit low-power timer * Hardware CRC module * Real-time clock with independent power domain * 128-bit unique identification (ID) number per chip * Programmable delay block * Hardware random-number generator * Flash access control to protect proprietary software Operating Characteristics * Voltage range (including flash writes): 1.71 to 3.6 V Human-machine interface * Temperature range (ambient): -40 to 105C * Up to 70 general-purpose I/O (GPIO) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Ordering Information Part Number Memory Number of GPIOs Flash (KB) SRAM (KB) MK22FN256VDC12 256 48 70 MK22FN256VLL12 256 48 66 MK22FN256VMP12 256 48 40 MK22FN256VLH12 256 48 40 Device Revision Number Device Mask Set Number SIM_SDID[REVID] JTAG ID Register[PRN] 0N51M 0001 0001 Related Resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector KINETISKMCUSELGD Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. K22FPB Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K22P121M120SF8RM Data Sheet The Data Sheet is this document. It includes electrical characteristics and signal connections. K22P121M120SF8 Chip Errata The chip mask set Errata provides additional or corrective information for KINETIS_K_xN51M 1 a particular device mask set. Package drawing Package dimensions are provided by part number: * MK22FN256VDC12 * MK22FN256VLL12 * MK22FN256VMP12 * MK22FN256VLH12 Package drawing: * 98ASA00595D * 98ASS23308W * 98ASA00420D * 98ASS23234W 1. To find the associated resource, go to nxp.com and perform a search using this term with the x replaced by the revision of the device you are using. Figure 1 shows the functional modules in the chip. 2 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 ARM (R) CortexTM-M4 Core System Memories and Memory Interfaces DMA (16ch) Program flash (256 KB) Serial programming interface (EzPort) Debug interfaces DSP Low-leakage wakeup Interrupt controller FPU Internal and external watchdogs RAM (48 KB) Clocks Phaselocked loop Frequencylocked loop Low/high frequency oscillators Internal reference clocks Security Analog Timers CRC 16-bit ADC x2 Timers x1 (8ch) x2 (2ch) Randomnumber generator Comparator with 6-bit DAC x2 Programmable Flash access control and Integrity Communication Interfaces 2 I C x2 I S delay block UART x3 USB OTG LS/FS 12-bit DAC Periodic interrupt timers LPUART x1 USB LS/FS transceiver High performance voltage ref 16-bit low-power timer SPI x2 USB voltage regulator 2 Human-Machine Interface (HMI) Up to 70 GPIOs Independent real-time clock Figure 1. Functional block diagram Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 3 NXP Semiconductors Table of Contents 1 Ratings.................................................................................... 5 1.1 Thermal handling ratings................................................. 5 1.2 Moisture handling ratings................................................ 5 1.3 ESD handling ratings....................................................... 5 1.4 Voltage and current operating ratings............................. 5 2 General................................................................................... 6 2.1 AC electrical characteristics.............................................6 2.2 Nonswitching electrical specifications..............................6 2.2.1 Voltage and current operating requirements....... 6 2.2.2 LVD and POR operating requirements................7 2.2.3 Voltage and current operating behaviors.............8 2.2.4 Power mode transition operating behaviors........ 9 2.2.5 Power consumption operating behaviors............ 10 2.2.6 EMC radiated emissions operating behaviors..... 17 2.2.7 Designing with radiated emissions in mind..........18 2.2.8 Capacitance attributes.........................................18 2.3 Switching specifications...................................................18 2.3.1 Device clock specifications..................................18 2.3.2 General switching specifications......................... 19 2.4 Thermal specifications..................................................... 20 2.4.1 Thermal operating requirements......................... 20 2.4.2 Thermal attributes................................................20 3 Peripheral operating requirements and behaviors.................. 21 3.1 Core modules.................................................................. 21 3.1.1 SWD electricals .................................................. 21 3.1.2 JTAG electricals.................................................. 22 3.2 System modules.............................................................. 25 3.3 Clock modules................................................................. 25 3.3.1 MCG specifications..............................................25 3.3.2 IRC48M specifications.........................................28 3.3.3 Oscillator electrical specifications........................28 3.3.4 32 kHz oscillator electrical characteristics........... 31 3.4 Memories and memory interfaces................................... 31 3.4.1 Flash electrical specifications.............................. 31 3.4.2 EzPort switching specifications........................... 33 3.5 Security and integrity modules........................................ 34 3.6 Analog............................................................................. 34 4 NXP Semiconductors 4 5 6 7 3.6.1 ADC electrical specifications............................... 34 3.6.2 CMP and 6-bit DAC electrical specifications....... 38 3.6.3 12-bit DAC electrical characteristics....................41 3.6.4 Voltage reference electrical specifications.......... 44 3.7 Timers..............................................................................45 3.8 Communication interfaces............................................... 45 3.8.1 USB electrical specifications............................... 46 3.8.2 USB VREG electrical specifications.................... 46 3.8.3 DSPI switching specifications (limited voltage range).................................................................. 47 3.8.4 DSPI switching specifications (full voltage range).................................................................. 49 3.8.5 Inter-Integrated Circuit Interface (I2C) timing...... 50 3.8.6 UART switching specifications............................ 52 3.8.7 I2S/SAI switching specifications.......................... 52 Dimensions............................................................................. 58 4.1 Obtaining package dimensions....................................... 58 Pinout...................................................................................... 59 5.1 K22F Signal Multiplexing and Pin Assignments.............. 59 5.2 Recommended connection for unused analog and digital pins........................................................................64 5.3 K22F Pinouts................................................................... 65 Part identification.....................................................................69 6.1 Description.......................................................................69 6.2 Format............................................................................. 69 6.3 Fields............................................................................... 70 6.4 Example...........................................................................70 6.5 121-pin XFBGA part marking.......................................... 71 6.6 64-pin MAPBGA part marking......................................... 71 Terminology and guidelines.................................................... 71 7.1 Definitions........................................................................ 71 7.2 Examples......................................................................... 72 7.3 Typical-value conditions.................................................. 72 7.4 Relationship between ratings and operating requirements....................................................................73 7.5 Guidelines for ratings and operating requirements..........73 8 Revision History...................................................................... 73 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Ratings 1 Ratings 1.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes -- 3 -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 1.4 Voltage and current operating ratings Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 5 NXP Semiconductors General Symbol Description Min. Max. Unit VDD Digital supply voltage -0.3 3.8 V IDD Digital supply current -- 158 mA VDIO Digital input voltage -0.3 VDD + 0.3 V VAIO Analog1 -0.3 VDD + 0.3 V ID VDDA Maximum current single pin limit (applies to all digital pins) Analog supply voltage -25 25 mA VDD - 0.3 VDD + 0.3 V VUSB0_DP USB0_DP input voltage -0.3 3.63 V VUSB0_DM USB0_DM input voltage -0.3 3.63 V VREGIN USB regulator input -0.3 6.0 V RTC battery supply voltage -0.3 3.8 V VBAT 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal High Low 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 2. Input signal measurement reference 2.2 Nonswitching electrical specifications 6 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 General 2.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD - VDDA VDD-to-VDDA differential voltage -0.1 0.1 V VSS - VSSA VSS-to-VSSA differential voltage -0.1 0.1 V 1.71 3.6 V 0.7 x VDD -- V 0.75 x VDD -- V -- 0.35 x VDD V -- 0.3 x VDD V 0.06 x VDD -- V VBAT VIH RTC battery supply voltage Input high voltage * 2.7 V VDD 3.6 V Notes * 1.7 V VDD 2.7 V VIL Input low voltage * 2.7 V VDD 3.6 V * 1.7 V VDD 2.7 V VHYS Input hysteresis IICIO Analog and I/O pin DC injection current -- single pin 1 -3 -- mA -25 -- mA VDD VDD V 1.2 -- V VPOR_VBAT -- V * VIN < VSS-0.3V (Negative current injection) IICcont Contiguous pin DC injection current --regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins * Negative current injection VODPU Open drain pullup voltage level VRAM VDD voltage required to retain RAM VRFVBAT VBAT voltage required to retain the VBAT register file 2 1. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VIO_MIN-VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD. 2.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold -- high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds -- high range VLVW1H * Level 1 falling (LVWV=00) Notes 1 2.62 2.70 2.78 V Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 7 NXP Semiconductors General Table 2. VDD supply LVD and POR operating requirements (continued) Symbol Min. Typ. Max. Unit VLVW2H Description * Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H * Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H * Level 4 falling (LVWV=11) 2.92 3.00 3.08 V -- 80 -- mV 1.54 1.60 1.66 V VHYSH Low-voltage inhibit reset/recover hysteresis -- high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) Low-voltage warning thresholds -- low range 1 VLVW1L * Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L * Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L * Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L * Level 4 falling (LVWV=11) 2.04 2.10 2.16 V -- 60 -- mV VHYSL Low-voltage inhibit reset/recover hysteresis -- low range Notes VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period -- factory trimmed 900 1000 1100 s 1. Rising threshold is the sum of falling threshold and hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes 2.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH VOH IOHT Description Min. Typ. Max. Unit Notes 2.7 V VDD 3.6 V, IOH = -5 mA VDD - 0.5 -- -- V 1 1.71 V VDD 2.7 V, IOH = -2.5 mA VDD - 0.5 -- -- V 2.7 V VDD 3.6 V, IOH = -20 mA VDD - 0.5 -- -- V 1.71 V VDD 2.7 V, IOH = -10 mA VDD - 0.5 -- -- V Output high current total for all ports -- -- 100 mA Output high voltage -- Normal drive pad except RESET_B Output high voltage -- High drive pad except RESET_B 1 Table continues on the next page... 8 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 General Table 4. Voltage and current operating behaviors (continued) Symbol Min. Typ. Max. Unit Notes 2.7 V VDD 3.6 V, IOL = 5 mA -- -- 0.5 V 1 1.71 V VDD 2.7 V, IOL = 2.5 mA -- -- 0.5 V 2.7 V VDD 3.6 V, IOL = 20 mA -- -- 0.5 V 1.71 V VDD 2.7 V, IOL = 10 mA -- -- 0.5 V 2.7 V VDD 3.6 V, IOL = 3 mA -- -- 0.5 V 1.71 V VDD 2.7 V, IOL = 1.5 mA -- -- 0.5 V Output low current total for all ports -- -- 100 mA All pins other than high drive port pins -- 0.002 0.5 A High drive port pins -- 0.004 0.5 A Input leakage current (total all pins) for full temperature range -- -- 1.0 A 2 RPU Internal pullup resistors 20 -- 50 k 3 RPD Internal pulldown resistors 20 -- 50 k 4 VOL VOL VOL IOLT IIN IIN Description Output low voltage -- Normal drive pad except RESET_B Output low voltage -- High drive pad except RESET_B 1 Output low voltage -- RESET_B Input leakage current (per pin) for full temperature range 1, 2 1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD=3.6V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS 4. Measured at VDD supply voltage = VDD min and Vinput = VDD 2.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSxRUN recovery times in the following table assume this clock configuration: * * * * CPU and system clocks = 80 MHz Bus clock = 40 MHz Flash clock = 20 MHz MCG mode: FEI Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the Min. Typ. Max. Unit Notes -- -- 300 s 1 Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 9 NXP Semiconductors General Table 5. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- -- 140 s -- -- 140 s -- -- 80 s -- -- 80 s -- -- -- -- -- -- 5.7 s -- -- 5.7 s Notes first instruction across the operating temperature range of the chip. * VLLS0 RUN * VLLS1 RUN * VLLS2 RUN * VLLS3 RUN * LLS2 RUN 6 * LLS3 RUN s 6 s * VLPS RUN * STOP RUN 1. Normal boot (FTFA_OPT[LPBOOT]=1) 2.2.5 Power consumption operating behaviors The current parameters in the table below are derived from code executing a while(1) loop from flash, unless otherwise noted. The IDD typical values represent the statistical mean at 25C, and the IDD maximum values for RUN, WAIT, VLPR, and VLPW represent data collected at 125C junction temperature unless otherwise noted. The maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 6. Power consumption operating behaviors Symbol IDDA Description Analog supply current Min. Typ. Max. Unit Notes -- -- See note mA 1 -- 25.66 26.35 mA 2, 3, 4 IDD_HSRUN High Speed Run mode current - all peripheral clocks disabled, CoreMark benchmark code executing from flash @ 1.8V Table continues on the next page... 10 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- 25.75 26.44 mA @ 1.8V -- 23.6 24.29 mA @ 3.0V -- 23.7 24.39 mA @ 1.8V -- 31.9 32.59 mA @ 3.0V -- 32.0 32.69 mA @ 1.8V -- 15.8 16.49 mA @ 3.0V -- 15.8 16.49 mA @ 1.8V -- 14.00 15.50 mA @ 3.0V -- 14.00 15.69 mA @ 1.8V -- 15.3 15.99 mA @ 3.0V -- 15.4 16.09 mA -- 20.4 21.09 mA * @ 25C -- 20.5 21.19 mA * @ 70C -- 20.5 21.19 mA * @ 85C -- 20.5 21.19 mA * @ 105C -- 21.4 22.09 mA -- 14.0 14.69 mA * @ 25C -- 14.0 14.69 mA * @ 70C -- 14.0 14.69 mA * @ 85C -- 14.0 14.69 mA * @ 105C -- 15.0 15.69 mA -- 8.1 8.79 mA @ 3.0V Notes IDD_HSRUN High Speed Run mode current - all peripheral clocks disabled, code executing from flash 2 IDD_HSRUN High Speed Run mode current -- all peripheral clocks enabled, code executing from flash IDD_RUN IDD_RUN IDD_RUN IDD_RUN 5 Run mode current in Compute operation -- CoreMark benchmark code executing from flash 3, 4, 6 Run mode current in Compute operation -- code executing from flash 6 Run mode current -- all peripheral clocks disabled, code executing from flash 7 Run mode current -- all peripheral clocks enabled, code executing from flash @ 1.8V 8 @ 3.0V IDD_RUN Run mode current -- Compute operation, code executing from flash @ 1.8V 9 @ 3.0V IDD_WAIT Wait mode high frequency current at 3.0 V -- all peripheral clocks disabled 7 Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 11 NXP Semiconductors General Table 6. Power consumption operating behaviors (continued) Symbol Description IDD_WAIT Wait mode reduced frequency current at 3.0 V -- all peripheral clocks disabled IDD_VLPR Very-low-power run mode current in Compute operation -- CoreMark benchmark code executing from flash IDD_VLPR Min. Typ. Max. Unit Notes -- 4.4 5.09 mA 10 @ 1.8V -- 0.70 0.88 mA 3, 4, 11 @ 3.0V -- 0.70 0.88 mA 0.61 0.79 Very-low-power run mode current in Compute operation, code executing from flash @ 1.8V -- mA 11 @ 3.0V -- 0.61 0.79 mA IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks disabled -- 0.68 0.87 mA 12 IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks enabled -- 1.10 1.28 mA 13 IDD_VLPW Very-low-power wait mode current at 3.0 V -- all peripheral clocks disabled -- 0.38 0.57 mA 14 IDD_STOP Stop mode current at 3.0 V @ -40C to 25C -- 0.27 0.35 mA @ 70C -- 0.32 0.47 mA @ 85C -- 0.32 0.51 mA @ 105C -- 0.45 0.77 mA @ -40C to 25C -- 4.5 12.00 A @ 70C -- 16.8 42.40 A @ 85C -- 28.9 73.45 A @ 105C -- 60.8 141.90 A @ -40C to 25C -- 2.6 3.75 A @ 70C -- 6.6 12.00 A @ 85C -- 10.5 17.25 A @ 105C -- 21.0 40.70 A @ -40C to 25C -- 2.4 3.40 A @ 70C -- 5.3 8.90 A @ 85C -- 5.1 10.05 A @ 105C -- 15.9 28.85 A @ -40C to 25C -- 1.9 2.30 A @ 70C -- 4.8 8.10 A @ 85C -- 7.6 11.30 A IDD_VLPS IDD_LLS3 IDD_LLS2 Very-low-power stop mode current at 3.0 V Low leakage stop mode 3 current at 3.0 V Low leakage stop mode 2 current at 3.0 V IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V Table continues on the next page... 12 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- 15.3 27.65 A @ -40C to 25C -- 1.7 2.10 A @ 70C -- 3.4 4.85 A @ 85C -- 5.1 8.80 A @ 105C -- 9.8 15.70 A @ -40C to 25C -- 0.71 0.96 A @ 70C -- 1.79 2.10 A @ 85C -- 2.9 4.70 A @ 105C -- 5.7 8.10 A @ -40C to 25C -- 0.40 0.56 A @ 70C -- 1.39 1.70 A @ 85C -- 2.5 4.25 A @ 105C -- 5.3 7.50 A @ -40C to 25C -- 0.12 0.38 A @ 70C -- 1.05 1.38 A @ 85C -- 2.20 3.95 A @ 105C -- 4.9 7.10 A @ -40C to 25C -- 0.18 0.21 A @ 70C -- 0.66 0.86 A @ 85C -- 1.52 2.24 A @ 105C -- 2.92 4.30 A * @ -40C to 25C -- 0.59 0.70 A * @ 70C -- 1.00 1.3 A * @ 85C -- 1.76 2.59 A * @ 105C -- 3.00 4.42 A -- 0.71 0.84 A @ 105C Notes IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled IDD_VBAT IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V Average current when CPU is not accessing RTC registers @ 1.8V 15 @ 3.0V * @ -40C to 25C Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 13 NXP Semiconductors General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit * @ 70C -- 1.22 1.59 A * @ 85C -- 2.08 3.06 A * @ 105C -- 3.50 5.15 A Notes 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. Cache on and prefetch on, low compiler optimization. 4. Coremark benchmark compiled using IAR 7.2 with optimization level low. 5. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 6. 80 MHz core and system clock, 40 MHz bus clock, and 26.67 MHz flash clock. MCG configured for PEE mode. Compute operation. 7. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All peripheral clocks disabled. 8. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. 9. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. Compute operation. 10. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. 11. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute operation. Code executing from flash. 12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 15. Includes 32kHz oscillator current and RTC operation. Table 7. Low power mode peripheral adders--typical value Symbol Description Temperature (C) Unit -40 25 50 70 85 105 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 A IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. 52 52 52 52 52 52 A IEREFSTEN4MHz External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 228 237 245 251 258 uA IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by Table continues on the next page... 14 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 General Table 7. Low power mode peripheral adders--typical value (continued) Symbol Description Temperature (C) Unit -40 25 50 70 85 105 VLLS1 440 490 540 560 570 580 VLLS3 440 490 540 560 570 580 LLS 490 490 540 560 570 680 VLPS 510 560 560 560 610 680 STOP 510 560 560 560 610 680 48 Mhz internal reference clock 350 350 350 350 350 350 A ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 A IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 432 357 388 475 532 810 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. 66 66 66 66 66 66 A 214 237 246 254 260 268 entering all modes with the crystal enabled. I48MIRC MCGIRCLK (4 MHz internal reference clock) >OSCERCLK (4 MHz external crystal) nA IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. 45 45 45 45 45 45 A IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 42 42 42 42 42 42 A 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 15 NXP Semiconductors General * MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at frequencies between 50 MHz and 100MHz. MCG in PEE mode at frequencies greater than 100 MHz. * USB regulator disabled * No GPIOs toggled * Code execution from flash with cache enabled * For the ALLOFF curve, all peripheral clocks are disabled except FTFA Figure 3. Run mode supply current vs. core frequency 16 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 General Figure 4. VLPR mode supply current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 8. EMC radiated emissions operating behaviors for 64 LQFP package Parame Conditions ter VEME Clocks Frequency range Level (Typ.) Unit Notes dBuV 1, 2, 3 Device configuration, FSYS = 120 MHz test conditions and EM FBUS = 60 MHz testing per standard IEC External crystal = 8 MHz 61967-2. 150 kHz-50 MHz 14 50 MHz-150 MHz 23 150 MHz-500 MHz 23 Supply voltages: * VREGIN (USB) = 5.0 V * VDD = 3.3 V 500 MHz-1000 MHz 9 IEC level L 4 Temp = 25C 1. Measurements were made per IEC 61967-2 while the device was running typical application code. 2. Measurements were performed on the 64LQFP device, MK22FN512VLH12 . Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 17 NXP Semiconductors General 3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 4. IEC Level Maximums: M 18dBmV, L 24dBmV, K 30dBmV, I 36dBmV, H 42dBmV . 2.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: * Go to nxp.com * Perform a keyword search for "EMC design." 2.2.8 Capacitance attributes Table 9. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins -- 7 pF CIN_D Input capacitance: digital pins -- 7 pF 2.3 Switching specifications 2.3.1 Device clock specifications Table 10. Device clock specifications Symbol Description Min. Max. Unit Notes High Speed run mode fSYS System and core clock -- 120 MHz fBUS Bus clock -- 60 MHz Normal run mode (and High Speed run mode unless otherwise specified above) fSYS System and core clock -- 80 MHz System and core clock when Full Speed USB in operation 20 -- MHz Bus clock -- 50 MHz fFLASH Flash clock -- 26.67 MHz fLPTMR LPTMR clock -- 25 MHz -- 4 MHz fSYS_USB fBUS VLPR mode1 fSYS System and core clock Table continues on the next page... 18 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 General Table 10. Device clock specifications (continued) Symbol Min. Max. Unit Bus clock -- 4 MHz fFLASH Flash clock -- 1 MHz fERCLK External reference clock -- 16 MHz LPTMR clock -- 25 MHz -- 16 MHz fBUS fLPTMR_pin Description fLPTMR_ERCLK LPTMR external reference clock fI2S_MCLK I2S master clock -- 12.5 MHz fI2S_BCLK I2S bit clock -- 4 MHz Notes 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, and timers. Table 11. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1, 2 External RESET and NMI pin interrupt pulse width -- Asynchronous path 100 -- ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, passive filter disabled) -- Asynchronous path 50 -- ns 4 Mode select (EZP_CS) hold time after reset deassertion 2 -- Bus clock cycles Port rise and fall time * Slew disabled * 1.71 VDD 2.7V 5 -- -- * 2.7 VDD 3.6V * Slew enabled * 1.71 VDD 2.7V * 2.7 VDD 3.6V 10 ns 5 ns 30 ns 16 ns -- -- 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater of synchronous and asynchronous timing must be met. 3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be recognized. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 19 NXP Semiconductors General 4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized. 5. 25 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 12. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature -40 125 C TA Ambient temperature -40 105 C Notes 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + RJA x chip power dissipation. 2.4.2 Thermal attributes Board type Symbol Descripti on 121 XFBGA 100 LQFP 64 LQFP 64 MAPBGA Unit Notes Single-layer RJA (1s) Thermal 44.4 resistance, junction to ambient (natural convection) 61 67 47.3 C/W 1 Four-layer (2s2p) Thermal 27.0 resistance, junction to ambient (natural convection) 48 48 38.9 C/W 2 Single-layer RJMA (1s) Thermal 37.2 resistance, junction to ambient (200 ft./min. air speed) 51 55 40.1 C/W 3 Four-layer (2s2p) Thermal 23.7 resistance, junction to ambient (200 ft./min. air speed) 42 42 35.3 C/W 3 RJA RJMA Table continues on the next page... 20 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Board type Symbol Descripti on 121 XFBGA 100 LQFP 64 LQFP 64 MAPBGA Unit Notes -- RJB Thermal resistance, junction to board 23.5 34 31 35.4 C/W 4 -- RJC Thermal resistance, junction to case 17.4 16 16 29.2 C/W 5 -- JT Thermal 0.2 characteriz ation parameter, junction to package top outside center (natural convection) 3 3 0.4 C/W 6 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification. 2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air). 3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions--Forced Convection (Moving Air) with the board horizontal. 4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions--Junction-to-Board. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 3 Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 SWD electricals Table 13. SWD full voltage range electricals Symbol S1 Description Min. Max. Unit Operating voltage 1.71 3.6 V 0 33 MHz SWD_CLK frequency of operation * Serial wire debug Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 21 NXP Semiconductors Peripheral operating requirements and behaviors Table 13. SWD full voltage range electricals (continued) Symbol Description Min. Max. Unit S2 SWD_CLK cycle period 1/S1 -- ns S3 SWD_CLK clock pulse width 15 -- ns * Serial wire debug S4 SWD_CLK rise and fall times -- 3 ns S9 SWD_DIO input data setup time to SWD_CLK rise 8 -- ns S10 SWD_DIO input data hold time after SWD_CLK rise 1.4 -- ns S11 SWD_CLK high to SWD_DIO data valid -- 25 ns S12 SWD_CLK high to SWD_DIO high-Z 5 -- ns S2 S3 S3 SWD_CLK (input) S4 S4 Figure 5. Serial wire clock input timing SWD_CLK S9 SWD_DIO S10 Input data valid S11 SWD_DIO Output data valid S12 SWD_DIO S11 SWD_DIO Output data valid Figure 6. Serial wire data timing 22 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors 3.1.2 JTAG electricals Table 14. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz * Boundary Scan 0 10 * JTAG and CJTAG 0 20 1/J1 -- ns * Boundary Scan 50 -- ns * JTAG and CJTAG 25 -- ns J4 TCLK rise and fall times -- 3 ns J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 1 -- ns J7 TCLK low to boundary scan output data valid -- 25 ns J8 TCLK low to boundary scan output high-Z -- 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1 -- ns J11 TCLK low to TDO data valid -- 19 ns J12 TCLK low to TDO high-Z -- 19 ns J13 TRST assert time 100 -- ns J14 TRST setup time (negation) to TCLK high 8 -- ns J2 TCLK cycle period J3 TCLK clock pulse width Table 15. JTAG full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V TCLK frequency of operation MHz * Boundary Scan 0 10 * JTAG and CJTAG 0 15 1/J1 -- ns * Boundary Scan 50 -- ns * JTAG and CJTAG 33 -- ns J4 TCLK rise and fall times -- 3 ns J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 1.4 -- ns J7 TCLK low to boundary scan output data valid -- 27 ns J2 TCLK cycle period J3 TCLK clock pulse width Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 23 NXP Semiconductors Peripheral operating requirements and behaviors Table 15. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J8 TCLK low to boundary scan output high-Z -- 27 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1.4 -- ns J11 TCLK low to TDO data valid -- 26.2 ns J12 TCLK low to TDO high-Z -- 26.2 ns J13 TRST assert time 100 -- ns J14 TRST setup time (negation) to TCLK high 8 -- ns J2 J3 J3 TCLK (input) J4 J4 Figure 7. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 8. Boundary scan (JTAG) timing 24 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 9. Test Access Port timing TCLK J14 J13 TRST Figure 10. TRST timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 25 NXP Semiconductors Peripheral operating requirements and behaviors 3.3.1 MCG specifications Table 16. MCG specifications Symbol Description Min. Typ. Max. Unit Notes fints_ft Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25 C -- 32.768 -- kHz fints_t Total deviation of internal reference frequency (slow clock) over voltage and temperature -- +0.5/-0.7 2 % 31.25 -- 39.0625 kHz -- 0.3 0.6 %fdco 1 fints_t Internal reference frequency (slow clock) -- user trimmed fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using SCTRIM and SCFTRIM fdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature -- +0.5/-0.7 2 %fdco 1, 2 fdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70C -- 0.3 1.5 %fdco 1 Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25C -- 4 -- MHz fintf_ft Frequency deviation of internal reference clock (fast clock) over temperature and voltage -- factory trimmed at nominal VDD and 25 C -- +1/-2 5 %fintf_ft fintf_t Internal reference frequency (fast clock) -- user trimmed at nominal VDD and 25 C 3 -- 5 MHz fintf_ft floc_low Loss of external clock minimum frequency -- RANGE = 00 (3/5) x fints_t -- -- kHz floc_high Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 (16/5) x fints_t -- -- kHz 31.25 -- 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz -- 23.99 -- MHz -- 47.97 -- MHz -- 71.99 -- MHz FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 3, 4 640 x ffll_ref Mid range (DRS=01) 1280 x ffll_ref Mid-high range (DRS=10) 1920 x ffll_ref High range (DRS=11) 2560 x ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS=00) 5, 6 732 x ffll_ref Mid range (DRS=01) 1464 x ffll_ref Mid-high range (DRS=10) Table continues on the next page... 26 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Table 16. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit -- 95.98 -- MHz Notes 2197 x ffll_ref High range (DRS=11) 2929 x ffll_ref Jcyc_fll FLL period jitter -- * fVCO = 48 MHz * fVCO = 98 MHz tfll_acquire -- -- 180 -- ps -- 150 FLL target frequency acquisition time -- -- 1 ms 48.0 -- 120 MHz -- 1060 -- A -- 600 -- A 2.0 -- 4.0 MHz -- 120 -- ps -- 75 -- ps -- 1350 -- ps -- 600 -- ps 7 PLL fvco VCO operating frequency Ipll PLL operating current * PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) Ipll PLL operating current * PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) fpll_ref PLL reference frequency range Jcyc_pll PLL period jitter (RMS) * fvco = 48 MHz 8 8 9 * fvco = 100 MHz Jacc_pll PLL accumulated jitter over 1s (RMS) * fvco = 48 MHz 9 * fvco = 100 MHz Dlock Lock entry frequency tolerance 1.49 -- 2.98 % Dunl Lock exit frequency tolerance 4.47 -- 5.97 % tpll_lock Lock detector detection time -- -- 150 x 10-6 + 1075(1/ fpll_ref) s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. 2.0 V <= VDD <= 3.6 V. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 27 NXP Semiconductors Peripheral operating requirements and behaviors 3.3.2 IRC48M specifications Table 17. IRC48M specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDD48M Supply current -- 400 500 A firc48m Internal reference frequency -- 48 -- MHz -- 0.2 0.5 %firc48m 1 -- 0.4 1.0 %firc48m 1 firc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over 0C to 70C Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) Notes -- firc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over full temperature Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) firc48m_ol_lv Open loop total deviation of IRC48M frequency at low voltage (VDD=1.71V-1.89V) over full temperature 1 Regulator disable (USB_CLK_RECOVER_IRC_EN[REG_EN]=0) -- 0.4 1.0 Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) -- 0.5 1.5 firc48m_cl Closed loop total deviation of IRC48M frequency over voltage and temperature -- -- 0.1 Jcyc_irc48m Period Jitter (RMS) -- 35 150 ps Startup time -- 2 3 s tirc48mst %firc48m %fhost 2 3 1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard deviation (mean 3 sigma). 2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). 3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by one of the following settings: * USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 or * MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or * SIM_SOPT2[PLLFLLSEL]=11 3.3.3 Oscillator electrical specifications 28 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors 3.3.3.1 Oscillator DC electrical specifications Table 18. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDOSC IDDOSC Supply current -- low-power mode (HGO=0) Notes 1 * 32 kHz -- 500 -- nA * 4 MHz -- 200 -- A * 8 MHz (RANGE=01) -- 300 -- A * 16 MHz -- 950 -- A * 24 MHz -- 1.2 -- mA * 32 MHz -- 1.5 -- mA Supply current -- high-gain mode (HGO=1) 1 * 32 kHz -- 25 -- A * 4 MHz -- 400 -- A * 8 MHz (RANGE=01) -- 500 -- A * 16 MHz -- 2.5 -- mA * 24 MHz -- 3 -- mA * 32 MHz -- 4 -- mA Cx EXTAL load capacitance -- -- -- 2, 3 Cy XTAL load capacitance -- -- -- 2, 3 RF Feedback resistor -- low-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- low-frequency, high-gain mode (HGO=1) -- 10 -- M Feedback resistor -- high-frequency, lowpower mode (HGO=0) -- -- -- M Feedback resistor -- high-frequency, high-gain mode (HGO=1) -- 1 -- M Series resistor -- low-frequency, low-power mode (HGO=0) -- -- -- k Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Series resistor -- high-frequency, low-power mode (HGO=0) -- -- -- k -- 0 -- k -- 0.6 -- V RS 2, 4 Series resistor -- high-frequency, high-gain mode (HGO=1) Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 29 NXP Semiconductors Peripheral operating requirements and behaviors Table 18. Oscillator DC electrical specifications (continued) Symbol 1. 2. 3. 4. 5. Description Min. Typ. Max. Unit Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) -- VDD -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) -- VDD -- V Notes VDD=3.3 V, Temperature =25 C See crystal or resonator manufacturer's recommendation Cx and Cy can be provided by using either integrated capacitors or external components. When low-power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other device. 3.3.3.2 Symbol Oscillator frequency specifications Table 19. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency -- lowfrequency mode (MCG_C2[RANGE]=00) 32 -- 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency -- highfrequency mode (low range) (MCG_C2[RANGE]=01) 3 -- 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 -- 32 MHz fec_extal Input clock frequency (external clock mode) -- -- 50 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) -- 750 -- ms Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) -- 250 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) -- 0.6 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) -- 1 -- ms tcst Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 30 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.3.4 32 kHz oscillator electrical characteristics 3.3.4.1 32 kHz oscillator DC electrical specifications Table 20. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VBAT Supply voltage 1.71 -- 3.6 V Internal feedback resistor -- 100 -- M Cpara RF Parasitical capacitance of EXTAL32 and XTAL32 -- 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation -- 0.6 -- V 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.4.2 Symbol fosc_lo tstart 32 kHz oscillator frequency specifications Table 21. 32 kHz oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal -- 32.768 -- kHz Crystal start-up time Notes -- 1000 -- ms 1 fec_extal32 Externally provided input clock frequency -- 32.768 -- kHz 2 vec_extal32 Externally provided input clock amplitude 700 -- VBAT mV 2, 3 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 31 NXP Semiconductors Peripheral operating requirements and behaviors 3.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 22. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes thvpgm4 Longword Program high-voltage time -- 7.5 18 s -- thversscr Sector Erase high-voltage time -- 13 113 ms 1 thversall Erase All high-voltage time -- 104 904 ms 1 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications -- commands Table 23. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec2k tpgmchk Read 1s Section execution time (flash sector) -- -- 60 s 1 Program Check execution time -- -- 45 s 1 trdrsrc Read Resource execution time -- -- 30 s 1 tpgm4 Program Longword execution time -- 65 145 s -- tersscr Erase Flash Sector execution time -- 14 114 ms 2 trd1all Read 1s All Blocks execution time -- -- 1.8 ms 1 trdonce Read Once execution time -- -- 30 s 1 Program Once execution time -- 100 -- s -- tersall Erase All Blocks execution time -- 175 1300 ms 2 tvfykey Verify Backdoor Access Key execution time -- -- 30 s 1 tpgmonce 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 24. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit IDD_PGM Average current adder during high voltage flash programming operation -- 2.5 6.0 mA IDD_ERS Average current adder during high voltage flash erase operation -- 1.5 4.0 mA 32 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors 3.4.1.4 Symbol Reliability specifications Table 25. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 -- years -- tnvmretp1k Data retention after up to 1 K cycles 20 100 -- years -- nnvmcycp Cycling endurance 10 K 50 K -- cycles 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 C Tj 125 C. 3.4.2 EzPort switching specifications Table 26. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V EP1 EZP_CK frequency of operation (all commands except READ) -- fSYS/2 MHz EP1a EZP_CK frequency of operation (READ command) -- fSYS/8 MHz EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK -- ns EP3 EZP_CS input valid to EZP_CK high (setup) 5 -- ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 -- ns EP5 EZP_D input valid to EZP_CK high (setup) 2 -- ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 -- ns EP7 EZP_CK low to EZP_Q output valid -- 25 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 -- ns EP9 EZP_CS negation to EZP_Q tri-state -- 12 ns Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 33 NXP Semiconductors Peripheral operating requirements and behaviors EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 11. EzPort Timing Diagram 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 3.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the differential pins ADCx_DPx, ADCx_DMx. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.6.1.1 16-bit ADC operating conditions Table 27. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 -- 3.6 V VDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV Notes 2 Table continues on the next page... 34 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Table 27. 16-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes VSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage * 16-bit differential mode VREFL -- 31/32 * VREFH V * All other modes VREFL -- * 16-bit mode -- 8 10 * 8-bit / 10-bit / 12-bit modes -- 4 5 -- 2 5 CADIN RADIN RAS Input capacitance Input series resistance VREFH pF k Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz -- -- 5 k fADCK ADC conversion clock frequency 13-bit mode 1.0 -- 24.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 -- 12.0 MHz 4 Crate ADC conversion rate 13-bit modes No ADC hardware averaging 3 5 20 -- 1200 Ksps Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16-bit mode No ADC hardware averaging 5 37 -- 461 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 35 NXP Semiconductors Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 12. ADC input impedance equivalency diagram 3.6.1.2 16-bit ADC electrical characteristics Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes 0.215 -- 1.7 mA 3 * ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz * ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK * ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz * ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 IDDA_ADC Supply current ADC asynchronous clock source fADACK Sample Time TUE DNL INL See Reference Manual chapter for sample times Total unadjusted error * 12-bit modes -- 4 6.8 * <12-bit modes -- 1.4 2.1 Differential nonlinearity * 12-bit modes -- 0.7 -1.1 to +1.9 * <12-bit modes -- 0.2 * 12-bit modes -- 1.0 Integral non-linearity -0.3 to 0.5 -2.7 to +1.9 Table continues on the next page... 36 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description Conditions1 Min. Typ.2 Max. -- 0.5 -0.7 to +0.5 * 12-bit modes -- -4 -5.4 * <12-bit modes -- -1.4 -1.8 * 16-bit modes -- -1 to 0 -- * 13-bit modes -- -- 0.5 * <12-bit modes EFS EQ ENOB Full-scale error Quantization error Effective number of bits Unit Notes LSB4 VADIN = VDDA5 LSB4 16-bit differential mode 6 * Avg = 32 12.8 14.5 * Avg = 4 11.9 13.8 -- -- bits bits 16-bit single-ended mode * Avg = 32 * Avg = 4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit differential mode * Avg = 32 12.2 13.9 11.4 13.1 -- -- 6.02 x ENOB + 1.76 bits bits dB dB -- -94 7 -- dB 16-bit single-ended mode * Avg = 32 SFDR Spurious free dynamic range -- -85 82 95 16-bit differential mode * Avg = 32 16-bit single-ended mode 78 -- -- dB -- dB 7 90 * Avg = 32 EIL Input leakage error IIn x RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device VTEMP25 Temp sensor voltage 25 C 1.55 1.62 1.69 mV/C 8 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 37 NXP Semiconductors Peripheral operating requirements and behaviors 4. 5. 6. 7. 8. 1 LSB = (VREFH - VREFL)/2N ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 15.00 14.70 14.40 14.10 ENOB 13.80 13.50 13.20 12.90 12.60 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 12.30 12.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 13. Typical ENOB vs. ADC_CLK for 16-bit differential mode Typical ADC 16-bit Single-Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 14.00 13.75 13.50 13.25 13.00 ENOB 12.75 12.50 12.25 12.00 11.75 11.50 11.25 11.00 Averaging of 4 samples Averaging of 32 samples 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 38 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors 3.6.2 CMP and 6-bit DAC electrical specifications Table 29. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 200 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- -- 20 A VAIN Analog input voltage VSS - 0.3 -- VDD V VAIO Analog input offset voltage -- -- 20 mV * CR0[HYSTCTR] = 00 -- 5 -- mV * CR0[HYSTCTR] = 01 -- 10 -- mV * CR0[HYSTCTR] = 10 -- 20 -- mV * CR0[HYSTCTR] = 11 -- 30 -- mV VH Analog comparator hysteresis1 VCMPOh Output high VDD - 0.5 -- -- V VCMPOl Output low -- -- 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns -- -- 40 s -- 7 -- A Analog comparator initialization IDAC6b delay2 6-bit DAC current adder (enabled) INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB3 DNL 6-bit DAC differential non-linearity -0.3 -- 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 39 NXP Semiconductors Peripheral operating requirements and behaviors 0.08 0.07 CMP Hystereris (V) 0.06 HYSTCTR Setting 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 40 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP Hysteresis (V) 0.12 HYSTCTR Setting 0.1 00 01 10 11 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 16. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.6.3 12-bit DAC electrical characteristics 3.6.3.1 Symbol 12-bit DAC operating requirements Table 30. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.6 V VDACR Reference voltage 1.13 3.6 V 1 2 CL Output load capacitance -- 100 pF IL Output load current -- 1 mA Notes 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 41 NXP Semiconductors Peripheral operating requirements and behaviors 3.6.3.2 Symbol 12-bit DAC operating behaviors Table 31. 12-bit DAC operating behaviors Description IDDA_DACL Supply current -- low-power mode Min. Typ. Max. Unit -- -- 330 A -- -- 1200 A Notes P IDDA_DACH Supply current -- high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) -- low-power mode -- 100 200 s 1 tDACHP Full-scale settling time (0x080 to 0xF7F) -- high-power mode -- 15 30 s 1 tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode and high-speed mode -- 0.7 1 s 1 Vdacoutl DAC output voltage range low -- highspeed mode, no load, DAC set to 0x000 -- -- 100 mV Vdacouth DAC output voltage range high -- highspeed mode, no load, DAC set to 0xFFF VDACR -100 -- VDACR mV INL Integral non-linearity error -- high speed mode -- -- 8 LSB 2 DNL Differential non-linearity error -- VDACR > 2 V -- -- 1 LSB 3 DNL Differential non-linearity error -- VDACR = VREF_OUT -- -- 1 LSB 4 -- 0.4 0.8 %FSR 5 Gain error -- 0.1 0.6 %FSR 5 Power supply rejection ratio, VDDA 2.4 V 60 -- 90 dB TCO Temperature coefficient offset voltage -- 3.7 -- V/C TGE Temperature coefficient gain error -- 0.000421 -- %FSR/C Rop Output resistance (load = 3 k) -- -- 250 SR Slew rate -80h F7Fh 80h VOFFSET Offset error EG PSRR BW 6 V/s * High power (SPHP) 1.2 1.7 -- * Low power (SPLP) 0.05 0.12 -- 3dB bandwidth kHz * High power (SPHP) 550 -- -- * Low power (SPLP) 40 -- -- 1. 2. 3. 4. 5. 6. Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR - 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device 42 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 NXP Semiconductors Peripheral operating requirements and behaviors 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 17. Typical INL error vs. digital code Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 43 NXP Semiconductors Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 25 -40 55 85 105 125 Temperature C Figure 18. Offset at half scale vs. temperature 3.6.4 Voltage reference electrical specifications Table 32. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference. 2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. 44 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Table 33. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1920 1.1950 1.1980 V 1 Vout Voltage reference output with user trim at nominal VDDA and temperature=25C 1.1945 1.1950 1.1955 V 1 Vstep Voltage reference trim step -- 0.5 -- mV 1 Vtdrift Temperature drift (Vmax -Vmin across the full temperature range) -- -- 15 mV 1 Ibg Bandgap only current -- -- 80 A Ilp Low-power buffer current -- -- 360 uA 1 Ihp High-power buffer current -- -- 1 mA 1 V 1, 2 VLOAD Load regulation * current = 1.0 mA Tstup Buffer startup time Tchop_osc_st Internal bandgap start-up delay with chop oscillator enabled up Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) -- 200 -- -- -- 100 s -- -- 35 ms -- 2 -- mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 34. VREF limited-range operating requirements Symbol Description Min. Max. Unit TA Temperature 0 70 C Notes Table 35. VREF limited-range operating behaviors Symbol Vtdrift Description Temperature drift (Vmax -Vmin across the limited temperature range) Min. Max. Unit -- 10 mV Notes 3.7 Timers See General switching specifications. 3.8 Communication interfaces Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 45 NXP Semiconductors Peripheral operating requirements and behaviors 3.8.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit usb.org. NOTE The MCGPLLCLK meets the USB jitter and signaling rate specifications for certification with the use of an external clock/crystal for both Device and Host modes. The MCGFLLCLK does not meet the USB jitter or signaling rate specifications for certification. The IRC48M meets the USB jitter and signaling rate specifications for certification in Device mode when the USB clock recovery mode is enabled. It does not meet the USB signaling rate specifications for certification in Host mode operation. 3.8.2 USB VREG electrical specifications Table 36. USB VREG electrical specifications Symbol Description Min. Typ.1 Max. Unit VREGIN Input supply voltage 2.7 -- 5.5 V IDDon Quiescent current -- Run mode, load current equal zero, input supply (VREGIN) > 3.6 V -- 125 186 A IDDstby Quiescent current -- Standby mode, load current equal zero -- 1.1 10 A IDDoff Quiescent current -- Shutdown mode -- 650 -- nA -- -- 4 A * VREGIN = 5.0 V and temperature=25 C * Across operating voltage and temperature ILOADrun Maximum load current -- Run mode -- -- 120 mA ILOADstby Maximum load current -- Standby mode -- -- 1 mA VReg33out Regulator output voltage -- Input supply (VREGIN) > 3.6 V 3 3.3 3.6 V 2.1 2.8 3.6 V * Run mode * Standby mode Notes Table continues on the next page... 46 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Table 36. USB VREG electrical specifications (continued) Symbol Description Min. Typ.1 Max. Unit Notes VReg33out Regulator output voltage -- Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 -- 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 F ESR External output capacitor equivalent series resistance 1 -- 100 m ILIM Short circuit current -- 290 -- mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. 3.8.3 DSPI switching specifications (limited voltage range) The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 37. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation -- 30 MHz 2 x tBUS -- ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 2 -- ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 2 -- ns 2 DS5 DSPI_SCK to DSPI_SOUT valid -- 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid -2 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 16.2 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 47 NXP Semiconductors Peripheral operating requirements and behaviors DSPI_PCSn DS3 DS4 DS8 DS7 (CPOL=0) DS1 DS2 DSPI_SCK DSPI_SIN Data First data DSPI_SOUT Last data DS5 DS6 First data Data Last data Figure 19. DSPI classic SPI timing -- master mode Table 38. Slave mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation -- 15 MHz 4 x tBUS -- ns (tSCK/2) - 2 (tSCK/2) + 2 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid -- 21.4 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 2.6 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 17 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 17 ns Notes 1 1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus clock is 60 MHz, the SPI clock must not be greater than 10 MHz. DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DSPI_SOUT First data DS13 DSPI_SIN DS12 DS16 DS11 Data Last data DS14 First data Data Last data Figure 20. DSPI classic SPI timing -- slave mode 48 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors 3.8.4 DSPI switching specifications (full voltage range) The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 39. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit Notes 1.71 3.6 V 1 -- 15 MHz 4 x tBUS -- ns DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 4 -- ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 4 -- ns 3 DS5 DSPI_SCK to DSPI_SOUT valid -- 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 24.6 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DSPI_SCK (CPOL=0) DSPI_SIN DSPI_SOUT DS7 DS1 DS2 DS4 DS8 First data First data Data Last data DS5 DS6 Data Last data Figure 21. DSPI classic SPI timing -- master mode Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 49 NXP Semiconductors Peripheral operating requirements and behaviors Table 40. Slave mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V -- 7.5 MHz 8 x tBUS -- ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS11 DSPI_SCK to DSPI_SOUT valid -- 29.5 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 3.2 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 25 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 25 ns DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 22. DSPI classic SPI timing -- slave mode 3.8.5 Inter-Integrated Circuit Interface (I2C) timing Table 41. I 2C timing Characteristic Symbol Standard Mode Fast Mode Minimum Maximum Minimum Maximum Unit SCL Clock Frequency fSCL 0 100 0 4001 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 -- 0.6 -- s LOW period of the SCL clock tLOW 4.7 -- 1.25 -- s HIGH period of the SCL clock tHIGH 4 -- 0.6 -- s Set-up time for a repeated START condition tSU; STA 4.7 -- 0.6 -- s Table continues on the next page... 50 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Table 41. I 2C timing (continued) Characteristic Data hold time for I2C Symbol bus devices Data set-up time Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum tHD; DAT 02 3.453 04 0.92 s tSU; DAT 2505 -- 1003, 6 Rise time of SDA and SCL signals tr -- 1000 -- ns 7 300 ns 6 20 +0.1Cb Fall time of SDA and SCL signals tf -- 300 20 +0.1Cb 300 ns Set-up time for STOP condition tSU; STO 4 -- 0.6 -- s Bus free time between STOP and START condition tBUF 4.7 -- 1.3 -- s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the High drive pins across the full voltage range and when using the Normal drive pins and VDD 2.7 V. 2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 7. Cb = total capacitance of the one bus line in pF. Table 42. I 2C 1 Mbps timing Characteristic Symbol Minimum Maximum Unit MHz SCL Clock Frequency fSCL 0 11 Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 0.26 -- s LOW period of the SCL clock tLOW 0.5 -- s HIGH period of the SCL clock tHIGH 0.26 -- s Set-up time for a repeated START condition tSU; STA 0.26 -- s Data hold time for I2C bus devices tHD; DAT 0 -- s Data set-up time tSU; DAT 50 Rise time of SDA and SCL signals tr -- ns ,2 120 ns 2 20 +0.1Cb Fall time of SDA and SCL signals tf 20 +0.1Cb 120 ns Set-up time for STOP condition tSU; STO 0.26 -- s Bus free time between STOP and START condition tBUF 0.5 -- s Pulse width of spikes that must be suppressed by the input filter tSP 0 50 ns Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 51 NXP Semiconductors Peripheral operating requirements and behaviors 1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across the full voltage range. 2. Cb = total capacitance of the one bus line in pF. SDA tf tLOW tSU; DAT tr tf tHD; STA tr tSP tBUF SCL S HD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 23. Timing definition for devices on the I2C bus 3.8.6 UART switching specifications See General switching specifications. 3.8.7 I2S/SAI switching specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. 3.8.7.1 Normal Run, Wait and Stop mode performance over a limited operating voltage range This section provides the operating performance over a limited operating voltage for the device in Normal Run, Wait and Stop modes. Table 43. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.6 V S1 I2S_MCLK cycle time 40 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period Table continues on the next page... 52 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Table 43. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage range) (continued) Num. Characteristic Min. Max. Unit S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 18 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 24. I2S/SAI timing -- master modes Table 44. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 4.5 -- ns Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 53 NXP Semiconductors Peripheral operating requirements and behaviors Table 44. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage range) (continued) Num. Characteristic Min. Max. Unit S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 20 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 4.5 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 2 -- ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 -- 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 25. I2S/SAI timing -- slave modes 3.8.7.2 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 45. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period Table continues on the next page... 54 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Table 45. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid -1.0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 27 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 26. I2S/SAI timing -- master modes Table 46. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 5.8 -- ns Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 55 NXP Semiconductors Peripheral operating requirements and behaviors Table 46. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 28.5 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 5.8 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 2 -- ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 -- 26.3 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 27. I2S/SAI timing -- slave modes 3.8.7.3 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 47. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 -- ns Table continues on the next page... 56 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Peripheral operating requirements and behaviors Table 47. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 45 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid -1 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 45 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 45 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 28. I2S/SAI timing -- master modes Table 48. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 30 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 7 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 63 ns Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 57 NXP Semiconductors Dimensions Table 48. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 30 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 4 -- ns -- 72 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 29. I2S/SAI timing -- slave modes 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing's document number: If you want the drawing for this package Then use this document number 64-pin LQFP 98ASS23234W 64-pin MAPBGA 98ASA00420D 100-pin LQFP 98ASS23308W 121-pin XFBGA 98ASA00595D 58 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Pinout 5 Pinout 5.1 K22F Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 121 100 64 64 BGA LQFP LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 E4 1 1 A1 PTE0/ ADC1_ CLKOUT32 SE4a K ADC1_ SE4a PTE0/ SPI1_ CLKOUT32 PCS1 K UART1_TX I2C1_SDA RTC_ CLKOUT E3 2 2 B1 PTE1/ LLWU_P0 ADC1_ SE5a ADC1_ SE5a PTE1/ LLWU_P0 SPI1_ SOUT UART1_RX I2C1_SCL SPI1_SIN E2 3 -- -- PTE2/ LLWU_P1 ADC1_ SE6a ADC1_ SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_ CTS_b F4 4 -- -- PTE3 ADC1_ SE7a ADC1_ SE7a PTE3 SPI1_SIN UART1_ RTS_b H7 5 -- -- PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_ PCS0 LPUART0_ TX G4 6 -- -- PTE5 DISABLED PTE5 SPI1_ PCS2 LPUART0_ RX F3 7 -- -- PTE6 DISABLED PTE6 SPI1_ PCS3 LPUART0_ I2S0_ CTS_b MCLK E6 8 3 C5 VDD VDD VDD G7 9 4 C4 VSS VSS VSS L6 -- -- -- VSS VSS VSS F1 10 5 E1 USB0_DP USB0_DP USB0_DP F2 11 6 D1 USB0_DM USB0_DM USB0_DM G1 12 7 E2 VOUT33 VOUT33 VOUT33 G2 13 8 D2 VREGIN VREGIN VREGIN H1 14 -- -- ADC0_DP1 ADC0_DP1 ADC0_DP1 H2 15 -- -- ADC0_ DM1 J1 16 -- -- ADC1_ ADC1_ ADC1_ DP1/ DP1/ DP1/ ADC0_DP2 ADC0_DP2 ADC0_DP2 J2 17 -- -- ADC1_ DM1/ ADC0_ DM2 ADC0_ DM1 ADC1_ DM1/ ADC0_ DM2 EzPort SPI1_ SOUT USB_SOF_ OUT ADC0_ DM1 ADC1_ DM1/ ADC0_ DM2 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 59 NXP Semiconductors Pinout 121 100 64 64 BGA LQFP LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 K1 18 9 G1 ADC0_ ADC0_ ADC0_ DP0/ DP0/ DP0/ ADC1_DP3 ADC1_DP3 ADC1_DP3 K2 19 10 F1 ADC0_ DM0/ ADC1_ DM3 L1 20 11 G2 ADC1_ ADC1_ ADC1_ DP0/ DP0/ DP0/ ADC0_DP3 ADC0_DP3 ADC0_DP3 L2 21 12 F2 ADC1_ DM0/ ADC0_ DM3 ADC1_ DM0/ ADC0_ DM3 ADC1_ DM0/ ADC0_ DM3 F5 22 13 F4 VDDA VDDA VDDA G5 23 14 G4 VREFH VREFH VREFH G6 24 15 G3 VREFL VREFL VREFL F6 25 16 F3 VSSA VSSA VSSA L3 26 17 H1 VREF_ OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_ SE18 VREF_ OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_ SE18 VREF_ OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_ SE18 K5 27 18 H2 DAC0_ OUT/ CMP1_IN3/ ADC0_ SE23 DAC0_ OUT/ CMP1_IN3/ ADC0_ SE23 DAC0_ OUT/ CMP1_IN3/ ADC0_ SE23 K4 -- -- -- CMP0_IN4/ CMP0_IN4/ CMP0_IN4/ ADC1_ ADC1_ ADC1_ SE23 SE23 SE23 L7 -- -- -- RTC_ RTC_ RTC_ WAKEUP_ WAKEUP_ WAKEUP_ B B B L4 28 19 H3 XTAL32 XTAL32 XTAL32 L5 29 20 H4 EXTAL32 EXTAL32 EXTAL32 K6 30 21 H5 VBAT VBAT VBAT H5 31 -- -- PTE24 ADC0_ SE17 ADC0_ SE17 PTE24 I2C0_SCL EWM_ OUT_b J5 32 -- -- PTE25 ADC0_ SE18 ADC0_ SE18 PTE25 I2C0_SDA EWM_IN H6 33 -- -- PTE26/ DISABLED CLKOUT32 K 60 NXP Semiconductors ADC0_ DM0/ ADC1_ DM3 ALT7 EzPort ADC0_ DM0/ ADC1_ DM3 PTE26/ CLKOUT32 K RTC_ CLKOUT USB_ CLKIN Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Pinout 121 100 64 64 BGA LQFP LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort J6 34 22 D3 PTA0 JTAG_ TCLK/ SWD_CLK/ EZP_CLK PTA0 UART0_ CTS_b FTM0_CH5 JTAG_ TCLK/ SWD_CLK EZP_CLK H8 35 23 D4 PTA1 JTAG_TDI/ EZP_DI PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI J7 36 24 E5 PTA2 JTAG_ TDO/ TRACE_ SWO/ EZP_DO PTA2 UART0_TX FTM0_CH7 JTAG_ TDO/ TRACE_ SWO EZP_DO H9 37 25 D5 PTA3 JTAG_ TMS/ SWD_DIO PTA3 UART0_ RTS_b FTM0_CH0 JTAG_ TMS/ SWD_DIO J8 38 26 G5 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b K7 39 27 F5 PTA5 DISABLED PTA5 E5 40 -- -- VDD VDD VDD G3 41 -- -- VSS VSS VSS K8 42 28 H6 PTA12 DISABLED L8 43 29 G6 PTA13/ LLWU_P4 K9 44 -- -- L9 45 -- J10 46 H10 FTM0_CH2 I2S0_TX_ BCLK PTA12 FTM1_CH0 I2S0_TXD0 FTM1_QD_ PHA DISABLED PTA13/ LLWU_P4 FTM1_CH1 I2S0_TX_ FS PTA14 DISABLED PTA14 SPI0_ PCS0 UART0_TX I2S0_RX_ BCLK -- PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0 -- -- PTA16 DISABLED PTA16 SPI0_ SOUT UART0_ CTS_b I2S0_RX_ FS 47 -- -- PTA17 ADC1_ SE17 ADC1_ SE17 PTA17 SPI0_SIN UART0_ RTS_b I2S0_ MCLK L10 48 30 G7 VDD VDD VDD K10 49 31 H7 VSS VSS VSS L11 50 32 H8 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_ FLT2 FTM_ CLKIN0 K11 51 33 G8 PTA19 XTAL0 XTAL0 PTA19 FTM1_ FLT0 FTM_ CLKIN1 J11 52 34 F8 RESET_b RESET_b RESET_b G11 53 35 F7 PTB0/ LLWU_P5 ADC0_ ADC0_ PTB0/ SE8/ SE8/ LLWU_P5 ADC1_SE8 ADC1_SE8 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA G10 54 36 F6 PTB1 ADC0_ ADC0_ PTB1 SE9/ SE9/ ADC1_SE9 ADC1_SE9 I2C0_SDA FTM1_CH1 FTM1_QD_ PHB G9 55 37 E7 PTB2 ADC0_ SE12 I2C0_SCL UART0_ RTS_b FTM0_ FLT3 ADC0_ SE12 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 PTB2 USB_ CLKIN EZP_CS_b JTAG_ TRST_b FTM1_QD_ PHB LPTMR0_ ALT1 61 NXP Semiconductors Pinout 121 100 64 64 BGA LQFP LQFP MAP BGA Pin Name G8 56 38 E8 PTB3 ADC0_ SE13 ADC0_ SE13 PTB3 F11 -- -- -- PTB6 ADC1_ SE12 ADC1_ SE12 PTB6 E11 -- -- -- PTB7 ADC1_ SE13 ADC1_ SE13 PTB7 D11 -- -- -- PTB8 DISABLED PTB8 E10 57 -- -- PTB9 DISABLED PTB9 SPI1_ PCS1 LPUART0_ CTS_b D10 58 -- -- PTB10 ADC1_ SE14 ADC1_ SE14 PTB10 SPI1_ PCS0 LPUART0_ RX FTM0_ FLT1 C10 59 -- -- PTB11 ADC1_ SE15 ADC1_ SE15 PTB11 SPI1_SCK LPUART0_ TX FTM0_ FLT2 -- 60 -- -- VSS VSS VSS -- 61 -- -- VDD VDD VDD B10 62 39 E6 PTB16 DISABLED PTB16 SPI1_ SOUT UART0_RX FTM_ CLKIN0 EWM_IN E9 63 40 D7 PTB17 DISABLED PTB17 SPI1_SIN UART0_TX FTM_ CLKIN1 EWM_ OUT_b D9 64 41 D6 PTB18 DISABLED PTB18 FTM2_CH0 I2S0_TX_ BCLK FTM2_QD_ PHA C9 65 42 C7 PTB19 DISABLED PTB19 FTM2_CH1 I2S0_TX_ FS FTM2_QD_ PHB F10 66 -- -- PTB20 DISABLED PTB20 CMP0_ OUT F9 67 -- -- PTB21 DISABLED PTB21 CMP1_ OUT F8 68 -- -- PTB22 DISABLED PTB22 E8 69 -- -- PTB23 DISABLED PTB23 B9 70 43 D8 PTC0 ADC0_ SE14 ADC0_ SE14 PTC0 SPI0_ PCS4 PDB0_ EXTRG USB_SOF_ OUT D8 71 44 C6 PTC1/ LLWU_P6 ADC0_ SE15 ADC0_ SE15 PTC1/ LLWU_P6 SPI0_ PCS3 UART1_ RTS_b FTM0_CH0 I2S0_TXD0 LPUART0_ RTS_b C8 72 45 B7 PTC2 ADC0_ ADC0_ PTC2 SE4b/ SE4b/ CMP1_IN0 CMP1_IN0 SPI0_ PCS2 UART1_ CTS_b FTM0_CH1 I2S0_TX_ FS LPUART0_ CTS_b B8 73 46 C8 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_ PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_ BCLK LPUART0_ RX -- 74 47 E3 VSS VSS VSS -- 75 48 E4 VDD VDD VDD A8 76 49 B8 PTC4/ LLWU_P8 DISABLED SPI0_ PCS0 UART1_TX FTM0_CH3 CMP1_ OUT LPUART0_ TX 62 NXP Semiconductors Default ALT0 ALT1 PTC4/ LLWU_P8 ALT2 I2C0_SDA ALT3 ALT4 ALT5 UART0_ CTS_b ALT6 ALT7 EzPort FTM0_ FLT0 LPUART0_ RTS_b SPI0_ PCS5 Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Pinout 121 100 64 64 BGA LQFP LQFP MAP BGA Pin Name Default D7 77 50 A8 PTC5/ LLWU_P9 DISABLED C7 78 51 A7 B7 79 52 A7 80 D6 ALT1 ALT2 ALT3 ALT4 PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 CMP0_ OUT PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_ LLWU_P10 LLWU_P10 SOUT PDB0_ EXTRG I2S0_RX_ BCLK I2S0_ MCLK B6 PTC7 CMP0_IN1 CMP0_IN1 PTC7 USB_SOF_ I2S0_RX_ OUT FS 53 A6 PTC8 ADC1_ ADC1_ PTC8 SE4b/ SE4b/ CMP0_IN2 CMP0_IN2 I2S0_ MCLK 81 54 B5 PTC9 ADC1_ ADC1_ PTC9 SE5b/ SE5b/ CMP0_IN3 CMP0_IN3 I2S0_RX_ BCLK C6 82 55 B4 PTC10 ADC1_ SE6b ADC1_ SE6b PTC10 C5 83 56 A5 PTC11/ ADC1_ LLWU_P11 SE7b ADC1_ SE7b PTC11/ I2C1_SDA LLWU_P11 B6 84 -- -- PTC12 DISABLED PTC12 A6 85 -- -- PTC13 DISABLED PTC13 A5 86 -- -- PTC14 DISABLED PTC14 B5 87 -- -- PTC15 DISABLED PTC15 -- 88 -- -- VSS VSS VSS -- 89 -- -- VDD VDD VDD D5 90 -- -- PTC16 DISABLED PTC16 LPUART0_ RX C4 91 -- -- PTC17 DISABLED PTC17 LPUART0_ TX B4 92 -- -- PTC18 DISABLED PTC18 LPUART0_ RTS_b A4 -- -- -- PTC19 DISABLED PTC19 LPUART0_ CTS_b D4 93 57 C3 PTD0/ DISABLED LLWU_P12 PTD0/ SPI0_ LLWU_P12 PCS0 UART2_ RTS_b LPUART0_ RTS_b D3 94 58 A4 PTD1 PTD1 UART2_ CTS_b LPUART0_ CTS_b C3 95 59 C2 PTD2/ DISABLED LLWU_P13 PTD2/ SPI0_ LLWU_P13 SOUT UART2_RX LPUART0_ I2C0_SCL RX B3 96 60 B3 PTD3 PTD3 UART2_TX LPUART0_ I2C0_SDA TX A3 97 61 A3 PTD4/ DISABLED LLWU_P14 A2 98 62 C1 PTD5 ADC0_ SE6b ADC0_ SE6b F7 -- -- -- VSS VSS VSS E7 -- -- -- VDD VDD VDD ADC0_ SE5b ALT0 ADC0_ SE5b DISABLED Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 SPI0_SIN I2C1_SCL SPI0_SCK SPI0_SIN ALT5 ALT6 ALT7 FTM0_CH2 FTM2_ FLT0 I2S0_RX_ FS PTD4/ SPI0_ LLWU_P14 PCS1 UART0_ RTS_b FTM0_CH4 EWM_IN SPI1_ PCS0 PTD5 UART0_ CTS_b FTM0_CH5 EWM_ OUT_b SPI1_SCK SPI0_ PCS2 EzPort 63 NXP Semiconductors Pinout 121 100 64 64 BGA LQFP LQFP MAP BGA Pin Name Default ALT0 B2 99 63 B2 PTD6/ ADC0_ LLWU_P15 SE7b ADC0_ SE7b A1 100 64 A2 PTD7 DISABLED A11 -- -- -- NC NC NC K3 -- -- -- NC NC NC H4 -- -- -- NC NC NC B11 -- -- -- NC NC NC C11 -- -- -- NC NC NC H11 -- -- -- NC NC NC C1 -- -- -- NC NC NC D2 -- -- -- NC NC NC D1 -- -- -- NC NC NC E1 -- -- -- NC NC NC J3 -- -- -- NC NC NC H3 -- -- -- NC NC NC J9 -- -- -- NC NC NC J4 -- -- -- NC NC NC A10 -- -- -- NC NC NC A9 -- -- -- NC NC NC B1 -- -- -- NC NC NC C2 -- -- -- NC NC NC ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 PTD6/ SPI0_ LLWU_P15 PCS3 UART0_RX FTM0_CH6 FTM0_ FLT0 SPI1_ SOUT PTD7 UART0_TX FTM0_CH7 FTM0_ FLT1 SPI1_SIN EzPort 5.2 Recommended connection for unused analog and digital pins The following table shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application. Table 49. Recommended connection for unused analog interfaces Pin Type Short recommendation Detailed recommendation Analog/non GPIO PGAx/ADCx Float Analog input - Float Analog/non GPIO ADCx/CMPx Float Analog input - Float Analog/non GPIO VREF_OUT Float Analog output - Float Analog/non GPIO DACx_OUT Float Analog output - Float Analog/non GPIO RTC_WAKEUP_B Float Analog output - Float Analog/non GPIO XTAL32 Float Analog output - Float Analog/non GPIO EXTAL32 Float Analog input - Float Table continues on the next page... 64 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Pinout Table 49. Recommended connection for unused analog interfaces (continued) Pin Type Short recommendation Detailed recommendation GPIO/Analog PTA18/EXTAL0 Float Analog input - Float GPIO/Analog PTA19/XTAL0 Float Analog output - Float GPIO/Analog PTx/ADCx Float Float (default is analog input) GPIO/Analog PTx/CMPx Float Float (default is analog input) GPIO/Digital PTA0/JTAG_TCLK Float Float (default is JTAG with pulldown) GPIO/Digital PTA1/JTAG_TDI Float Float (default is JTAG with pullup) GPIO/Digital PTA2/JTAG_TDO Float Float (default is JTAG with pullup) GPIO/Digital PTA3/JTAG_TMS Float Float (default is JTAG with pullup) GPIO/Digital PTA4/NMI_b 10k pullup or disable and float Pull high or disable in PCR & FOPT and float GPIO/Digital PTx Float Float (default is disabled) USB USB0_DP Float Float USB USB0_DM Float Float USB VOUT33 Tie to input and ground through 10k Tie to input and ground through 10k USB VREGIN Tie to output and ground through 10k Tie to output and ground through 10k VBAT VBAT Float Float VDDA VDDA Always connect to VDD potential Always connect to VDD potential VREFH VREFH Always connect to VDD potential Always connect to VDD potential VREFL VREFL Always connect to VSS potential Always connect to VSS potential VSSA VSSA Always connect to VSS potential Always connect to VSS potential 5.3 K22F Pinouts The following figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 65 NXP Semiconductors PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ADC0_DP0/ADC1_DP3 9 40 PTB17 ADC0_DM0/ADC1_DM3 10 39 PTB16 ADC1_DP0/ADC0_DP3 11 38 PTB3 ADC1_DM0/ADC0_DM3 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 RESET_b VSSA 16 33 PTA19 32 PTB18 PTA18 41 31 8 VSS VREGIN 30 PTB19 VDD 42 29 7 PTA13/LLWU_P4 VOUT33 28 PTC0 PTA12 43 27 6 PTA5 USB0_DM 26 PTC1/LLWU_P6 PTA4/LLWU_P3 44 25 5 PTA3 USB0_DP 24 PTC2 PTA2 45 23 4 PTA1 VSS 22 PTC3/LLWU_P7 PTA0 46 21 3 VBAT VDD 20 VSS EXTAL32 47 19 2 XTAL32 PTE1/LLWU_P0 18 VDD DAC0_OUT/CMP1_IN3/ADC0_SE23 48 17 1 VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 PTE0/CLKOUT32K Figure 30. K22F 64 LQFP Pinout Diagram (top view) 66 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Pinout A B 1 2 3 4 5 6 PTE0/ CLKOUT32K PTD7 PTD4/ LLWU_P14 PTD1 PTC11/ LLWU_P11 PTC8 PTD3 PTC10 PTC9 PTC7 VSS VDD PTE1/ PTD6/ LLWU_P0 LLWU_P15 PTD2/ PTD0/ LLWU_P13 LLWU_P12 7 8 PTC6/ PTC5/ LLWU_P10 LLWU_P9 A PTC2 PTC4/ LLWU_P8 B PTC1/ LLWU_P6 PTB19 PTC3/ LLWU_P7 C C PTD5 D USB0_DM VREGIN PTA0 PTA1 PTA3 PTB18 PTB17 PTC0 D E USB0_DP VOUT33 VSS VDD PTA2 PTB16 PTB2 PTB3 E F ADC0_DM0/ ADC1_DM0/ ADC1_DM3 ADC0_DM3 VSSA VDDA PTA5 PTB1 PTB0/ LLWU_P5 RESET_b F G ADC0_DP0/ ADC1_DP0/ ADC1_DP3 ADC0_DP3 VREFL VREFH PTA4/ LLWU_P3 PTA13/ LLWU_P4 VDD PTA19 G H VREF_OUT/ DAC0_OUT/ CMP1_IN5/ CMP1_IN3/ CMP0_IN5/ ADC0_SE23 ADC1_SE18 XTAL32 EXTAL32 VBAT PTA12 VSS PTA18 H 3 4 5 6 7 8 1 2 Figure 31. K22F 64 MAPBGA Pinout Diagram (transparent top view) Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 67 NXP Semiconductors PTC17 PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 90 89 88 87 86 85 84 83 82 81 80 PTC4/LLWU_P8 PTC18 92 91 76 PTD0/LLWU_P12 PTC5/LLWU_P9 PTD1 93 77 PTD2/LLWU_P13 94 PTC7 PTD3 96 95 PTC6/LLWU_P10 PTD4/LLWU_P14 78 PTD5 98 97 79 PTD6/LLWU_P15 PTD7 1 100 PTE0/CLKOUT32K 99 Pinout 75 VDD PTE1/LLWU_P0 2 74 VSS PTE2/LLWU_P1 3 73 PTC3/LLWU_P7 PTE3 4 72 PTC2 PTE4/LLWU_P2 5 71 PTC1/LLWU_P6 PTC0 PTE5 6 70 PTE6 7 69 PTB23 VDD 8 68 PTB22 VSS 9 67 PTB21 PTB20 USB0_DP 10 66 USB0_DM 11 65 PTB19 VOUT33 12 64 PTB18 VREGIN 13 63 PTB17 ADC0_DP1 14 62 PTB16 ADC0_DM1 15 61 VDD ADC1_DP1/ADC0_DP2 16 60 VSS ADC1_DM1/ADC0_DM2 17 59 PTB11 ADC0_DP0/ADC1_DP3 18 58 PTB10 ADC0_DM0/ADC1_DM3 19 57 PTB9 ADC1_DP0/ADC0_DP3 20 56 PTB3 48 49 50 VDD VSS PTA18 42 PTA12 47 41 VSS 46 40 VDD PTA17 39 PTA5 PTA16 38 PTA4/LLWU_P3 45 37 PTA3 PTA15 36 PTA2 44 35 PTA1 PTA14 34 PTA0 43 33 PTE26/CLKOUT32K PTA13/LLWU_P4 32 PTA19 PTE25 51 31 25 30 VSSA VBAT RESET_b PTE24 PTB0/LLWU_P5 52 29 53 24 28 23 VREFL XTAL32 VREFH EXTAL32 PTB1 27 PTB2 54 26 55 22 DAC0_OUT/CMP1_IN3/ADC0_SE23 21 VDDA VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 ADC1_DM0/ADC0_DM3 Figure 32. K22F 100 LQFP Pinout Diagram (top view) 68 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Part identification 1 2 3 4 5 6 7 8 9 10 11 A PTD7 PTD5 PTD4/ LLWU_P14 PTC19 PTC14 PTC13 PTC8 PTC4/ LLWU_P8 NC NC NC A B NC PTD6/ LLWU_P15 PTD3 PTC18 PTC15 PTC12 PTC7 PTC3/ LLWU_P7 PTC0 PTB16 NC B C NC NC PTD2/ LLWU_P13 PTC17 PTC11/ LLWU_P11 PTC10 PTC6/ LLWU_P10 PTC2 PTB19 PTB11 NC C D NC NC PTD1 PTD0/ LLWU_P12 PTC16 PTC9 PTC5/ LLWU_P9 PTC1/ LLWU_P6 PTB18 PTB10 PTB8 D E NC PTE2/ LLWU_P1 VDD VDD VDD PTB23 PTB17 PTB9 PTB7 E F USB0_DP USB0_DM PTE6 PTE3 VDDA VSSA VSS PTB22 PTB21 PTB20 PTB6 F G VOUT33 VREGIN VSS PTE5 VREFH VREFL VSS PTB3 PTB2 PTB1 PTB0/ LLWU_P5 G PTA1 PTA3 PTA17 NC H PTE1/ PTE0/ LLWU_P0 CLKOUT32K H ADC0_DP1 ADC0_DM1 NC NC PTE24 J ADC1_DP1/ ADC1_DM1/ ADC0_DP2 ADC0_DM2 NC NC PTE25 K ADC0_DP0/ ADC0_DM0/ ADC1_DP3 ADC1_DM3 NC L VREF_OUT/ ADC1_DP0/ ADC1_DM0/ CMP1_IN5/ ADC0_DP3 ADC0_DM3 CMP0_IN5/ ADC1_SE18 1 2 PTE26/ PTE4/ CLKOUT32K LLWU_P2 CMP0_IN4/ DAC0_OUT/ ADC1_SE23 CMP1_IN3/ ADC0_SE23 PTA0 PTA2 PTA4/ LLWU_P3 NC PTA16 RESET_b J VBAT PTA5 PTA12 PTA14 VSS PTA19 K PTA15 VDD PTA18 L 9 10 11 XTAL32 EXTAL32 VSS 4 5 6 3 RTC_ PTA13/ WAKEUP_B LLWU_P4 7 8 Figure 33. K22F 121 XFBGA Pinout Diagram (transparent top view) 6 Part identification 6.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 69 NXP Semiconductors Part identification 6.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 6.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status * M = Fully qualified, general market flow, full reel * P = Prequalification * K = Fully qualified, general market flow, 100 piece reel K## Kinetis family * K22 A Key attribute * D = Cortex-M4 w/ DSP * F = Cortex-M4 w/ DSP and FPU M Flash memory type * N = Program flash only * X = Program flash and FlexMemory FFF Program flash memory size * 128 = 128 KB * 256 = 256 KB * 512 = 512 KB R Silicon revision * Z = Initial * (Blank) = Main * A = Revision after main T Temperature range (C) * V = -40 to 105 * C = -40 to 85 PP Package identifier * * * * * LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LL = 100 LQFP (14 mm x 14 mm) MC = 121 XFBGA (8 mm x 8 mm) DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm) CC Maximum CPU frequency (MHz) * * * * * 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz N Packaging type * R = Tape and reel 70 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Terminology and guidelines 6.4 Example This is an example part number: MK22FN256VDC12 6.5 121-pin XFBGA part marking The 121-pin XFBGA package parts follow the part-marking scheme in the following table. Table 50. 121-pin XFBGA part marking MK Partnumber MK Part Marking MK22FN256VDC12 M22J8VDC 6.6 64-pin MAPBGA part marking The 64-pin MAPBGA package parts follow the part-marking scheme in the following table. Table 51. 64-pin MAPBGA part marking MK Partnumber MK Part Marking MK22FN256VMP12 M22J8V 7 Terminology and guidelines 7.1 Definitions Key terms are defined in the following table: Term Rating Definition A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. Table continues on the next page... Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 71 NXP Semiconductors Terminology and guidelines Term Definition NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. 7.2 Examples EX AM PL E Operating rating: EX AM PL E Operating requirement: EX AM PL E Operating behavior that includes a typical value: 7.3 Typical-value conditions Typical values assume you meet the following conditions (or other conditions as specified): 72 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Revision History Symbol Description Value Unit TA Ambient temperature 25 C VDD Supply voltage 3.3 V 7.4 Relationship between ratings and operating requirements .) ) ) ing rat e Op ng ati in. (m in. t (m ax t (m n me r rat e Op ing ire qu re ing rat e Op .) en rem re i qu rat e Op ing ng ati ax (m r Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure - Operating (power on) g lin nd Ha n.) mi g( in rat g( ng li nd Ha in rat .) x ma Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure - Handling (power off) 7.5 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8 Revision History The following table provides a revision history for this document. Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 73 NXP Semiconductors Revision History Table 52. Revision History Rev. No. Date Substantial Changes 7 08/2016 * * * * 6 10/2015 * In "Power consumption operating behaviors" section, added "Low power mode peripheral adders--typical value" table * In "Thermal operating requirements" table, in footnote, corrected "TJ = TA + JA" to "TJ = TA + RJA" * Updated "IRC48M specifications" table * Updated "NVM program/erase timing specifications" table; updated values for thversall (Erase All high-voltage time) * In "Slave mode DSPI timing (limited voltage range)" table, added footnote regarding maximum frequency of operation * Added new section, "Recommended connections for unused analog and digital pins" 5 4/2015 * Throughout: Removed notes stating that the 64-pin MAPBGA package for this product is not yet available * On page 1: * In first bullet of introduction, updated power consumption data to align with the data in the "Power consumption operating behaviors" table * In second bullet of introduction, added "USB FS device crystal-less functionality" * Under "Security and integrity modules" added "Hardware random-number generator" * Under "Communication interfaces," updated I2C bullet to indicate support for up to 1 Mbps operation * Under "Timers," updated 8-channel general purpose/PWM timer * Under "Operating characteristics," specified that voltage range includes flash writes * In figure, "Functional block diagram," added "Random-number generator" and "Flash access control" * In "Voltage and current operating requirements" table: * Removed content related to positive injection * Updated footnote 1 to say that all analog and I/O pins are internally clamped to VSS only (not VSS and VDD)through ESD protection diodes. * In "Power consumption operating behaviors" table: * Added additional temperature data in power consumption table * Added Max IDD values based on characterization results equivalent to mean + 3 sigma * Updated "EMC radiated emissions operating behaviors" table * In "Thermal operating requirements" table, added the following footnote for ambient temperature: "Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + JA x chip power dissipation" * Updated "IRC48M Specifications": * Updated maximum values for firc48m_ol_lv and firc48m_ol_hv (full temperature) * Added specifications for firc48m_ol_hv (-40C to 85C) * Updated notes in "USB electrical specifications" section * In "I2C timing" table, * Added the following footnote on maximum Fast mode value for SCL Clock Frequency: "The maximum SCL Clock Frequency in Fast mode with maximum Added Terminology and Guideline section Added Device Revision Number Table Editorial Updates Updated Chip Errata naming convention in Related Resource table Table continues on the next page... 74 NXP Semiconductors Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 Revision History Table 52. Revision History (continued) Rev. No. Date Substantial Changes * * * * * * bus loading can only be achieved when using the High drive pins across the full voltage range and when using the Normal drive pins and VDD 2.7 V." * Updated minimum Fast mode value for LOW period of the SCL clock to 1.25 Added "I2C 1 Mbps timing" table Specified that the figure, "K22F 64 LQFP Pinout Diagram" is a top view Specified that the figure, "K22F 64 MAPBGA Pinout Diagram" is a transparent top view Specified that the figure, "K22F 100 LQFP Pinout Diagram" is a top view Removed Section 6, "Ordering parts." Corrected part marking shown in "64-pin MAPBGA part marking" table 4 7/2014 * In "Power consumption operating behaviors table": * Updated existing typical power measurements * Added new typical power measurements for the following: * IDD_HSRUN (High Speed Run mode current executing CoreMark code) * IDD_RUNCO (Run mode current in Compute operation, executing CoreMark code) * IDD_RUN (Run mode current in Compute operation, executing while(1) loop) * IDD_VLPR (Very Low Power mode current executing CoreMark code) * IDD_VLPR (Very Low Power Run mode current in Compute operation, executing while(1) loop) * In "Thermal attributes" table, added values for 64-pin MAPBGA package. 3 7/2014 * On p. 1: * Updated introduction * Under "Memories and memory interfaces," added bullet, "Pre-programmed Kinetis flashloader for one-time, in-system factory programming" * Under "Security and integrity modules," added bullet, "Hardware randomnumber generator" * In "Voltage and current operating ratings" table, updated maximum digital supply current * Updated "Voltage and current operating behaviors" table * Updated "Power mode transition operating behaviors" table * Updated "Power consumption operating behaviors" table * Updated figure, "Run Mode Current vs Core Frequency" * Updated figure, "Very Low Power Run (VLPR) Current vs Core Frequency" * Updated "EMC radiated emissions operating behaviors for 64 LQFP package" table * Updated "Thermal attributes" table * Updated "MCG specifications" table * Updated "IRC48M specifications" table * Updated "16-bit ADC operating conditions" table * Updated "Voltage reference electrical specifications" section * Added "121-pin XFBGA part marking" table * Added "64-pin MAPBGA part marking" table 2 3/2014 Initial public release Kinetis K22F 256 KB Flash, Rev. 7, 08/2016 75 NXP Semiconductors How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address:nxp.com/SalesTermsandConditions. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM, the ARM Powered logo, and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. (c) 2014-2016 NXP B.V. Document Number K22P121M120SF8 Revision 7, 08/2016