FUJITSU SEMICONDUCTOR DATA SHEET Revision 1.1 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89480/MB89480L Series MB89485/485L/P485/P485L/PV480 DESCRIPTION The MB89480 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as 21-bit time-base timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, 6-bit PPG, LCD controller/driver, external interrupt 1 (edge), external interrupt 2 (level), 10-bit A/D converter, UART/SIO, buzzer, watchdog timer reset. The MB89480 series is designed suitable for LCD remote controller as well as in a wide range of applications for consumer product. *: F2MC stands for FUJITSU Flexible Microcontroller. FEATURES * Package used QFP package and SH-DIP package for MB89P485/P485L, MB89485/485L MQFP package for MB89PV480 * High-speed operating capability at low voltage * Minimum execution time: 0.32 s/12.5MHz (Continued) PACKAGE 64-pin Plastic SH-DIP (DIP-64P-M01) (DIP-64P-M01) 64-pin Plastic QFP (FPT-64P-M09) (FPT-64P-M09) 64-pin Ceramic MQFP (MQP-64C-P01) (MQP-64C-P01) 1 MB89480/480L Series (Continued) * F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. * Six timers PWC timer (also usable as a interval timer) PWM timer 8/16-bit timer/counter x 2 21-bit timebase timer watch prescaler * Programmable pulse generator 6-bit PPG with program-selectable pulse width and period * External interrupts Edge detection (Selectable edge) : 4 channels Low-level interrupt (Wake-up function) : 8 channels * A/D converter (4 channels) 10-bit successive approximation type * UART/SIO Synchronous/asynchronous data transfer capable * LCD controller/driver max. 31 segments output x 4 commons booster for LCD driving (selected by mask option) * Buzzer 7 frequency types are selectable by software * Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) Watch mode (Everything except the watch prescaler stops to reduce the power comsumption to an extremely low level.) Subclock mode * Watch dog timer reset * I/O ports: max. 42 channels PRODUCT LINEUP Part number Parameter MB89485L MB89485 Classification Mass production products (mask ROM product) ROM size 16K x 8-bit (internal ROM) RAM size MB89P485L MB89P485 MB89PV480 OTP Piggy-back 16K x 8-bit (internal PROM with read protection *2) 32K x 8-bit (external ROM)*1 512 x 8 bits 1K x 8 bits *1 : Use MBM27C256A as the external ROM. *2 : Read protection feature is selected by part number, detail please refer to MASK OPTIONS. 2 MB89480/480L Series Part number Parameter MB89485L MB89485 MB89P485L MB89P485 MB89PV480 CPU functions Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Minimum interrupt processing time: : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.32 s/12.5 MHz : 2.88 s/12.5 MHz Ports I/O ports (CMOS) N-channel open drain I/O ports Output ports (N-channel open drain) Input port Total : 11 pins : 28 pins : 2 pins : 1 pin : 42 pins 21-Bit Time-based timer Interrupt period (0.66ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz Watchdog timer Reset period (167.8 ms to 335.5 ms) at 12.5 MHz Pulse width count timer 2 channels 8-bit one-shot timer operation (supports underflow output, operating clock period: 1, 4, 32 tinst, external) 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst, external) 8-bit pulse width measurement operation (supports continuous measurement, H width, L width, rising edge to rising edge, falling edge to falling edge measurement and both edge measurement) PWM timer 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst, external) 8-bit resolution PWM operation 6- Bit programmable pulse generator Can generate square pulse with programmable period. 8/16-Bit timer/ counter 11,12 Can be operated either as a 2-channel 8-bit timer/counter (Timer 11 and Timer 12, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 11 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable 8/16-Bit timer/ counter 21,22 Can be operated either as a 2-channel 8-bit timer/counter (Timer 21 and Timer 22, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 21 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable External interrupt 4 independent channels (selectable edge, interrupt vector, request flag) 8 channels (low level interrupt) A/D converter 10-bit resolution x 4 channels A/D conversion function (conversion time: 60 tinst ) Supports repeated activation by internal clock. Common output: Segment output: LCD controller/driver Bias power supply pins: LCD display RAM size: Dividing resistor/booster: 4 (max.) 31 (max.) (selected resistor ladder) 26 (max.) (selected booster) 4 31 x 4 bits selected by mask option UART/SIO Synchronous/asynchronous data transfer capable (Max. baud rate: 97.656 Kbps at 12.5 MHz) (7 and 8 bits with parity bit ; 8 and 9 bits without parity bit) Buzzer output 7 frequency types are selectable by software. 3 MB89480/480L Series Part number MB89485L Parameter MB89485 MB89P485L MB89P485 Standby mode Sleep mode, stop mode, watch mode, subclock mode. Process CMOS Operating Voltage 2.2V ~ 3.6V 2.2V ~ 5.5V 2.7V ~ 3.6V MB89PV480 3.5V ~ 5.5V 2.7V ~ 5.5V Note: 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock. PACKAGE AND CORRESPONDING PRODUCTS Device MB89485/485L MB89P485/P485L MB89PV480 DIP-64P-M01 O O X FPT-64P-M09 O O X MQP-64C-P01 X X O Package O : Availabe X : Not available DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: * The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption * For the MB89PV480, add the current consumed by the EPROM mounted in the piggy-back socket. * When operating at low speed, the current consumed by the one-time PROM product is greater than that for the mask ROM product. However, the current consumption are roughly the same in sleep or stop mode. * For more information, see " Electrical Characteristics." 3. Oscillation stabilization time after power-on reset * For MB89PV480,MB89P485L and MB89485L, there is no power-on stabilization time after power-on reset. * For MB89P485, there is power-on stabilization time after power-on reset. * For MB89485, the power-on stabilization time can be selected. * For more information, refer to " Mask Option". 4 MB89480/480L Series PIN ASSIGNMENT (TOP VIEW) COM0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P57 P10/SEG23/INT10 P11/SEG24/INT11 P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A C *2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 P26/V1/TO1 V0/SEG0 P25/C0/EC2 *1 P24/C1/TO2 *1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 *1 P04/INT24 *1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P17/SEG30/AN3 *1 P16/SEG29/AN2 *1 P15/SEG28/AN1 *1 P14/SEG27/AN0 *1 RST MODE X1 X0 (DIP-64P-M01) *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled. *2: For product other than MB89P485, pin 31 is NC pin. 5 MB89480/480L Series 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 P26/V1/TO1 V0/SEG0 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P25/C0/EC2 *1 P24/C1/TO2 *1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 *1 P04/INT24 *1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P10/SEG23/INT10 P11/SEG24/INT11 P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A *2 C Vss X0 X1 MODE RST *1 P14/SEG27/AN0 *1 P15/SEG28/AN1 *1 P16/SEG29/AN2 *1 P17/SEG30/AN3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P57 (FPT-64P-M09) *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled. *2: For product other than MB89P485, pin 23 is NC pin. 6 P27/V2/EC1 V3 COM1 P30/COM2 P31/COM3 55 54 53 52 SEG1 Vss X1A *2 C X0A P12/SEG25/INT12 P13/SEG26/INT13 20 21 22 23 24 25 P11/SEG24/INT11 P16/SEG29/AN2 P57 P10/SEG23/INT10 P15/SEG28/AN1 P56/SEG22 *1 P54/SEG20 P55/SEG21 *1 P53/SEG19 P26/V1/TO1 V0/SEG0 P25/C0/EC2 *1 P24/C1/TO2 *1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 *1 P04/INT24 *1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P17/SEG30/AN3 *1 29 30 31 32 P51/SEG17 P52/SEG18 RST *1 P14/SEG27/AN0 P50/SEG16 77 76 75 74 73 72 71 70 69 85 86 87 88 89 90 91 92 93 MODE P46/SEG14 P47/SEG15 26 27 28 P45/SEG13 X0 X1 P43/SEG11 P44/SEG12 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 84 83 82 81 80 79 78 P42/SEG10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 94 95 96 65 66 67 68 SEG7 P40/SEG8 P41/SEG9 58 57 56 SEG3 SEG2 SEG4 64 63 62 61 60 59 SEG6 SEG5 (TOP VIEW) COM0 Vcc MB89480/480L Series (MQP-64C-P01) *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled. *2: Pin 24 is NC pin. Pin assignment on package top Pin Pin Pin No. Symbo Symbol l Pin No. Pin Symbol Pin No. Pin No. Pin Symbol 65 N.C. 73 A2 81 N.C. 89 OE 66 Vpp 74 A1 82 O4 90 N.C. 67 A12 75 A0 83 O5 91 A11 68 A7 76 N.C. 84 O6 92 A9 69 A6 77 O1 85 O7 93 A8 70 A5 78 O2 86 O8 94 A13 71 A4 79 O3 87 CE 95 A14 72 A3 80 VSS 88 A10 96 VCC N.C.: As connected internally, do not use. 7 MB89480/480L Series PIN DESCRIPTION Pin Number SH-DIP*1 MQFP*2 33 26 QFP*3 25 Pin Name I/O Circuit Type A Connection pins for a crystal or other oscillator. An external clock can be connected to X0. In this case, leave X1 open. A Connection pins for a crystal or other oscillator. An external clock can be connected to X0A. In this case, leave X1A open. B Input pins for setting the memory access mode. Connect directly to VSS. X0 34 27 26 X1 29 22 21 X0A 30 23 22 X1A 35 28 27 MODE Function 36 29 28 RST C Reset I/O pin. The pin is a N-ch open-drain type with pullup resistor and a hysteresis input. The pin outputs a "L" level when an internal reset request is present. Inputting an "L" level initializes internal circuits. 50 ~ 48 43 ~ 41 42 ~ 40 P00/INT20 ~ P02/INT22 D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input. D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/counter 21, 22 input when booster is selected. D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/counter 21, 22 output when booster is selected. 47 46 40 39 39 P03/INT23 38 P04/INT24 D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and PWC input. 45 38 37 P05/INT25/ PWC 44 37 36 P06/INT26/ PPG D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and 6-bit PPG output. 43 36 35 P07/INT27/ BUZ D General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input and buzzer output. 17 ~ 20 P10/SEG23/ INT10 ~ P13/SEG26/ INT13 29 ~ 32 P14/SEG27/ AN0 ~ P17/SEG30/ AN3 25 ~ 28 37 ~ 40 18 ~ 21 30 ~ 33 F/K General-purpose N-ch Open-drain I/O port. A hysteresis input. The pin is shared with external interrupt 1 input and LCD segment output. G/K General-purpose N-ch Open-drain I/O port. An analog input. The pin is shared with A/D converter input and LCD segment output. LCD segment output will be disabled when booster is selected. *1: DIP-64P-M01 *2: MQP-64C-P01 *3: FPT-64P-M09 (Continued) 8 MB89480/480L Series (Continued) Pin Number SH-DIP*1 MQFP*2 Pin Name I/O Circuit Type QFP*3 Function 51 44 43 P20/PWM E General-purpose CMOS I/O port. The pin is shared with PWM output. 52 45 44 P21/SCK E General-purpose CMOS I/O port. The pin is shared with UART/SIO clock I/O. 53 46 45 P22/SO E General-purpose CMOS I/O port. The pin is shared with UART/SIO data output. 54 47 46 P23/SI D General-purpose CMOS I/O port. The pin is shared with UART/SIO data input. H General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer 21,22 output (It is redirected to P04/INT24 when booster is selected), and as a capacitor connecting pin when booster is selected. 55 48 47 P24/C1/TO2 56 49 48 P25/C0/EC2 F General-purpose CMOS I/O port. A hysteresis input. The pin is shared with 8/16-bit timer 21,22 input (It is redirected to P03/INT23 when booster is selected), and as a capacitor connecting pin when booster is selected. 58 51 50 P26/V1/TO1 H General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer 11,12 output, and LCD power driving pin. 59 52 51 P27/V2/EC1 F General-purpose CMOS I/O port. A hysteresis input. The pin is shared with 8/16-bit timer 11,12 input, and LCD power driving pin. 62 55 54 P30/COM2 I/K General-purpose N-ch Open-drain output port. The pin is shared with the LCD common output 61 54 53 P31/COM3 I/K General-purpose N-ch Open-drain output port. The pin is shared with the LCD common output 9 ~ 16 2~9 1~8 P40/SEG8 ~ P47/SEG15 H/K General-purpose N-ch Open-drain I/O port. The pin is shared with LCD segment output. 17 ~ 23 10 ~ 16 9 ~ 15 P50/SEG16 ~ P56/SEG22 H/K General-purpose N-ch Open-drain I/O port. The pin is shared with LCD segment output. 24 17 16 P57 J General-purpose CMOS input port. *1: DIP-64P-M01 *2: MQP-64C-P01 *3: FPT-64P-M09 (Continued) 9 MB89480/480L Series (Continued) Pin Number SH-DIP*1 MQFP*2 Pin Name I/O Circuit Type QFP*3 Function 2~8 59 ~ 64, 1 58 ~ 64 SEG1 ~ SEG7 K LCD segment output only pins. 1, 63 58, 56 57, 55 COM0 ~ COM1 K LCD common output only pins. 60 53 52 V3 -- LCD driving power supply pin. 57 50 49 V0/SEG0 --/K 31 24 23 C -- Capacitor connection pin *4 64 57 56 VCC -- Power supply pin (+3V or +5V). 32 25 24 VSS -- Power supply pin (GND). 41 34 33 AVCC -- A/D converter power supply pin. 42 35 34 AVSS -- A/D converter power supply pin. Use at the same voltage level as VSS. LCD driving power supply pin when booster is selected. LCD segment output when booster is not selected. *1: DIP-64P-M01 *2: MQP-64C-P01 *3: FPT-64P-M09 *4: When MB89485/485L, MB89P485L or MB89PV480 is used, this pin will become a N.C. pin. When MB89P485 is used, connect this pin to an external 0.1uF capacitor to ground. 10 MB89480/480L Series * External EPROM Socket (MB89PV480 only) Pin Numbe Pin Name I/O 95 94 67 91 88 92 93 68 69 70 71 72 73 74 75 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins. 86 85 84 83 82 79 78 77 O8 O7 O6 O5 O4 O3 O2 O1 I Data input pins. 65 76 81 90 N.C. -- Internally connected pins. Always leave open. 66 Vpp O "H" level output pin. 80 VSS O Power supply pin (GND). 87 CE O Chip enable pin for the EPROM. Outputs "H" in standby mode. 89 OE O Output enable pin for the EPROM. Always outputs "L". 96 VCC O Power supply pin for the EPROM. Function MQFP*1 *1: MQP-64C-P01 11 MB89480/480L Series I/O CIRCUIT TYPE Circuit Class Circuit Remarks X1 (X1A) Nch X0 (X0A) A Pch Pch * Main/Sub clock circuit Nch Stop mode control signal * Hysteresis input * The pull-down resistor Approx. 50k. (not available in MB89P485/ P485L) B R Pch * The pull-up resistance (Pchannel) Approx. 50 k. * Hysteresis input C Nch pull-up resistor register R Pch * * * * D Nch port CMOS output CMOS input Hysteresis input Selectable pull-up resistor Approx. 50 k resources pull-up resistor register R Pch * CMOS output * CMOS input * Selectable pull-up resistor Approx. 50 k E Nch port (Continued) 12 MB89480/480L Series (Continued) F * N-ch open-drain output * CMOS input * Hysteresis input Nch port resources G Nch port * N-ch open-drain output * CMOS input * Analog input analog input H * N-ch open-drain output * CMOS input Nch port I * N-ch open-drain output Nch port J * CMOS input P-ch N-ch K * LCD segment output P-ch N-ch 13 MB89480/480L Series HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in " Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = VCC and AVSS = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode. 14 MB89480/480L Series PROGRAMMING OTPROM IN MB89P485/P485L WITH SERIAL PROGRAMMER 1. Programming the OTPROM with serial programmer * All OTP products can be programmed with serial programmer 2. Programming the OTPROM * To program the OTPROM using EPROM programmer AF200 (manufacturer: Yokogawa Digital Computer Corp.). Inquiry : Yokogawa Digital Computer Corp. : TEL (81)-42-333-6224 * To program the OTPROM using FUJITSU MCU programmer MB91919-001. Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770 FAX (65)-2810220 3. Programming Adaptor for OTPROM * To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adapter listed below. Package Compatible socker adaptor DIP-64P-M01 MB91919-812 FPT-64P-M09 MB91919-813 Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770 FAX (65)-2810220 4. OTPROM Content Protection For product with OTPROM content protection feature (MB89P485-103, MB89P485-104), OTPROM content can be read using serial programmer if the OTPROM content protection mechanism is not activated. One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM content. If the protection code "00H" is written in this address (FFFCH), the OTPROM content cannot be read by any serial programmer. Note: The program written into the OTPROM cannot be verified once the OTPROM protection code is written ("00H" in FFFCH). It is advised to write the OTPROM protection code at last. 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 15 MB89480/480L Series PROGRAMMING OTPROM IN MB89P485/P485L WITH GENERAL PURPOSE EPROM PROGRAMMER 1. Programming OTPROM with general purpose EPROM programmer * Only products without protection feature (i.e. MB89P485/P485L-101 and MB89P485/P485L-102) can be programmed with general purpose EPROM programmer. Product with protection feature (i.e. MB89P485/P485L103 and MB89P485/P485L-104) cannot be programmed with general purpose programmer. 2. ROM Writer Adapters and Recommended ROM Writers * The following shows ROM writer adapters and recommended ROM writers. Applicable adapter model Recommended writer maker and writer Package name Fujitsu Microelectronics Asia Pte Ltd. Minato electronics Co., Ltd. DIP-64P-M01 MB91919-604 Under evaluation FPT-64P-M09 MB91919-605 Under evaluation MODEL1890A * Contact information Minato electronics Co., Ltd.: Phone 045-591-5611 3. Memory Space Memory Map of Piggyback/Evaluation Device Address Normal operating mode Corresponding addresses on the EPROM programmer 0000H I/O 0080H RAM 0280H C000H Not available C000H PROM 16Kbyte FFFFH EPROM 16Kbyte 7FFFH 4. Writing data to the EPROM (1) Set the EPROM writer for the CU50-OTP (device code: T.B.D). (2) Load the program data to the EPROM writer. (3) Write data using the EPROM writer. 16 MB89480/480L Series 4. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 17 MB89480/480L Series PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-S Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403 3. Memory Space Memory space in each mode is diagrammed below. Address Normal operating mode Corresponding addresses on the EPROM programmer 0000H I/O 0080H RAM 0480H 8000H Not available 0000H PROM 32KB FFFFH EPROM 32KB 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 18 MB89480/480L Series Block Diagram CMOS I/O port Main clock oscillator X0 X1 Buzzer output P07/INT27/BUZ Clock controller 6-bit PPG Sub-clock oscillator 8-bit PWC timer Reset circuit (Watchdog timer) RST P06/INT26/PPG External interrupt 2 (level) Port 0 X0A X1A P05/INT25/PWC P04/INT24 *1 8 P03/INT23 *1 21-bit timebase timer P02/INT22 to P00/INT20 AVcc AVss 8-bit PWM timer P20/PWM P24/C1/TO2 *1 P25/C0/EC2 *1 P26/V1/TO1 P27/V2/EC1 UART/SIO Port 2 *4 P21/SCK P22/SO P23/SI 8/16-bit timer/counter 21,22 10-bit A/D converter N-ch open-drain I/O port External interrupt 2 (egde) 8/16-bit timer/counter 11,12 2 4 4 Port 1 CMOS I/O port *4 Internal data bus Watch prescaler Booster 7 Port 3 2 LCD controller/driver P10/SEG23/INT10 to P13/SEG26/INT13 SEG1 t0 SEG7 COM0 to COM1 V3 V0/SEG0 *3 N-ch open-drain output port RAM (512 bytes / 1K bytes) 32 x 4-bit display RAM (16 bytes) 16 F2MC-8L CPU ROM (16K bytes / 32K bytes) Port 4 and Port 5 *4 P31/COM3 2 4 P14/SEG27/AN0 *1 to P17/SEG30/AN3 *1 8 2 P30/COM2 4 N-ch open-drain I/O port P57 3 P56/SEG22 to P54/SEG20 4 P53/SEG19 to P50/SEG16 4 P47/SEG15 to P44/SEG12 4 P43/SEG11 to P40/SEG8 Other pins Vcc, Vss, MODE, C *2 *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P14/SEG27/AN0 to P17/SEG30/AN3 will be disabled. *2: For product other than MB89P485, C pin is NC pin. *3: If booster is selected, it serves as V0. If booster is not selected, it serves as SEG0. *4: P20 to P23 are CMOS I/O ports. P24 to P27 are N-ch open-drain I/O ports. P57 is input-only port. 19 MB89480/480L Series CPU CORE 1. Memory Space The microcontrollers of the MB89480 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89480 series is structured as illustrated below. Memory Space MB89485/485L 0000H MB89P485/P485L 0080H RAM 0080H 0280H RAM RAM 0100H 0100H Generalpurpose registers I/O I/O 0080H 0100H 0200H 0000H 0000H I/O MB89PV480 0200H Generalpurpose registers Generalpurpose 0200H registers 0280H 0480H Vacant Vacant Vacant 8000H C000H C000H FFC0H FFFFH ROM FFC0H FFFFH ROM FFC0H FFFFH Vector table (reset, interrupt, vector call instruction) 20 External ROM (32K) MB89480/480L Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator. When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code Initial value 16 bits PC FFFDH : Program counter A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 12 RP 11 10 9 8 Vacancy Vacancy Vacancy RP 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR 21 MB89480/480L Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0 Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 22 MB89480/480L Series The following general-purpose registers are provided: General-purpose registers: An 8-bit resister for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used on the MB89480 series. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 23 MB89480/480L Series I/O MAP Address Register name Register Description 00H PDR0 Port 0 data register 01H DDR0 Port 0 data direction register 02H PDR1 Port 1 data register 03H DDR1 Port 1 data direction register 04H PDR2 Port 2 data register 05H Read/Write Initial value R/W XXXXXXXXB W* 00000000B R/W XXXXXXXXB W* 00000000B R/W 00000000B (Reserved) 06H DDR2 Port 2 data direction register R/W 00000000B 07H SYCC System clock control register R/W X-1MM100B 08H STBC Standby control register R/W 00010XXXB 09H WDTC Watchdog timer control register W* 0---XXXXB 0AH TBTC Timebase timer control register R/W 00---000B 0BH WPCR Watch prescaler control register R/W 00--0000B 0CH PDR3 Port 3 data register R/W ------11B R XXXX----B R/W 11111111B R/W X1111111B UART/SIO mode control register 1 R/W 00000000B 0DH 0EH 0F (Reserved) RSFR Reset flag register (Reserved) H 10H PDR4 Port 4 data register 11H 12H (Reserved) PDR5 Port 5 data register 13H (Reserved) 14H to 1FH (Reserved) 20H SMC1 21H SMC2 UART/SIO mode control register 2 R/W 00000000B 22H SRC UART/SIO rate control register R/W XXXXXXXXB 23H SSD UART/SIO status/data register R 00001---B 24H SIDR/SODR UART/SIO data register R/W XXXXXXXXB 25H EIC1 External interrupt 1 control register 1 R/W 00000000B 26H EIC2 External interrupt 1 control register 2 R/W 00000000B 27H EIE2 External interrupt 2 enable register R/W 00000000B 28H EIF2 External interrupt 2 flag register R/W -------0B 2CH ADC1 A/D control register 1 R/W -0000000B 2DH ADC2 A/D control register 2 R/W -0000001B 2EH ADDH A/D data register (Upper byte) R ------XXB 2FH ADDL A/D data register (Lower byte) R XXXXXXXXB 30H ADEN A/D input enable register R/W 1111----B 31H PCR1 PWC control register 1 R/W 0-0--000B 32H PCR2 PWC control register 2 R/W 00000000B 33H PLBR PWC reload buffer register R/W XXXXXXXXB 29H to 2BH (Reserved) (Continued) 24 MB89480/480L Series (Continued) Address Register name Register Description PWM timer control register Read/Write Initial value R/W 0-000000B 34H CNTR 35H COMR PWM timer compare register W* XXXXXXXXB 36H T4CR Timer 22 control register R/W 000000X0B 37H T3CR Timer 21 control register R/W 000000X0B 38H T4DR Timer 22 data register R/W XXXXXXXXB 39H T3DR Timer 21 data register R/W XXXXXXXXB 3AH T2CR Timer 12 control register R/W 000000X0B 3BH T1CR Timer 11 control register R/W 000000X0B 3CH T2DR Timer 12 data register R/W XXXXXXXXB 3DH T1DR Timer 11 data register R/W XXXXXXXXB 3EH PPGC1 PPG control register 1 R/W 00000000B 3FH PPGC2 PPG control register 2 R/W 0-000000B 40H BUZR Buzzer control register R/W -----000B 5EH LCR1 LCD controller control register 1 R/W 00010000B 5FH LCR2 LCD controller control register 2 R/W -0000000B 60 to 6FH VRAM LCD data RAM R/W XXXXXXXXB 70H PURC0 Port 0 pull up resistor control register R/W 11111111B R/W ----1111B 41 to 5DH (Reserved) 71H 72H (Reserved) PURC2 Port 2 pull up resistor control register 73H to 76H (Reserved) 77H (Reserved) 78H (Reserved) 79H (Reserved) 7AH (Reserved) 7BH ILR1 Interrupt level setting register 1 W* 11111111B 7CH ILR2 Interrupt level setting register 2 W* 11111111B 7DH ILR3 Interrupt level setting register 3 W* 11111111B 7EH ILR4 Interrupt level setting register 4 W* 11111111B 7FH (Reserved) * Bit manipulation instruction cannot be used. Read/write access symbols R/W : Readable and writable R : Read-only W : Write-only Initial value symbols 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". X: The initial value of this bit is undefined. - : Unused bit. M: The initial value of this bit is determined by mask option. 25 MB89480/480L Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC AVCC VSS - 0.3 VSS + 6.0 V MB89PV480, MB89P485, MB89485 AVCC must not exceed VCC VCC AVCC VSS - 0.3 VSS + 4.0 V MB89P485L, MB89485L AVCC must not exceed VCC LCD Power supply voltage V0 to V3 VSS - 0.3 VSS+ 6.0 V Input voltage VI VSS - 0.3 VCC + 0.3 V P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57 Output voltage VO VSS - 0.3 VCC + 0.3 V P00 to P07, P10 to P17, P20 to P27, P30 to P31, P40 to P47, P50 to P56 "L" level maximum output current IOL 15 mA "L" level average output current IOLAV 4 mA "L" level total maximum output current IOL 100 mA "L" level total average output current IOLAV 40 mA "H" level maximum output current IOH -15 mA "H" level average output current IOHAV -4 mA "H" level total maximum output current IOH -50 mA "H" level total average output current IOHAV -20 mA Power consumption PD 300 mW Operating temperature TA -40 +85 C Storage temperature Tstg -55 +150 C Power supply voltage Average value (operating current x operating rate) Average value (operating current x operating rate) Average value (operating current x operating rate) Average value (operating current x operating rate) Precautions: Permanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 26 MB89480/480L Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Symbol Parameter VCC AVCC Power supply voltage Value Unit Remarks Min. Max. 2.2* 5.5 V Operation assurance range MB89485 3.5* 5.5 V Operation assurance range MB89P485 2.7* 5.5 V Operation assurance range MB89PV480 1.5 5.5 V Retains the RAM state in stop mode MB89485, MB89P485, MB89PV480 2.2* 3.6 V Operation assurance range 1.5 3.6 V Retains the RAM state in stop mode LCD power supply voltage V0 to V3 Vss Vcc V Operating temperature TA -40 +85 C MB89485L, MB89P485L * : These values depend on the operating conditions and the analog assurance range. See Figure 1,2 and "5. A/D Converter Electrical Characteristics." Operating Voltage (V) 5.5 Analog accuracy assurance range : Vcc = AVcc =4.5V~5.5V 5.0 4.5 4.0 3.5 3.0 2.7 2.2 2.0 Main clock operating Freq. (MHz) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 4.0 2.0 1.33 1.0 0.8 0.66 0.57 0.50 0.44 0.4 0.36 0.33 0.32 Min execution time (inst. cycle) (s) Note : The shaded area is not assured for MB89P485 Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MB89P485/485) 27 MB89480/480L Series Operating Voltage (V) 3.6 Analog accuracy assurance range : Vcc = AVcc =2.7V~3.6V 3.0 2.7 2.2 2.0 Main clock operating Freq. (MHz) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 4.0 2.0 1.33 1.0 0.8 0.66 0.57 0.50 0.44 0.4 0.36 0.33 0.32 Min execution time (inst. cycle) (s) Note : The shaded area is not assured for MB89P485L Figure 2 Operating Voltage vs. Main Clock Operating Frequency (MB89P485L/485L) Operating Voltage (V) 5.5 Analog accuracy assurance range : Vcc = AVcc =4.5V~5.5V 5.0 4.5 4.0 3.5 3.0 2.7 Main clock operating Freq. (MHz) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 4.0 2.0 1.33 1.0 0.8 0.66 0.57 0.50 0.44 0.4 0.36 0.33 0.32 Figure 3 Min execution time (inst. cycle) (s) Operating Voltage vs. Main Clock Operating Frequency (MB89PV480) Figure 1,2 and 3 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 28 MB89480/480L Series 3. DC Characteristics AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485 AVCC = VCC = 3.0 V for MB89P485L, MB89485L (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Condition Value Min. Typ. Max. Unit VIH P00 ~ P07, P10 ~ P17, P20 ~ P27, P40 ~ P47, P50 ~ P57 -- 0.7 VCC -- VCC + 0.3 V VIHS RST, MODE, EC1, EC2, PWC, SCK, SI, INT10 ~ INT13, INT20 ~ INT27 -- 0.8 VCC -- VCC + 0.3 V VIL P00 ~ P07, P10 ~ P17, P20 ~ P27, P40 ~ P47, P50 ~ P57 -- VSS - 0.3 -- 0.3 VCC V VILS RST, MODE, EC1, EC2, PWC, SCK, SI, INT10 ~ INT13, INT20 ~ INT27 -- VSS - 0.3 -- 0.2 VCC V VD P10 ~ P17, P24 ~ P27, P30 ~ P31, P40 ~ P47, P50 ~ P56 "H" level input voltage "L" level input voltage Open-drain output pin application voltage Pin "H" level VOH output voltage P00 ~ P07, P20 ~ P23 Product without booster VCC + 0.3 -- VSS - 0.3 -- Remarks V V3 Product with booster 4.0 -- -- V MB89PV480 MB89P485 MB89485 2.2 -- -- V MB89P485L MB89485L IOH = -2.0mA "L" level VOL output voltage P00 ~ P07, P10 ~ P17, P20 ~ P27, P30 ~ P31, P40 ~ P47, P50 ~ P56, RST IOL = 4.0 mA -- -- 0.4 V Input leakage current P00 ~ P07, P10 ~ P17, P20 ~ P27, P40 ~ P47, P50 ~ P57 0.45 V < VI < VCC -5 -- +5 A Without pull-up resister P10 ~ P17, P24 ~ P27, P30 ~ P31, P40 ~ P47, P50 ~ P56 0.45 V < VI < VCC -5 -- +5 A ILI Open-drain output leakage ILOD current (Continued) 29 MB89480/480L Series (Continued) Parameter Pull-down resistance Pull-up resistance Common output impedance Segment output impedance Symbol Pin RDOWN MODE RPULL P00 ~ P07, P20 ~ P23, RST Condition VI = VCC VI = 0.0 V Value Min. Typ. Max. 25 50 100 25 50 100 Unit k Except MB89P485, MB89P485L k When pull-up resistor is selected (except RST) MB89P485L, MB89485L V1 to V3 = +3.0 V RVCOM RVSEG COM0 to COM3 -- -- 2.5 k V1 to V3 = +5.0 V MB89PV480, MB89P485, MB89485 V1 to V3 = +3.0 V MB89P485L, MB89485L SEG0 to SEG30 -- -- 15 k V1 to V3 = +5.0 V -- Between VCC and Vss 300 500 750 k ILCDL V0 to V3, COM0 to COM3, SEG0 to SEG30 -- -- -- 1 A VV3 V3 V1 = 1.5V 4.3 4.5 4.7 V VV2 V2 V1 = 1.5V 2.9 3.0 3.1 V Reference input voltage VV1 for LCD driving V1 1.4 1.5 1.7 V Reference voltage input RRIN impedance V1 8.5 9.8 11 k Input capacitance Other than VCC,VSS,AVCC,AVSS -- 10 -- pF LCD divided RLCD resistance LCD controller/ driver leakage current Booster for LCD driving output voltage CIN Remarks IIN = 0 A -- f=1MHz MB89PV480, MB89P485, MB89485 Products with booster only (Continued) 30 MB89480/480L Series (Continued) Parameter Symbol Pin Value Unit Remarks Min. Typ. Max. ICC1 FCH = 12.5MHz tinst = 0.32 s Main clock run mode -- 8 13 mA ICC2 FCH = 12.5MHz tinst = 5.12 s Main clock run mode -- 0.7 3 mA ICCS1 FCH = 12.5MHz tinst = 0.32 s Main clock sleep mode -- 2.5 5 mA ICCS2 FCH = 12.5MHz tinst = 5.12 s Main clock sleep mode -- 0.4 2 mA -- 50 85 A Except MB89P485 -- 54 91 A MB89P485 -- 15 30 A Except MB89P485 -- 19 36 A MB89P485 -- 1.6 15 A Except MB89P485 -- 5.6 21 A MB89P485 -- 3 10 A -- 4 6 mA A/D converting -- 1 5 A A/D stop VCC Power supply current Condition FCL = 32.768kHz Subclock mode ICCL FCL = 32.768kHz Subclock sleep mode ICCLS FCL = 32.768kHz * Watch mode * Main clock stop mode ICCT Ta=+250C Subclock stop mode ICCH IA IAH AVcc Ta=+250C 31 MB89480/480L Series 4. AC Characteristics (1) Reset Timing VCC = 5.0 V for MB89PV480, MB89P485, MB89485 VCC = 3.0 V for MB89P485L, MB89485L (AVSS = VSS = 0.0 V, TA = -40C to +85C) Symbol Parameter RST "L" pulse width Value Condition tZLZH -- Min. Max. 48 tHCYL -- Unit Remarks ns Note: tHCYL is the oscillation cycle (1/FC) to input to the X0 pin. The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH. tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition Value Unit Min. Max. -- 50 ms 1 -- ms -- Remarks Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF Vth VCC 0.2 V Vth = 3.5 V for MB89PV480, MB89P485 and MB89485 Vth = 1.8 V for MB89P485L and MB89485L 32 0.2 V 0.2 V MB89480/480L Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = -40C to +85C) Symbol Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Value Pin Min. Typ. Max. Unit FCH X0, X1 1 -- 12.5 MHz FCL X0A, X1A -- 32.768 -- kHz tHCYL X0, X1 80 -- 1000 ns tLCYL X0A, X1A -- 30.5 -- s PWH PWL X0 20 -- -- ns PWHL PWLL X0A -- 15.2 -- s tCR tCF X0, X0A -- -- 10 ns Remarks External clock X0 and X1 Timing and Conditions tHCYL PWH PWL tCR tCF 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Main Clock Conditions When a crystal or ceramic reasonator is used X0 When an external clock is used X1 X0 X1 Open FCH C1 C2 FCH 33 MB89480/480L Series Subclock Timing and Conditions tLCYL 0.8 VCC X0A 0.2 VCC PWHL PWLL tCR tCF Subclock Conditions When a crystal or ceramic oscillator is used X0A X0A X 1A FCL When an external clock is used X1A Rd X0A Open X1A Open FCL C0 When subclock is not used C1 (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) 34 Symbol Value Unit Remarks 4/FCH, 8/FCH, 16/FCH, 64/FCH s (4/FCH)tinst = 0.32 s when operating at FCH = 12.5 MHz 2/FCL s tinst = 61.036 s when operating at FCL = 32.768 kHz tinst MB89480/480L Series (5) Serial I/O Timing VCC = 5.0 V for MB89PV480, MB89P485, MB89485 ,VCC = 3.0 V for MB89P485L, MB89485L (AVSS = VSS= 0.0 V, TA = -40C to +85C) Value Symbol Pin Condition Unit Parameter Min. Max. Serial clock cycle time tSCYC 2 tinst* -- s -200 200 ns 1/2 tinst* -- ns 1/2 tinst* -- ns 1 tinst* -- s 1 tinst* -- s 0 200 ns 1/2 tinst* -- ns 1/2 tinst* -- ns SCK SCK SO time tSLOV SCK, SO Valid SI SCK tIVSH SI, SCK SCK valid SI hold time tSHIX SCK, SI Serial clock "H" pulse width tSHSL Serial clock "L" pulse width tSLSH SCK SO time tSLOV SCK, SO Valid SI SCK tIVSH SI, SCK SCK valid SI hold time tSHIX SCK, SI Internal shift clock mode SCK External shift clock mode * : For information on tinst, see "(4) Instruction Cycle." Internal Clock Operation tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV SO 2.4 V 0.8 V tIVSH SI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External Clock Operation tSLSH tSHSL SCK 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH SI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 35 MB89480/480L Series (6) Peripheral Input Timing VCC = 5.0 V for MB89PV480, MB89P485, MB89485 VCC = 3.0 V for MB89P485L, MB89485L (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Peripheral input "H" pulse width 1 tILIH1 Peripheral input "L" pulse width 1 tIHIL1 Value Pin INT10 ~ 13, INT20 ~ INT27, EC1, EC2, PWC Unit Min. Max. 2 tinst* -- s 2 tinst* -- s * : For information on tinst, see "(4) Instruction Cycle." t IHIL1 INT10 to 13, INT20 to 27, EC1, EC2, PWC 36 t ILIH1 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC Remarks MB89480/480L Series 5. A/D Converter Electrical Characteristics (1) A/D Converter Electrical Characteristics ( AVCC = VCC = 4.5 V ~ 5.5 V for MB89PV480, MB89P485, MB89485, AVCC = VCC = 2.7 V ~ 3.6 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Pin Resolution Total error -- Linearity error Differential linearity error -- Value Unit Min. Typ. Max. -- 10 -- bit -- -- 3.0 LSB -- -- 2.5 LSB -- -- 1.9 LSB Zero transition voltage VOT AVSS - 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB LSB Full-scale transition voltage VFST AVCC - 3.5 LSB AVCC - 1.5 LSB AVCC + 0.5 LSB LSB A/D mode conversion time -- Analog port input current IAIN Analog input voltage VAIN AN0 to AN3 -- -- 60 tinst* s -- -- 10 A AVSS -- AVCC V Remarks * : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics". (2) A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics. * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. * Total error (unit: LSB) The difference between theoretical and actual conversion values. 37 MB89480/480L Series Theoretical I/O characteristics 3FF Total error 3FF VFST 3FE 3FE 3FD 1.5 LSB Digital output Digital output 3FD 004 003 Actual conversion value {1 LSB x N + VOT} 004 VNT 003 VOT 002 Actual conversion value 002 1 LSB Theoretical value 001 001 0.5 LSB AVCC AVSS 1 LSB = Analog input VFST - VOT 1022 Total error = VNT - {1 LSB x N + 0.5 LSB} 1 LSB (V) Zero transition error Full-scale transition error 004 Theoretical value Actual conversion value 3FF Actual conversion value Digital output 003 Digital output AVCC AVSS Analog input 002 3FE VFST (Actual measurement) 3FD Actual conversion value 001 Actual conversion value 3FC VOT (Actual measurement) AVCC AVSS Analog input Analog input Differential linearity error Linearity error Theoretical value 3FF Actual conversion value 3FE N+1 {1 LSB x N + VOT} Actual conversion value VNT VFST (Actual measurement) 004 Digital output Digital output 3FD V(N + 1)T N N-1 003 VNT Actual conversion value Actual conversion value 002 Theoretical value 001 N-2 VOT (Actual measurement) AVCC AVSS Analog input Linearity error = 38 VNT - {1 LSB x N + VOT} 1 LSB AVCC AVSS Analog input Differential linearity error = V(N + 1)T - VNT 1 LSB -1 MB89480/480L Series (3) Notes on Using A/D Converter * Input impedance of the analog input pins The A/D converter used for the MB89470 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for 16 instruction cycles after activation A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low. Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin. Sample hold circuit Analog Input Circuit Model Analog input pin Comparator If the analog input impedance is too low, it is recommended to connect an external capacitor of approx. 0.1 F. R C Close for 16 instruction cycles after activating A/D conversion. Analog channel selector R: analog input equivalent resistance C: analog input equivalent capacitance MB89485 MB89PV480 2.2 k 45 pF MB89485L MB89P485 MB89P485L 7.1 k 48.3 pF 2.6 k 28 pF 2.8 k 46 pF * Error The smaller the |AVR - AVSS|, the greater the error would become relatively. 39 MB89480/480L Series INSTRUCTIONS Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) (Continued) 40 MB89480/480L Series (Continued) Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) x Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (x) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( x )) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH immediately before the instruction is executed. * 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F. 41 MB89480/480L Series Table 2 Transfer Instructions (48 instructions) Mnemonic ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 - - - - - AL AL AL AL AL AL AL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 - - - AL AL AL - - - AH AH AH - - - dH dH dH ---- ---- ---- ++-- ++-- ++-- D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) AL AL AL - - - - - - - - - - - - - - - AL AL - - - - AH AH AH - - - - - - - - - - - - - - - - AH - - - - dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 42 MB89480/480L Series Table 3 Arithmetic Operation Instructions (62 instructions) Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Operation TL TH AH NZVC OP code (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C A - - - ++-+ 02 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (Continued) 43 MB89480/480L Series (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 TL TH AH NZVC OP code - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Table 4 Branch Instructions (17 instructions) Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Operation If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt TL TH AH NZVC OP code - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - dH - - ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 TL TH AH NZVC OP code - - - - - - - - - - - - - - - - - - - dH - - - - - - - ---- ---- ---- ---- ---- ---R ---S ---- ---- 40 50 41 51 00 81 91 80 90 Table 5 Other Instructions (9 instructions) Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 44 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel 9 A B C D E F A A A SUBC A XCH A, T XOR A AND A OR ADDC A,@IX +d SUBC A,@IX +d MOV @IX +d,A A A XOR AND @A,IX A,@IX +d +d OR A,@IX +d CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC R7 R6 R5 R4 R3 R2 R1 R0 DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 rel rel rel rel rel CALLV BLT #7 rel CALLV BGE #6 rel CALLV BZ #5 CALLV BNZ #4 CALLV BN #3 CALLV BP #2 CALLV BC #1 CALLV BNC #0 rel MOV CMP CLRB BBC MOVW MOVW MOVW XCHW @IX @IX dir: 6 dir: 6,rel A,@IX @IX IX,#d16 A,IX +d,#d8 +d,#d8 +d +d,A DAS MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP 8 CMP A,@IX +d CMPW CMP SETC MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP F 7 E MOV A,@IX +d D 6 C MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A 5 A A JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A SETI 9 MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 8 4 7 RORC 6 3 A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 ROLC DIVU RETI 3 2 A RET 2 MULU SWAP 1 1 0 NOP H 0 L MB89480/480L Series INSTRUCTION MAP 45 MB89480/480L Series MASK OPTIONS Part number No. 46 MB89485 MB89485L MB89P485 MB89P485L Specifying procedure Specify when ordering masking Setting not possible 1 Booster selection (KSV) * Internal resistor ladder * Booster Selectable 101: Internal resistor ladder 102: Booster 2 Selection of OTPROM content protection feature * No protection feature * With protection feature -- 3 Selection of oscillation stabilization time (OSC) * The initial value of the oscillation stabilization OSC time for the main clock 1 can be set by 2 3 selecting the values of the WTM1 and WTM0 bits on the right. 4 Selection of power-on stabilization time * Nil * 217/FCH 101/102: No protection 103/104: with protection MB89PV480 Setting not possible 101: Internal resistor ladder 102: Booster -- Selectable : 214/FCH : 217/FCH : 218/FCH Selectable Fixed to nil Fixed to oscillation stabilization time of 218/FCH Fixed to oscillation stabilization time of 218/FCH 217/FCH Fixed to nil Fixed to nil MB89480/480L Series ORDERING INFORMATION Part number Package MB89485PFM MB89P485PFM-101 MB89P485PFM-102 MB89P485PFM-103 MB89P485PFM-104 MB89485LPFM MB89P485LPFM-101 MB89P485LPFM-102 MB89P485LPFM-103 MB89P485LPFM-104 64-pin Plastic QFP (FPT-64P-M09) MB89485P-SH MB89P485P-SH-101 MB89P485P-SH-102 MB89P485P-SH-103 MB89P485P-SH-104 MB89485LP-SH MB89P485LP-SH-101 MB89P485LP-SH-102 MB89P485LP-SH-103 MB89P485LP-SH-104 64-pin Plastic SH-DIP (DIP-64P-M01) MB89PV480CF-101 MB89PV480CF-102 64-pin Ceramic MQFP (MQP-64C-P01) Remarks 101: With internal resistor ladder, without content protection 102: With booster, without content protection 103: With internal resistor ladder, with content protection 104: With booster, with content protection 47 MB89480/480L Series PACKAGE DIMENSIONS 64-pin Plastic SH-DIP DIP-64P-M01 +0.22 +.009 58.00 -0.55 2.283 -.022 INDEX-1 17.000.25 (.669.010) INDEX-2 +0.70 4.95 -0.20 +.028 .195 -.008 +0.50 0.70 -0.19 +.020 .028 -.007 0.270.10 (.011.004) +0.20 3.30 -0.30 +.008 +0.40 .130 -.012 .0543 C 1.778(.0700) 1.378 -0.20 0.470.10 (.019.004) +.016 -.008 19.05(.750) +0.50 0.25(.010) 1.00 -0 M .039 0~15 +.020 -.0 2001 FUJITSU LIMITED D64001S-c-4-5 Dimensions in mm (inches) 64-pin Plastic LQFP FPT-64P-M09 14.000.20(.551.008)SQ 12.000.10(.472.004)SQ 48 0.1450.055 (.0057.0022) 33 32 49 0.10(.004) Details of "A" part +0.20 1.50 -0.10 +.008 .059 -.004 (Mounting height) 0.25(.010) INDEX 0~8 17 64 1 0.65(.026) C "A" 16 0.320.05 (.013.002) 0.13(.005) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) (Stand off) M 2001 FUJITSU LIMITED F64018S-c-2-4 Dimensions in mm (inches) 48 MB89480/480L Series 64-pin Ceramic MQFP MQP-64C-P01 49 MB89480/480L Series MEMO MB89480/480L Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support. 51