MB89P485LP-SH-101 - Fujitsu Limited

Revision 1.1

FUJITSU SEMICONDUCTOR

DATA SHEET

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89480/MB89480L Series

MB89485/485L/P485/P485L/PV480

■DESCRIPTION

The MB 89480 se ries has b een develope d as a gene ral-purpos e version of the F2MC*-8L fa mily co nsistin g of

proprietary 8-bit, single-chip microcontrollers.

In additio n to a compact instruc tion set, the microc ontroller con tains a variety of perip heral functions such as

21-bit time-base timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, 6-bit PPG, LCD

controller/driver, external interrupt 1 (edge), external interrupt 2 (level), 10-bit A/D converter, UART/SIO, buzzer,

watchdog timer reset.

The MB 89 480 se ri es is de si gne d s ui tabl e fo r L CD rem ote c on tr oll er as wel l a s in a wid e r ang e of app li ca tio ns

for consumer product.

*: F2MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• Package used

QFP package and SH-DIP package for MB89P485/P485L, MB89485/485L

MQFP package for MB89PV480

• High-s pee d operati ng ca pabi li ty at low volta ge

• Minimum execution time: 0.32 µs/12.5MHz (Continued)

■PACKAGE

(MQP-64C-P01)

64-p in Ceramic MQFP

(FPT-64P-M09)

64-pin Plastic QFP

(MQP-64C-P01)

(FPT-64P-M09)

(DIP-64P-M01)

64-pin Plastic SH-DIP

MB89480/480L Series

(Continued)

•F2MC-8L family CPU core

•Six tim ers

PWC timer (also usable as a interval timer)

PWM ti mer

8/16-bit timer/counter x 2

21-bit timebase timer

watch prescaler

•Programmable pulse generator

6-bit PPG with program-selectable pulse width and period

•External interrupts

Edge detection (Selectable edge) : 4 channels

Low-level interrupt (Wake-up function) : 8 channels

•A/D converter (4 channels)

10-bit successive approximation type

•UART/SIO

Synchronous/asynchronous data transfer capable

•LCD controller/driver

max. 31 segments output x 4 commons

booster for LCD driving (selected by mask option)

•Buzzer

7 frequency types are selectable by software

•Low-powe r co nsumption modes

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

W atch mode (Everything except the watch prescaler stops to reduce the power comsumption to an extremely

low level.)

Subclock mode

•W atch dog timer reset

•I/O ports: max. 42 channels

■PRODUCT LINEUP

MB89485L MB89485 MB89P485L MB89P485 MB89PV480

Classification Mass production products

(mask ROM product) OTP Piggy-back

ROM size 16K x 8-bit (internal ROM) 16K x 8 -bit (internal PROM with

read protection *2)32K x 8-bit (external ROM)*1

RAM size 512 x 8 bits 1K × 8 bits

*1 : Use MBM27C256A as the external ROM.

*2 : Read protection feature is selected by part number, detail please refer to MASK OPTIONS.

Multiplication and division instructions

16-bit arithmetic operations

Test and branc h instr uc tio ns

Bit manipulation instructions, etc.

Instruction set optimized for controllers

Part number

Parameter

MB89480/480L Series

MB89485L MB89485 MB89P485L MB89P485 MB89PV480

CPU functions Number of instructions: : 136

Instruction bit length: : 8 bits

Instruction length: : 1 to 3 bytes

Data bit length: : 1, 8, 16 bits

Minimum execution time: : 0.32 µs/12.5 MHz

Minimum interrupt p rocessing time: : 2.88 µs/12.5 MHz

Ports I/O ports (CMOS) : 11 pins

N-channel open drain I/O ports : 28 pins

Output ports (N-channel open drain) : 2 pins

Input port : 1 pin

Total : 42 pins

21-Bit Time-based

timer Interrupt period (0.66ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz

Watchdog timer Reset period (167.8 ms to 335.5 ms) at 12.5 MHz

Pulse width count

timer

2 chann els

8-bit one-shot timer operation (supports underflow output, operating clock period: 1, 4, 32 tinst,

external)

8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst,

external)

8-bit pulse width measurement operation (supports continuous measurement, H width, L width,

rising edge to rising edge, falling edge to falling edge measurement and both edge

measurement)

PWM timer 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst,

external)

8-bit resolution PWM operation

6- Bit programmable

pulse generator Can generate square pulse with programmable period.

8/16-Bit time r/

counter 11,12

Can be operated either as a 2-channel 8-bit timer/counter (Timer 11 and Timer 12, each with its

own independent operating clock cycle), or as one 16-bit timer/counter

In Timer 11 or 16-bit timer/counter operation, event counter operation (external clock-triggered)

and square wave output capable

8/16-Bit time r/

counter 21,2 2

Can be op erat ed ei the r as a 2-chann el 8 -bit timer/counter (Timer 21 and Timer 22, each with its

own independent operating clock cycle), or as one 16-bit timer/counter

In Timer 21 or 16-bit timer/counter operation, event counter operation (external clock-triggered)

and square wave output capable

External interrupt 4 independent channels (selectable edge, interrupt vector, request flag)

8 channels (low level interrupt)

A/D converter 10-bit resolution × 4 channels

A/D conversion function (conversion time: 60 tinst )

Supports repeated activation by internal clock.

LCD controller/driver

Common output: 4 (max.)

Segment output: 31 (max.) (selected resistor ladder)

26 (max.) (selected booster)

Bias power supply pins: 4

LCD display RAM size: 31 × 4 bits

Dividing re si st or /boo ste r: selec ted by mask option

UART/SIO Synchronous/asynchronous data transfer capable

(Max. baud rate: 97.656 Kbps at 12.5 MHz)

(7 and 8 bits with parity bit ; 8 and 9 bits without parity bit)

Buzzer output 7 frequency types are selectable by software.

Part number

Parameter

MB89480/480L Series

Note: 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock.

■PACKAGE AND CORRESPONDING PRODUCTS

O : Availabe

X : Not available

■DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

Take particular care on the following points:

•The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

•For the MB89PV480, add the current consumed by the EPROM mounted in the piggy-back socket.

•When o per at ing a t low spe ed, th e curr en t c on su med b y th e one -time P RO M pr od uct i s g reater tha n that fo r

the mask ROM product. However, the current consumption are roughly the same in sleep or stop mode.

•For more information, see “■ Electrical Characteristics.”

3. Oscillat ion stabiliz ation time after power- on reset

•For MB89PV480,MB89P485L and MB89485L, there is no power-on stabilization time after power-on reset.

•For MB89P485, there is power-on stabilization time after power-on reset.

•For MB89485, the power-on stabilization time can be selected.

•For more information, refer to “■ Mask Option”.

MB89485L MB89485 MB89P485L MB89P485 MB89PV480

Standby mode Sleep mode, stop mode, watch mode, subclock mode.

Process CMOS

Operating Voltage 2.2V ~ 3.6V 2.2V ~ 5.5V 2.7V ~ 3.6V 3.5V ~ 5.5V 2.7V ~ 5.5V

Device

Package MB89485/485L MB89P485/P485L MB89PV480

DIP-64P-M01 O O X

FPT-64P-M09 OOX

MQP-64C-P01 XXO

Part number

Parameter

MB89480/480L Series

■PIN ASSIGNMENT

COM0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

P40/SEG8

P41/SEG9

P42/SEG10

P43/SEG11

P44/SEG12

P45/SEG13

P46/SEG14

P47/SEG15

P50/SEG16

P51/SEG17

P52/SEG18

P53/SEG19

P54/SEG20

P55/SEG21

P56/SEG22

P57

P10/SEG23/INT10

P11/SEG24/INT11

P12/SEG25/INT12

P13/SEG26/INT13

X0A

X1A

C *2

VSS

Vcc

COM1

P30/COM2

P31/COM3

P27/V2/EC1

P26/V1/TO1

V0/SEG0

P25/C0/EC2 *1

P24/C1/TO2 *1

P23/SI

P22/SO

P21/SCK

P20/PWM

P00/INT20

P01/INT21

P02/INT22

P03/INT23 *1

P04/INT24 *1

P05/INT25/PWC

P06/INT26/PPG

P07/INT27/BUZ

AVss

AVcc

P17/SEG30/AN3 *1

P16/SEG29/AN2 *1

P15/SEG28/AN1 *1

P14/SEG27/AN0 *1

RST

MODE

(DIP-64P-M01)

*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively.

Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled.

*2: For product other than MB89P485, pin 31 is NC pin.

(TOP VIEW)

MB89480/480L Series

(FPT-64P-M09)

*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively.

Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled.

*2: For product other than MB89P485, pin 23 is NC pin.

P40/SEG8

P41/SEG9

P42/SEG10

P43/SEG11

P44/SEG12

P45/SEG13

P46/SEG14

P47/SEG15

P50/SEG16

P51/SEG17

P52/SEG18

P53/SEG19

P54/SEG20

P55/SEG21

P56/SEG22

P57

P10/SEG23/INT10

P11/SEG24/INT11

P12/SEG25/INT12

P13/SEG26/INT13

X0A

X1A

Vss

MODE

RST

P14/SEG27/AN0

P15/SEG28/AN1

P16/SEG29/AN2

P17/SEG30/AN3

P25/C0/EC2 *1

P24/C1/TO2 *1

P23/SI

P22/SO

P21/SCK

P20/PWM

P00/INT20

P01/INT21

P02/INT22

P03/INT23 *1

P04/INT24 *1

P05/INT25/PWC

P06/INT26/PPG

P07/INT27/BUZ

AVss

AVcc

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

COM0

Vcc

COM1

P30/COM2

P31/COM3

P27/V2/EC1

P26/V1/TO1

V0/SEG0

(TOP VIEW)

MB89480/480L Series

SEG7

P40/SEG8

P41/SEG9

P42/SEG10

P43/SEG11

P44/SEG12

P45/SEG13

P46/SEG14

P47/SEG15

P50/SEG16

P51/SEG17

P52/SEG18

P53/SEG19

P54/SEG20

P55/SEG21

P56/SEG22

P57

P10/SEG23/INT10

P11/SEG24/INT11

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

COM0

Vcc

COM1

P30/COM2

P31/COM3

P27/V2/EC1

P12/SEG25/INT12

P13/SEG26/INT13

X0A

X1A

Vss

MODE

RST

P14/SEG27/AN0

P15/SEG28/AN1

P16/SEG29/AN2

(TOP VIEW)

(MQP-64C-P01)

*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT 23 and P04/INT24 respectively.

Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled.

*2: Pin 24 is NC pin.

Pin assignment on package top

N.C.: As connect e d int ernally, d o not u s e.

No. Pin

Symbol Pin

No. Pin

Symbol Pin No. Pin

Symbo

No. Pin

Symbol

65 N.C. 73 A2 81 N.C. 89 OE

66 Vpp 74 A1 82 O4 90 N.C.

67 A12 75 A0 83 O5 91 A11

68 A7 76 N.C. 84 O6 92 A9

69 A6 77 O1 85 O7 93 A8

70 A5 78 O2 86 O8 94 A13

71 A4 79 O3 87 CE 95 A14

72 A3 80 VSS 88 A10 96 VCC

P26/V1/TO1

V0/SEG0

P25/C0/EC2 *1

P24/C1/T O2 *1

P23/SI

P22/SO

P21/SCK

P20/PWM

P00/INT20

P01/INT21

P02/INT22

P03/INT23 *1

P04/INT24 *1

P05/INT25/PWC

P06/INT26/PPG

P07/INT27/BUZ

AVss

AVcc

P17/SEG30/AN3 *1

MB89480/480L Series

■PIN DESCRIPTION

(Continued)

Pin Number Pin Name I/O Circuit

Type Function

SH-DIP*1 MQFP*2 QFP*3

33 26 25 X0 AConnection pins for a crystal or other oscillator.

An external clock can be connected to X0. In this case,

leave X1 open.

34 27 26 X1

29 22 21 X0A AConnection pins for a crystal or other oscillator.

An external clock can be connected to X0A. In this case,

leave X1A open.

30 23 22 X1A

35 28 27 MODE B Input pins for setting the memory access mode.

Connect directly to VSS.

36 29 28 RST C

Reset I/O pin. The pin is a N-ch open-drain type with pull-

up resistor and a hysteresis input. The pin outputs a “L”

level when an internal reset request is present. Inputting

an “L” level initializes internal circuits.

50 ~ 48 43 ~ 41 42 ~ 40 P00/INT20

P02/INT22 DGeneral-purpose CMOS I/O port.

A hysteresis input.

The pin is shared with external interrupt 2 input.

47 40 39 P03/INT23 D

General-purpose CMOS I/O port.

A hysteresis input.

The pin is shared with external interrupt 2 input, and

shared with 8/16-bit timer/counter 21, 22 input when

booster is selected.

46 39 38 P04/INT24 D

General-purpose CMOS I/O port.

A hysteresis input.

The pin is shared with external interrupt 2 input, and

shared with 8/16-bit timer/counter 21, 22 output when

booster is selected.

45 38 37 P05/INT25/

PWC D

General-purpose CMOS I/O port.

A hysteresis input.

The pin is shared with external interrupt 2 input, and PWC

input.

44 37 36 P06/INT26/

PPG D

General-purpose CMOS I/O port.

A hysteresis input.

The pin is shared with external interrupt 2 input, and 6-bit

PPG output.

43 36 35 P07/INT27/

BUZ D

General-purpose CMOS I/O port.

A hysteresis input.

The pin is shared with external interrupt 2 input and

buzzer output.

25 ~ 28 18 ~ 21 17 ~ 20

P10/SEG23/

INT10

P13/SEG26/

INT13

F / K

General-purpose N-ch Open-drain I/O port.

A hysteresis input.

The pin is shared with external interrupt 1 input and LCD

segment output.

37 ~ 40 30 ~ 33 29 ~ 32

P14/SEG27/

AN0

P17/SEG30/

AN3

G / K

General-purpose N-ch Open-drain I/O port.

An analog input.

The pin is shared with A/D converter input and LCD

segment output.

LCD segment output will be disabled when booster is

selected.

*1: DIP-64P-M01

*2: MQP-64C-P01

*3: FPT-64P-M09

MB89480/480L Series

(Continued)

Pin Number Pin Name I/O Circuit

Type Function

SH-DIP*1 MQFP*2 QFP*3

51 44 43 P20/PWM E General-purpose CMOS I/O port.

The pin is shared with PWM output.

52 45 44 P21/SCK E General-purpose CMOS I/O port.

The pin is shared with UART/SIO clock I/O.

53 46 45 P22/SO E General-purpose CMOS I/O port.

The pin is shared with UART/SIO data output.

54 47 46 P23/SI D General-purpose CMOS I/O port.

The pin is shared with UART/SIO data input.

55 48 47 P24/C1/TO2 H

General-purpose CMOS I/O port.

The pin is shared with 8/16-bit timer 21,22 output (It is

redirected to P04/INT24 when booster is selected), and

as a capacitor connecting pin when booster is selected.

56 49 48 P25/C0/EC2 F

General-purpose CMOS I/O port.

A hysteresis input.

The pin is shared with 8/16-bit timer 21,22 input (It is

redirected to P03/INT23 when booster is selected), and

as a capacitor connecting pin when booster is selected.

58 51 50 P26/V1/TO1 H General-purpose CMOS I/O port.

The pin is shared with 8/16-bit timer 11,12 output, and

LCD power driving pin.

59 52 51 P27/V2/EC1 F

General-purpose CMOS I/O port.

A hysteresis input.

The pin is shared with 8/16-bit timer 1 1,12 input, and LCD

power driving pin.

62 55 54 P30/COM2 I / K General-purpose N-ch Open-drain output port.

The pin is shared with the LCD common output

61 54 53 P31/COM3 I / K General-purpose N-ch Open-drain output port.

The pin is shared with the LCD common output

9 ~ 16 2 ~ 9 1 ~ 8 P40/SEG8 ~

P47/SEG15 H / K General-purpose N-ch Open-drain I/O port.

The pin is shared with LCD segment output.

17 ~ 23 10 ~ 16 9 ~ 15 P50/SEG16 ~

P56/SEG22 H / K General-purpose N-ch Open-drain I/O port.

The pin is shared with LCD segment output.

24 17 16 P57 J General-purpose CMOS input port.

*1: DIP-64P-M01

*2: MQP-64C-P01

*3: FPT-64P-M09

MB89480/480L Series

(Continued)

*1: DIP-64P-M01

*2: MQP-64C-P01

*3: FPT-64P-M09

*4: When MB89485/485L, MB89P485L or MB89PV480 is used, this pin will become a N.C. pin. When MB89P485 is

used, connect this pin to an external 0.1uF capacitor to ground.

Pin Number Pin Name I/O Circuit

Type Function

SH-DIP*1 MQFP*2 QFP*3

2 ~ 8 59 ~ 64,

158 ~ 64 SEG1 ~

SEG7 K LCD segm ent output only pins.

1, 63 58, 56 57, 55 COM0 ~

COM1 K LCD common output only pins.

60 53 52 V3 —LCD driving power supply pin.

57 50 49 V0/SEG0 — / K LCD driving power supply pin when booster is selected.

LCD segment output when booster is not selected.

31 24 23 C —Capacitor connection pin *4

64 57 56 VCC —Power supply pin (+3V or +5V).

32 25 24 VSS —Power supply pin (GND).

41 34 33 AVCC —A/D converter power supply pin.

42 35 34 AVSS —A/D converter power supply pin.

Use at the same voltage level as VSS.

MB89480/480L Series

• External EPROM Socket (MB89PV480 only)

*1: MQP-64C-P01

Numbe Pin

Name I/O Function

MQFP*1

A14

A13

A12

A11

A10

O Address output pins.

I Data input pins.

N.C. —Internally connected pins. Always leave open.

66 Vpp O“H” level output pin.

80 VSS O Power supply pin (GND).

87 CE O Chip enable pin for the EPROM. Outputs “H” in standby mode.

89 OE O Output enable pin for the EPROM. Always outputs “L”.

96 VCC O Power supply pin for the EPROM.

MB89480/480L Series

■I/O CIRCUIT TYPE

(Continued)

Circuit

Class Circuit Remarks

A•Main/ Sub clock circuit

•Hysteresis input

•The pull-down resistor

Approx. 50kΩ.

(not avai lab le in MB89 P485/

P485L)

•The pull-up resistance (P-

channel)

Approx. 50 kΩ.

•Hysteresis input

•CMOS output

•CMOS input

•Hysteresis input

•Selectable pull-up resistor

Approx. 50 kΩ

•CMOS output

•CMOS input

•Selectable pull-up resistor

Approx. 50 kΩ

X1 (X1A)

X0 (X0A)

Nch Pch

Pch

Nch

Stop mode control signal

Pch

Nch

Pch

Nch

port

resources

pull-up

resistor register

Pch

Nch

port

pull-up

resistor register

MB89480/480L Series

(Continued)

F•N-ch open-drain output

•CMOS input

•Hysteresis input

G•N-ch open-drain output

•CMOS input

•Analog input

H•N-ch open-drain output

•CMOS input

I•N-ch open-drain output

J•CMOS input

K•LCD segment output

Nch

port

resources

Nch

port

analog input

Nch

port

Nch

port

N-ch

P-ch

N-ch

MB89480/480L Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other t han medium- to hi gh-voltage pi ns or if highe r than the voltag e which show s on “1. Absolute Maximum

Ratings” in “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prev ent the analo g power sup ply (A VCC) a nd ana log in put from ex ceedi ng the digit al powe r

supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = VCC and AVSS = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is

therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations

(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

6. Precautions when Using an External Clock

Even when a n e xte r nal c lo ck i s us ed , osc il la tio n st ab iliz ati on ti me is req ui re d f or po wer- on re se t a nd wak e-up

from stop mode.

MB89480/480L Series

■PROGRAMMING OTPROM IN MB89P485/P485L WITH SERIAL PROGRAMMER

1. Programming the OTPROM with serial progr ammer

•All OTP products can be programmed with serial programmer

2. Programming the OTPROM

•To program the OTPROM using EPROM programmer AF200 (manufacturer: Yokogawa Digital Computer

Corp.).Inquiry : Yokogawa Digital Computer Corp. : TEL (81)-42-333-6224

•To program the OTPROM using FUJITSU MCU programmer MB91919-001.

Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770

FAX (65)-2810220

3. Programming Adaptor for OTPROM

•To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adapter

listed below.

Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770

FAX (65)-2810220

4. OTPROM Content Protection

For product with OTPROM content protection feature (MB89P485-103, MB89P485-104), OTPROM content can

be read using serial programmer if the OTPROM content protection mechanism is not activated.

One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM

content. If the protection code "00H" is wri tten in this address (FFFCH), the OTPROM content cannot be read by

any serial programmer.

Note: The program written into the OTPROM cannot be verified once the OTPROM protection code is written

("00H" in FFFCH). It is advised to write the OTPROM protection code at last.

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer , due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

Package Compatible socker adaptor

DIP-64P-M01 MB91919-812

FPT-64P-M09 MB91919-813

MB89480/480L Series

■PROGRAMMING OTPROM IN MB89P485/P485L WITH GENERAL PURPOSE EPROM

PROGRAMMER

1. Programming OTPROM with general purpose EPROM programmer

•Only products without protection feature (i.e. MB89P485/P485L-101 and MB89P485/P485L-102) can be pro-

grammed with general purpose EPROM programmer . Product with protection feature (i.e. MB89P485/P485L-

103 and MB89P485/P485L-104) cannot be programmed with general purpose programmer.

2. ROM Writer Adapters and Recommended ROM Writers

•The following shows ROM writer adapters and recommended ROM writers.

•Contact information

Minato electronics Co., Ltd.: Phone 045-591-5611

3. Memory Space

■ Memory Map of Piggyback/Evaluation Device

4. Writing data to the EPROM

(1) Set the EPROM writer for the CU50-OTP (device code: T.B.D).

(2) Load the program data to the EPROM writer.

(3) Write data using the EPROM writer.

Package name

Applicable adapter model Recommended writer maker and writer

Fujitsu Microelectronics

Asia Pte Ltd. Minato electronics Co., Ltd.

MODEL1890A

DIP-64P-M01 MB91919-604 Under evaluation

FPT-64P-M09 MB91919-605 Under evaluation

Address

Normal operating mode Corresponding addres s es on the EPROM pr ogra mmer

C000H

7FFFH

0000H

0080H

0280H

C000H

FFFFH

I/O

RAM

Not available

PROM

16Kbyte EPROM

16Kbyte

MB89480/480L Series

4. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer , due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

MB89480/480L Series

■PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Programming Socket Adapter

To prog ram to the PROM usi ng an EPROM program mer, use the so cket adapter (manuf acturer: Sun Hay ato

Co., Ltd.) listed below.

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403

3. Memory Space

Memory space in each mode is diagrammed below.

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256.

(2) Load program data into the EPROM programmer at 0000H to 7FFFH.

(3) Program to 0000H to 7FFFH with the EPROM programmer.

Package Adapter socket part number

LCC-32 (Recta ngle) ROM-32LC- 28DP- S

Address

Normal operating mode Corresponding addres s es on the EPROM pr ogra mmer

0000H

7FFFH

0000H

0080H

0480H

8000H

FFFFH

I/O

RAM

Not available

PROM

32KB EPROM

32KB

MB89480/480L Series

■ Block Diagram

Main clock

Clock controller

Sub-clock

RAM (512 bytes / 1K bytes)

F2MC-8L

CPU

ROM (16K bytes / 32K bytes)

Other pins

Vcc, Vss, MODE, C *2

Internal data bus

21-bit timebase

UART/SIO

Port 0

Port 1

P07/INT27/BUZ

P21/SCK

P22/SO

P23/SI

timer

X0A

X1A

Port 3

N-ch open-drain output port

Buzzer output

LCD controller/driver

32 × 4-bit display

RAM (16 bytes)

8-bit PWM timer

Port 4 and Port 5 *

N-ch open-drain I/O po rt

P10/SEG23/INT10

P13/SEG26/INT13

SEG1 t0 SEG7

COM0 to COM1

V0/SEG0 *3

P30/COM2

P31/COM3

Reset circuit

(Watchdog timer)

RST

External interrupt 2

(egde)

16 P56/SEG22

to P54/SEG20

oscillator

Watch prescaler

8/16-bit

timer/counter 21,22

CMOS I/O port *4

Port 2 *

8/16-bit

timer/counter 11,12

Booster

P20/PWM

P24/C1/TO2 *1

P25/C0/EC2 *1

P26/V1/TO1

P27/V2/EC1

CMOS I/O port

External interrupt 2

(level)

8-bit P05/INT25/PWC

PWC timer

6-bit PPG P06/INT26/PPG

P04/INT24 *1

P02/INT22

P03/INT23 *1

to P00/INT20

10-bit

A/D converter

P14/SEG27/AN0 *1

P17/SEG30/AN3 *1

AVcc

AVss

*1: If booster is selected, EC2 and TO2 will be r edirected to P03/INT23 and P04/INT24 respectively.

Segment output of P14/SEG27/AN0 to P17/SEG30/AN3 will be disabled.

*2: For product other than MB89P485, C pin is NC pin.

*3: If booster is selected, it serves as V0. If booster is not selected, it serves as SEG0.

*4: P20 to P23 are CMOS I/O ports. P24 to P27 are N-ch open-drain I/O ports. P57 is input-only port.

N-ch open-drain I/O port

P57

P53/SEG19

to P50/SEG16

P47/SEG15

to P44/SEG12

P43/SEG11

to P40/SEG8

MB89480/480L Series

■CPU CORE

1. Memory Space

The microcontrollers of the MB89480 series offer a memory space of 64 Kbytes for storing all of I/O, data, and

progr am areas . Th e I/O are a is loc ated t he lowe st add ress . The da ta a rea is provide d imme diatel y abo ve the

I/O ar ea. The da ta are a can b e divide d into reg ister, s tack , and di rect ar eas acc ording to the app licat ion. T he

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89480 series is structured as illustrated below.

Memory Space

MB89P485/P485L

General-

purpose

registers

I/O

RAM

ROM

0000H

0080H

0100H

0280H

FFFFH

0200H

Vacant

MB89485/485L

General-

purpose

registers

I/O

RAM

ROM

0000H

0080H

0100H

0280H

FFFFH

0200H

Vacant

MB89PV480

General-

purpose

registers

I/O

RAM

0000H

0080H

0100H

FFFFH

0200H

0480H

ROM

External

(32K)

8000H

Vacant

C000HC000H

FFC0HFFC0HFFC0H

Vector table (reset, interrupt, vector call instruction)

MB89480/480L Series

2. Registers

The F2MC-8L famil y has tw o ty pe s of r eg ister s; de dicat ed r eg is ters i n th e CP U a nd g ene ral- pu rp ose r eg ister s

in the memory. The following registers are provided:

Program counter (PC): A 16-bit register for indicating instruction storage positions

Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator.

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX): A 16-bit register for index modification

Extra pointer (EP): A 16-bit pointer for indicating a memory address

Stack pointer (SP): A 16-bit register for indicating a stack area

Program status (PS): A 16-bit register for storing a register pointer, a condition code

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

16 bits

: Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

FFFDH

Undefined

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

Initial value

Structure of the Program Status Register

Vacancy Vacancy Vacancy

H I IL1, 0 N Z VC

RPPS

109876 321015 14 13 12 11

RP CCR

MB89480/480L Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

The CCR con sists of bits indica ting the results of ar ithmetic operati ons and the conten ts of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

IL1 IL0 Interrupt level High-low

00 1High

Low = no interrupt

10 2

11 3

Rule for Conversion of Actual Addresses of the General-purpose Register Area

“0”

↓

A15

“0”

↓

A14

“0”

↓

A13

“0”

↓

A12

“0”

↓

A11

“0”

↓

A10

“0”

↓

“1”

↓

Lower OP codes

Generated addresses

MB89480/480L Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit resister for storing data

The gen eral-pu rpos e registe rs are 8 bit s and loca ted in the registe r bank s of the memo ry. One ba nk contai ns

eight registers. Up to a total of 32 banks can be used on the MB89480 series. The bank currently in use is

indicated by the register bank pointer (RP).

This address = 0100H + 8 × (RP)

Memory area

32 banks

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

MB89480/480L Series

■ I/O MAP

(Continued)

Address Register name Register Description Read/Write Initial value

00HPDR0 Port 0 data register R/W XXXXXXXXB

01HDDR0 Port 0 data direction register W* 00000000B

02HPDR1 Port 1 data register R/W XXXXXXXXB

03HDDR1 Port 1 data direction register W* 00000000B

04HPDR2 Port 2 data register R/W 00000000B

05H(Reserved)

06HDDR2 Port 2 data direction register R/W 00000000B

07HSYCC System clock control register R/W X-1MM100B

08HSTBC Standby control register R/W 00010XXXB

09HWDTC Watchdog timer control register W* 0---XXXXB

0AHTBTC Timebase timer control register R/W 00---000B

0BHWPCR Watch prescaler control register R/W 00--0000B

0CHPDR3 Port 3 data register R/W ------11B

0DH(Reserved)

0EHRSFR Reset flag register R XXXX----B

0FH(Reserved)

10HPDR4 Port 4 data register R/W 11111111B

11H(Reserved)

12HPDR5 Port 5 data register R/W X1111111B

13H(Reserved)

14H to 1FH(Reserved)

20HSMC1 UART/SIO mode control register 1 R/W 00000000B

21HSMC2 UART/SIO mode control register 2 R/W 00000000B

22HSRC UART/SIO rate control register R/W XXXXXXXXB

23HSSD UART/SIO sta tus /da ta reg ister R 00001- --B

24HSIDR/S ODR UART/SIO data register R/W XXXXXXXXB

25HEIC1 External interrupt 1 control register 1 R/W 00000000B

26HEIC2 External interrupt 1 control register 2 R/W 00000000B

27HEIE2 External interrupt 2 enable register R/W 00000000B

28HEIF2 External interrupt 2 flag register R/W -------0B

29H to 2BH(Reserved)

2CHADC1 A/D control register 1 R/W -0000000B

2DHADC2 A/D control register 2 R/W -0000001B

2EHADDH A/D data register (Upper byte) R ------XXB

2FHADDL A/D data register (Lower byte) R XXXXXXXXB

30HADEN A/D input enable register R/W 1111----B

31HPCR1 P WC co ntr ol register 1 R/W 0-0--0 00B

32HPCR2 P WC co ntr ol register 2 R/W 0000000 0B

33HPLBR PWC reload buffer register R/W XXXXXXXXB

MB89480/480L Series

(Continued)

* Bit manipulation instruction cannot be used.

●Read/write access symbols

R/W : Readable and writable

R : Read-onl y

W: Write- onl y

●Initial value symbols

0: The initia l value of this bit is “0”.

1: The initia l value of this bit is “1”.

X: The initial value of this bit is undefined.

- : Unused bit.

M: The initial value of this bit is determined by mask option.

Address Register name Register Description Read/Write Initial value

34HCNTR PWM timer control register R/W 0-000000B

35HCOMR PWM timer compare register W* XXXXXXXXB

36HT4CR Timer 22 control register R/W 000000X0B

37HT3CR Timer 21 control register R/W 000000X0B

38HT4DR Timer 22 data register R/W XXXXXXXXB

39HT3DR Timer 21 data register R/W XXXXXXXXB

3AHT2CR Timer 12 control register R/W 000000X0B

3BHT1CR Timer 11 control register R/W 000000X0B

3CHT2DR Timer 12 data register R/W XXXXXXXXB

3DHT1DR Timer 11 data register R/W XXXXXXXXB

3EHPPGC1 PPG control register 1 R/W 00000000B

3FHPPGC2 PPG control register 2 R/W 0-000000B

40HBUZR Buzzer control register R/W - ----000B

41 to 5DH(Reserved)

5EHLCR1 LCD controller control register 1 R/W 00010000B

5FHLCR2 LCD controller control register 2 R/W -0000000B

60 to 6FHVRAM LCD data RAM R/W XXXXXXXXB

70HPURC0 Port 0 pull up resistor control register R/W 11111111B

71H(Reserved)

72HPURC2 Port 2 pull up resistor control register R/W ----1111B

73H to 76H(Reserved)

77H(Reserved)

78H(Reserved)

79H(Reserved)

7AH(Reserved)

7BHILR1 Interrupt level setting register 1 W* 11111111B

7CHILR2 Interrupt level setting register 2 W* 11111111B

7DHILR3 Interrupt level setting register 3 W* 11111111B

7EHILR4 Interrupt level setting register 4 W* 11111111B

7FH(Reserved)

MB89480/480L Series

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.

Funct ion al ope r atio n s ho ul d b e res tr icted to the c ond itions a s detail ed in the ope ra tio nal s ec tio ns of

this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Parameter Symbol Value Unit Remarks

Min. Max.

Power su ppl y vol tag e

VCC

AVCC VSS – 0.3 VSS + 6.0 V MB89PV480, MB89P485,

MB89485

AVCC must not exceed VCC

VCC

AVCC VSS – 0.3 VSS + 4.0 V MB89P485L, MB89485L

AVCC must not exceed VCC

LCD Power supply voltage V0 to V3 VSS – 0.3 VSS+ 6.0 V

Input voltage VIVSS – 0.3 VCC + 0.3 V P00 to P07, P10 to P17, P20 to

P27, P40 to P47, P50 to P57

Output voltage VOVSS – 0.3 VCC + 0.3 V P00 to P07, P10 to P17, P20 to

P27, P30 to P31, P40 to P47, P50

to P56

“L” level maximum output current IOL 15 mA

“L” level average output current IOLAV 4mA

Average value (operating current

× operating rate)

“L” level total maximum output

current ∑IOL 100 mA

“L” level total average output

current ∑IOLAV 40 mA Average value (operating current

× operating rate)

“H” level maximum output current IOH –15 mA

“H” level average output current IOHAV –4mA

Average value (operating current

× operating rate)

“H” level total maximum output

current ∑IOH –50 mA

“H” level total average output

current ∑IOHAV –20 mA Average value (operating current

× operating rate)

Power co nsu m pt ion PD300 mW

Operating temperature TA–40 +85 °C

Storage temperature Tstg –55 +150 °C

MB89480/480L Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

* :These values depend on the operating conditions and the analog assurance range. See Figure 1,2 and

“5. A/D Converter Electrical Char acteristics.”

Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MB89P485/485)

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage VCC

AVCC

2.2* 5.5 V Operation assurance

range MB89485

3.5* 5.5 V Operation assurance

range MB89P485

2.7* 5.5 V Operation assurance

range MB89PV480

1.5 5.5 V Retains the RAM state in

stop mode MB89485,

MB89P485,

MB89PV480

2.2* 3.6 V Operation assurance

range MB89485L,

MB89P485L

1.5 3.6 V Retains the RAM state in

stop mode

LCD power supply voltage V0 to V3 Vss Vcc V

Operating temp er atu re TA–40 +85 °C

2.0

4.0

5.0

3.0

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Operating

Voltage (V)

4.0 2.0 1.0 0.41.33 0.8 0.66 0.57 0.50 0.44

Main clock

operating Freq. (MHz)

Min execution

time (inst. cycle) (µs)

3.5

2.7

11.0 12.0 12.5

0.36 0.33 0.32

Analog accuracy

assurance range :

Vcc = AVcc =4.5V~ 5.5V

5.5

2.2

4.5

Note : The shaded area is not assured for MB89P485

MB89480/480L Series

Figure 2 Operating Voltage vs. Main Clock Operating Frequency (MB89P485L/485L)

Figure 3 Operating Voltage vs. Main Clock Operating Frequency (MB89PV480)

Figure 1,2 and 3 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating

speed is switched using a gear.

2.0

3.0

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Operating

Voltage (V)

4.0 2.0 1.0 0.41.33 0.8 0.66 0.57 0.50 0.44

3.6

2.7

11.0 12.0 12.5

0.36 0.33 0.32

Analog accuracy

assurance range :

Vcc = AVcc =2.7V~ 3. 6V

2.2

Min execution

time (inst. cycle) (µs)

Main clock

operating Freq. (MHz)

Note : The shaded area is not assured for MB89P485L

4.0

5.0

3.0

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Operating

Voltage (V)

4.0 2.0 1.0 0.41.33 0.8 0.66 0.57 0.50 0.44

Main clock

operating Freq. (MHz)

Min execution

time (inst. cycle) (µs)

3.5

2.7

11.0 12.0 12.5

0.36 0.33 0.32

Analog accuracy

assurance range :

Vcc = AVcc =4.5 V~ 5.5 V

5.5

4.5

MB89480/480L Series

3. DC Characteristics

AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485

AVCC = VCC = 3.0 V for MB89P485L, MB89485L

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

(Continued)

Parameter Symbol Pin Condition Value Unit Remarks

Min. Typ. Max.

“H” level

input voltage

VIH

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P40 ~ P47,

P50 ~ P57

—0.7 VCC —VCC + 0.3 V

VIHS

RST, MODE, EC1,

EC2, PWC, SCK, SI,

INT10 ~ INT13, INT20

~ INT27 —0.8 VCC —VCC + 0.3 V

“L” level

input voltage

VIL

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P40 ~ P47,

P50 ~ P57

—VSS − 0.3 —0.3 VCC V

VILS

RST, MODE, EC1,

EC2, PWC, SCK, SI,

INT10 ~ INT13, INT20

~ INT27 —VSS − 0.3 —0.2 VCC V

Open-drain

output pi n

application

voltage VD

P10 ~ P17,

P24 ~ P27,

P30 ~ P31,

P40 ~ P47,

P50 ~ P56

—VSS − 0.3 —VCC + 0.3 V

Product without

booster

V3 Product with

booster

“H” level

output voltage VOH P00 ~ P07,

P20 ~ P23 IOH = –2.0mA 4.0 ——VMB89PV480

MB89P485

MB89485

2.2 ——VMB89P485L

MB89485L

“L” level

output voltage VOL

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P30 ~ P31,

P40 ~ P47,

P50 ~ P56, RST

IOL = 4.0 mA ——0.4 V

Input leakage

current ILI

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P40 ~ P47,

P50 ~ P57

0.45 V < VI <

VCC -5 —+5µA Without

pull-up resister

Open-drain

output leakage

current ILOD

P10 ~ P17,

P24 ~ P27,

P30 ~ P31,

P40 ~ P47,

P50 ~ P56

0.45 V < VI <

VCC -5 —+5µA

MB89480/480L Series

(Continued)

Parameter Symbol Pin Condition Value Unit Remarks

Min. Typ. Max.

Pull-down

resistance RDOWN MODE VI = VCC 25 50 100 kΩExcept

MB89P485,

MB89P485L

Pull-up

resistance RPULL P00 ~ P07,

P20 ~ P23,

RST VI = 0.0 V 25 50 100 kΩ

When pull-up

resistor is

selected

(except RST)

Common

output

impedance RVCOM COM0 to COM3

V1 to V3 = +3.0 V

——2.5 kΩ

MB89P485L,

MB89485L

V1 to V3 = +5.0 V MB89PV480,

MB89P485,

MB89485

Segment

output

impedance RVSEG SEG0 to SEG30

V1 to V3 = +3.0 V

——15 kΩ

MB89P485L,

MB89485L

V1 to V3 = +5.0 V MB89PV480,

MB89P485,

MB89485

LCD divided

resistance RLCD —Between VCC and

Vss 300 500 750 kΩ

LCD

controller/

driver

leakage

current

ILCDL V0 to V3,

COM0 to COM3,

SEG0 to SEG30 ———

±1µA

Booste r for

LCD driving

output

voltage

VV3 V3 V1 = 1.5V 4.3 4.5 4.7 V

Products with

booster only

VV2 V2 V1 = 1.5V 2.9 3.0 3.1 V

Reference

input voltage

for LCD

driving VV1 V1 IIN = 0 µA1.41.51.7

Reference

voltage input

impedance RRIN V1 —8.5 9.8 11 kΩ

Input

capacitance CIN Other than

VCC,VSS,AVCC,AVSS f=1MHz —10 —pF

MB89480/480L Series

(Continued)

Parameter Symbol Pin Condition Value Unit Remarks

Min. Typ. Max.

Power supply

current

ICC1

VCC

FCH = 12.5MHz

tinst = 0.32 µs

Main cl ock

run mode —813mA

ICC2

FCH = 12.5MHz

tinst = 5.12 µs

Main cl ock

run mode —0.7 3 mA

ICCS1

FCH = 12.5MHz

tinst = 0.32 µs

Main cl ock

sleep mode —2.5 5 mA

ICCS2

FCH = 12.5MHz

tinst = 5.12 µs

Main cl ock

sleep mode —0.4 2 mA

ICCL FCL = 32.768kHz

Subclock mode —50 85 µAExcept

MB89P485

—54 91 µA MB89P485

ICCLS FCL = 32.768kHz

Subclock sleep

mode

—15 30 µAExcept

MB89P485

—19 36 µA MB89P485

ICCT

FCL = 32.768kHz

• Watch mode

• Main c lo ck stop

mode

—1.6 15 µAExcept

MB89P485

—5.6 21 µA MB89P485

ICCH Ta=+250C

Subclock stop

mode —310µA

IAAVcc Ta=+250C—46mA

A/D

converting

IAH —15µA A/D stop

MB89480/480L Series

4. AC Characteristics

(1) Reset Timing VCC = 5.0 V for MB89PV480, MB89P485, MB89485

VCC = 3.0 V for MB89P485L, MB89485L

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Note: tHCYL is the oscillation cycle (1/FC) to input to the X0 pin.

The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH.

(2) Power-on Reset

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Note: Make sure that power supply rises within the selected oscillation stabilization time.

Rapid chan ges in po wer su pply voltag e may c ause a power- on reset. If power suppl y voltag e ne eds to

be varied in the course of operation, a smooth voltage rise is recommended.

Parameter Symbol Condition Value Unit Remarks

Min. Max.

RST “L” pulse width tZLZH —48 tHCYL —ns

Parameter Symbol Condition Value Unit Remarks

Min. Max.

Power supply rising time tR——50 ms

Power supply cut-off time tOFF 1—ms Due to repeated operations

tZLZH

0.2 VCC 0.2 VCC

RST

0.2 V 0.2 V

0.2 V

VCC

tOFF

Vth

Vth = 3.5 V for MB89PV480, MB89P485 and MB89485

Vth = 1.8 V for MB89P485L and MB89485L

MB89480/480L Series

(3) Clock Timing

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin Value Unit Remarks

Min. Typ. Max.

Clock freque nc y FCH X0, X1 1 —12.5 MHz

FCL X0A, X1A —32.768 —kHz

Clock cy cle time tHCYL X0, X1 80 —1000 ns

tLCYL X0A, X1A —30.5 —µs

Input clock pulse width

PWH

PWL X0 20 ——ns

External clock

PWHL

PWLL X0A —15.2 —µs

Input clock rising/falling time tCR

tCF X0, X0A ——10 ns

0.2

0.8

X0 0.2

0.8

0.2

X0 X1 X0 X1

When a crystal

ceramic reasonator is used When an external clock is used

Open

HCYL

C1 C2 F

X0 and X1 Timing and Conditions

Main Clock Conditions

MB89480/480L Series

(4) Instruction Cycle

Parameter Symbol Value Unit Remarks

Instruction cycle

(minim um executio n time) tinst

4/FCH, 8/FCH, 16/FCH, 64/FCH µs(4/FCH)tinst = 0.32 µs when operating

at FCH = 12.5 MHz

2/FCL µstinst = 61.036 µs when operating at

FCL = 32.768 kHz

X0A X1A

C0C1

Rd Open

When a crystal

ceramic oscillator is used When subclock is not used

X0A X1A

FCL

0.8 VCC

tLCYL

0.2 VCC

PWHL PWLL

tCF tCR

X0A

Open

When an external clock is used

FCL

X0A X1A

Subclock Timing and Conditions

Subclock Conditions

MB89480/480L Series

(5) Serial I/O Timing

VCC = 5.0 V for MB89PV480, MB89P485, MB89485 ,VCC = 3.0 V for MB89P485L, MB89485L

(AVSS = VSS= 0.0 V, T A = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle.”

Parameter Symbol Pin Condition Value Unit

Min. Max.

Serial clock cycle time tSCYC SCK Internal

shift clock

mode

2 tinst*—µs

SCK ↓ → SO time tSLOV SCK, SO –200 200 ns

Valid SI → SCK ↑tIVSH SI, SCK 1/2 tinst*—ns

SCK ↑ → valid SI hold time tSHIX SCK, SI 1/2 tinst*—ns

Serial cloc k “H” puls e width tSHSL SCK External

shift clock

mode

1 tinst*—µs

Seri al cl oc k “L” pulse width tSLSH 1 tinst*—µs

SCK ↓ → SO time tSLOV SCK, SO 0 200 ns

Valid SI → SCK ↑tIVSH SI, SCK 1/2 tinst*—ns

SCK ↑ → valid SI hold time tSHIX SCK, SI 1/2 tinst*—ns

0.2 VCC

0.8 VCC

tSLSH

2.4 V

0.2 VCC

0.8 VCC

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

SCK

0.2 VCC

tSHSL

tSHIX

tIVSH

tSLOV

External Clock Operation

0.8 V

2.4 V

tSCYC

2.4 V

0.2 VCC

tSHIX

0.8 V

tIVSH

0.8 VCC

0.2 VCC

0.8 VCC

SCK

tSLOV

Internal Clock Operation

MB89480/480L Series

(6) Peripheral Input Timing

VCC = 5.0 V for MB89PV480, MB89P485, MB89485

VCC = 3.0 V for MB89P485L, MB89485L

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) In struction Cycle.”

Parameter Symbol Pin Value Unit Remarks

Min. Max.

Peripheral input “H” pulse width 1 tILIH1 INT10 ~ 13, INT20 ~

INT27, EC1, EC2, PWC 2 tinst*—µs

Peripheral input “L” pulse width 1 tIHIL1 2 tinst*—µs

0.2 VCC

0.8 VCC

t IHIL1

0.8 VCC

INT10 to 13,

INT20 to 27,

EC1, EC2,

PWC 0.2 VCC

t ILIH1

MB89480/480L Series

5. A/D Converter Elect rical Characteristics

(1) A/D Converter Electrical Characteristics

( AVCC = VCC = 4.5 V ~ 5.5 V for MB89PV480, MB89P485, MB89485,

AVCC = VCC = 2.7 V ~ 3.6 V for MB89P485L, MB89485L,

AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics".

(2) A/D Converter Glossary

•Resolution

Analog changes that are identifiable with the A/D converter

When the number of bits is 10, analog voltage can be divided into 210 = 1024.

•Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point ("00 0000 0000" ↔ "00 0000 0001") with

the full-scale transition point ("11 1111 1111" ↔ "11 1111 1110") from actual conversion characteristics.

•Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.

•Total error (unit: LSB)

The difference between theoretical and actual conversion values.

Parameter Symbol Pin Value Unit Remarks

Min. Typ. Max.

Resolution

—

—10 —bit

Total error ——±3.0 LSB

Linearity error ——±2.5 LSB

Dif fere nti al lin ear ity error ——±1.9 LSB

Zero transition voltage VOT AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB LSB

Full-scale transition

voltage VFST AVCC – 3.5 LSB AVCC – 1.5 LSB AVCC + 0.5 LSB LSB

A/D mode conversion time ———60 tinst* µs

Analog port input current IAIN AN0 to

AN3 ——10 µA

Analog i nput voltage VAIN AVSS —AVCC V

MB89480/480L Series

0.5 LSB

1 LSB

Analog input

AVSS

1.5 LSB

Theoretical I/O characteristics

3FF

3FE

3FD

004

003

002

001

AVCC

Theoretical value

Analog input

AVSS

VNT

Actual conversion

value

Total error

3FF

3FE

3FD

004

003

002

001

AVCC

{1 LSB × N + V

}

VFST

VOT Actual conversion

value

Total error = VNT – {1 LSB × N + 0.5 LSB}

1 LSB

1 LSB = VFST – VOT

1022

Digital output

(V)

Analog input

AVSS

Linearity error

3FF

3FE

3FD

004

003

002

001

AVCC

Theoretical value

Analog input

AVSS

VNT

V(N + 1)T

Actual conversion

value

Differential linearity error

N + 1

N – 1

N – 2

AVCC

VOT (Actual measurement)

Actual conversion value

Differential linearity error = 1 LSB

V(N + 1)T – VNT

Digital output

Linearity error = VNT – {1 LSB × N + VOT}

1 LSB – 1

{1 LSB × N + VOT}

Actual conversion

value

VFST

(Actual

measurement)

Theoretical value

Analog input

AVSS

Zero transition error

004

003

002

001

Theoretical value

Analog input

Actual conversion

value

Full-scale transition error

AVCC

Actual conversion value

Digital output

Actual conversion

value

Actual conversion

value

VOT (Actual measurement)

VFST

(Actual

measurement)

3FF

3FE

3FD

3FC

MB89480/480L Series

(3) Notes on Using A/D Converter

•Input impedance of the analog input pins

The A/D co nverter used for the MB 89470 series conta ins a sample hold c ircuit as illustrate d below to fetch

analog input voltage into the sample hold capacitor for 16 instruction cycles after activation A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize wi thi n th e an alo g input sam pl ing per io d. T he refor e, i t is rec omm end ed to keep the ou tput

impedance of the external circuit low.

Note that if the impedanc e cann ot be kept lo w, it is rec ommend ed to conn ect an exter nal capac itor of about

0.1 µF for the analog input pin.

•Error

The smaller the |AVR - AVSS|, the greater the error would bec ome rela tivel y.

MB89485

MB89PV480 MB89485L MB89P485 MB89P485L

R: analog input equiv ale nt res i sta nce 2.2 kΩ7.1 kΩ2.6 kΩ2.8 kΩ

C: analog in put equiv ale nt cap ac itan ce 45 pF 48.3 pF 28 pF 46 pF

Analog input pin

Sample hold circuit

If the analog input

impedance is too low,

it is recommended to

connect an external

capacitor of approx.

0.1 µF.

Comparator

R C

Analog channel selector

Close for 16 instruction cycles after

activating A/D conversion.

Analog Input Circuit Model

MB89480/480L Series

■INSTRUCTIONS

Execution instructions can be divided into the following four groups:

•Transfer

•Arithm etic ope ra tio n

•Branch

•Others

Table 1 lists symbols used for notation of instructions.

(Continued)

Table 1 Instruction Symbols

Symbol Meaning

dir Direct address (8 bits)

off Offset (8 bits)

ext Extended address (16 bits)

#vct Vector table number (3 bits)

#d8 Immediate data (8 bits)

#d16 Immediate data (16 bits)

dir: b Bit direct address (8:3 bits)

rel Branch relative address (8 bits)

@ Register indirect (Example: @A, @IX, @EP)

A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

AH Upper 8 bits of accumulator A (8 bits)

AL Lower 8 bits of accumulator A (8 bits)

TTemporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

TH Upper 8 bits of temporary accumulator T (8 bits)

TL Lower 8 bits of temporary accumulator T (8 bits)

IX Index register IX (16 bits)

MB89480/480L Series

(Continued)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~: Number of instructions

#: Number of bytes

Operation: Operation of an instruction

TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

•“–” indicates no change.

•dH is the 8 upper bits of operation description data.

•AL and AH must become the contents of AL and AH immediately before the instruction

is executed.

•00 becomes 00.

N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

OP code: Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

Symbol Meaning

EP Extra pointer EP (16 bits)

PC Program counter PC (16 bits)

SP Stack pointer SP (16 bits)

PS Program status PS (16 bits)

dr Accumulator A or index register IX (16 bits)

CCR Condition code register CCR (8 bits)

RP Register bank pointer RP (5 bits)

Ri General-purpose register Ri (8 bits, i = 0 to 7)

×Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × ) Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

(( × )) The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

MB89480/480L Series

Notes: •During byte transfer to A, T ← A is restricted to low bytes.

•Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F2MC-8 family)

Table 2 Transfer Instructions (48 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

SETB dir: b

CLRB dir: b

XCH A,T

XCHW A,T

XCHW A,E P

XCHW A,IX

XCHW A,S P

MOVW A,PC

(dir) ← (A)

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

(A) ← (Ri)

(dir) ← d8

( (IX) +off ) ← d8

( (EP) ) ← d8

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL )

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

– – – –

+ + – –

– – – –

+ + – –

– – – –

+ + + +

– – – –

48 to 4F

08 to 0F

88 to 8F

A8 to AF

A0 to A7

MB89480/480L Series

(Continued)

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

ROLC A

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

DAS

XOR A

XOR A,# d8

XOR A,d ir

XOR A,@ EP

XOR A,@ IX +o ff

XOR A,Ri

AND A

AND A,#d8

AND A,dir

(A) ← (A) + (Ri) + C

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) ∧ (T)

(A) ← (A) ∨ (T)

(A) ← (A) ∀ (T)

(TL) − (AL)

(T) − (A)

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +of f)

(A) − (Ri)

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) ∀ (TL)

(A) ← (AL) ∀ d8

(A) ← (AL) ∀ (dir)

(A) ← (AL) ∀ ( (EP) )

(A) ← (AL) ∀ ( (IX) +off)

(A) ← (AL) ∀ (Ri)

(A) ← (AL) ∧ (TL )

(A) ← (AL) ∧ d8

(A) ← (AL) ∧ (dir)

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

+ + + +

+ + R –

28 to 2F

38 to 3F

C8 to CF

D8 to DF

18 to 1F

58 to 5F

←

→→

MB89480/480L Series

(Continued)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

DECW SP

(A) ← (AL) ∧ ( (EP) )

(A) ← (AL) ∧ ( (IX) +off)

(A) ← (AL) ∧ (Ri)

(A) ← (AL) ∨ (TL)

(A) ← (AL) ∨ d8

(A) ← (AL) ∨ (dir)

(A) ← (AL) ∨ ( (EP) )

(A) ← (AL) ∨ ( (IX) +off)

(A) ← (AL) ∨ (Ri)

(dir) – d8

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

–

+ + R –

+ + + +

– – – –

68 to 6F

78 to 7F

98 to 9F

Table 4 Branch Instructions (17 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BL O re l

BNC/BHS rel

BN rel

BP rel

BLT rel

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

RETI

If Z = 1 then PC ← PC + re l

If Z = 0 then PC ← PC + re l

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V ∀ N = 1 then PC ← PC + rel

If V ∀ N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

– – – –

– + – –

– – – –

Restore

B0 to B7

B8 to BF

E8 to EF

Table 5 Other Instructions (9 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

CLRI

SETI

–

– – – –

– – – R

– – – S

– – – –

MB89480/480L Series

■ INSTRUCTION MAP

0123456789ABCDEF

0NOP SWAP RET RETI PUSHWAPOPW AMOV

A,ext MOVW

A,PS CLRI SETI CLRB

dir: 0 BBC

dir: 0,rel INCW ADECW AJMP @A MOVW

A,PC

1MULU ADIVU AJMP

addr16 CALL

addr16 PUSHW

IX POPWIX MOV

ext,A MOVW

PS,A CLRC SETC CLRB

dir: 1 BBC

dir: 1,rel INCWSP DECWSP MOVW

SP,A MOVW

A,SP

2ROLC ACMP AADDC ASUBC AXCH A, T XOR AAND AOR AMOV

@A,T MOV

A,@A CLRB

dir: 2 BBC

dir: 2,rel INCW IX DECWIX MOVW

IX,A MOVW

A,IX

3RORC ACMPW AADDCW

ASUBCWAXCHW

A, T XORW AANDW AORW AMOVW

@A,T MOVW

A,@A CLRB

dir: 3 BBC

dir: 3,rel INCWEP DECWEP MOVW

EP,A MOVW

A,EP

4MOV

A,#d8 CMP

A,#d8 ADDC

A,#d8 SUBC

A,#d8 XOR

A,#d8 AND

A,#d8 ORA,#d8 DAA DAS CLRB

dir: 4 BBC

dir: 4,rel MOVW

A,ext MOVW

ext,A MOVW

A,#d16 XCHW

A,PC

5MOVA,dir CMPA,dir ADDC

A,dir SUBC

A,dir MOVdir,A XORA,dir ANDA,dir OR A,dir MOV

dir,#d8 CMP

dir,#d8 CLRB

dir: 5 BBC

dir: 5,rel MOVW

A,dir MOVW

dir,A MOVW

SP,#d16 XCHW

A,SP

6MOV

A,@I X

CMP

A,@IX

ADDC

A,@I X

SUBC

A,@IX

MOV

@IX

+d,A

XOR

@A,IX

AND

A,@IX

MOV@IX

+d,#d8

CMP@IX

+d,#d8

CLRB

dir: 6 BBC

dir: 6,rel MOVW

A,@IX

MOVW

@IX

+d,A

MOVW

IX,#d16 XCHW

A,IX

7MOV

A,@EP CMP

A,@EP ADDC

A,@EP SUBC

A,@EP MOV

@EP,A XOR

A,@EP AND

A,@EP OR

A,@EP MOV

@EP,#d8 CMP

@EP,#d8 CLRB

dir: 7 BBC

dir: 7,rel MOVW

A,@EP MOVW

@EP,A MOVW

EP,#d16 XCHW

A,EP

8MOV

A,R0 CMP

A,R0 ADDC

A,R0 SUBC

A,R0 MOV

R0,A XORA,R0 ANDA,R0 OR A,R0 MOV

R0,#d8 CMP

R0,#d8 SETB

dir: 0 BBS

dir: 0,rel INC R0 DEC R0 CALLV

#0 BNC rel

9MOV

A,R1 CMP

A,R1 ADDC

A,R1 SUBC

A,R1 MOV

R1,A XORA,R1 ANDA,R1 OR A,R1 MOV

R1,#d8 CMP

R1,#d8 SETB

dir: 1 BBS

dir: 1,rel INC R1 DEC R1 CALLV#1 BC rel

AMOV

A,R2 CMP

A,R2 ADDC

A,R2 SUBC

A,R2 MOV

R2,A XORA,R2 ANDA,R2 OR A,R2 MOV

R2,#d8 CMP

R2,#d8 SETB

dir: 2 BBS

dir: 2,rel INC R2 DEC R2 CALLV#2 BP rel

BMOV

A,R3 CMP

A,R3 ADDC

A,R3 SUBC

A,R3 MOV

R3,A XORA,R3 ANDA,R3 OR A,R3 MOV

R3,#d8 CMP

R3,#d8 SETB

dir: 3 BBS

dir: 3,rel INC R3 DEC R3 CALLV#3 BN rel

CMOV

A,R4 CMP

A,R4 ADDC

A,R4 SUBC

A,R4 MOV

R4,A XORA,R4 ANDA,R4 OR A,R4 MOV

R4,#d8 CMP

R4,#d8 SETB

dir: 4 BBS

dir: 4,rel INC R4 DEC R4 CALLV

#4 BNZ rel

DMOV

A,R5 CMP

A,R5 ADDC

A,R5 SUBC

A,R5 MOV

R5,A XORA,R5 ANDA,R5 OR A,R5 MOV

R5,#d8 CMP

R5,#d8 SETB

dir: 5 BBS

dir: 5,rel INC R5 DEC R5 CALLV#5 BZ rel

EMOV

A,R6 CMP

A,R6 ADDC

A,R6 SUBC

A,R6 MOV

R6,A XORA,R6 ANDA,R6 OR A,R6 MOV

R6,#d8 CMP

R6,#d8 SETB

dir: 6 BBS

dir: 6,rel INC R6 DEC R6 CALLV

#6 BGE rel

FMOV

A,R7 CMP

A,R7 ADDC

A,R7 SUBC

A,R7 MOV

R7,A XORA,R7 ANDA,R7 OR A,R7 MOV

R7,#d8 CMP

R7,#d8 SETB

dir: 7 BBS

dir: 7,rel INC R7 DEC R7 CALLV

#7 BLT rel

MB89480/480L Series

■MASK OPTIONS

No. Part number MB89 485 MB8 9485 L MB89P 485 MB89P4 85L MB89PV480

Specifying procedur e Specify when

ordering masking Setting not possible Setting not possible

Booster selection (KSV)

•Internal resistor

ladder

•Booster

Selectable 101: Internal resistor ladder

102: Booster 101: Internal resistor

ladder

102: Booster

Selection of OTPROM

content pr otecti on

feature

•No protection feature

•With protection

feature

-- 101/102: No protection

103/104: with protection --

Selection of oscillation

stabilization time (OSC)

•The initial value of the

oscillation stabilization

time for the main clock

can be set by

selecting the values of

the WTM1 and WTM0

bits on the right.

Selectable

OSC

1 : 214/FCH

2 : 217/FCH

3 : 218/FCH

Fixed to oscillation

stabilization time of 218/FCH

Fixed to oscillation

stabilization time of

218/FCH

Selectio n of power- on

stabilization time

•Nil

•217/FCH

Selectab le Fixed to n il 217/FCH Fixed to nil Fixed to nil

MB89480/480L Series

■ORDERING INFORMATION

Part number Package Remar ks

MB89485PFM

MB89P485PFM-101

MB89P485PFM-102

MB89P485PFM-103

MB89P485PFM-104

MB89485LPFM

MB89P485LPFM-101

MB89P485LPFM-102

MB89P485LPFM-103

MB89P485LPFM-104

64-pin Pl as tic QFP

(FPT-64P-M09) 101: With internal resistor

ladder, without con-

tent protection

102: With booster, with-

out content protec-

tion

103: With internal resistor

ladder, with content

protection

104: With booster, with

content protection

MB89485P-SH

MB89P485P-SH-101

MB89P485P-SH-102

MB89P485P-SH-103

MB89P485P-SH-104

MB89485LP-SH

MB89P485LP-SH-101

MB89P485LP-SH-102

MB89P485LP-SH-103

MB89P485LP-SH-104

64-pin Plastic SH-DIP

(DIP-64P-M01)

MB89PV480CF-101

MB89PV480CF-102 64 -p in Cerami c MQFP

(MQP-64C-P01)

MB89480/480L Series

■PACKAGE DIMENSIONS

2001 FUJITSU LIMITED D64001S-c-4-5

58.00

+0.22

–0.55 +.009

–.022

2.283

17.00±0.25

(.669±.010)

3.30

+0.20

–0.30

.130

–.012

+.008

+.028

–.008

.195

–0.20

+0.70

4.95

+.016

–.008

.0543

–0.20

+0.40

1.378 1.778(.0700) 0.47±0.10

(.019±.004) 1.00

+0.50

–0

.039

–.0

+.020

–.007

.028

–0.19

+0.50

0.70

19.05(.750)

(.011±.004)

0.27±0.10

0~15°

INDEX-2

INDEX-1

0.25(.010)

Dimensions in mm (inches)

64-pin Plastic SH-DIP

DIP-64P-M01

64-pin Plastic LQFP

FPT-64P-M09

Dimensions in mm (inches)

2001 FUJITSU LIMITED F64018S-c-2-4

0.65(.026)

0.10(.004)

116

3348

12.00±0.10(.472±.004)SQ

14.00±0.20(.551±.008)SQ

INDEX

0.32±0.05

(.013±.002)

0.13(.005)

0.145±0.055

(.0057±.0022)

"A"

.059 –.004

+.008

–0.10

+0.20

1.50

0~8°

0.25(.010)

(Mounting height)

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

Details of "A" part

(Stand off)

0.10(.004)

MB89480/480L Series

MQP-64C-P01

64-pin Ceramic MQFP

MB89480/480L Series

MEMO

MB89480/480L Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: (044) 754-3763

Fax: (044) 754-3329

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866- 860 8

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreie ic h-Bu chsc hlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE L TD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

http://www.fmap.com.sg/

Circuit diagrams utilizing Fujitsu products are included as a

means of illustrating typical semiconductor applications.

Complete information sufficient for construction purposes is not

necessar ily given.

The info rmation contai ned in th is document has been care fully

checked and is believed to be reliable. However, Fujitsu

assumes no responsibility for inaccuracies.

The information contained in this document does not convey any

license under the copyrights, patent rights or trademarks claimed

and owned by Fujitsu.

Fujitsu reserves the right to change products or specifications

without notice.

No part of this p ublica tio n may be copied or repr oduced i n any

form or by any means, or transfe rred to any third party without

prior written consent of Fujitsu.

The infor mation c ontain ed in this docu ment a re not i ntended fo r

use with equipments which require extremely high reliability

such as aerospace equipments, undersea repeaters, nuclear

contro l syst ems or medical equi pments for life sup port.