SP3232EUCA-L/TR - Sipex Corporation

3.3V, 1000 Kbps RS-232 Transceiver s

SP3222EU/3232EU

DESCRIPTION

■ Meets true EIA/TIA-232-F Standards

from a +3.0V to +5.5V power supply

■ Interoperable with EIA/TIA - 232 and

adheres to EIA/TIA - 562 down to a +2.7V

power source

■ 1µA Low-Power Shutdown with Receivers

Active (SP3222EU)

■ Enhanced ESD Specifications:

±15kV Human Body Model

±15kV IEC1000-4-2 Air Discharge

±8kV IEC1000-4-2 Contact Discharge

■ 1000 kbps Minimum Transmission Rate

■ Ideal for Handheld, Battery Operated

Applications

SELECTION TABLE

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The SP3222EU and the SP3232EU are 2 driver, 2 receiver RS-232 transceiver solutions

intended for portable or hand-held applications such as notebook or palmtop computers.

Their data transmission rate of 1000 kbps meets the demands of high speed RS-232

applications. Both ICs have a high-efficiency, charge-pump power supply that requires

only 0.1µF capacitors in 3.3V operation. This charge pump allows the SP3222EU and the

3232EU to deliver true RS-232 performance from a single power supply ranging from

+3.0V to +5.5V. The ESD tolerance of the SP3222EU/3232EU devices are over ±15kV

for both Human Body Model and IEC1000-4-2 Air discharge test methods.

The SP3222EU device has a low-power shutdown mode where the devices' driver

outputs and charge pumps are disabled. During shutdown, the supply current falls to less

than 1uA.

NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional

operation of the device at these ratings or any other

above those indicated in the operation sections of

the specifications below is not implied. Exposure to

absolute maximum rating conditions for extended

periods of time may affect reliability and cause

permanent damage to the device.

VCC ...................................................... -0.3V to +6.0V

V+ (NOTE 1) ...................................... -0.3V to +7.0V

V- (NOTE 1) ....................................... +0.3V to -7.0V

V+ + |V-| (NOTE 1)...........................................+13V

ICC (DC VCC or GND current)......................... ±100mA

Input Voltages

TxIN, EN ............................................ -0.3V to +6.0V

RxIN .................................................................. ±25V

Output Voltages

TxOUT.......................................................±13.2V

RxOUT............. ..................-0.3V to (VCC + 0.3V)

Short-Circuit Duration

TxOUT.................................................Continuous

Storage Temperature.................-65°C to +150°C

Power Dissipation Per Package

20-pin SSOP (derate 9.25mW/oC above +70oC)........750mW

18-pin PDIP (derate 15.2mW/oC above +70oC) .......1220mW

18-pin SOIC (derate 15.7mW/oC above +70oC) ....... 1260mW

20-pin TSSOP (derate 11.1mW/oC above +70oC)...... 890mW

16-pin SSOP (derate 9.69mW/oC above +70oC)........775mW

16-pin PDIP (derate 14.3mW/oC above +70oC) .......1150mW

16-pin Wide SOIC (derate 11.2mW/oC above +70oC) .... 900mW

16-pin TSSOP (derate 10.5mW/oC above +70oC)...... 850mW

16-pin nSOIC (derate 13.57mW/°C above +70°C) ...... 1086mW

SPECIFICATIONS

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX, C1 to

C4=0.1µF

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

DC CHARACTERISTICS

Supply Current 0.3 1.0 mA no load, TAMB = +25°C, VCC = 3.3V,

TxIN = GND or VCC

Shutdown Supply Current 1.0 10 µASHDN = GND,TAMB = +25°C,

VCC= +3.3V, TxIN = GND or VCC

LOGIC INPUTS AND RECEIVER OUTPUTS

Input Logic Threshold LOW GND 0.8 V TxIN, EN, SHDN, Note 2

Input Logic Threshold HIGH 2.0 V VCC = 3.3V, Note2

2.4 VCC VCC = 5.0V, Note 2

Input Leakage Current ±0.01 ±1.0 µATxIN, EN, SHDN, TAMB = +25°C,

VIN= 0V to VCC

Output Leakage Current ±0.05 ±10 µAreceivers disabled, VOUT = 0V to VCC

Output Voltage LOW 0.4 V IOUT = 1.6mA

Output Voltage HIGH VCC-0.6 VCC-0.1 V IOUT = -1.0mA

DRIVER OUTPUTS

Output Voltage Swing ±5.0 ±5.4 V 3kΩ load to ground at all driver

outputs,TAMB = +25°C

Output Resistance 300 ΩVCC = V+ = V- = 0V, TOUT = +2V

Output Short-Circuit Current ±35 ±60 mA VOUT = 0V

Output Leakage Current ±25 µAV

OUT = +12V,VCC= 0V to 5.5V,drivers

disabled

SPECIFICATIONS (continued)

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX , C1 to

C4=0.1µF. Typical Values apply at VCC = +3.3V or +5.5V and TAMB = 25oC.

NOTE 2: Driver input hysteresis is typically 250mV.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

RECEIVER INPUTS

Input Voltage Range -25 +25 V

Input Threshold LOW 0.6 1.2 V VCC=3.3V

0.8 1.5 V VCC=5.0V

Input Threshold HIGH 1.5 2.4 V VCC=3.3V

1.8 2.4 V VCC=5.0V

Input Hysteresis 0.3 V

Input Resistance 3 5 7 kΩ

TIMING CHARACTERISTICS

Maximum Data Rate 1000 kbps RL=3kΩ, CL=250pF, one driver

switching

Receiver Propagation Delay 0.15 µst

PHL, RxIN to RxOUT, CL=150pF

0.15 tPLH, RxIN to RxOUT, CL=150pF

Receiver Output Enable Time 200 ns

Receiver Output Disable Time 200 ns

Driver Skew 100 ns | tPHL - tPLH |, TAMB = 25°C

Receiver Skew 50 ns | tPHL - tPLH |

Transition-Region Slew Rate 90 V/µsV

CC = 3.3V, RL = 3KΩ, TAMB = 25°C,

measurements taken from -3.0V to

+3.0V or +3.0V to -3.0V

Figure 1. Transmitter Output Voltage vs Load

Capacitance for the SP3222EU and the SP3232EU Figure 2. Slew Rate vs Load Capacitance for the

SP3222EU and the SP3232EU

Figure 3. Supply Current vs Load Capacitance when

Transmitting Data for the SP3222EU and the SP3232EU

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 1000kbps data rates, all drivers

loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C.

0 250 500 1000 1500

Load Capacitance (pF)

Transmitter

Output Voltage (V)

-2

-4

-6

T1 at 1Mbps

T2 at 62.5Kbps

0 250 500 1000 1500 2000

Load Capacitance (pF)

Slew Rate (V / µs)

120

100

T1 at 1Mbps

T2 at 62.5Kbps

All TX loaded 3K // CLoad

0 250 500 1000 1500

Load Capacitance (pF)

Supply Current (mA)

T1 at 1Mbps

T2 at 62.5Kbps

2.7 3 3.5 4 4.5 5

Supply Voltage (V)

Supply Current (mA)

T1 at Mbps

T2 at 62.5Kbps

2.7 3 3.5 4 4.5 5

Supply Voltage (V)

Transmitter Output

Voltage (V)

-2

-4

-6

T1 at 1Mbps

T2 at 62.5Kbps

0 250 500 1000 1500 2000

200

150

100

Load Capacitance (pF)

Skew (nS)

T1 at 500Kbps

T2 at 31.2Kbps

All TX loaded 3K // CLoad

Figure 4. Supply Current vs Supply Voltage for the

SP3222EU and the SP3232EU

Figure 5. Transmitter Output Voltage vs Supply Voltage

for the SP3222EU and the SP3232EU Figure 6. Transmitter Skew vs Load Capacitance for the

SP3222EU and the SP3232EU

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Table 1. Device Pin Description

Figure 8. Pinout Configuration for the SP3232EU

Figure 7. Pinout Configurations for the SP3222EU

V-

417

SHDN

C1+

V+

C1-

C2+

C2-

N.C.

R1IN

GND

VCC

T1OUT

N.C.

10 11

R2IN

R2OUT

SP3222EU

T2OUT T1IN

T2IN

R1OUT

SSOP/TSSOP

V-

415

SHDN

C1+

V+

C1-

C2+

C2-

R1IN

GND

T1OUT

910

R2IN

SP3222EU

T2OUT T2IN

T1IN

R1OUT

DIP/SO

R2OUT

V-

413

C1+

V+

C1-

C2+

C2-

R1IN

R2IN

GND

VCC

T1OUT

T2IN

SP3232EU

T1IN

R1OUT

R2OUT

T2OUT

Figure 9. SP3222EU Typical Operating Circuits

Figure 10. SP3232EU Typical Operating Circuit

SP3222EU

GND

T1IN

T2IN

T1OUT

T2OUT

C1+

C1-

C2+

C2-

V+

V-

0.1µF

+*C3

0.1µF

17 RS-232

OUTPUTS

RS-232

INPUTS

LOGIC

INPUTS

5kΩ

R1IN

R1OUT

5kΩ

R2IN

R2OUT

LOGIC

OUTPUTS

EN 20

SHDN

*can be returned to

either V

or GND

SSOP

TSSOP

SP3222EU

GND

T1IN

T2IN

T1OUT

T2OUT

C1+

C1-

C2+

C2-

V+

V-

0.1µF

+*C3

0.1µF

15 RS-232

OUTPUTS

RS-232

INPUTS

LOGIC

INPUTS

5kΩ

R1IN

R1OUT

5kΩ

R2IN

R2OUT

LOGIC

OUTPUTS

EN 18

SHDN

*can be returned to

either V

or GND

DIP/SO

SP3232EU

GND

T1IN

T2IN

T1OUT

T2OUT

C1+

C1-

C2+

C2-

V+

V-

0.1µF

+*C3

0.1µF

7RS-232

OUTPUTS

RS-232

INPUTS

LOGIC

INPUTS

5kΩ

R1IN

R1OUT

12 13

5kΩ

R2IN

R2OUT

LOGIC

OUTPUTS

*can be returned to

either V

or GND

DESCRIPTION

The SP3222EU and SP3232EU are 2 driver/

2receiver devices ideal for portable or hand-

held applications. The SP3222EU features a

1µA shutdown mode that reduces power

consumption and extends battery life in

portable systems. Its receivers remain active

in shutdown mode, allowing external devices

such as modems to be monitored using only 1

µA supply current.

The SP3222EU/3232EU transceivers meet the

EIA/TIA-232 and V.28/V.24 communication

protocols They feature Sipex's proprietary on-

board charge pump circuitry that generates 2 x

VCC for RS-232 voltage levels from a single

+3.0V to +5.5V power supply. The

SP3222EU/3232EU drivers operate at a

minimum data rate of 1000kbps.

THEORY OF OPERATION

The SP3222EU/3232EU series are made up of

three basic circuit blocks: 1. Drivers, 2.

Receivers, and 3. the Sipex proprietary

charge pump.

Drivers

The drivers are inverting level transmitters that

convert TTL or CMOS logic levels to ±5.0V

EIA/TIA-232 levels inverted relative to the

input logic levels. Typically, the RS-232

output voltage swing is ±5.5V with no load

and at least ±5V minimum fully loaded. The

driver outputs are protected against infinite

short-circuits to ground without degradation in

reliability. Driver outputs will meet EIA/TIA-

562 levels of ±3.7V with supply voltages as

low as 2.7V.

The drivers have a minimum data rate of

1000kbps fully loaded with 3KΩ in

parallel with 250pF, ensuring compatibility

with PC-to-PC communication software.

Figure 11 shows a loopback test circuit used

to the RS-232 drivers. Figure 12 shows the

test results of the loopback circuit with all

drivers active at 250kbps with RS-232 loads in

parallel with 1000pF capacitors. Figure 13

shows the test results where one driver was

active at 1000kbps and all drivers loaded with

an RS-232 receiver in parallel with a 250pF

capacitor.

The SP3222EU driver's output stages are

tristated in shutdown mode. When the power

is off, the SP3222EU device permits the

outputs to be driven up to ±12V. Because the

driver's inputs do not have pull-up resistors,

unused inputs should be connected to VCC or

GND.

In the shutdown mode, the supply current is

less than 1µA, where SHDN = LOW. When

the SP3222EU device is shut down, the

device's driver outputs are disabled (tri-stated)

and the charge pumps are turned off with V+

pulled down to VCC and V- pulled to GND.

The time required to exit shutdown is typically

100µs. Connect SHDN to VCC if the shutdown

mode is not used.

Receivers

The receivers convert EIA/TIA-232 levels to

TTL or CMOS logic output levels. The

SP3222EU receivers have an inverting tri-state

output. Receiver outputs (RxOUT) are tri-

stated when the enable control EN = HIGH.

In the shutdown mode, the receivers can be

active or inactive. EN has no effect on

TxOUT. The truth table logic of the

SP3222EU driver and receiver outputs can be

found in Table 2.

Figure 12. Driver Loopback Test All Drivers at 250kbps Figure 13. Driver Loopback Test One Driver 1Mbps

Figure 11. SP3222EU/3232EU Driver Loopback Test Circuit

SP3222EU

SP3232EU

GND

TxIN TxOUT

C1+

C1-

C2+

C2-

V+

V-

VCC

0.1µF

+C3

0.1µF

LOGIC

INPUTS

VCC

5kΩ

RxIN

RxOUT

LOGIC

OUTPUTS

EN *SHDN

250pF or 1000pF

VCC

* SP3222EB only

Since receiver input is usually from a trans-

mission line where long cable lengths and

system interference can degrade the signal and

inject noise, the inputs have a typical hyster-

esis margin of 300mV. Should an input be left

unconnected, a 5kΩ pulldown resistor to

ground will commit the output of the receiver

to a HIGH state.

Charge Pump

The charge pump is a Sipex–patented design

(5,306,954) and uses a unique approach

compared to older less–efficient designs. The

charge pump still requires four external

capacitors, but uses a four–phase voltage

shifting technique to attain symmetrical 5.5V

power supplies. The internal power supply

consists of a regulated dual charge pump that

provides output voltages 5.5V regardless of

the input voltage (VCC) over the +3.0V to

+5.5V range.

In most circumstances, decoupling the power

supply can be achieved adequately using a

0.1µF bypass capacitor at C5 (refer to Figures

9 and 10). In applications that are sensitive to

power-supply noise, decouple VCC to ground

with a capacitor of the same value as charge-

pump capacitor C1. Physically connect

bypass capacitors as close to the IC as

possible.

The charge pumps operate in a discontinuous

mode using an internal oscillator. If the

output voltages are less than a magnitude of

5.5V, the charge pumps are enabled. If the

output voltage exceed a magnitude of 5.5V,

the charge pumps are disabled. This oscillator

controls the four phases of the voltage

shifting. A description of each phase follows.

Phase 1

— VSS charge storage — During this phase of

the clock cycle, the positive side of capacitors

C1 and C2 are initially charged to VCC. Cl+ is

then switched to GND and the charge in C1– is

transferred to C2–. Since C2+ is connected to

VCC, the voltage potential across capacitor C2

is now 2 times VCC.

Phase 2

— VSS transfer — Phase two of the clock

connects the negative terminal of C2 to the VSS

storage capacitor and the positive terminal of

C2 to GND. This transfers a negative gener-

ated voltage to C3. This generated voltage is

regulated to a minimum voltage of -5.5V.

Simultaneous with the transfer of the voltage

to C3, the positive side of capacitor C1 is

switched to VCC and the negative side is

connected to GND.

Phase 3

— VDD charge storage — The third phase of

the clock is identical to the first phase — the

charge transferred in C1 produces –VCC in the

negative terminal of C1, which is applied to

the negative side of capacitor C2. Since C2+ is

at VCC, the voltage potential across C2 is 2

times VCC.

Phase 4

— VDD transfer — The fourth phase of the

clock connects the negative terminal of C2 to

GND, and transfers this positive generated

voltage across C2 to C4, the VDD storage

capacitor. This voltage is regulated to +5.5V.

At this voltage, the internal oscillator is

disabled. Simultaneous with the transfer of

the voltage to C4, the positive side of capaci-

tor C1 is switched to VCC and the negative side

Table 2. SP3222EU Truth Table Logic for Shutdown

and Enable Control

NDHSNETUOxTTUOxR

00 etats-irTevitcA

01 etats-irTetats-irT

10 evitcAevitcA

11 evitcAetats-irT

is connected to GND, allowing the charge

pump cycle to begin again. The charge pump

cycle will continue as long as the operational

conditions for the internal oscillator are

present.

Since both V+ and V– are separately generated

from VCC; in a no–load condition V+ and V–

will be symmetrical. Older charge pump

approaches that generate V– from V+ will

show a decrease in the magnitude of V–

compared to V+ due to the inherent inefficien-

cies in the design.

The clock rate for the charge pump typically

operates at 250kHz. The external capacitors

can be as low as 0.1µF with a 16V breakdown

voltage rating.

ESD Tolerance

The SP3222EU/3232EU series incorporates

ruggedized ESD cells on all driver output and

receiver input pins. The ESD structure is

improved over our previous family for more

rugged applications and environments

sensitive to electrostatic discharges and

associated

transients. The improved ESD tolerance is at

least ±15kV without damage nor latch-up.

There are different methods of ESD testing

applied: a) MIL-STD-883, Method 3015.7

b) IEC1000-4-2 Air-Discharge

c) IEC1000-4-2 Direct Contact

The Human Body Model has been the

generally accepted ESD testing method for

semiconductors. This method is also speci-

fied in MIL-STD-883, Method 3015.7 for

ESD testing. The premise of this ESD test is

to simulate the human body’s potential to

store electrostatic energy and

discharge it to an integrated circuit. The

simulation is performed by using a test model

as shown in Figure 20. This method will test

the IC’s capability to withstand an ESD

transient during normal handling such as in

manufacturing areas where the ICs tend to be

handled

frequently.

The IEC-1000-4-2, formerly IEC801-2, is

generally used for testing ESD on equipment

and systems. For system manufacturers, they

must guarantee a certain amount of ESD

protection since the system itself is exposed to

the outside environment and human presence.

The premise with IEC1000-4-2 is that the

system is required to withstand an amount of

static electricity when ESD is applied to

points and surfaces of the equipment that are

accessible to personnel during normal usage.

The transceiver IC receives most of the ESD

current when the ESD source is applied to the

connector pins. The test circuit for IEC1000-4-2

is shown on Figure 21. There are two

methods within IEC1000-4-2, the Air Dis-

charge method and the Contact Discharge

method.

With the Air Discharge Method, an ESD

voltage is applied to the equipment under

test (EUT) through air. This simulates an

electrically charged person ready to connect a

cable onto the rear of the system only to find

an unpleasant zap just before the person

touches the back panel. The high energy

potential on the person discharges through

an arcing path to the rear panel of the system

before he or she even touches the system.

This energy, whether discharged directly or

through air, is predominantly a function of the

discharge current rather than the discharge

voltage.

Variables with an air discharge such as

approach speed of the object carrying the ESD

potential to the system and humidity will tend

to change the discharge current. For example,

the rise time of the discharge current varies

with the approach speed.

The Contact Discharge Method applies the

ESD current directly to the DUT.

Figure 15. Charge Pump — Phase 1

Figure 16. Charge Pump — Phase 2

Figure 17. Charge Pump Waveforms

Figure 18. Charge Pump — Phase 3

Figure 19. Charge Pump — Phase 4

Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V

T[]

+6V

a) C

b) C

GND

-6V

= +5V

–5V –5V

+5V

Storage Capacitor

–

––

VCC = +5V

–10V

VSS Storage Capacitor

VDD Storage Capacitor

C1C2

–

––

= +5V

–5V

+5V

–5V

Storage Capacitor

–

––

= +5V

+10V

Storage Capacitor

–

––

This method was devised to reduce the

unpredictability of the ESD arc. The dis-

charge current rise time is constant since the

energy is directly transferred without the air-

gap arc. In situations such as hand held

systems, the ESD charge can be directly

discharged to the equipment from a person

already holding the equipment. The current is

transferred on to the keypad or the serial port

of the equipment directly and then travels

through the PCB and finally to the IC.

The circuit models in Figures 20 and 21

represent the typical ESD testing circuits used

for all three methods. The CS is initially

charged with the DC power supply when the

first switch (SW1) is on. Now that the

capacitor is charged, the second switch (SW2)

is on while SW1 switches off. The voltage

stored in the capacitor is then applied through

RS, the current limiting resistor, onto the

device under test (DUT). In ESD tests, the

SW2 switch is pulsed so that the device under

test receives a duration of voltage.

Figure 20. ESD Test Circuit for Human Body Model

Figure 21. ESD Test Circuit for IEC1000-4-2

SW1 SW2

Device

Under

Test

DC Power

Source

SW1 SW2

and

add up to 330Ω for IEC1000-4-2.

and

add up to 330Ω for IEC1000-4-2.

Contact-Discharge Module

SW1 SW2

Device

Under

Test

DC Power

Source

SW1 SW2

Contact-Discharge Module

Figure 22. ESD Test Waveform for IEC1000-4-2

30A

I ➙

15A

t=30ns

t ➙

t=0ns

For the Human Body Model, the current

limiting resistor (RS) and the source capacitor

(CS) are 1.5kΩ an 100pF, respectively. For

IEC-1000-4-2, the current limiting resistor

(RS) and the source capacitor (CS) are 330Ω

an 150pF, respectively.

The higher CS value and lower RS value in

the IEC1000-4-2 model are more stringent

than the Human Body Model. The larger

storage capacitor injects a higher voltage to

the test point when SW2 is switched on. The

lower current limiting resistor increases the

current charge onto the test point.

Device Pin Human Body IEC1000-4-2

Tested Model Air Discharge Direct Contact Level

Driver Outputs ±15kV ±15kV ±8kV 4

Receiver Inputs ±15kV ±15kV ±8kV 4

Table 3. Transceiver ESD Tolerance Levels

PACKAGE: PLASTIC SHRINK

SMALL OUTLINE

(SSOP)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) 20–PIN

0.068/0.078

(1.73/1.99)

0.002/0.008

(0.05/0.21)

0.010/0.015

(0.25/0.38)

0.278/0.289

(7.07/7.33)

0.205/0.212

(5.20/5.38)

0.0256 BSC

(0.65 BSC)

0.301/0.311

(7.65/7.90)

0.022/0.037

(0.55/0.95)

0°/8°

(0°/8°)

16–PIN

0.068/0.078

(1.73/1.99)

0.002/0.008

(0.05/0.21)

0.010/0.015

(0.25/0.38)

0.239/0.249

(6.07/6.33)

0.205/0.212

(5.20/5.38)

0.0256 BSC

(0.65 BSC)

0.301/0.311

(7.65/7.90)

0.022/0.037

(0.55/0.95)

0°/8°

(0°/8°)

ALTERNATE

END PINS

(BOTH ENDS)

D1 = 0.005" min.

(0.127 min.)

PACKAGE: PLASTIC

DUAL–IN–LINE

(NARROW)

A = 0.210" max.

(5.334 max).

LA2

A1 = 0.015" min.

(0.381min.)

e = 0.100 BSC

(2.540 BSC) e

= 0.300 BSC

(7.620 BSC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

16–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.780/0.800

(19.812/20.320)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

18–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.880/0.920

(22.352/23.368)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC)

(WIDE)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

16–PIN

0.090/0.104

(2.29/2.649)

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.398/0.413

(10.10/10.49)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

18–PIN

0.090/0.104

(2.29/2.649))

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.447/0.463

(11.35/11.74)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC)

(NARROW)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

h x 45°

16–PIN

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249)

0.013/0.020

(0.330/0.508)

0.386/0.394

(9.802/10.000)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

Gage

Plane

1.0 OIA

0.169 (4.30)

0.177 (4.50)

0.252 BSC (6.4 BSC)

0’-8’ 12’REF

0.039 (1.0)

e/2

0.039 (1.0)

0.126 BSC (3.2 BSC)

0.007 (0.19)

0.012 (0.30)

0.033 (0.85)

0.037 (0.95)

0.002 (0.05)

0.006 (0.15)

0.043 (1.10) Max

(θ3)

1.0 REF

0.020 (0.50)

0.026 (0.75) (θ1)

0.004 (0.09) Min

0.010 (0.25)

(θ2)

0.008 (0.20)

DIMENSIONS

in inches (mm) Minimum/Maximum

Symbol 14 Lead 16 Lead 20 Lead 24 Lead 28 Lead 38 Lead

D 0.193/0.201 0.193/0.201 0.252/0.260 0.303/0.311 0.378/0.386 0.378/0.386

(4.90/5.10) (4.90/5.10) (6.40/6.60) (7.70/7.90) (9.60/9.80) (9.60/9.80)

e 0.026 BSC 0.026 BSC 0.026 BSC 0.026 BSC 0.026 BSC 0.020 BSC

(0.65 BSC) (0.65 BSC) (0.65 BSC) (0.65 BSC) (0.65 BSC) (0.50 BSC)

PACKAGE: PLASTIC THIN

SMALL OUTLINE

(TSSOP)

ORDERING INFORMATION

Model Temperature Range Package Type

SP3222EUCA .......................................... 0˚C to +70˚C.......................................... 20-Pin SSOP

SP3222EUCP .......................................... 0˚C to +70˚C............................................18-Pin PDIP

SP3222EUCT .......................................... 0˚C to +70˚C ........................................ 18-Pin WSOIC

SP3222EUCY .......................................... 0˚C to +70˚C........................................ 20-Pin TSSOP

SP3232EUCA .......................................... 0˚C to +70˚C.......................................... 16-Pin SSOP

SP3232EUCP .......................................... 0˚C to +70˚C............................................16-Pin PDIP

SP3232EUCT .......................................... 0˚C to +70˚C ........................................ 16-Pin WSOIC

SP3232EUCY .......................................... 0˚C to +70˚C ........................................ 16-Pin TSSOP

SP3232EUCN........................................... 0˚C to +70˚C......................................... 16-Pin nSOIC

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Sipex Corporation

Headquarters and

Sales Office

22 Linnell Circle

Billerica, MA 01821

TEL: (978) 667-8700

FAX: (978) 670-9001

e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Please consult the factory for pricing and availability on a Tape-On-Reel option.