FPD1500DFN
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• PERFORMANCE (1850 MHz)
♦ 27 dBm Output Power (P1dB)
♦ 18 dB Small-Signal Gain (SSG)
♦ 1.2 dB Noise Figure
♦ 42 dBm Output IP3
♦ 45% Power-Added Efficiency
♦ Evaluation Boards Available
♦ Featuring Lead Free Finish Package
• DESCRIPTION AND APPLICATIONS
The FPD1500DFN is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron
Mobility Transistor (pHEMT). It utilizes a 0.25 μm x 1500 μm Schottky barrier Gate, defined by
high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes
parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a
range of bias conditions and input power levels. The FPD1500DFN is available in die form and in
other packages.
Typical applications include drivers or output stages in PCS/Cellular base station high-intercept-
point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
• ELECTRICAL SPECIFICATIONS AT 22°C
Parameter Symbol Test Conditions Min Typ Max Units
RF SPECIFICATION S M E ASU RED AT f = 1850 MHz USING CW SIGNAL
Power at 1dB Gain Compression P1dB VDS = 5 V; IDS = 50% IDSS 27 dBm
Small-Signal Gain SSG VDS = 5 V; IDS = 50% IDSS 18 dB
Power-Added Efficiency PAE VDS = 5 V; IDS = 50% IDSS;
POUT = P1dB
45 %
Noise Figure NF VDS = 5 V; IDS = 50% IDSS 1.2 dB
Output Third-Order Intercept Point
(from 15 to 5 dB below P1dB)
IP3 VDS = 5V; IDS = 50% IDSS
Matched for o pt imal power
Matched for best IP3
40
42
dBm
Saturated Drai n-S o urce Current IDSS VDS = 1.3 V; VGS = 0 V 375 465 550 mA
Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 750 mA
Transconductance GMVDS = 1.3 V; VGS = 0 V 400 mS
Gate-Source Leakage Current IGSO VGS = -5 V 1 15 μA
Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 1.5 mA 0.7 0.9 1.3 V
Gate-Source Breakdown Voltage |VBDGS| IGS = 1.5 mA 12 18 V
Gate-Drain Breakdown Voltage |VBDGD| IGD = 1.5 mA 12 18 V
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 11/14/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500DFN
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 11/14/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• ABSOLUTE MAXIMUM RATINGS1
Parameter Symbol Test Conditions Min Max Units
Drain-Source Vol t a ge VDS -3V < VGS < +0V 8 V
Gate-Source Voltage VGS 0V < VDS < +8V -3 V
Drain-Source Current IDS For VDS > 2V IDSS mA
Gate Current IGForward or reverse current 15 mA
RF Input Power2PIN Under any acceptable bias state 350 mW
Channel Operating Temperature TCH Under any acceptable bias state 175 ºC
Storage Temperature TSTG Non-Operating Storage -40 150 ºC
Total Power Dissipation PTOT See De-Rating Note below 2.2 W
Gain Compression Comp. Under any bias conditions 5 dB
Simultaneous Combination of Limits3 2 or more Max. Limits 80 %
1TAmbient = 22°C unless otherwise not ed 2Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3Users should avoid e xcee di n g 80 % of 2 o r more Limits sim ult aneou sl y
Notes:
• Operating conditio ns that exceed the Absolute Maximum Ratings will result in permanent damage to the dev ice.
• Total Power D issi pat i on defined as: PTOT ≡ (PDC + PIN) – POUT, where:
P
DC: DC Bias Power
PIN: RF Input Power
POUT: RF Output Power
• Total Power Di ssi pat i on t o be de -rate d as fol l ows ab o ve 22 °C:
PTOT= 2.2W – (0.0167W/°C) x TPACK
where TPACK = source lead temperature above 22
°
C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65°C source lead temperature: PTOT = 2.2W – (0.0167 x (6 5 – 2 2) ) = 1.48 W
• The use of a filled via-hole directly beneath the exposed heatsink tab on the bottom of the package is strongly
recommended to provide for adequate thermal management. Ideally the bottom of the circuit board is
affixed to a heatsi n k or ther mal r adia tor.
• HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.
Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
• APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site. Evaluation Boards available upon request.
FPD1500DFN
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• BIASING GUIDELINES
¾ Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative
voltage supply for depletion-mode devices such as the FPD1500DFN.
¾ For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at
50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25%
to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3
performance.
• PACKAGE OUTLINE (dimensions in mm)
All information and specifications subject to change without notice.
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 11/14/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500DFN
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• PCB FOOT PRINT
• TYPICAL I-V CHARACTERISTICS
DC IV Curves FPD1500SOT89
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Drain-Source Voltage (V)
Drain-Source Current (A)
VG=-1.5V
VG-1.25V
VG=-1.00V
VG=-0.75V
VG=-0.5V
VG=-0.25V
VG=0V
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 11/14/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500DFN
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 11/14/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source
voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which
would normally distort the current measurement (this effect has been filtered from the I-V curves
presented above). Setting the VDS > 1.3V will generally cause errors in the current measurements,
even in stabilized circuits.
Recommendation: Traditionally a device’s IDSS rating (IDS at VGS = 0V) was used as a predictor of
RF power, and for MESFETs there is a correlation between IDSS and P1dB (power at 1dB gain
compression). For pHEMTs it can be shown that there is no meaningful statistical correlation
between IDSS and P1dB; specifically a linear regression analysis shows r2 < 0.7, and the regression
fails the F-statistic test. IDSS is sometimes useful as a guide to circuit tuning, since the S22 does vary
with the quiescent operating point IDS.
