R5F212G6SDFP - Renesas Technology / Hitachi Semiconductor

Rev.1.00 Apr 04, 2008 Page 1 of 41

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R8C/2G Group

RENESAS MCU

1. Overview

1.1 Features

The R8C/2G Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated

instructions for a high level of efficienc y. With 1 Mbyte of address space, and it is capable of executing instructions

at high speed. In addition, the CPU core boasts a multiplier for high-speed operatio n pro c essin g.

Power consumption is low, and the supported operating modes allow additional power control. These MCUs also

use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.

Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of

system components.

1.1.1 Applications

Electric power meters, electronic household appliances, office equipment, audio equipment, consumer

equipment, etc.

1.1.2 Specifications

Table 1.1 outlines the Specifications for R8C/2 G Gro up.

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R8C/2G Group 1. Overview

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NOTE:

1. Specify the D version if D version functions are to be used.

Table 1.1 Specifications for R8C/2G Group

Item Function Specification

CPU Central processing

unit R8C/Tiny series core

• Number of fundamental instructions: 89

• Minimum instruction execution time:

125 ns (System clock = 8 MHz, VCC = 2.7 to 5.5 V)

250 ns (System clock = 4 MHz, VCC = 2.2 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operation mode: Single-chip mode (address space: 1 Mbyte)

Memory ROM, RAM Refer to Table 1.2 Product List for R8C/2G Group.

Power Supply

Voltage

Detection

Voltage detection

circuit • Power-on reset

• Voltage detection 3

Comparator • 2 circuits (shared with voltage monitor 1 and voltage monitor 2)

• External reference voltage input is available

I/O Ports • Output-only: 1

• CMOS I/O ports: 27, selectable pull-up resistor

Clock Clock generation

circuits • 2 circuits: On-chip oscillator (high-speed, low-speed)

(high-speed on-chip oscillator has a frequency adjustment function),

XCIN clock oscillation circuit (32 kHz)

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (low-speed cloc k, high-speed on-chip oscillator,

low-speed on-chip oscillato r), wait mode, stop mode

Real-time clock (timer RE)

Interrupts • External: 5 so urces, Internal: 17 sources, Software: 4 sources

• Priority levels: 7 levels

Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable

Timer Timer RA 8 bits × 1 (with 8-bit prescaler)

Timer mode (period timer), pulse output mode (ou tput level inverted every

period), event counter mode, pulse width measurement mode, pulse period

measurement mode

Timer RB 8 bits × 1 (with 8-bit prescaler)

T imer mode (period timer), programmable waveform generation mode (PWM

output), programmable one-shot generation mode, prog rammable wait one-

shot generation mode

Timer RE 8 bits × 1

Real-time clock mode (count seconds, minutes, hours, days of week), output

compare mode

Timer RF 16 bits × 1 (with capture/compare register pin and compare register pin)

Input capture mode, output compare mode

Serial

Interface UART0, UART2 Clock synchronous serial I/O/U ART × 2

LIN Module Hardware LIN: 1 (timer RA, UART0)

Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V

• Programming and erasure endurance: 100 times

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board flash rewrite function

Operating Frequency/Supply

Voltage System clock = 8 MHz (VCC = 2.7 to 5.5 V)

System clock = 4 MHz (VCC = 2.2 to 5.5 V)

Current consumption 5 mA (VCC = 5 V, system clock = 8 MHz)

23 µA (VCC = 3 V, wait mode (low-speed on-chip oscillator on))

0.7 µA (VCC = 3 V, stop mode, BGR trimming circuit disabled)

Operating Ambient Temperature -20 to 85°C (N version)

-40 to 85°C (D version)(1)

Package 32-pin LQFP

Package code: PLQP0032GB-A (previous code: 32 P6U-A)

R8C/2G Group 1. Overview

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1.2 Product List

Table 1.2 lists Product List for R8C/2G Group, Figure 1.1 shows a Part Number, Memory Size, and Package of

R8C/2G Group.

Figure 1.1 Part Number, Memory Size, and Package of R8C/2G Group

Table 1.2 Product List for R8C/2G Group Current of Apr. 2008

Part No. ROM Capacity RAM Capacity Package Type Remarks

R5F212G4SNFP 16 Kbytes 512 bytes PLQP0032GB-A N version

R5F212G5SNFP 24 Kbytes 1 Kbytes PLQP0032GB-A

R5F212G6SNFP 32 Kbytes 1 Kbytes PLQP0032GB-A

R5F212G4SDFP 16 Kbytes 512 bytes PLQP0032GB-A D version

R5F212G5SDFP 24 Kbytes 1 Kbytes PLQP0032GB-A

R5F212G6SDFP 32 Kbytes 1 Kbytes PLQP0032GB-A

Part No. R 5 F 21 2G 4 S N FP

Package type:

FP: PLQP0032GB-A

Classification

N: Operating ambient temperature -20°C to 85°C

D: Operating ambient temperature -40°C to 85°C

S: Low-voltage versi on ( ot he r no s ymbols)

ROM capacity

4: 16 KB

5: 24 KB

6: 32 KB

R8C/2G Group

R8C/Tiny Series

Memory type

F: Flash memory version

Renesas MCU

Renesas semiconductor

R8C/2G Group 1. Overview

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1.3 Block Diagram

Figure 1.2 shows a Block Diagram.

Figure 1.2 Block Diagra m

R8C/Tiny Series CPU core Memory

Watchdog timer

(15 bits)

ROM(1)

RAM(2)

Multiplier

R0H R0L

R1H R2

R1L

USP

ISP

INTB

FLG

I/O ports

NOTES:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

System clock

generation circuit

High-speed on-chip oscillator

Low- Sp ee d o n -ch ip o scilla tor

XCIN-XCOUT

Timers

Timer RA (8 bits)

Timer RB (8 bits)

Timer RE (8 bits)

Timer RF (16 bits)

UART or

clock synchronous serial I/O

(8 bits × 2 channels)

LIN module

(1 channel)

Port P0

Port P1

Port P3

Port P4

Port P6

Peripheral functions

Voltage detection circuit

(3 circuits)

Comparator

(2 circuits)

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1.4 Pin Assignment

Figure 1.3 shows Pin Assignment (Top View). Table 1.3 outlines the Pin Name Information by Pin Number.

Figure 1.3 Pin Assignment (Top View)

R8C/2G Group

PLQP0032GB-A

(32P6U-A)

(top view)

XCIN/(P4_3)(1)

XCOUT/(P4_4)(1)

VSS

RESET

VCC

P3_7/(TRAO)/(TRFO11)(1)

MODE

P4_5/INT0

P1_7/TRAIO/INT1

P3_6/(INT1)(1)

P3_5/TRFO12

P1_0/KI0/TRFO00/VCMP1

P1_4/TXD0

P6_5/CLK2/(TREO)(1)

P1_3/KI3/VCOUT1/(TRBO)(1)

P3_3/TRFO10/TRFI

P1_1/KI1/TRFO01/VCMP2

P1_2/KI2/TRFO02/CVREF

P6_3/TXD2

P6_0/TREO

P6_6/(Kl1)(1)

P6_4/RXD2

P0_7/(Kl0)(1)

P0_6/INT4

P0_5

P1_5/RXD0/(TRAIO)/(INT1)(1)

P1_6/CLK0/VCOUT2

P3_2/INT2

P3_0/TRAO

P3_1/TRBO

P3_4/TRFO11

P0_4/(TREO)(1)

24 23 22 21 20 19 18 17

5781234 6

NOTES:

1. Can be assigned to t he pin in parentheses by a program.

2. Confirm the pin 1 posit ion on the package by referrin g t o the package dimensions.

R8C/2G Group 1. Overview

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NOTE:

1. Can be assigned to the pin in parentheses by a program.

Table 1.3 Pin Name Information by Pin Number

Number Control Pin Port I/O Pin Functions for of Peripheral Modules

Interrupt Timer Serial Interface

Comparator

1 P3_5 TRFO12

2 P3_7 (TRAO)/(TRFO11)(1)

3RESET

4 XCOUT (P4_4)

5VSS

6 XCIN (P4_3)

7VCC

8MODE

9 P4_5 INT0

10 P1_7 INT1 TRAIO

11 P3_6 (INT1)(1)

12 P3_1 TRBO

13 P3_0 TRAO

14 P3_2 INT2

15 P1_6 CLK0 VCOUT2

16 P1_5 (INT1)(1) (TRAIO)(1) RXD0

17 P1_4 TXD0

18 P1_3 KI3 (TRBO)(1) VCOUT1

19 P1_2 KI2 TRFO02 CVREF

20 P6_5 (TREO)(1) CLK2

21 P1_1 KI1 TRFO01 VCMP2

22 P1_0 KI0 TRFO00 VCMP1

23 P3_3 TRFO10/TRFI

24 P3_4 TRFO11

25 P0_7 (Kl0)(1)

26 P0_6 INT4

27 P0_5

28 P0_4 (TREO)(1)

29 P6_3 TXD2

30 P6_0 TREO

31 P6_6 (Kl1)(1)

32 P6_4 RXD2

R8C/2G Group 1. Overview

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1.5 Pin Functions

Table 1.4 lists Pin Functions.

I: Input O: Output I/O: Input and output

NOTE:

1. Refer to the oscillator manufacturer for oscillation characteristics.

Table 1.4 Pin Functions

Ty pe Symbol I/O Type Description

Power supply input VCC, VSS –Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.

Reset input RESET I Input “L” on this pin resets the MCU.

MODE MODE I Connect this pin to VCC via a resistor.

XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.

Connect a crystal oscillator between the XCIN and XCOUT

pins.(1) To use an external clock, input it to the XCIN pin and

leave the XCOUT pin open.

XCIN clock output XCOUT O

INT interrupt input INT0 to INT2, INT4 IINT interrupt input pins

Key input interrupt KI0 to KI3 I Key input interrupt input pins

Timer RA TRAIO I/O Timer RA I/O pin

TRAO O Timer RA output pin

Timer RB TRBO O Timer RB output pin

Timer RE TREO O Divided clock output pin

Timer RF TRFI I Timer RF input pin

TRFO00 to TRFO02,

TRFO10 to TRFO12 O Timer RF output pins

Serial interface CLK0, CLK2 I/O Clock I/O pin

RXD0, RXD2 I Serial data input pin

TXD0, TXD2 O Serial data output pin

Comparator VCMP1, VCMP2 I Analog input pins to comparator

CVREF I Reference voltage input pin to comparator

VCOUT1, VCOUT2 O Comparator output pins

I/O port P0_4 to P0_7,

P1_0 to P1_7,

P3_0 to P3_7,

P4_3, P4_5,

P6_0, P6_3 to P6_6

I/O CMOS I/O ports. Each port has an I/O select direction

or output individually.

Any port set to input can be set to use a pull-up resistor or not

by a program.

Output port P4_4 O Outpu t-only port

R8C/2G Group 2. Central Processing Unit (CPU)

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2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a

Figure 2.1 CPU Registers

b31 b15 b8b7 b0

Data registers(1)

Address registers(1)

R3 R0H (high-order of R0)

INTBHb15b19 b0

INTBL

FB Frame base register(1)

The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.

Interrupt table register

b19 b0

USP

Program counter

ISP

User stack pointer

Interrupt stack pointer

Static base register

FLG Flag register

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

Reserved bit

IPL DZSBOIU

b15 b0

b8 b7

NOTE:

1. These registers comprise a register bank. There are two register banks.

R1H (high-order of R1)

R0L (low-order of R0)

R1L (low-order of R1)

R8C/2G Group 2. Central Processing Unit (CPU)

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2.1 Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split

into high-order bits (R 0H) and low-order bit s (R0L) to be used sep aratel y as 8-bit data regist ers. R1H and R 1L are

analogous to R0H and R0L. R2 can be combined with R0 and used a s a 32-bit data regi ster (R2R0). R3R1 is

analogous to R2R0.

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also

used for transfer, arithmetic, and logic operations. A1 is analogou s to A0. A1 can be combined with A0 to be used

as a 32-bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between

USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.

2.8.2 Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative valu e; otherwise to 0.

2.8.5 Register Bank Select Flag (B)

2.8.6 Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

R8C/2G Group 2. Central Processing Unit (CPU)

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2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor inte rrupt priorit y levels from level 0 to level 7.

If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

R8C/2G Group 3. Memory

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3. Memory

Figure 3.1 is a Memory Map of R8C/2G Group. The R8C/2G group has 1 Mbyte of address space from addresses

00000h to FFFFFh.

The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal

ROM area is allocated addresses 0C000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each

interrupt routine.

The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM

area is allocated addresses 00400h to 007FFh. The internal RA M is used not only for storing data bu t also for calling

subroutines and as stacks when interrupt requests are acknowledged.

Special function registers (SFRs) are allocated addresses 0 0000h to 002FFh. The pe ripheral function control regi sters

are allocated here. All addresses within the SFR, which have not hing allocated are reserved for fu ture use and ca nnot

be accessed by users.

Figure 3.1 Memory Map of R8C/2G Group

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer/vo ltag e monitor/comparat or

(Reserved)

Reset

00400h

002FFh

00000h

Internal RAM

SFR

(Refer to 4. Special

Function Registers

(SFRs))

0FFFFh

0FFDCh

NOTE:

1. The blan k regions are res e rv ed . Do no t access locations in t hese regions.

FFFFFh

0FFFFh

0YYYYh Internal ROM

(program ROM)

0XXXh

Part Number Internal ROM Inter na l RA M

Size Size

R5F212G4SNFP, R5F212G4SDFP

R5F212G5SNFP, R5F212G5SDFP

R5F212G6SNFP, R5F212G6SDFP

16 Kbytes

24 Kbytes

32 Kbytes

0C000h

0A000h

08000h

512 bytes

1 Kbyt e

005FFh

007FFh

Address 0YYYYh Address 0XXXXh

R8C/2G Group 4. S pecial Function Registers (SFRs)

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4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special

function registers.

Table 4.1 SFR Information (1)(1)

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. The CSPROINI bit in the OFS register is set to 0.

Address Register Symbol After reset

0000h

0001h

0002h

0003h

0004h Processor Mode Register 0 PM0 00h

0005h Processor Mode Register 1 PM1 00h

0006h System Clock Control Register 0 CM0 01011000b

0007h System Clock Control Register 1 CM1 00h

0008h

0009h

000Ah Protect Register PRCR 00h

000Bh

000Ch System Clock Select Register OCD 00000100b

000Dh Watchdog Timer Reset Register WDTR XXh

000Eh Watchdog Timer Start Register WDTS XXh

000Fh Watchdog Timer Control Register WDC 00X11111b

0010h Address Match Interrupt Register 0 RMAD0 00h

0011h 00h

0012h 00h

0013h Address Match Interrupt Enable Regist er AIER 00h

0014h Address Match Interrupt Register 1 RMAD1 00h

0015h 00h

0016h 00h

0017h

0018h

0019h

001Ah

001Bh

001Ch Count Source Protection Mode Register CSPR 00h

10000000b(2)

001Dh

001Eh

001Fh

0020h High-Speed On-Chip Oscillator Control Register 0 HRA0 00h

0021h High-Speed On-Chip Oscillator Control Register 1 HRA1 When Shipping

0022h High-Speed On-Chip Oscillator Control Register 2 HRA2 00h

0023h

0024h

0025h

0026h

0027h

0028h Clock Prescaler Reset Flag CPSRF 00h

0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 Whe n Shipping

002Ah

002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When Shipping

002Ch

002Dh

002Eh BGR Trimming Auxiliary Register A BGRTRMA When Shipping

002Fh BGR Trimming Auxiliary Register B BGRTRMB When Shipping

R8C/2G Group 4. S pecial Function Registers (SFRs)

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Table 4.2 SFR Information (2)(1)

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. Software reset, wat chdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.

3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.

4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset.

5. Software reset, wat chdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.

Address Register Symbol After reset

0030h

0031h Voltage Detection Register 1(2) VCA1 00001000b

0032h Voltage Detection Register 2(2) VCA2 00h(3)

00100000b(4)

0033h

0034h

0035h

0036h Voltage Monitor 1 Circuit Control Register(5) VW1C 00001010b

0037h Voltage Monitor 2 Circuit Control Register(5) VW2C 00000010b

0038h Voltage Monitor 0 Circuit Control Register(2) VW0C 1000X010b(3)

1100X011b(4)

0039h

003Ah

003Bh Voltage Detection Circuit External Input Control Register VCAB 00h

003Ch Comparator Mode Register ALCMR 00h

003Dh Voltage Monitor Circuit Edge Select Register VCAC 00h

003Eh BGR Control Register BGRCR 00h

003Fh BGR Trimming Register BGRTRM When Shipping

0040h

0041h Comparator 1 Interrupt Control Register VCMP1IC XXXXX000b

0042h Comparator 2 Interrupt Control Register VCMP2IC XXXXX000b

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah Timer RE Interrupt Control Register TREIC XXXXX000b

004Bh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b

004Ch UART2 Receive Interrupt Control Register S2RIC XXXXX000b

004Dh Key Input Interrupt Control Register KUPIC XXXXX000b

004Eh

004Fh

0050h Compare 1 Interrupt Control Register CMP1IC XXXXX000b

0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b

0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b

0053h

0054h

0055h INT2 Interrupt Control Register INT2IC XX00X000b

0056h Timer RA Interrupt Control Register TRAIC XXXXX000b

0057h

0058h Timer RB Interrupt Control Register TRBIC XXXXX000b

0059h INT1 Interrupt Control Register INT1IC XX00X000b

005Ah

005Bh Timer RF Interrupt Control Register TRFIC XXXXX000b

005Ch Compare 0 Interrupt Control Register CMP0IC XXXXX000b

005Dh INT0 Interrupt Control Register INT0IC XX00X000b

005Eh INT4 Interrupt Control Register INT4IC XX00X000b

005Fh Capture Interrupt Control Register CAPIC XXXXX000b

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

R8C/2G Group 4. S pecial Function Registers (SFRs)

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Table 4.3 SFR Information (3)(1)

X: Undefined

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Address Register Symbol After reset

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h

0089h

008Ah

008Bh

008Ch

008Dh

008Eh

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h UART0 Transmit/Receive Mode Register U0MR 00h

00A1h UART0 Bit Ra te Register U0BRG XXh

00A2h UART0 Transmit Buffer Register U0TB XXh

00A3h XXh

00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b

00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b

00A6h UART0 Receive Buffer Register U0RB XXh

00A7h XXh

00A8h

00A9h

00AAh

00ABh

00ACh

00ADh

00AEh

00AFh

R8C/2G Group 4. S pecial Function Registers (SFRs)

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Table 4.4 SFR Information (4)(1)

X: Undefined

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Address Register Symbol After reset

00B0h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh

00BCh

00BDh

00BEh

00BFh

00C0h

00C1h

00C2h

00C3h

00C4h

00C5h

00C6h

00C7h

00C8h

00C9h

00CAh

00CBh

00CCh

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h

00D5h

00D6h

00D7h

00D8h

00D9h

00DAh

00DBh

00DCh

00DDh

00DEh

00DFh

00E0h Port P0 Register P0 00h

00E1h Port P1 Register P1 00h

00E2h Port P0 Direction Register PD0 00h

00E3h Port P1 Direction Register PD1 00h

00E4h

00E5h Port P3 Register P3 00h

00E6h

00E7h Port P3 Direction Register PD3 00h

00E8h Port P4 Register P4 00h

00E9h

00EAh Port P4 Direction Register PD4 00h

00EBh

00ECh Po r t P6 Register P6 00h

00EDh

00EEh Port P6 Direction Register PD6 00h

00EFh

R8C/2G Group 4. S pecial Function Registers (SFRs)

Rev.1.00 Apr 04, 2008 Page 16 of 41

REJ03B0223-0100

Table 4.5 SFR Information (5)(1)

X: Undefined

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Address Register Symbol After reset

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h Pin Select Register 2 PINSR2 00h

00F7h Pin Select Register 3 PINSR3 00h

00F8h Port Mode Register PMR 00h

00F9h External Input Enable Register INTEN 00h

00FAh INT Input Filter Select Register INTF 00h

00FBh Key Input Enable Register KIEN 00h

00FCh Pull-Up Control Register 0 PUR0 00h

00FDh Pull-Up Control Register 1 PUR1 00h

00FEh

00FFh

0100h Timer RA Control Register TRACR 00h

0101h Timer RA I/O Control Register TRAIOC 00h

0102h Timer RA Mode Register TRAMR 00h

0103h Timer RA Prescaler Register TRAPRE FFh

0104h Timer RA Register TRA FFh

0105h

0106h LIN Control Register LINCR 00h

0107h LIN Status Register LINST 00h

0108h Timer RB Control Register TRBCR 00h

0109h Timer RB One-Shot Control Register TRBOCR 00h

010Ah Timer RB I/O Control Register TRBIOC 00h

010Bh Timer RB Mode Register TRBMR 00h

010Ch Timer RB Prescaler Register TRBPRE FFh

010Dh Timer RB Secondary Register TRBSC FFh

010Eh Timer RB Primary Register TRBPR FFh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h Timer RE Second Data Register / Counter Data Register TRESEC XXh

0119h Timer RE Minute Data Register / Compare Data Register TREMIN XXh

011Ah Timer RE Hour Data Register TREHR X0XXXXXXb

011Bh Timer RE Day of Week Data Register TREWK X0000XXXb

011Ch Timer RE Control Register 1 TRECR1 XXX0X0X0b

011Dh Timer RE Control Register 2 TRECR2 00XXXXXXb

011Eh Timer RE Count Source Select Register TRECSR 00001000b

011Fh Timer RE Real-Time Clock Precision Adjust Register TREOPR 00h

0120h

0121h

0122h

0123h

0124h

0125h

0126h

0127h

0128h

0129h

012Ah

012Bh

012Ch

012Dh

012Eh

012Fh

R8C/2G Group 4. S pecial Function Registers (SFRs)

Rev.1.00 Apr 04, 2008 Page 17 of 41

REJ03B0223-0100

Table 4.6 SFR Information (6)(1)

X: Undefined

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Address Register Symbol After reset

0130h

0131h

0132h

0133h

0134h

0135h

0136h

0137h

0138h

0139h

013Ah

013Bh

013Ch

013Dh

013Eh

013Fh

0140h

0141h

0142h

0143h

0144h

0145h

0146h

0147h

0148h

0149h

014Ah

014Bh

014Ch

014Dh

014Eh

014Fh

0150h

0151h

0152h

0153h

0154h

0155h

0156h

0157h

0158h

0159h

015Ah

015Bh

015Ch

015Dh

015Eh

015Fh

0160h UART2 Transmit/Receive Mode Regi ster U2MR 00h

0161h UART2 Bit Rate Reg i ster U2BRG XXh

0162h UART2 Transmit Buffer Register U2TB XXh

0163h XXh

0164h UART2 Transmit/Receive Control Register 0 U2C0 00001000b

0165h UART2 Transmit/Receive Control Register 1 U2C1 00000010b

0166h UART2 Receive Buffer Register U2RB XXh

0167h XXh

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

R8C/2G Group 4. S pecial Function Registers (SFRs)

Rev.1.00 Apr 04, 2008 Page 18 of 41

REJ03B0223-0100

Table 4.7 SFR Information (7)(1)

X: Undefined

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Address Register Symbol After reset

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

0180h

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

018Ch

018Dh

018Eh

018Fh

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

R8C/2G Group 4. S pecial Function Registers (SFRs)

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REJ03B0223-0100

Table 4.8 SFR Information (8)(1)

X: Undefined

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Address Register Symbol After reset

01B0h

01B1h

01B2h

01B3h Flash Memory Control Register 4 FMR4 01000000b

01B4h

01B5h Flash Memory Control Register 1 FMR1 1000000Xb

01B6h

01B7h Flash Memory Control Register 0 FMR0 00000001b

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

01C0h

01C1h

01C2h

01C3h

01C4h

01C5h

01C6h

01C7h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

01E0h

01E1h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

R8C/2G Group 4. S pecial Function Registers (SFRs)

Rev.1.00 Apr 04, 2008 Page 20 of 41

REJ03B0223-0100

Table 4.9 SFR Information (9)(1)

X: Undefined

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Address Register Symbol After reset

01F0h

01F1h

01F2h

01F3h

01F4h

01F5h

01F6h

01F7h

01F8h

01F9h

01FAh

01FBh

01FCh

01FDh

01FEh

01FFh

0200h

0201h

0202h

0203h

0204h

0205h

0206h

0207h

0208h

0209h

020Ah

020Bh

020Ch

020Dh

020Eh

020Fh

0210h

0211h

0212h

0213h

0214h

0215h

0216h

0217h

0218h

0219h

021Ah

021Bh

021Ch

021Dh

021Eh

021Fh

0220h

0221h

0222h

0223h

0224h

0225h

0226h

0227h

0228h

0229h

022Ah

022Bh

022Ch

022Dh

022Eh

022Fh

R8C/2G Group 4. S pecial Function Registers (SFRs)

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REJ03B0223-0100

Table 4.10 SFR Information (10)(1)

X: Undefined

NOTE:

1. The blank regions are reserved. Do not access locations in these regions.

Address Register Symbol After reset

0230h

0231h

0232h

0233h

0234h

0235h

0236h

0237h

0238h

0239h

023Ah

023Bh

023Ch

023Dh

023Eh

023Fh

0240h

0241h

0242h

0243h

0244h

0245h

0246h

0247h

0248h

0249h

024Ah

024Bh

024Ch

024Dh

024Eh

024Fh

0250h

0251h

0252h

0253h

0254h

0255h

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

025Fh

0260h

0261h

0262h

0263h

0264h

0265h

0266h

0267h

0268h

0269h

026Ah

026Bh

026Ch

026Dh

026Eh

026Fh

R8C/2G Group 4. S pecial Function Registers (SFRs)

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REJ03B0223-0100

Table 4.11 SFR Information (11)(1)

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. After input capture mode.

3. After output compare mode.

Address Register Symbol After reset

0270h

0271h

0272h

0273h

0274h

0275h

0276h

0277h

0278h

0279h

027Ah

027Bh

027Ch

027Dh

027Eh

027Fh

0280h

0281h

0282h

0283h

0284h

0285h

0286h

0287h

0288h

0289h

028Ah

028Bh

028Ch

028Dh

028Eh

028Fh

0290h Timer RF Register TRF 00h

0291h 00h

0292h

0293h

0294h

0295h

0296h

0297h

0298h

0299h Time r RF Control Register 2 TRFCR2 00h

029Ah Timer RF Control Register 0 TRFCR0 00h

029Bh Timer RF Control Register 1 TRFCR1 00h

029Ch Capture and Compare 0 Register TRFM0 0000h(2)

029Dh FFFFh(3)

029Eh Compare 1 Register TRFM1 FFh

029Fh FFh

02A0h

02A1h

02A2h

02A3h

02A4h

02A5h

02A6h

02A7h

02A8h

02A9h

02AAh

02ABh

02ACh

02ADh

02AEh

02AFh

R8C/2G Group 4. S pecial Function Registers (SFRs)

Rev.1.00 Apr 04, 2008 Page 23 of 41

REJ03B0223-0100

Table 4.12 SFR Information (12)(1)

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. The OFS register cannot be changed by a pr ogram. Use a flash programmer to write to it.

Address Register Symbol After reset

02B0h

02B1h

02B2h

02B3h

02B4h

02B5h

02B6h

02B7h

02B8h

02B9h

02BAh

02BBh

02BCh

02BDh

02BEh

02BFh

02C0h

02C1h

02C2h

02C3h

02C4h

02C5h

02C6h

02C7h

02C8h

02C9h

02CAh

02CBh

02CCh

02CDh

02CEh

02CFh

02D0h

02D1h

02D2h

02D3h

02D4h

02D5h

02D6h

02D7h

02D8h

02D9h

02DAh

02DBh

02DCh

02DDh

02DEh

02DFh

02E0h

02EFh

02F0h

02F1h

02F2h

02F3h

02F4h

02F5h

02F6h

02F7h

02F8h

02F9h

02FAh

02FBh Pin Select Register 4 PINSR4 00h

02FCh

02FDh External Input Enable Register 2 INTEN2 00h

02FEh INT Input Filter Select Register 2 INTF2 00h

02FFh Timer RF Output Control Register TRFOUT 00h

FFFFh Option Function Select Register OFS (Note 2)

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 24 of 41

REJ03B0223-0100

5. Electrical Characteristics

NOTES:

1. VCC = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. The average output current indicates the average value of current measured during 100 ms.

Figure 5.1 Ports P0, P1, P3, P4, and P6 Timing Measurement Circuit

Table 5.1 Absolute Maximum Ratings

Symbol Parameter Condition Rated Value Unit

VCC Supply voltage −0.3 to 6.5 V

VIInput voltage −0.3 to VCC + 0.3 V

VOOutput voltage −0.3 to VCC + 0.3 V

PdPower dissipation Topr = 25°C500mW

Topr Operating ambient temperature −20 to 85 (N version) /

−40 to 85 (D version) °C

Tstg Storage temperature −65 to 150 °C

Table 5.2 Recommended Operating Conditions

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

VCC Supply voltage 2.2 −5.5 V

VSS Supply voltage −0−V

VIH Input “H” voltage 0.8 VCC −VCC V

VIL Input “L” voltage 0 −0.2 VCC V

IOH(sum) Peak sum output “H”

current Sum of all pins IOH(peak) −−−160 mA

IOH(sum) Average sum output “H”

current Sum of all pins IOH(avg) −−−80 mA

IOH(peak) Peak output “H” current All pins −−−10 mA

IOH(avg) Average output “H”

current All pins −−−5mA

IOL(sum) Peak sum output “L”

currents Sum of all pins IOL(peak) −−160 mA

IOL(sum) Average sum output “L”

currents Sum of all pins IOL(avg) −−80 mA

IOL(peak) Peak output “L” currents All pins −−10 mA

IOL(avg) Average output “L” current All pins −−5mA

f(XCIN) XCIN clock input oscillation frequency 2.2 V ≤ VCC ≤ 5.5 V 0 −70 kHz

−System clock OCD2 = 0

XClN clock selected 2.2 V ≤ VCC ≤ 5.5 V 0 −70 kHz

OCD2 = 1

On-chip oscillator clock

selected

HRA01 = 0

Low-speed on-chip

oscillator selected

−125 −kHz

HRA01 = 1

High-speed on-chip

oscillator selected

2.7 V ≤ VCC ≤ 5.5 V

−−8MHz

HRA01 = 1

High-speed on-chip

oscillator selected

2.2 V ≤ VCC ≤ 5.5 V

−−4MHz

30pF

R8C/2G Group 5. Electrical Characteristics

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REJ03B0223-0100

NOTES:

1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024

1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance

still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as p ossible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the

number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. The data hold time includes time that the power supply is off or the clock is not supplied.

Table 5.3 Flash Memory (Program ROM) Electrical Characteristics

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

−Program/erase endurance(2) 100(3) −−times

−Byte program time −50 400 µs

−Block erase time −0.4 9 s

−Program, erase voltage 2.7 −5.5 V

−Read voltage 2.2 −5.5 V

−Program, erase temperature 0 −60 °C

−Data hold time(7) Ambient temperature = 55°C20 −−year

R8C/2G Group 5. Electrical Characteristics

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REJ03B0223-0100

NOTES:

1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2

NOTES:

1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.

3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2

4. This parameter shows the voltage detection level when the power supply drops.

The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply

drops by approximately 0.1 V.

NOTES:

1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.

3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2

Table 5.4 Voltage Detection 0 Circuit Elec t rica l Ch ara ct eristi cs

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet0 Voltage detection level 2.2 2.3 2.4 V

−Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V −0.9 −µA

td(E-A) Waiting time until voltage detection circuit operation

starts(2) −−300 µs

Vccmin MCU operating voltage minimum value 2.2 −−V

Table 5.5 Voltage Detection 1 Circuit Elec t rica l Ch ara ct eristi cs

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet1 Voltage detection level(4) 2.70 2.85 3.00 V

−Voltage monitor 1 interrupt request generation time(2) −40 −µs

−Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V −0.6 −µA

td(E-A) Waiting time until voltage detection circuit operation

starts(3) −−100 µs

Table 5.6 Voltage Detection 2 Circuit Elec t rica l Ch ara ct eristi cs

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet2 Voltage detection level 3.3 3.6 3.9 V

−Voltage monitor 2 interrupt request generation time(2) −40 −µs

−Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V −0.6 −µA

td(E-A) Waiting time until voltage detection circuit operation

starts(3) −−100 µs

R8C/2G Group 5. Electrical Characteristics

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REJ03B0223-0100

NOTES:

1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.

3. To use the power- on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the

VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.

4. tw(por1) indicates the duration the externa l power VCC must be held below the effective voltage (Vpor1) to enable a power on

reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for

3,000 s or more if −40°C ≤ Topr < −20°C.

Figure 5.2 Reset Circuit Electrical Characteristics

Table 5.7 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vpor1 Power-on reset valid voltage(4) −−0.1 V

Vpor2 Power-on reset or voltage monitor 0 reset valid

voltage 0−Vdet0 V

trth External power VCC rise gradient(2) 20 −−mV/msec

NOTES:

1. When using the voltage monitor 0 digital filter, ensure t ha t the voltage is within the MCU opera t ion voltage

range (2.2 V or above) during the samplin g time.

2. The sampling cl ock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.

3. Vdet0 indi cates the voltage detection level of t he voltage detection 0 circuit. Refer to 6. Voltage Detection

Circuit of Hardware Manual for detai l s .

Vdet0(3)

Vpor1

Internal

reset signal

(“L” valid)

tw(por1) Sampling time(1, 2)

Vdet0(3)

fOCO-S × 32 1

fOCO-S × 32

Vpor2

External

Power VCC trth trth

2.2 V

R8C/2G Group 5. Electrical Characteristics

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REJ03B0223-0100

NOTE:

1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

NOTES:

1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. These standard values show when the HRA1 register is set to the value before shipment and the HRA2 register is set to 00h.

3. These standard values show when the correction value in the FRA6 register is written into the HRA1 register.

NOTE:

1. VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

NOTES:

1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.

2. Waiting time until the internal power supply generation circuit stabilizes during power-on.

3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.

Table 5.8 Comparator Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vref Internal reference voltage VCC = 2.2 V to 5.5 V, Topr = 25°C 1.15 1.25 1.35 V

VCC = 2.2 V to 5.5 V,

Topr = −40 to 85°C−1.25 −V

Vcref External input reference voltage VCC = 2.2 V to 4.0 V 0.5 −VCC − 1.1 V

VCC = 4.0 V to 5.5 V 0.5 −VCC − 1.5

Vcin External comparison voltage input

range −0.3 −VCC + 0.3 V

Vofs Input offset voltage −20 120 mV

Tcrsp Response time −4−µs

Table 5.9 High-speed On-Chip Oscillator Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

fOCO-F High-speed on-chip oscillator frequency

temperature • supply voltage dependence VCC = 4.75 V to 5.25 V

Topr = 0 to 60°C(2) 7.76 8 8.24 MHz

VCC = 2.7 V to 5.5 V

Topr = −20 to 85°C(2) 7.68 8 8.32 MHz

VCC = 2.7 V to 5.5 V

Topr = −40 to 85°C(2) 7.44 8 8.32 MHz

VCC = 2.2 V to 5.5 V

Topr = −20 to 85°C(3) 7.04 8 8.96 MHz

VCC = 2.2 V to 5.5 V

Topr = −40 to 85°C(3) 6.8 8 9.2 MHz

Table 5.10 Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

fOCO-S Low-speed on-chip oscillator frequency 30 125 250 kHz

−Oscillation stability time −10 100 µs

−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−15 −µA

Table 5.11 Power Supply Circuit Timing Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

td(P-R) Time for internal power supply stabilization during

power-on(2) 1−2000 µs

td(R-S) STOP exit time(3) −−150 µs

R8C/2G Group 5. Electrical Characteristics

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REJ03B0223-0100

NOTE:

1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

Table 5.12 Electrical Characteristics (1) [VCC = 5 V]

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

VOH Output “H” voltage IOH = −5 mA VCC − 2.0 −VCC V

IOH = −200 µAVCC − 0.5 −VCC V

VOL Output “L” voltage IOL = 5 mA −−2.0 V

IOL = 200 µA−−0.45 V

VT+-VT- Hysteresis INT0, INT1, INT2, INT4,

KI0, KI1, KI2, KI3,

RXD0, RXD2,

CLK0, CLK2

0.1 0.5 −V

RESET 0.1 1.0 −V

IIH Input “H” current VI = 5 V, VCC = 5 V −−5.0 µA

IIL Input “L” current VI = 0 V, VCC = 5 V −−−5.0 µA

RPULLUP Pull-up resistance VI = 0 V, VCC = 5 V 30 50 167 kΩ

RfXCIN Feedback resistance XCIN −18 −MΩ

VRAM RAM hold voltage During stop mode 2.0 −−V

R8C/2G Group 5. Electrical Characteristics

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REJ03B0223-0100

Table 5.13 Electrical Characteristics (2) [Vcc = 5 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

ICC Power supply current

(VCC = 3.3 to 5.5 V)

Single-chip mode,

output pins are open,

other pins are VSS

High-speed

on-chip oscillator mode High-speed on-chip oscillator on = 8 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

−58mA

High-speed on-chip oscillator on = 8 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−2−mA

Low-speed

on-chip oscillator mode High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR47 = 1

−130 300 µA

Low-speed clock mode High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

FMR47 = 1

−130 300 µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

Program operation on RAM

Flash memory off, FMSTP = 1

−30 −µA

Wait mode High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

−25 75 µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

−23 60 µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit disabled (BGRCR0 = 1)

−4−µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit disabled (BGRCR0 = 1)

−2.2 −µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit enabled (BGRCR0 = 0)

−8−µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit enabled (BGRCR0 = 0)

−6−µA

Stop mode XCIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit disabled (BGRCR0 = 1)

−0.8 3 µA

XCIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit disabled (BGRCR0 = 1)

−1.2 −µA

XCIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit enabled (BGRCR0 = 0)

−58µA

XCIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit enabled (BGRCR0 = 0)

−5.5 −µA

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 31 of 41

REJ03B0223-0100

Timing Requirements

(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]

Figure 5.3 XCIN Input Timing Diagram when VCC = 5 V

Figure 5.4 TRAIO Input Ti ming Diagram when VCC = 5 V

Table 5.14 XCIN Input

Symbol Parameter Standard Unit

Min. Max.

tc(XCIN) XCIN input cycle time 14 −µs

tWH(XCIN) XCIN input “H” width 7 −µs

tWL(XCIN) XCIN input “L” width 7 −µs

Table 5.15 TRAIO Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRAIO) TRAIO input cycle time 100 −ns

tWH(TRAIO) TRAIO input “H” width 40 −ns

tWL(TRAIO) TRAIO input “L” width 40 −ns

XCIN input

tWH(XCIN)

tC(XCIN)

tWL(XCIN)

VCC = 5 V

TRAIO input

VCC = 5 V

tC(TRAIO)

tWL(TRAIO)

tWH(TRAIO)

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 32 of 41

REJ03B0223-0100

i = 0 or 2

Figure 5.5 Serial Interface Timing Diagram when VCC = 5 V

NOTES:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.6 External Interrupt INTi Input Timing Diagram when VCC = 5 V

Table 5.16 Serial Interfac e

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 200 −ns

tW(CKH) CLKi input “H” width 100 −ns

tW(CKL) CLKi input “L” width 100 −ns

td(C-Q) TXDi output delay time −50 ns

th(C-Q) TXDi hold time 0 −ns

tsu(D-C) RXDi input setup time 50 −ns

th(C-D) RXDi input hold time 90 −ns

Table 5.17 External Interrupt INTi (i = 0, 1, 2, 4) Input

Symbol Parameter Standard Unit

Min. Max.

tW(INH) INTi input “H” width 250(1) −ns

tW(INL) INTi input “L” width 250(2) −ns

tW(CKH)

tC(CK)

tW(CKL) th(C-Q)

th(C-D)

tsu(D-C)td(C-Q)

CLKi

TXDi

RXDi

i = 0 or 2

VCC = 5 V

INTi input

tW(INL)

tW(INH)

i = 0, 1, 2, 4

VCC = 5 V

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 33 of 41

REJ03B0223-0100

NOTE:

1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

Table 5.18 Electrical Characteristics (3) [VCC = 3 V]

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

VOH Output “H” voltage IOH = −1 mA VCC − 0.5 −VCC V

VOL Output “L” voltage IOL = 1 mA −−0.5 V

VT+-VT- Hysteresis INT0, INT1, INT2, INT4,

KI0, KI1, KI2, KI3,

RXD0, RXD2,

CLK0, CLK2

0.1 0.3 −V

RESET 0.1 0.4 −V

IIH Input “H” current VI = 3 V, VCC = 3 V −−4.0 µA

IIL Input “L” current VI = 0 V, VCC = 3 V −−−4.0 µA

RPULLUP Pull-up resistance VI = 0 V, VCC = 3 V 66 160 500 kΩ

RfXCIN Feedback resistance XCIN −18 −MΩ

VRAM RAM hold voltage During stop mode 1.8 −−V

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 34 of 41

REJ03B0223-0100

Table 5.19 Electrical Characteristics (4) [Vcc = 3 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

ICC Power supply current

(VCC = 2.7 to 3.3 V)

Single-chip mode,

output pins are open,

other pins are VSS

High-speed

on-chip oscillator mode High-speed on-chip oscillator on = 8 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

−5−mA

High-speed on-chip oscillator on = 8 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−2−mA

Low-speed

on-chip oscillator mode High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR47 = 1

−130 300 µA

Low-speed clock mode High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

FMR47 = 1

−130 300 µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

Program operation on RAM

Flash memory off, FMSTP = 1

−30 −µA

Wait mode High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

−25 70 µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

−23 55 µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit disabled (BGRCR0 = 1)

−3.8 −µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit disabled (BGRCR0 = 1)

−2−µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit enabled (BGRCR0 = 0)

−8−µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit enabled (BGRCR0 = 0)

−6−µA

Stop mode XCIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit disabled (BGRCR0 = 1)

−0.7 3 µA

XCIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit disabled (BGRCR0 = 1)

−1.1 −µA

XCIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit enabled (BGRCR0 = 0)

−57µA

XCIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit enabled (BGRCR0 = 0)

−5.5 −µA

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 35 of 41

REJ03B0223-0100

Timing requirements

(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]

Figure 5.7 XCIN Input Timing Diagram when VCC = 3 V

Figure 5.8 TRAIO Input Ti ming Diagram when VCC = 3 V

Table 5.20 XCIN Input

Symbol Parameter Standard Unit

Min. Max.

tc(XCIN) XCIN input cycle time 14 −µs

tWH(XCIN) XCIN input “H” width 7 −µs

tWL(XCIN) XCIN input “L” width 7 −µs

Table 5.21 TRAIO Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRAIO) TRAIO input cycle time 300 −ns

tWH(TRAIO) TRAIO input “H” width 120 −ns

tWL(TRAIO) TRAIO input “L” width 120 −ns

XCIN input

tWH(XCIN)

tC(XCIN)

tWL(XCIN)

VCC = 3 V

TRAIO in pu t

VCC = 3 V

tC(TRAIO)

tWL(TRAIO)

tWH(TRAIO)

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 36 of 41

REJ03B0223-0100

i = 0 or 2

Figure 5.9 Serial Interface Timing Diagram when VCC = 3 V

NOTES:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.10 External Interrupt INTi Input Timing Diagram when VCC = 3 V

Table 5.22 Serial Interfac e

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 300 −ns

tW(CKH) CLKi input “H” width 150 −ns

tW(CKL) CLKi Input “L” width 150 −ns

td(C-Q) TXDi output delay time −80 ns

th(C-Q) TXDi hold time 0 −ns

tsu(D-C) RXDi input setup time 70 −ns

th(C-D) RXDi input hold time 90 −ns

Table 5.23 External Interrupt INTi (i = 0, 1, 2, 4) Input

Symbol Parameter Standard Unit

Min. Max.

tW(INH) INTi input “H” width 380(1) −ns

tW(INL) INTi input “L” width 380(2) −ns

tW(CKH)

tC(CK)

tW(CKL) th(C-Q)

th(C-D)

tsu(D-C)td(C-Q)

CLKi

TXDi

RXDi

VCC = 3 V

i = 0 or 2

INTi input

tW(INL)

tW(INH)

VCC = 3 V

i = 0, 1, 2, 4

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 37 of 41

REJ03B0223-0100

NOTE:

1. VCC = 2.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

Table 5.24 Electrical Characteristics (5) [VCC = 2.2 V]

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

VOH Output “H” voltage IOH = −1 mA VCC − 0.5 −VCC V

VOL Output “L” voltage IOL = 1 mA −−0.5 V

VT+-VT- Hysteresis INT0, INT1, INT2, INT4,

KI0, KI1, KI2, KI3,

RXD0, RXD2,

CLK0, CLK2

0.05 0.3 −V

RESET 0.05 0.15 −V

IIH Input “H” current VI = 2.2 V −−4.0 µA

IIL Input “L” current VI = 0 V −−−4.0 µA

RPULLUP Pull-up resistance VI = 0 V 100 200 600 kΩ

RfXCIN Feedback resistance XCIN −35 −MΩ

VRAM RAM hold voltage During stop mode 1.8 −−V

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 38 of 41

REJ03B0223-0100

Table 5.25 Electrical Characteristics (6) [Vcc = 2.2 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

ICC Power supply current

(VCC = 2.2 to 2.7 V)

Single-chip mode,

output pins are open,

other pins are VSS

High-speed

on-chip oscillator mode High-speed on-chip oscillator on = 4 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

−3.5 −mA

High-speed on-chip oscillator on = 4 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−1.5 −mA

Low-speed

on-chip oscillator mode High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR47 = 1

−100 230 µA

Low-speed clock mode High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

FMR47 = 1

−100 230 µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

Program operation on RAM

Flash memory off, FMSTP = 1

−25 −µA

Wait mode High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

−22 60 µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

−20 55 µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit disabled (BGRCR0 = 1)

−3−µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit disabled (BGRCR0 = 1)

−1.8 −µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit enabled (BGRCR0 = 0)

−7−µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

BGR trimming circuit enabled (BGRCR0 = 0)

−6−µA

Stop mode XCIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit disabled (BGRCR0 = 1)

−0.7 3 µA

XCIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit disabled (BGRCR0 = 1)

−1.1 −µA

XCIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit enabled (BGRCR0 = 0)

−57µA

XCIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

BGR trimming circuit enabled (BGRCR0 = 0)

−5.5 −µA

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 39 of 41

REJ03B0223-0100

Timing requirements

(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]

Figure 5.11 XCIN Input Timing Diagram when VCC = 2.2 V

Figure 5.12 TRAIO Input Timing Diagram when VCC = 2.2 V

Table 5.26 XCIN Input

Symbol Parameter Standard Unit

Min. Max.

tc(XCIN) XCIN input cycle time 14 −µs

tWH(XCIN) XCIN input “H” width 7 −µs

tWL(XCIN) XCIN input “L” width 7 −µs

Table 5.27 TRAIO Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRAIO) TRAIO input cycle time 500 −ns

tWH(TRAIO) TRAIO input “H” width 200 −ns

tWL(TRAIO) TRAIO input “L” width 200 −ns

XCIN input

tWH(XCIN)

tC(XCIN)

tWL(XCIN)

VCC = 2.2 V

TRAIO input

tC(TRAIO)

tWL(TRAIO)

tWH(TRAIO)

VCC = 2.2 V

R8C/2G Group 5. Electrical Characteristics

Rev.1.00 Apr 04, 2008 Page 40 of 41

REJ03B0223-0100

i = 0 or 2

Figure 5.13 Serial Interface Timing Diagram when VCC = 2.2 V

NOTES:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.14 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V

Table 5.28 Serial Interfac e

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 800 −ns

tW(CKH) CLKi input “H” width 400 −ns

tW(CKL) CLKi input “L” width 400 −ns

td(C-Q) TXDi output delay time −200 ns

th(C-Q) TXDi hold time 0 −ns

tsu(D-C) RXDi input setup time 150 −ns

th(C-D) RXDi input hold time 90 −ns

Table 5.29 External Interrupt INTi (i = 0, 1, 2, 4) Input

Symbol Parameter Standard Unit

Min. Max.

tW(INH) INTi input “H” width 1000(1) −ns

tW(INL) INTi input “L” width 1000(2) −ns

tW(CKH)

tC(CK)

tW(CKL) th(C-Q)

th(C-D)

tsu(D-C)td(C-Q)

CLKi

TXDi

RXDi

VCC = 2.2 V

i = 0 or 2

INTi input

tW(INL)

tW(INH)

VCC = 2.2 V

i = 0, 1, 2, 4

R8C/2G Group Package Dimensions

Rev.1.00 Apr 04, 2008 Page 41 of 41

REJ03B0223-0100

Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of

the Renesas Technology website.

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

Index mark

24 17

Detail F

Previous CodeJEITA Package Code RENESAS Code

PLQP0032GB-A 32P6U-A

MASS[Typ.]

0.2gP-LQFP32-7x7-0.80

1.0

0.125

0.35

0.7

0.20

0.145

0.09

0.420.370.32

MaxNomMin

Dimension in Millimeters

Symbol

Reference

7.17.06.9

1.4

9.29.08.8

1.7

0.20.1

0.70.50.3

8°0°

0.8

0.10

Terminal cross section

C - 1

REVISION HISTORY R8C/2G Group Datasheet

Rev. Date Description

Page Summary

0.10 Jul 20, 2007 −First Edition issued

0.20 Nov 12, 2007 2 Table 1.1 I/O Ports: “• Output-only: 1” added

“• CMOS I/O ports: 28” → “• CMOS I/O ports: 27”

4 Figure 1.2 revised

5 Figure 1.3 revised

6 Table 1.3 Pin Number: 4, 6, 20 revised

7 Table 1. 4 I/O port: “P4_3 to P4_5” → “P4_3, P4_5”

Output port added

12 Table 4.1 0006h “01001000b” → “01011000b”

16 Table 4.5 0118h to 011Dh: After reset revised

011Fh “Timer RE Real-Time Clock Precision Adjust Register”

added

24 Table 5.2 NOTE2 revi sed

1.00 Apr 04, 2008 All pages “Under development” deleted

2 Table 1.1 revised

3 Table 1.2 “(D): Under developme nt” deleted

11 Figure 3.1 “Expanded area” deleted

12 Table 4. 1 “0 02Eh” “002Fh” revised

13 Table 4. 2 “0 03Eh” “003Fh” revised

25 Table 5. 3 re vised

Figure 5. 2 deleted

28 Table 5.8, Table 5.11 revised

Table 5.9 revised, NOTE3 added

30 Table 5.13 revised

34 Table 5.19 revised

38 Table 5.25 revised

All trademarks and registered trademarks are the property of their respective owners.

R8C/2G Group Datasheet

REVISION HISTORY

Notes:

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or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality

and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or

undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall

have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing

applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,

movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages

arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain

rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage

caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and

malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software

alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as

swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.

Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have

any other inquiries.

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

Renesas Technology (Shanghai) Co., Ltd.

Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120

Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898

Renesas Technology Hong Kong Ltd.

7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2377-3473

Renesas Technology Taiwan Co., Ltd.

10th Floor, No.99, Fushing North Road, Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399

Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

Renesas Technology Korea Co., Ltd.

Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea

Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145

Renesas Technology Malaysia Sdn. Bhd

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

RENESAS SALES OFFICES

Colophon .7.2