Publication Number 21444 Revision EAmendment 9Issue Date November 16, 2009
Am29F016D
Am29F016 D Cover Sh eet
Data Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
2 Am29F016D 21444_E9 November 16, 2009
Data Sheet
This page left intentionally blank.
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21444 Rev: EAmendment: 9
Issue Date: November 16, 2009
DATA SHEET
Am29F016D
16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■5.0 V ± 10%, single power supply operation
— Minimizes system level power requirements
■Manufactured on 0.23 µm process technology
— Compatible with 0.5 µm Am29F016 and 0.32 µm
Am29F016B devices
■High performance
— Access times as fast as 70 ns
■Low power consumption
— 25 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access
time to active mode)
■Flexible sector architecture
— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Group sector protection:
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
■Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■Minimum 1,000,000 program/erase cycles per
sector guaranteed
■20-year data retention at 125°C
— Reliable operation for the life of the system
■Package options
— 48-pin and 40-pin TSOP
— 44-pin SO
— Known Good Die (KGD)
(see publication number 21551)
■Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
■Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
■Ready/Busy# output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
■Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
■Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
2 Am29F016D 21444E9 November 16, 2009
DATA SHEET
GENERAL DESCRIPTION
The Am29F016D is a 16 Mbit, 5.0 volt-only Flash mem-
ory organized as 2,097,152 bytes. The 8 bits of data
appear on DQ0–DQ7. The Am29F016D is offered in
48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.
The device is also available in Known Good Die (KGD)
form. For more information, refer to publication number
21551. This device is designed to be programmed
in-system with the standard system 5.0 volt VCC supply.
A 12.0 volt VPP is not required for program or erase
operations. The device can also be programmed in
standard EPROM programmers.
This device is manufactured using AMD’s 0.23 µm pro-
cess technology, and offers all the features and
benefits of the Am29F016, which was manufactured
using 0.5 µm process technology.
The standard device offers access times of 70 and
90 ns, allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention, the de-
vice has separate chip enable (CE#), write enable
(WE#), and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
November 16, 2009 21444E9 Am29F016D 3
DATA SHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29F016D Device Bus Operations .................................. 8
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 9
Standby Mode .......................................................................... 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode................................................................ 9
Table 2. Sector Address Table........................................................ 10
Autoselect Mode..................................................................... 11
Table 3. Am29F016D Autoselect Codes (High Voltage Method).... 11
Sector Group Protection/Unprotection.................................... 11
Table 4. Sector Group Addresses................................................... 11
Temporary Sector Group Unprotect ....................................... 11
Figure 1. Temporary Sector Group Unprotect Operation............... 12
Hardware Data Protection ...................................................... 12
Low VCC Write Inhibit ...................................................................... 12
Write Pulse “Glitch” Protection........................................................ 12
Logical Inhibit .................................................................................. 12
Power-Up Write Inhibit .................................................................... 12
Common Flash Memory Interface (CFI) . . . . . . . 13
Table 5. CFI Query Identification String .......................................... 13
Table 6. System Interface String..................................................... 13
Table 7. Device Geometry Definition .............................................. 14
Table 8. Primary Vendor-Specific Extended Query ........................ 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data ................................................................ 15
Reset Command..................................................................... 15
Autoselect Command Sequence ............................................ 15
Byte Program Command Sequence....................................... 15
Unlock Bypass Command Sequence.............................................. 16
Figure 2. Program Operation ......................................................... 16
Chip Erase Command Sequence ........................................... 16
Sector Erase Command Sequence ........................................ 17
Erase Suspend/Erase Resume Commands........................... 17
Figure 3. Erase Operation.............................................................. 18
Command Definitions ............................................................. 19
Table 9. Am29F016D Command Definitions................................... 19
Write Operation Status . . . . . . . . . . . . . . . . . . . . 20
DQ7: Data# Polling................................................................. 20
Figure 4. Data# Polling Algorithm ................................................. 20
RY/BY#: Ready/Busy#............................................................ 21
DQ6: Toggle Bit I .................................................................... 21
DQ2: Toggle Bit II ................................................................... 21
Reading Toggle Bits DQ6/DQ2............................................... 21
DQ5: Exceeded Timing Limits ................................................ 22
DQ3: Sector Erase Timer ....................................................... 22
Figure 5. Toggle Bit Algorithm....................................................... 22
Table 10. Write Operation Status................................................... 23
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 24
Figure 6. Maximum Negative Overshoot Waveform ..................... 24
Figure 7. Maximum Positive Overshoot Waveform....................... 24
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
TTL/NMOS Compatible .......................................................... 25
CMOS Compatible.................................................................. 25
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Test Setup..................................................................... 26
Table 11. Test Specifications ......................................................... 26
Key to Switching Waveforms. . . . . . . . . . . . . . . . 26
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Read-only Operations............................................................. 27
Figure 9. Read Operation Timings ................................................ 27
Figure 10. RESET# Timings ......................................................... 28
Erase/Program Operations ..................................................... 29
Figure 11. Program Operation Timings......................................... 30
Figure 12. Chip/Sector Erase Operation Timings ......................... 31
Figure 13. Data# Polling Timings (During Embedded Algorithms) 32
Figure 14. Toggle Bit Timings (During Embedded Algorithms)..... 32
Figure 15. DQ2 vs. DQ6................................................................ 33
Figure 16. Temporary Sector Group Unprotect Timings ............... 33
Erase and Program Operations .............................................. 34
Alternate CE# Controlled Writes .................................................... 34
Figure 17. Alternate CE# Controlled Write Operation Timings ..... 35
Erase and Programming Performance . . . . . . . 36
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 36
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 36
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37
TS 040—40-Pin Standard Thin Small Outline Package ......... 37
TS 048—48-Pin Standard Thin Small Outline Package ......... 38
SO 044—44-Pin Small Outline Package ................................ 39
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40
4 Am29F016D 21444E9 November 16, 2009
DATA SHEET
PRODUCT SELECTOR GUIDE
Note: See the AC Characteristics section for more information.
BLOCK DIAGRAM
Family Part Number Am29F016D
Speed Options (VCC = 5.0 V ± 10%) -70 -90
Max Access Time (ns) 70 90
CE# Access (ns) 70 90
OE# Access (ns) 40 40
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip En ab le
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
WE#
CE#
OE#
STB
STB
DQ0
–
DQ7
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Ma tri x
Address Latch
A0–A20
November 16, 2009 21444E9 Am29F016D 5
DATA SHEET
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for
more information.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
40-Pin Standard TSOP
1
24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NC
NC
NC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
48
25
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
NC
NC
NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC
48-Pin Standard TSOP
6 Am29F016D 21444E9 November 16, 2009
DATA SHEET
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for
more information.
PIN CONFIGURATION
A0–A20 = 21 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
WE# = Write Enable
OE# = Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
VCC =+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
V
SS
V
SS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
CC
CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
SO
21
8
DQ0–DQ7
A0–A20
CE#
OE#
WE#
RESET# RY/BY#
November 16, 2009 21444E9 Am29F016D 7
DATA SHEET
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29F016D -70 E F
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
F = Industrial (–40°C to +85°C)with Pb-free package
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
E4 = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040)
S = 44-Pin Small Outline Package (SO 044)
This device is also available in Known Good Die (KGD) form. See publication number
21551 for more information.
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F016D
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase
Valid Combinations
AM29F016D-70 EI, EF, E4F, SF, E4I, SI
AM29F016D-90 EI, E4I, SI, EF, E4F, SF
8 Am29F016D 21444E9 November 16, 2009
DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is composed of latches that store
the commands, along with the address and data infor-
mation needed to execute the command. The contents
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F016D Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the
entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Operation CE# OE# WE# RESET# A0–A20 DQ0–DQ7
Read L L H H AIN DOUT
Write L H L H AIN DIN
CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V XHigh-Z
TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Hardware Reset X X X L X High-Z
Temporary Sector Unprotect
(See Note) X X X VID AIN DIN
November 16, 2009 21444E9 Am29F016D 9
DATA SHEET
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device re-
quires standard access time (tCE) for read access when
the device is in either of these standby modes, before it
is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS ±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
10 Am29F016D 21444E9 November 16, 2009
DATA SHEET
Table 2. Sector Address Table
Note: All sectors are 64 Kbytes in size.
Sector A20 A19 A18 A17 A16 Address Range
SA0 00000 000000h-00FFFFh
SA1 00001 010000h-01FFFFh
SA2 00010 020000h-02FFFFh
SA3 00011 030000h-03FFFFh
SA4 00100 040000h-04FFFFh
SA5 00101 050000h-05FFFFh
SA6 00110 060000h-06FFFFh
SA7 00111 070000h-07FFFFh
SA8 01000 080000h-08FFFFh
SA9 01001 090000h-09FFFFh
SA10 01010 0A0000h-0AFFFFh
SA11 01011 0B0000h-0BFFFFh
SA12 01100 0C0000h-0CFFFFh
SA13 01101 0D0000h-0DFFFFh
SA14 01110 0E0000h-0EFFFFh
SA15 01111 0F0000h-0FFFFFh
SA16 10000 100000h-10FFFFh
SA17 10001 110000h-11FFFFh
SA18 10010 120000h-12FFFFh
SA19 10011 130000h-13FFFFh
SA20 10100 140000h-14FFFFh
SA21 10101 150000h-15FFFFh
SA22 10110 160000h-16FFFFh
SA23 10111 170000h-17FFFFh
SA24 11000 180000h-18FFFFh
SA25 11001 190000h-19FFFFh
SA26 11010 1A0000h-1AFFFFh
SA27 11011 1B0000h-1BFFFFh
SA28 11100 1C0000h-1CFFFFh
SA29 11101 1D0000h-1DFFFFh
SA30 11110 1E0000h-1EFFFFh
SA31 11111 1F0000h-1FFFFFh
November 16, 2009 21444E9 Am29F016D 11
DATA SHEET
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi-
tion, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
Table 3. Am29F016D Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Group Protection/Unprotection
The hardware sector group protection feature dis-
ables both program and erase operations in any
sector group. Each sector group consists of four adja-
cent sectors. Table 4 shows how the sectors are
grouped, and the address range that each sector
group contains. The hardware sector group unprotec-
tion feature re-enables both program and erase
operations in previously protected sector groups.
Sector group protection/unprotection must be imple-
mented using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 23922. Contact an
AMD representative to obtain a copy of the appropriate
document. Note that the sector group protection and
unprotection scheme differs from that used with the
previous versions of this device, namely the
Am29F016B and Am29F016.
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and
protecting sector groups at its factory prior to shipping
the device through AMD’s ExpressFlash™ Service.
Contact an AMD representative for details.
It is possible to determine whether a sector group is
protected or unprotected. See “Autoselect Mode” for
details.
Table 4. Sector Group Addresses
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previ-
ously protected sector groups to change data
in-system. The Sector Group Unprotect mode is acti-
vated by setting the RESET# pin to VID. During this
mode, formerly protected sector groups can be pro-
grammed or erased by selecting the sector group
Description CE# OE# WE# A20-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0 DQ7-DQ0
Manufacturer ID:
AMD L L H X X VID X VIL X VIL VIL 01h
Device ID:
Am29F016D L L H X X VID X VIL X VIL VIH ADh
Sector Group
Protection
Verification
L L H
Sector
Group
Address
X VID X VIL X VIH VIL
01h (protected)
00h (unprotected)
Sector
Group A20 A19 A18 Sectors
SGA0 000SA0–SA3
SGA1 001SA4–SA7
SGA2 010SA8–SA11
SGA3 011SA12–SA15
SGA4 100SA16–SA19
SGA5 101SA20–SA23
SGA6 110SA24–SA27
SGA7 111SA28–SA31
12 Am29F016D 21444E9 November 16, 2009
DATA SHEET
addresses. Once VID is removed from the RESET#
pin, all the previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
the Temporary Sector Group Unprotect diagram (Fig-
ure 16) shows the timing waveforms, for this feature.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= VIL, CE# = VIH or WE# = VIH. To initiate a write cy-
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary
Sector Group Unprotect
Completed (Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group Unprotect
Operation
November 16, 2009 21444E9 Am29F016D 13
DATA SHEET
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of de-
vices. Software support can then be device-
independent, JEDEC ID-independent, and forward-
and backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 5–8. To terminate reading CFI data, the
system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The sys-
tem must write the reset command to return the device
to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD
representative for copies of these documents.
Table 5. CFI Query Identification String
Addresses Data Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h Primary OEM Command Set
15h
16h
40h
00h Address for Primary Extended Table
17h
18h
00h
00h Alternate OEM Command Set (00h = none exists)
19h
1Ah
00h
00h Address for Alternate OEM Extended Table (00h = none exists)
Table 6. System Interface String
Addresses Data Description
1Bh 45h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 55h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 00h VPP Min. voltage (00h = no VPP pin present)
1Eh 00h VPP Max. voltage (00h = no VPP pin present)
1Fh 03h Typical timeout per single byte/word write 2N µs
20h 00h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 0Ah Typical timeout per individual block erase 2N ms
22h 00h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 05h Max. timeout for byte/word write 2N times typical
24h 00h Max. timeout for buffer write 2N times typical
25h 04h Max. timeout per individual block erase 2N times typical
26h 00h Max. timeout for full chip erase 2N times typical (00h = not supported)
14 Am29F016D 21444E9 November 16, 2009
DATA SHEET
Table 7. Device Geometry Definition
Addresses Data Description
27h 15h Device Size = 2N byte
28h
29h
00h
00h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
00h
00h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch 01h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
1Fh
00h
00h
01h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Table 8. Primary Vendor-Specific Extended Query
Addresses Data Description
40h
41h
42h
50h
52h
49h
Query-unique ASCII string “PRI”
43h 31h Major version number, ASCII
44h 31h Minor version number, ASCII
45h 00h Address Sensitive Unlock
0 = Required, 1 = Not Required
46h 02h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 04h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 01h Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported
49h 04h
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah 00h Simultaneous Operation: 00 = Not Supported, 01 = Supported
4Bh 00h Burst Mode Type: 00 = Not Supported, 01 = Supported
4Ch 00h Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,
02 = 8 Word Page
4Dh 00h ACC supply minimum
4Eh 00h ACC supply maximum
4Fh 00h Top/bottom boot sector flag
2 = bottom, 3 = top. If address 2Ch = 01h, ignore this field
November 16, 2009 21444E9 Am29F016D 15
DATA SHEET
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
16 Am29F016D 21444E9 November 16, 2009
DATA SHEET
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the device has reset to read-
ing array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock by-
pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de-
vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Tab l e 9 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Note:
See the appropriate Command Definitions table for program
command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
November 16, 2009 21444E9 Am29F016D 17
DATA SHEET
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command
sequence should be reinitiated once the device has re-
turned to reading array data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The in-
terrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sec-
tor erase commands can be assumed to be less than
50 µs, the system need not monitor DQ3. Any com-
mand other than Sector Erase or Erase Suspend
during the time-out period resets the device to
reading array data. The system must rewrite the com-
mand sequence and any additional sector addresses
and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
18 Am29F016D 21444E9 November 16, 2009
DATA SHEET
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more
information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See the appropriate Command Definitions table for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
November 16, 2009 21444E9 Am29F016D 19
DATA SHEET
Command Definitions
Table 9. Am29F016D Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data r ead fr om lo cation RA during r e ad operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on
the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode)
or erased. Address bits A20–A16 select a unique sector.
SGA = Address of the sector group to be verified. Address bits
A20–A18 sele ct a unique sector group.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus
cycles are write operations.
4. Address bits A20–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading
array data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5
goes high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is
a read cycle.
8. The data is 00h for an unprotected sector group and 01h
for a protected sector group.See “Autoselect Command
Sequence” for more information.
9. Command is valid when device is ready to read array data
or when device is in autoselect mode.
10. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the unlock
bypass mode.
12. The system may read and program in non-erasing
sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid
only during a sector erase operation.
13. The Erase Resume command is valid only during the
Erase Suspend mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA R D
Reset (N ote 6) 1 XXX F0
Autoselect
(Note 7)
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID 4 555 AA 2AA 55 555 90 X01 AD
Sector Group Protect
Verify (Note 8) 4 555 AA 2AA 55 555 90 SGA
X02
XX00
XX01
CFI Query (Note 9) 1 55 98
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 10)2XXXA0PAPD
Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30
20 Am29F016D 21444E9 November 16, 2009
DATA SHEET
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Ta ble 10 and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is be-
cause DQ7 may change asynchronously with
DQ0–DQ6 while Output Enable (OE#) is asserted low.
The Data# Polling Timings (During Embedded Algo-
rithms) figure in the “AC Characteristics” section
illustrates this.
Table 10 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 4. Data# Polling Algorithm
November 16, 2009 21444E9 Am29F016D 21
DATA SHEET
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 10 shows the outputs for RY/BY#. The timing di-
agrams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Ta b l e 10 to compare out-
puts for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically,
a system would note and store the value of the toggle
bit after the first read. After the second read, the sys-
tem would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
22 Am29F016D 21444E9 November 16, 2009
DATA SHEET
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50 µs. See also the “Sector Erase Command Se-
quence” section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Ta ble 10 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 5. Toggle Bit Algorithm
(Notes
1, 2)
(Note
November 16, 2009 21444E9 Am29F016D 23
DATA SHEET
Table 10. Write Operation Status
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
Operation
DQ7
(Note 1) DQ6
DQ5
(Note 2)DQ3
DQ2
(Note 1)RY/BY#
Standard
Mode
Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector 1No toggle 0 N/A Toggle 1
Reading within Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
24 Am29F016D 21444E9 November 16, 2009
DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . .–65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .–55°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . –2.0 V to 7.0 V
A9, OE#, RESET# (Note 2) . . . . –2.0 V to 12.5 V
All other pins (Note 1). . . . . . . . . . –2.0 V to 7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, inputs may overshoot VSS to
–2.0 V for periods of up to 20 ns. See . Maximum DC
voltage on output and I/O pins is VCC + 0.5 V. During
voltage transitions, outputs may overshoot to VCC + 2.0
V for periods up to 20 ns. See .
2. Minimum DC input voltage on A9, OE#, RESET# pins is
–0.5 V. During voltage transitions, A9, OE#, RESET# pins
may overshoot VSS to –2.0 V for periods of up to 20 ns.
See . Maximum DC input voltage on A9, OE#, and
RESET# is 12.5 V which may overshoot to 13.5 V for
periods up to 20 ns.
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one secon d .
Stresses greater than those listed in this section may cause
permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections
of this specification is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods
may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TC) . . . . . . . . .–40°C to +85°C
VCC Supply Voltages
VCC for ± 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 6. Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 7. Maximum Positive
Overshoot Waveform
November 16, 2009 21444E9 Am29F016D 25
DATA SHEET
DC CHARACTERISTICS
TTL/NMOS Compatible
CMOS Compatible
Notes for DC Characteristics (both tables):
1. The ICC current is typically less than 1 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Program or Embedded Erase algorithm is in progress.
3. Not 100% tested.
4. For CMOS mode only ICC3, ICC4 = 20 µA at extended temperature (>+85°C).
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA
ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH 25 40 mA
ICC2 VCC Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 40 60 mA
ICC3
VCC Standby Current
(CE# Controlled)
VCC = VCC Max, CE# = VIH,
RESET# = VIH
0.4 1.0 mA
ICC4
VCC Standby Current
(RESET# Controlled) VCC = VCC Max, RESET# = VIL 0.4 1.0 mA
VIL Input Low Level –0.5 0.8 V
VIH Input High Level 2.0 VCC + 0.5 V
VID
Voltage for Autoselect and Sector
Protect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V
VOH Output High Level IOH = –2.5 mA VCC = VCC Min 2.4 V
VLKO Low VCC Lock-out Voltage 3.2 4.2 V
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA
ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH 25 40 mA
ICC2 VCC Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 30 40 mA
ICC3
VCC Standby Current
(CE# Controlled) (Note 4)
VCC = VCC Max, CE# = VCC ± 0.5 V,
RESET# = VCC ± 0.5 V 1 5 µA
ICC4
VCC Standby Current
(RESET# Controlled) (Note 4)
VCC = VCC Max,
RESET# = VSS ± 0.5 V 1 5 µA
VIL Input Low Level –0.5 0.8 V
VIH Input High Level 0.7x VCC VCC + 0.3 V
VID
Voltage for Autoselect
and Sector Protect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V
VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V
VOH2 IOH = –100 μA, VCC = VCC Min VCC – 0.4 V
VLKO Low VCC Lock-out Voltage 3.2 4.2 V
26 Am29F016D 21444E9 November 16, 2009
DATA SHEET
TEST CONDITIONS
Table 11. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
5.0 V
Device
Under
Test
Figure 8. Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition
All speed
options Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 100 pF
Input Rise and Fall Times 20 ns
Input Pulse Levels 0.45–2.4 V
Input timing measurement
reference levels 0.8 V
Output timing measurement
reference levels 2.0 V
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
November 16, 2009 21444E9 Am29F016D 27
DATA SHEET
AC CHARACTERISTICS
Read-only Operations
Notes:
1. Not 100% tested.
2. Refer to and for test specifications.
Parameter Symbol
Parameter Description Test Setup
Speed Options
UnitJEDEC Std -70 -90
tAVAV tRC Read Cycle Time (Note 1)Min 70 90 ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL
Max 70 90 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 ns
tGLQV tOE Output Enable to Output Delay Max 40 40 ns
tOEH
Output Enable Hold Time
(Note 1)
Read Min 0 0 ns
Toggle and Data#
Polling Min 10 10 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1)Max 20 20 ns
tGHQZ tDF Output Enable to Output High Z (Note 1)Max 20 20 ns
tAXQX tOH
Output Hold Time From Addresses CE# or OE#
Whichever Occurs First Min 0 0 ns
tReady
RESET# Pin Low to Read Mode
(Note 1)Max 20 20 µs
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tOH
Figure 9. Read Operation Timings
28 Am29F016D 21444E9 November 16, 2009
DATA SHEET
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note:
Not 100% tested.
Parameter
Description All Speed OptionsJEDEC Std Test Setup Unit
tREADY
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note) Max 20 µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See Note) Min 50 ns
tRB RY/BY# Recovery Time Min 0ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 10. RESET# Timings
November 16, 2009 21444E9 Am29F016D 29
DATA SHEET
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter
Parameter Description
Speed Options
UnitJEDEC Std -70 -90
tAVAV tWC Write Cycle Time (Note 1)Min 70 90 ns
tAVWL tAS Address Setup Time Min 0ns
tWLAX tAH Address Hold Time Min 40 45 ns
tDVWH tDS Data Setup Time Min 40 45 ns
tWHDX tDH Data Hold Time Min 0ns
tOES Output Enable Setup Time Min 0ns
tGHWL tGHWL
Read Recover Time Before Write
(OE# high to WE# low) Min 0ns
tELWL tCS CE# Setup Time Min 0ns
tWHEH tCH CE# Hold Time Min 0ns
tWLWH tWP Write Pulse Width Min 40 45 ns
tWHWL tWPH Write Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2)Ty p 7µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Typ 1sec
Max 8sec
tVCS VCC Set Up Time (Note 1)Min 50 µs
tBUSY WE# to RY/BY# Valid Max 40 40 ns
30 Am29F016D 21444E9 November 16, 2009
DATA SHEET
AC CHARACTERISTICS
OE#
WE#
CE#
VCC
Data
Addresses
tDS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
tBUSY
t
CH
PA
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 11. Program Operation Timings
November 16, 2009 21444E9 Am29F016D 31
DATA SHEET
AC CHARACTERISTICS
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
RY/BY#
tRB
tBUSY
Note:
SA = Sector Address. VA = Valid Address for reading status data.
Figure 12. Chip/Sector Erase Operation Timings
32 Am29F016D 21444E9 November 16, 2009
DATA SHEET
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 13. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
tOE
DQ6/DQ2
RY/BY#
tBUSY
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
tACC
tRC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
November 16, 2009 21444E9 Am29F016D 33
DATA SHEET
AC CHARACTERISTICS
Temporary Sector Unprotect
Note:
Not 100% tested.
Parameter
All Speed OptionsJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect Min 4µs
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
Note:
The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended
sector.
Figure 15. DQ2 vs. DQ6
RESET#
tVIDR
12 V
0 or 5 V
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
0 or 5 V
Figure 16. Temporary Sector Group Unprotect Timings
34 Am29F016D 21444E9 November 16, 2009
DATA SHEET
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter Symbol
Parameter Description
Speed Options
UnitJEDEC Std -70 -90
tAVAV tWC Write Cycle Time (Note 1)Min 70 90 ns
tAVEL tAS Address Setup Time Min 0ns
tELAX tAH Address Hold Time Min 40 45 ns
tDVEH tDS Data Setup Time Min 40 45 ns
tEHDX tDH Address Hold Time Min 0ns
tGHEL tGHEL Read Recover Time Before Write Min 0ns
tWLEL tWS CE# Setup Time Min 0ns
tEHWH tWH CE# Hold Time Min 0ns
tELEH tCP Write Pulse Width Min 40 45 ns
tEHEL tCPH Write Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2)Ty p 7µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Ty p 1sec
Max 8sec
November 16, 2009 21444E9 Am29F016D 35
DATA SHEET
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
tBUSY
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 17. Alternate CE# Controlled Write Operation Timings
36 Am29F016D 21444E9 November 16, 2009
DATA SHEET
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further
information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 1 8sec Excludes 00h programming prior to
erasure (Note 4)
Chip Erase Time 32 256 sec
Byte Programming Time 7300 µs Excludes system-level overhead
(Note 5)
Chip Programming Time (Note 3) 14.4 43.2 sec
Min Max
Input Voltage with respect to VSS on I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
CIN Input Capacitance VIN = 0 67.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time
150°C10 Ye a r s
125°C20 Ye a r s
November 16, 2009 21444E9 Am29F016D 37
DATA SHEET
PHYSICAL DIMENSIONS
TS 040—40-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
38 Am29F016D 21444E9 November 16, 2009
DATA SHEET
PHYSICAL DIMENSIONS (continued)
TS 048—48-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
November 16, 2009 21444E9 Am29F016D 39
DATA SHEET
PHYSICAL DIMENSIONS (continued)
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
40 Am29F016D 21444E9 November 16, 2009
DATA SHEET
REVISION SUMMARY
Revision A (May 1997)
Initial release of Am29F016B (0.35 µm) device.
Revision B (January 1998)
Global
Made formatting and layout consistent with other data
sheets. Used updated common tables and diagrams.
Revision B+1 (January 1998)
AC Characteristics—Read-only Operations
Deleted note referring to output driver disable time.
Figure 16—Temporary Sector Group Unprotect
Timings
Corrected title to indicate “sector group.”
Revision B+2 (April 1998)
Global
Added -70 speed option, deleted -75 speed option.
Distinctive Characteristics
Changed minimum 100K write/erase cycles guaran-
teed to 1,000,000.
Ordering Information
Added extended temperature availability to -90, -120,
and -150 speed options.
Operating Ranges
Added extended temperature range.
DC Characteristics, CMOS Compatible
Corrected the CE# and RESET# test conditions for
ICC3 and ICC4 to VCC ±0.5 V.
AC Characteristics
Erase/Program Operations; Erase and Program Oper-
ations Alternate CE# Controlled Writes: Corrected the
notes reference for tWHWH1 and tWHWH2. These param-
eters are 100% tested. Corrected the note reference for
tVCS. This parameter is not 100% tested.
Temporary Sector Unprotect Table
Added note reference for tVIDR. This parameter is not
100% tested.
Erase and Programming Performance
Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.
Revision C (January 1999)
Global
Updated for CS39S process technology.
Distinctive Characteristics
Added:
■20-year data retention at 125°C
— Reliable operation for the life of the system
DC Characteristics—CMOS Compatible
ICC3, ICC4: Added Note 4, “For CMOS mode only ICC3,
ICC4 = 20 µA at extended temperature (>+85°C)”.
DC Characteristics—TTL/NMOS Compatible and
CMOS Compatible
ICC1, ICC2, ICC3, ICC4: Added Note 2 “Maximum ICC
specifications are tested with VCC = VCCmax”.
ICC3, ICC4: Deleted VCC = VCCMax.
Revision C+1 (March 23, 1999)
Operating Ranges
The temperature ranges are now specified as ambient.
Revision C+2 (May 17, 1999)
Product Selector Guide
Corrected the tOE specification for the -150 speed op-
tion to 55 ns.
Operating Ranges
VCC Supply Voltages: Added “VCC for ± 5% devices .
+4.75 V to +5.25 V”.
Revision C+3 (July 2, 1999)
Global
Added references to availability of device in Known
Good Die (KGD) form.
Revision D (November 16, 1999)
AC Characteristics—Figure 11. Program
Operations Timing and Figure 12. Chip/Sector
Erase Operations
Deleted tGHWL and changed OE# waveform to start at
high.
Physical Dimensions
Replaced figures with more detailed illustrations.
Revision E (May 19, 2000)
Global
Changed part number to Am29F016D. This reflects the
new 0.23 µm process technology upon which this de-
vice will now be built.
The Am29F016D is compatible with the previous 0.32
µm Am29F016B device, with the exception of the sec-
tor group protect and unprotect algorithms. These
algorithms are provided in a seperate document. Con-
tact AMD for more information or to request a copy of
that document.
November 16, 2009 21444E9 Am29F016D 41
DATA SHEET
This data sheet will be marked preliminary until the de-
vice has been in full production for a number of months.
The -75 speed option (70 ns, ±5% VCC) has been re-
placed by a -70 speed option (70 ns, ±10 VCC).
The burn-in option is no longer available.
The device now has the Unlock Bypass Program
feature.
The publication number of the document describing
sector protection/unprotection implementation is now
23922.
Revision E+1 (December 4, 2000)
Global
Added table of contents. Removed Preliminary status
from document.
Revision E+2 (March 23, 2001)
Common Flash Memory Interface (CFI)
Added section.
Table 9, Am29F016D Command Definitions
Corrected the addresses for the three-cycle unlock by-
pass command sequence. Added Note 9 and CFI
Query command to table.
Revision E+3 (June 4, 2004)
Ordering Information
Added Lead-free (Pb-free) options to the Temperature
Range breakout of the OPN table and the Valid Combi-
nations table..
Revision E+4 (January 4, 2006)
Global
Deleted 150 speed option
Deleted TSR048 48-pin Reverse Thin Small Outline
Package Option
Deleted TSR040 40-pin Reverse Thin Small Outline
Package Option
Revision E5 (July 27, 2006)
Global
Added product availability notice to cover page and first
page of data sheet.
AC Characteristics
Erase/Program Operations table: Changed tBUSY to a
maximum specification.
Revision E6 (November 2, 2006)
Global
Deleted product availability notice to cover page and
first page of data sheet.
Revision E7 (March 3, 2009)
Global
Added obsolescence information.
Revision E8 (August 3, 2009)
Global
Removed obsolescence information.
Revision E9 (November 16, 2009)
Global
Removed 120 ns speed option.
Removed all commercial temperature range options.
42 Am29F016D 21444E9 November 16, 2009
DATA SHEET
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