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Revision: November 11, 2010 1300 Henley Court | Pullman, WA 99163
(509) 334 6306 Voice and Fax
Introduction
The Basys2 board is a circuit design and
implementation platform that anyone can use
to gain experience building real digital circuits.
Built around a Xilinx Spartan-3E Field
Programmable Gate Array and a Atmel
AT90USB2 USB controller, the Basys2 board
provides complete, ready-to-use hardware
suitable for hosting circuits ranging from basic
logic devices to complex controllers. A large
collection of on-board I/O devices and all
required FPGA support circuits are included,
so countless designs can be created without
the need for any other components.
Four standard expansion connectors allow
designs to grow beyond the Basys2 board
using breadboards, user-designed circuit
boards, or Pmods (Pmods are inexpensive
analog and digital I/O modules that offer A/D
& D/A conversion, motor drivers, sensor
inputs, and many other features). Signals on
the 6-pin connectors are protected against
ESD damage and short-circuits, ensuring a
long operating life in any environment. The
Basys2 board works seamlessly with all
versions of the Xilinx ISE tools, including the free WebPack. It ships with a USB cable that provides
power and a programming interface, so no other power supplies or programming cables are required.
The Basys2 board can draw power and be programmed via its on-board USB2 port. Digilent’s freely
available PC-based Adept software automatically detects the Basys2 board, provides a programming
interface for the FPGA and Platform Flash ROM, and allows user data transfers (see
www.digilentinc.com for more information).
The Basys2 board is designed to work with the free ISE WebPack CAD software from Xilinx.
W ebPack can be used to define circuits using schematics or HDLs, to simulate and synthesize
circuits, and to create programming files. Webpack can be downloaded free of charge from
www.xilinx.com/ise/.
The Basys2 board ships with a built-in self-test/demo stored in its ROM that can be used to test all
board features. To run the test, set the Mode Jumper (see below) to ROM and apply board power. If
the test is erased from the ROM, it can be downloaded and reinstalled at any time. See
www.digilentinc.com/Basys2 for the test project as well as further documentat ion, reference designs,
and tutorials.
Xilinx Spartan3E-100 CP132
VGA Port
Platform
Flash
(config ROM)
Settable Clock
Source
(25 / 50 / 100 MHz)
Full Speed
USB2 Port
(JTAG and data transfers)
20
JA JB JC JD
JTAG
port
I/O Devices PS/2
Port Pmod Connectors
4
4
4
4
8 bit
color
2
32
Data
port
• 100,000-gate Xilinx Spartan 3E FP GA
• Atmel AT90USB2 Full-speed USB 2 port pr ov idin g board po w er
and programming/data transfer interface
• Xilinx Platform Flash ROM to store FPGA configurations
• 8 LEDs, 4-digit 7-segment display, 4 buttons, 8 slide switches
• PS/2 port and 8-bit VGA port
• User-settable clock (25/ 5 0/10 0 MHz), plus socket for 2nd clock
• Four 6-pin head er expa nsi on c onne ctor s
• ESD and short-circuit protection on all I/O signals.
Figure 1. Basys2 board block diagram and features
Doc: 502-155 page 1 of 12
Copyright Digi l ent, Inc. All rights res erv ed. Ot her product and company names mentioned may be trademarks of their respective owners.
Basys2 Reference Manual
Digilent
www.digilentinc.com
Board Power
The Basys2 board is typically powered from a USB cable, but a
battery connector is also provided so that external supplies can be
used. To use USB power, simply attach the USB cable. To power
the Basys2 using a battery or other external source, attach a 3.5V-
5.5V battery pack (or other power source) to the 2-pin, 100-mil
spaced battery connector (three AA cells in series make a good
4.5+/- volt supply). Voltages higher than 5.5V on either power
connector may cause permanent damage.
Input power is routed through the power switch (SW 8) to the four
6-pin expansion connectors and to a Linear Technology LTC3545
voltage regulator. The LTC3545 produces the main 3.3V supply
for the board, and it also produces 2.5V and 1.2V supply voltages
required by the FPGA. Total board current is dependent on FPGA
configuration, clock frequency, and external connections. In test circuits with roughly 20K gates
routed, a 50MHz clock source, and all LEDs illuminated, about 100mA of current is drawn from the
1.2V supply, 50mA from the 2.5V supply, and 50mA from the 3.3V supply. Required current will
increase if larger circuits are configured in the FPGA, or if peripheral boards are attached.
The Basys2 board uses a four layer PCB, with the inner layers dedicated to VCC and GND planes.
The FPGA and the other ICs on the board have large complements of ceramic bypass capacitors
placed as close as possible to each VCC pin, resulting in a very clean, low-noise power supply.
Configuration
After power-on, the FPGA on the Basys2 board must be configured before it can perform any useful
functions. During configuration, a “bit” file is transferred into memory cells within the FPGA to define
the logical functions and circuit interconnects. The free ISE/WebPack CAD software from Xilinx can
be used to create bit files from VHDL, Verilog, or schematic-based source files.
Digilent’s PC-based program called Adept can be used to configure the FPGA with any suitable bit file
stored on the computer. Adept uses the USB cable to transfer a selected bit file from the PC to the
FPGA (via the FPGA’s JTAG programming port). Adept can also program a bit file into an on-board
non-volatile RO M called “Platform Flash”. Once programmed, the Platform Flash can automatically
transfer a stored bit file to the FPGA at a subsequent power-on or reset event if the Mode Jumper
(JP3) is set to ROM. The FPGA will remain configured until it is reset by a power-cycle event. The
Platform Flash ROM will retain a bit file until it is reprogrammed, regardless of power-cycle events.
Figure 2 . Basys2 power circuits
Doc: 502-138 page 2 of 12
Basys2 Reference Manual
Digilent
www.digilentinc.com
To program the Basys2 board, set the mode
jumper to PC and attach the USB cable to
the board. Start the Adept software, and
wait for the FPGA and the Platform Flash
ROM to be recognized. Use the browse
function to ass ociat e the desired .bit file with
the FPGA, and/or the desired .mcs file with
the Platform Flash ROM. Right-clic k on the
device to be programmed, and select the
“program” function. The con figuration file
will be sent to the FPGA or Platform Flash,
and the software will indicate whether
programming was successful. The “Status
LED” LED (LD_8) will also blink after the
FPGA has been successfully configur ed.
For further information on using Adept,
please see the Adept documentation
available at the Digilent website.
Oscillators
The Basys2 board includes a primary, user-settable silicon oscillator that produces 25MHz, 50MHz, or
100MHz based on the position of the clock select jumper at JP4. Initially, this jumper is not loaded
and must be soldered in place. A socket for a second oscillator is provided at IC6 (the IC6 socket can
accommodate any 3.3V CMOS oscillator in a half-size DIP package). The primary and secondary
oscillators are connected to global clock input
pins at pin B8 and pin M6 respectively.
Both clock inputs can drive the clock synthesizer
DLL on the Spartan 3E, allowing for a wide range
if internal frequencies, from 4 times the input
frequency to any integer divisor of the input
frequency.
The primary silicon oscillator is flexible and
inexpensive, but it lacks the frequency stability of
a crystal oscillator. Some circuits that drive a
VGA monitor may realize a slight improvement in
imag e stability by using a crystal oscillator
installed in the IC6 socket. For these applications,
a 25MHz (or 50MHz) crystal oscillator, available
from any catalog distributor, is recommended
(see for example part number SG-8002JF-PCC at
www.digikey.com ).
Spartan-3E
FPGA
B8CLK_OUT
Linear Tech.
LTC6905
Oscillator
Frequency
Select
Jumper
25MHz
50MHz
100MHz
Figure 5. Basys2 oscillator circuits
XCF02
Platform
Flash
JTAG
Spartan 3E
FPGA
Mode
Jumper
PC ROM
USB miniB
connector
Atmel
AT90USB2
Slave
serial
port
JTAG
port
LD8
Figure 4. Basys2 Programming Circuits
Doc: 502-138 page 3 of 12
Basys2 Reference Manual
Digilent
www.digilentinc.com
User I/O
Four pushbuttons and eight slide switches
are provided for circuit inputs. Pushbutton
inputs are normally low and driven high
only when the pushbutton is pressed.
Slide switches generate constant high or
low inputs depending on position.
Pushbuttons and slide switches all have
series resistors for protection against
short circuits (a short circuit would occur if
an FPGA pin assigned to a pushbutton or
slide switch was inadvertently def ined as
an output).
Eight LEDs and a four-digit seven-
segment LED display are provided for
circuit outputs. LED anodes are driven
from the FPGA via current-limiting
resistors, so they will illum ina te when a
logic ‘1’ is written to the corresponding
FPGA pin. A ninth L E D is provided as a
power-indicator LED, and a tenth LED
(LD-D) illuminates any time the FPGA has
been successfully programmed.
Seven-segment display
Each of the four digits o f the seven-
segment LED display is composed of
seven LED segments arranged in a “figure
8” pattern. Segment LEDs can be
individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain
LED segments and leaving the others dark. Of these 128 possible patterns, the ten corresponding to
the decimal digits are the most us eful.
The anodes of the seven LEDs forming each digit are tied together into one common anode circuit
node, but the LED cathodes remain separate. The common anode signals are available as four “digit
enable” input signals to the 4-digit display. The cathodes of similar segments on all four displays are
connected into seven circuit nodes labeled CA through CG (so, for example, the four “D” cathodes
from the four digits are grouped together into a single circuit node called “CD”). These seven cathode
signals are available as inputs to the 4-digit display. This signal connection scheme creates a
multiplexed display, where the cathode signals are common to all digits but they can only illuminate
the segments of the digit whose corresponding anode signal is asserted.
A scanning display controller circuit can be used to show a four-digit number on this display. This
circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating,
continuous succession, at an update rate that is faster than the human eye response. Each digit is
illuminated just one-quarter of the time, but because the eye cannot perceive the darkening of a digit
before it is illuminated again, the digit appears continuously illuminated. If the update or “refresh” rate
is slowed to a given point (around 45 hertz), then most people will begin to see the display flicker.
Figure 6. Basys2 I/O circuits
Doc: 502-138 page 4 of 12
Basys2 Reference Manual
Digilent
www.digilentinc.com
For each of the four digits to appear
bright and continuously illuminated, all
four digits should be driven once every 1
to 16ms (for a refres h fr equenc y of
1KHz to 60Hz). For example, in a 60Hz
refresh scheme, the entire display would
be refreshed once every 16ms, and
each digit would be illuminated for ¼ of
the refresh cycle, or 4ms. The controller
must assure that the correct cathode
pattern is present when the
corresponding anode signal is driven.
To illustrate the process, if AN1 is
asserted while CB and CC are asserted, then a “1” will be displayed in digit position 1. Then, if AN2 is
asserted while CA, CB and CC are asserted, then a “7” will be displayed in digit position 2. If A1 and
CB, CC are driven for 4ms, and then A2 and CA, CB, CC are driven for 4ms in an endless
succession, the display will show “17” in the first two digits. Figure 8 shows an example timing
diagram for a four-digit seven-segment controller.
PS/2 Port
The 6-pin mini-DIN connector can accommodate a PS/2 mouse or keyboard. The PS/2 connector is
supplied with 5VDC.
Both the mouse and keyboard use a two-wire serial bus (clock and data) to communicate with a host
device. Both use 11-bit words that include a start, stop and odd parity bit, but the data packets are
organized differently, and the keyboard interface allows bi-directional data transfers (so the host
device can illuminate state LEDs on the keyboard). Bus timings are shown in the figure.
The clock and data signals are only driven when data transfers occur, and otherwise they are held in
the “idle” state at logic ‘1’. The timings define signal requirements for mouse-to-host communications
and bi-directional keyboard communications. A PS/2 interface circuit can be implemented in the
FPGA to create a keyboard or mouse interface.
AN0
AN1
AN2
AN3
Cathodes Digit 0
Refresh period = 1ms to 16ms
Digit period = Refresh / 4
Digit 1 Digit 2 Digit 3
Figure 8 . Multiplexed 7seg display timing
A
F
E
D
C
B
G
Common anode
Individual cathodes
DP
AN1 AN2 AN3 AN4
CA CB CC CD CE CF CG DP
Four-digit Seven
Segment Display
An un-illuminated seven-segment display, and nine
illumination patterns corresponding to decimal digits
Figure 7. Seven-segment display
Doc: 502-138 page 5 of 12
Basys2 Reference Manual
Digilent
www.digilentinc.com
Keyboard
The keyboard uses open-collector drivers so the
keyboard or an attached host device can drive the
two-wire bus ( if the host device will not send data to
the keyboard, then the host can use input-only ports).
PS2-style keyboards use scan codes to
communicate key press data. Each key is assigned a
code that is sent whenever the key is pressed; if the
key is held down, the scan code will be sent
repeatedly about once every 100ms. When a key is
released, a “F0” key-up code is sent, followed by the
scan code of the released key. If a key can be “shifted” to produce a new character (like a capital
letter), then a shift character is sent in addition to the scan code, and the host must determine which
ASCII c haracter to use. Some keys, called extended keys, send an “E0” ahead of the scan code (and
they may send more than one scan code). When an extended key is released, an “E0 F0” key-up
code is sent, followed by the scan code. Scan codes for most keys are shown in the figure. A host
device can also send data to the keyboard. Below is a short list of some common commands a host
might send.
ED Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns “FA” after receiving “ED”,
then host sends a byte to set LED status: Bit 0 sets Scroll Lock; bit 1 sets Num Lock; and Bit 2
sets Caps lock. Bits 3 to 7 are ignored.
EE Echo (test). Keyboard return s “EE” after rece iving “EE”.
F3 Set scan code repeat rate. Keyboard returns “F3” on receiving “FA”, then host sends second
byte to set the repeat rate.
FE Resend. “FE” directs keyboard to re-send most recent scan code.
FF Reset. Resets the keyboard.
The keyboard can send data to the host only when both the data and clock lines are high (or idle).
Since the host is the “bus master”, the keyboard must check to see whether the host is sending data
before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host
pulls the clock line low, the keyboard must not send any data until the clock is released.
TCK
TSU
Clock time
Data-to-clock setup time 30us
5us 50us
25us
Symbol Parameter Min Max
THLD Clock-to-data hold time 5us 25us
Edge 0
‘0’ start bit ‘1’ stop bit
Edge 10
Tsu
T
hld
Tck Tck
Figure 10. PS/2 signal timing
Pin1: Data
Pin2: Data
Pin3: GND
Pin5: Vdd
Pin6: Clock
Pin8: Clock
21 35
8 6
1
3
6
2
5
8
(bottom up)
B1
Spartan 3E
FPGA
CLK
DATA
6-pin
mini-DIN
C3
200 Ω
200 Ω
Figure 9. PS/2 connector and Basys2 P S/2 cir cu it
Doc: 502-138 page 6 of 12
Basys2 Reference Manual
Digilent
www.digilentinc.com
The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of
scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard
generates 11 clock transitions (at around 20 - 30KHz) when the data is sent, and data is valid on the
falling edge of the clock.
Mouse
The mouse outputs a clock and data signal when it is moved; otherwise, these signals remain at logic
‘1’. Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device.
Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an
odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where
bits 0, 11, and 22 are ‘0’ start bits, and bits 11, 21, and 33 are ‘1’ stop bits. The three 8-bit data fields
contain movement data as shown in the figure above. Data is valid at the falling edge of the clock, and
the clock period is 20 to 30KHz.
The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a
positive number in the X field, and moving to the left generates a negative number. Likewise, moving
the mouse up generates a positive number in the Y field, and moving down represents a negative
number (the XS and YS bits in the status byte are the sign bits – a ‘1’ indicates a negative number).
The magni tude of the X and Y numbers represent the rate of mouse movement – the larger the
number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow
indicators – a ‘1’ means overflow has occurred). If the mouse moves continuously, the 33-bit
transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and
Right button presses (a ‘1’ indicates the button is being pressed).
ESC
76
` ~
0E
TAB
0D
Caps Lock
58
Shift
12
Ctrl
14
1 !
16 2 @
1E 3 #
26 4 $
25 5 %
2E
Q
15 W
1D E
24 R
2D T
2C
A
1C S
1B D
23 F
2B G
34
Z
1Z X
22 C
21 V
2A B
32
6 ^
36 7 &
3D 8 *
3E 9 (
46 0 )
45 - _
4E = +
55 BackSpace
66
Y
35 U
3C I
43 O
44 P
4D [ {
54 ] }
5B \ |
5D
H
33 J
3B K
42 L
4B ; :
4C ' "
52 Enter
5A
N
31 M
3A , <
41 > .
49 / ?
4A Shift
59
Alt
11 Space
29 Alt
E0 11 Ctrl
E0 14
F1
05 F2
06 F3
04 F4
0C F5
03 F6
0B F7
83 F8
0A F9
01 F10
09 F11
78 F12
07 E0 75
E0 74
E0 6B
E0 72
Figure 11. Keyboard scan codes
L R 0 1 XS YS XY YY P X0 X1 X2 X3 X4 X5 X6 X7 P Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P1 0 1 00 11
Idle state Start bit
Mouse status byte X direction byte Y direction byte
Stop bit Start bit Stop bitIdle state
Stop bit Start bit
Figure 12. Mouse data format
Doc: 502-138 page 7 of 12
Basys2 Reference Manual
Digilent
www.digilentinc.com
VGA Port
The Basys2 board uses 10 FPGA signals to
create a VGA port with 8-bit color and the two
standard sync signals (HS – Horizontal Sync,
and VS – Vertic a l Sync). The color signals use
resistor-divider circuits that work in conjunction
with the 75-ohm termination resistance of the
VGA display to create eight signal levels on the
red and green VGA signals, and four on blue
(the human eye is less sensitive to blue levels).
This circuit, shown in figure 13, produces video
color signals that proceed in equal increments
between 0V (fully off) and 0.7V (fully on). A
video controller circuit must be created in the
FPGA to drive the sync and color signals with
the correct timing in order to produce a working
display system.
VGA System Tim ing
VGA signal timings are specified, published,
copyrighted and sold by the VESA organization
(www .vesa.org). The foll owi ng VGA system
timing information is provided as an example of
how a VGA monitor might be driven in 640 by
480 mode. For more precise information, or for
information on other VGA frequencies, refer to documentation available at the VESA website.
CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to
display information on a phosphor-coated screen. LCD displays use an array of switches that can
impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through
the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD
displays have evolved to use the same signal
timings as CRT displays (so the “signals”
discussion below pertains to both CRTs and
LCDs). Color CRT displays use three electron
beams (one for red, one for blue, and one for
green) to energize the phosphor that coats
the inner side of the display end of a cathode
ray tube (see illustration). Electron beams
emanate from “electron guns” which are
finely-pointed heated cathodes placed in
close proximity to a positively charged
annular plate called a “grid”. The electrostatic
force imposed by the grid pulls rays of
energized electrons from the cathodes, and
those rays are fed by the current that flows
into the cathodes. These particle rays are
initially accelerated towards the grid, but they
soon fall under the influence of the much
larger electrostatic force that results from the
C14
Spartan 3E
FPGA
HD-DB15
D13
F13
J14
K13
2KΩ
1KΩ
510Ω
200Ω
200Ω
15
10 5
11
6
1Pin 1: Red
Pin 2: Grn
Pin 3: Blue
Pin 13: HS
Pin 14: VS
Pin 5: GND
Pin 6: Red GND
Pin 7: Grn GND
Pin 8: Blu GND
Pin 10: Sync GND
RED0
RED1
RED2
F14
G13
G14
2KΩ
1KΩ
510Ω
GRN0
GRN1
GRN2
H13
J13
1KΩ
510Ω
BLUE0
BLUE1
RED
GRN
BLU
HS
VS
Figure 13. VGA pin definitions an d Basys2 circuit
Anode (entire screen)
High voltage
supply (>20kV)
Deflection coils
Grid Electron guns
(Red, Blue, Green)
gun
control
grid
control
deflection
control
R,G,B signals
(to guns)
Cathode ray tube
Cathode ray
VGA
cable
Figure 14. CRT deflection system
Doc: 502-138 page 8 of 12
Basys2 Reference Manual
Digilent
www.digilentinc.com
entire phosphor-coated display surface of the CRT being charged to 20kV (or more). The rays are
focused to a fine beam as they pass through the center of the grids, and then they accelerate to
impact on the phosphor-coated display surface. The phosphor surface glows brightly at the impact
point, and it continues to glow for several hundred microseconds after the beam is removed. The
larger the current fed into the cathode, the brighter the phosphor will glow.
Between the grid and the display surface, the beam passes through the neck of the CRT where two
coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of
charged particles (electrons), they can be deflected by these magnetic fields. Current waveforms are
passed through the coils to produce magnetic fields that interact with the cathode rays and cause
them to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically
from top to bottom. As the cathode ray moves over the surface of the display, the current sent to the
electron guns can be increased or decreased to change the brightness of the display at the cathode
ray impact point.
Information is only displayed when the beam is moving in the “forward” direction (left to right and top
to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much
of the potential display time is therefore lost in “blanking” periods when the beam is reset and
stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at
which the beam can be traced across the display, and the frequency at which the electron beam can
be modulated determine the display resolution. Modern VGA displays can accommodate different
resolutions, and a VGA controller
circuit dictates the resolution by
producing timing signals to control the
raster patterns. The controller must
produce synchronizing pulses at 3.3V
(or 5V) to set the frequency at which
current flows through the deflection
coils, and it must ensure that video
data is applied to the electron guns at
the correct time. Raster video displays
define a number of “rows” that
corresponds to the number of
horizontal passes the cathode makes
over the display area, and a number of
“columns” that corresponds to an area
on each row that is assigned to one
“picture element” or pixel. Typical
displays use from 240 to 1200 rows
and from 320 to 1600 columns. The
overall size of a display and the
number of rows and columns
determines the size of each pixel.
Video data typically comes from a
video refresh memory, with one or
more bytes assigned to each pixel
location (the Basys2 uses three bits
per pixel). The controller must index
into video memory as the beams move
across the display, and retrieve and apply video data to the display at precisely the time the electron
beam is moving across a given pixel.
Current
waveform
through
horizontal
defletion
coil
Stable current ramp - information
is displayed during this time
Retrace - no
information
displayed
during this
time
Total horizontal time
Horizontal display time
Horizontal sync signal
sets retrace frequency
retrace
time
time
HS
"back porch""front porch"
Display Surface
640 pixels per row are displayed
during forward beam trace
pixel 0,639
pixel 0,0
pixel 479,0 pixel 479,639
Figure 15. VGA system signals
Doc: 502-138 page 9 of 12
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Digilent
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A VGA cont roller circuit must generate the
HS and VS timings signals and coordinate
the delivery of video data based on the pixel
clock. The pixel clock defines the time
available to display one pixel of information.
The VS signal defines the “refresh”
frequency of the display, or the frequency at
which all information on the display is
redrawn. The minimum refresh frequency is
a function of the display’s phosphor and
electron beam intensity, with practical
refresh frequencies falling in the 50Hz to
120Hz range. The number of lines to be
displayed at a given refresh frequency
defines the horizontal “retrace” frequency.
For a 640-pixel by 480-row display using a
25MHz pixel clock and 60 +/-1Hz refresh,
the signal timings shown in the table at right
can be derived. Timings for sync pulse width and front and back porch intervals (porch intervals are
the pre- and post-sync pulse times during which information cannot be displayed) are based on
observations taken from actual VGA displays.
A VGA controller circuit decodes the output of a horizontal-sync counter driven by the pixel clock to
generate HS signal timings. This counter can be used to locate any pixel location on a given row.
Likewise, t he output of a vertical-sync counter that increments with each HS pulse can be used to
generate VS signal timings, and this counter can be used to locate any given row. These two
continually running counters can be used to form an address into video RAM. No time relationship
between the onset of the HS pulse and the onset of the VS pulse is specified, so the designer can
arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync
pulse generation.
T
S
T
disp
T
pw
T
fp
T
bp
TS
Tdisp
Tpw
Tfp
Tbp
Sync pulse
Display time
Pulse width
Front porch
Back porch
16.7ms
15.36ms
64 us
320 us
928 us
416,800
384,000
1,600
8,000
23,200
521
480
2
10
29
Symbol Parameter Time Clocks Lines
Vertical Sync
32 us
25.6 us
3.84 us
640 ns
1.92 us
800
640
96
16
48
Clks
Horiz. Sync
Time
Figure 16. VGA system timings for 640x480 display
Horizontal
Counter
Zero
Detect
3.84us
Detect
Horizontal
Synch
Set
Reset
Vertical
Counter
Zero
Detect
64us
Detect
Vertical
Synch
Set
Reset
CE VS
HS
Pixel
CLK
Figure 17. Schematic for a VGA controller circ uit
Doc: 502-138 page 10 of 12
Basys2 Reference Manual
Digilent
www.digilentinc.com
Expansion Connectors (6-pin headers)
The Basys2 board provides four 6-pin
peripheral module connectors. Each connector
provides Vdd, GND, and four unique FPGA
signals. Several 6-pin module boards that can
attach to this connector are available from
Digilent, including A/D converters, speaker
amplifiers, microphones, H-bridge amplifiers,
etc. Please see www.digilentinc.com for more
information.
FPGA Pin Definitions
The table below shows all pin definitions for the
Spartan-3E on the Basys2 board. Pins in grey
boxes are not available to the user
FPGA pin definition tabl e color key
Grey
Not available to user
Green
User I/O devices
Yellow
Data ports
Tan
Pmod connector signals
Blue
USB signals
Basys2 Spartan-3E pin definitions
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
C12
JD1
P11
SW0
N14
CC
B2
JA1
P8
MODE0
M7
GND
A13
JD2
M2
USB-DB1
N13
DP
C2
USB-WRITE
N7
MODE1
P5
GND
A12
NC
N2
USB-DB0
M13
AN2
C3
PS2D
N6
MODE2
P10
GND
B12
NC
M9
NC
M12
CG
D1
NC
N12
CCLK
P14
GND
B11
NC
N9
NC
L14
CA
D2
USB-WAIT
P13
DONE
A6
VDDO-3
C11
BTN1
M10
NC
L13
CF
L2
USB-DB4
A1
PROG
B10
VDDO-3
C6
JB1
N10
NC
F13
RED2
L1
USB-DB3
N8
DIN
E13
VDDO-3
B6
JB2
M11
LD1
F14
GRN0
M1
USB-DB2
N1
INIT
M14
VDDO-3
C5
JB3
N11
CD
D12
JD4
L3
SW1
P1
NC
P3
VDDO-3
B5
JA4
P12
CE
D13
RED1
E2
SW6
B3
GND
M8
VDDO-3
C4
NC
N3
SW7
C13
JD3
F3
SW5
A4
GND
E1
VDDO-3
B4
SW3
M6
UCLK
C14
RED0
F2
USB-ASTB
A8
GND
J2
VDDO-3
A3
JA2
P6
LD3
G12
BTN0
F1
USB-DSTB
C1
GND
A5
VDDO-2
A10
JC3
P7
LD2
K14
AN3
G1
LD7
C7
GND
E12
VDDO-2
C9
JC4
M4
BTN2
J12
AN1
G3
SW4
C10
GND
K1
VDDO-2
B9
JC2
N4
LD5
J13
BLU2
H1
USB-DB6
E3
GND
P9
VDDO-2
A9
JC1
M5
LD0
J14
HSYNC
H2
USB-DB5
E14
GND
A11
VDDO-1
B8
MCLK
N5
LD4
H13
BLU1
H3
USB-DB7
G2
GND
D3
VDDO-1
C8
RCCLK
G14
GRN2
H12
CB
B14
TMS
H14
GND
D14
VDDO-1
A7
BTN3
G13
GRN1
J3
JA3
B13
TCK-FPGA
J1
GND
K2
VDDO-1
B7
JB4
F12
AN0
K3
SW2
A2
TDO-USB
K12
GND
L12
VDDO-1
P4
LD6
K13
VSYNC
B1
PS2C
A14
TDO-S3
M3
GND
P2
VDDO-1
Spartan 3E
FPGA
B2
A3
J3
B5
ESD protection
diodes
1
6-pin
header
2
3
4
5
6
JA
Short-circuit protection
resistors
3.3V
16-pin
header
2
3
4JB
16-pin
header
2
3
4JC
16-pin
header
2
3
4JD
C6
B6
C5
B7
A9
B9
A10
C9
C12
A13
C13
D12
Figure 18. Basys2 Pmod connector circuits
Doc: 502-138 page 11 of 12
Basys2 Reference Manual
Digilent
www.digilentinc.com
Built in Self Test
The Basys2 board comes preloaded with a simple sel f test/demonstration project stored in its ROM.
The demo project (available at the website) shows how the Xilinx CAD tools connect FPGA signals to
Basys2 circuits. Since the project is stored in ROM, it can also be used to check board functions. To
run the demo, set the ROM/USB jumper (JP3) to ROM and apply power to the board; the seven-
segment display will show counting digits, the switches will turn on individual LEDs, the buttons will
turn off individual digits on the seven segment display, and a test pattern is driven on the VGA port.
If the self test is not resident in the Platform Flash ROM, it can be programmed into the FPGA or
reloaded into the ROM using the Adept programming software.
Doc: 502-138 page 12 of 12
Mouser Electronics
Authorized Distributor
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