PI74AVC+16374 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 2.5V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Outputs Product Features Product Description * PI74AVC+16374 is designed for low-voltage operation, VCC = 1.65V to 3.6V The PI74ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the Clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. OE can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In that state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. * True 24mA Balanced Drive @ 3.3V * Compatible with Philips and T.I. AVC Logic family * IOFF supports partial power-down operation * 3.6V I/O Tolerant inputs and outputs * All outputs contain a patented DDC (Dynamic DriveControl) circuit that reduces noise without degrading propagation delay. * Industrial operation at -40C to +85C * Packaging (Pb-free & Green available): - 48-pin 240-mil wide plastic TSSOP (A) - 48-pin 173-mil wide plastic TVSOP (K) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Logic Block Diagram 1OE 1CLK 1 48 C1 2 1D1 47 1Q1 1D To Seven Other Channels 2OE 2CLK 24 25 C1 13 2D1 36 2Q1 1D To Seven Other Channels 1 06-0168 PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Supply voltage range, VCC ............................................. -0.5V to +4.6V Input voltage range, VI ................................................... -0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ...................... -0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ......................................... -0.5V to VCC +0.5V Input clamp current, IIK (VI <0) .................................................... -50mA Output clamp current, IOK (VO <0) .............................................. -50mA Continuous output current, IO .................................................... 50mA Continuous current through each VCC or GND ......................... 100mA Package thermal impedance, JA(3): package A ......................... 64C/W package K ......................... 48C/W Storage Temperature range, Tstg .................................... -65C to 150C Product Pin Configuration Product Pin Description 1OE 1 48 1Q1 2 47 Pin Name Description 1D1 OE CLK 3-State Output Enable Inputs (Active LOW) Clock Input (Active HIGH) Dx Data Inputs 1CLK 1Q2 3 46 1D2 GND 4 45 GND Qx 3-State Outputs GND VCC Ground Power 1Q3 5 44 1D3 1Q4 VCC 6 43 7 42 1D4 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 1Q8 12 37 1D8 2Q1 13 36 Truth Table(1) Inputs Outputs OE CLK D Q L H H 2D1 L L L L H or L X Q0 H X X Z 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 2Q4 17 32 2D4 VCC 2Q5 18 31 19 30 VCC 2D5 2Q6 20 29 2D6 GND 21 28 GND 2Q7 22 27 2D7 2Q8 23 26 2D8 2OE 24 25 2CLK Notes: 1. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance 2 06-0168 1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Recommended Operating Conditions(1) VCC Supply Voltage M in. M a x. Operating 1. 4 3.6 Data retention only 1.2 VCC = 1.2V VIH High- level Input Voltage VCC VCC = 1.4V to 1.6V 0.65 x VCC VCC = 1.65V to 1.95V 0.65 x VCC VCC = 2.3V to 2.7V VCC = 3V to 3.6V 1. 7 2 VCC = 1.2V VIL Low- level Input Voltage VI Input Voltage VO Output Voltage IOHS High- level output current IOLS Low- level output current tv Input transition rise or fall rate TA Units V GND VCC = 1.4V to 1.6V 0.35 x VCC VCC = 1.65V to 1.95V 0.35 x VCC VCC = 2.3V to 2.7V 0.7 VCC = 3V to 3.6V 0.8 0 3 .6 Active State 0 VCC 3- State 0 3.6 VCC = 1.4V to 1.6V -4 VCC = 1.65V to 1.95V -6 VCC = 2.3V to 2.7V - 12 VCC = 3V to 3.6V - 24 mA VCC = 1.4V to 1.6V 4 VCC = 1.65V to 1.95V 6 VCC = 2.3V to 2.7V 12 VCC = 3V to 3.6V 24 VCC = 1.4V to 3.6V 5 ns/V 85 C Operating free- air temperature -40 Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation. 3 06-0168 PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 DC Electrical Characteristics (Over the Operating Range, TA = -40C +85C) Te s t Conditions (1) Parame te rs IO H = -100A VO H M in. 1.4V to 3.6V VC C -0.2V IO HS = -4mA VIH = 0.91V 1.4V 1.05 IO HS = -6mA VIH = 1.07V 1.65V 1.2 IO HS = -12mA VIH = 1.7V 2.3V 1.75 IO HS = -24mA VIH = 2V 3V 2. 0 IO LS = 100A VO L VCC Typ. M ax. 1.4V to 3.6V 0. 2 IO LS = 4mA VIL = 0.49V 1.4V 0. 4 IO LS = 6mA VIL = 0.57V 1.65V 0.4 5 IO LS = 12mA VIL = 0.7V 2.3V 0.5 5 IO LS = 24mA VIL = 0.8V 3V 0.8 II VI = VC C or GND 3 . 6V 2.5 IO F F VI or VO = 3.6V 0 10 IO Z VO = VC C or GND 3.6V 10 IC C VI = VC C or GND 3 . 6V 40 IO = 0 Control Inputs VI = VC C or GND CI Data Inputs CO Outputs VO = VC C or GND 2.5V 3.5 3.3V 3.5 2.5V 6 3.3V 6 2.5V 6.5 3.3V 6.5 Units V A pF Notes: 1. Typical values are measured at TA = 25C. 4 06-0168 PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Timing Requirements (Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4) VCC = 1.2V VCC = 1.5V 0.1V M in. M in. M a x. VCC = 1.8V 0.15V M ax. M in. M ax. fclock Clock frequency VCC = 2.5V 0.2V M in. M a x. 160 tw Pulse duration, CLK high or low tsu Setup time, data before CLK 4.1 th Hold time, data after CLK 1.7 VCC = 3.3V 0.3V M in. Units M a x. 2 00 20 0 3.1 2. 5 2.5 2.7 1.9 1.4 1.4 1.3 1. 2 1.1 1. 1 ns Switching Characteristics (Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4) Parame te rs From (Input) To (Output) VCC = 1.2V Typ. VCC = 1.5V 0.1V M in. VCC = 1.8V 0.15V M ax. M in. M ax. 160 fmax VCC = 2.5V 0.2V M in. M a x. 20 0 VCC = 3.3V 0.3V M in. Units M a x. 200 tpd CLK Q 7.3 1.5 8.4 1.2 6 .7 0 .8 4. 1 0.7 3 .3 ten OE Q 7 .4 1. 6 8.5 1.6 6 .7 0 .9 4.3 0. 7 3 .4 tdis OE Q 8 .4 2.5 9 .4 2.3 7 .8 1 4.2 1. 5 3.9 ns Operating Characteristics, TA= 25C Parame te rs Cpd Power Dissipation Capacitance Outputs Enabled Outputs Disabled Te s t Conditions CL = 0pF, f = 10 MHz 2 outputs switching 5 06-0168 VCC = 1.8V 0.15V VCC = 2.5V 0.2V VCC = 3.3V 0.3V Typical Typical Typical 74 81 89 52 57 63 Units pF PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 PARAMETER MEASUREMENT INFORMATION VCC = 1.2V and 1.5V 0.1V 2xVCC S1 2 From Output Under Test CL = 15pF Open GND 2 (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V VOL tPHZ VCC/2 VOH -0.1V VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. * All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. * The outputs are measured one at a time with one transition per measurement. * tPLZ and tPHZ are the same as tdis * tPZL and tPZH are the same as ten * tPLH and tPHL are the same as tpd 6 06-0168 PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 PARAMETER MEASUREMENT INFORMATION VCC = 1.8V 0.15V 2xVCC S1 12k From Output Under Test CL = 30 15pF Open GND 2 1 k (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V 0.15V VOL tPHZ VCC/2 VOH -0.1V 0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 2. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. * All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. * The outputs are measured one at a time with one transition per measurement. * tPLZ and tPHZ are the same as tdis * tPZL and tPZH are the same as ten * tPLH and tPHL are the same as tpd 7 06-0168 PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V 2xVCC S1 500 2 From Output Under Test CL =30 15pF Open GND 500 2 (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.15V VOL tPHZ VCC/2 VOH -0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 3. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. * All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. * The outputs are measured one at a time with one transition per measurement. * tPLZ and tPHZ are the same as tdis * tPZL and tPZH are the same as ten * tPLH and tPHL are the same as tpd 8 06-0168 PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 PARAMETER MEASUREMENT INFORMATION VCC = 3.3V 0.3V 2xVCC S1 500 2 From Output Under Test CL = 30 15pF Open GND 500 2 (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V 0.3V VOL tPHZ VCC/2 VOH -0.1V 0.3V VOH 0V Voltage Waveforms Enable and Disable Times Figure 4. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. * All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. * The outputs are measured one at a time with one transition per measurement. * tPLZ and tPHZ are the same as tdis * tPZL and tPZH are the same as ten * tPLH and tPHL are the same as tpd 9 06-0168 PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Packaging Mechanical: 48-pin TSSOP (A) 48 .236 .244 1 6.0 6.2 .488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 X.XX X.XX .0197 BSC 0.50 DENOTES DIMENSIONS IN MILLIMETERS 0.45 .018 0.75 .030 .002 .006 0.05 0.15 .007 .010 0.17 0.27 .319 BSC 8.1 Packaging Mechanical: 48-pin TVSOP (K) 48 .169 .177 4.30 4.50 .0035 .008 .031 .041 0.80 1.05 1 .378 9.60 .386 9.80 0.09 0.20 0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS .016 BSC 0.40 .002 .006 0.05 0.15 .0051 .009 0.13 0.23 10 06-0168 Max. .047 1.20 PS8527A 06/01/06 PI74AVC+16374 2.5V 16-Bit Edge Triggered D-Type Flip Flop with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Ordering Information Orde ring Code Package Type Package De s cription PI74ALC+16374A A 56- pin, 240 mil wide plastic TSSOP PI74ALC+16374AE A Pb- free & Green, 56- pin, 240 mil wide plastic TSSOP PI74ALC+16374K K 56- pin, 173mil wide plastic TSVOP PI74ALC+16374KE K Pb- free & Green, 56- pin, 173 mil wide plastic TVSOP Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free & Green * Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 11 06-0168 PS8527A 06/01/06