IBM043612PQK32K x 36Burst (Pentium), TQFP package. IBM043614PQK 32K X 36 BURST SRAM Features * 32K x 36 Organization * Asynchronous Output Enable * 0.5 CMOS Technology * Self-Timed Write Operation and Byte Write Capability * Supports PowerPCTM Processor Operation * Single +3.3V 5% Power Supply and Ground * Low Power Dissipation - 960 mW Active at 66MHz - 90 mW Standby * 5V Tolerant I/O * 100 Pin Thin Quad Flat Pack * LVTTL I/O Compatible * Fast OE times: 4, 5, 6ns * Common I/O * Registered Addresses, Data Ins and Control Signals Description IBM Microelectronics 1M SRAM is a Synchronous Burstable, high performance CMOS Static RAM that is versatile, wide I/O, and achieves 8 nsec access. A single clock is used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of the Clock, all Addresses, Data Ins and Control Signals are registered internally. Burst mode operation, is accomplished by integrating input registers, internal 2-bit burst counter and high speed SRAM in a single chip. Burst reads are initiated with either ADSP or ADSC being LOW with a valid address during the rising edge of clock. Data from this address plus the three subsequent addresses will be output. The chip is operated with a single +3.3 V power supply and is compatible with LVTTL I/O interfaces. 8190747 SA14-4652-02 Revised 07/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 12 IBM043614PQK 32K X 36 BURST SRAM ADSP ADV A8 A9 82 81 NC 88 83 CLK 89 ADSC VSS 90 84 VDD 81 85 CS2 92 NC WEa 93 OE WEb 94 86 WEc 95 87 CS2 WEd 98 96 CS 99 97 A6 A7 100 X36 TQFP Pin Array Layout VSS 15 66 NC NC 16 65 VDD VSS 17 64 NC DQ27 18 63 DQ8 DQ28 19 62 DQ7 VDDQ 20 61 VDDQ VSS 21 60 VSS DQ29 22 59 DQ6 DQ30 23 58 DQ5 DQ31 24 57 DQ4 DQ32 25 56 DQ3 VSS 26 55 VSS VDDQ 27 54 VDDQ DQ33 28 53 DQ2 DQ34 29 52 DQ1 DQ35 30 51 DQ0 50 67 NC 14 49 DQ9 NC VDD NC 68 48 13 A14 DQ10 DQ26 47 69 46 12 A13 VDDQ DQ25 A12 70 45 11 A11 VSS VDDQ 44 71 43 10 A10 DQ11 VSS NC 72 42 9 NC DQ12 DQ24 41 73 40 8 VDD DQ13 DQ23 VSS 74 39 7 NC DQ14 DQ22 38 75 NC 6 37 VSS DQ21 36 76 A0 5 A1 VDDQ VSS 35 77 A2 4 34 DQ15 VDDQ 33 78 A3 3 32 DQ16 DQ20 A4 DQ17 79 A5 80 2 31 1 DQ19 NC DQ18 Pin Description A0-A14 DQa - DQd CLK Address input ADSP Address Status Processor Data Input/Output (0-8,9-17,18-26,27-35) ADSC Address Status Controller Clock ADV Burst Advance Control WEa Write Enable, Byte a (0 to 8) CS ADSP Gated Chip Select WEb Write Enable, Byte b (9 to 17) VDD Power Supply (+3.3V) WEc Write Enable, Byte c (18 to 26) VSS Ground WEd Write Enable, Byte d (27 to 35) VDDQ Output Power Supply (+3.3V) OE Output Enable CS2, CS2 No Connect Chip Selects (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 12 NC 8190747 SA14-4652-02 Revised 07/95 IBM043614PQK 32K X 36 BURST SRAM Block Diagram Row Address A0 - A14 DQ0 - DQ8 A2 - A9 Column A10 - A14 Address Register 32K x 36 Array Register DQ9 - DQ17 SA0 CLK ADV Burst Binary A0 DQ18 - DQ26 SA1 Counter ADSC Clear A1 DQ27 - DQ35 ADSP CS CS CS2 CS2 Select Registers Byte Write Register WEa Byte Write Register WEb Byte Write Register WEc Byte Write Register WEd OE Ordering Information Part Number Organization Speed Leads IBM043614PQK-8 32K x 36 8 ns Access / 15 ns Cycle 100 pin TQFP IBM043614PQK-9 32K x 36 9 ns Access / 15 ns Cycle 100 pin TQFP IBM043614PQK-10 32K x 36 10 ns Access / 15 ns Cycle 100 pin TQFP IBM043614PQK-11 32K x 36 11 ns Access / 15 ns Cycle 100 pin TQFP 8190747 SA14-4652-02 Revised 07/95 Notes (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 12 IBM043614PQK 32K X 36 BURST SRAM Burst SRAM Clock Truth Table CLK CS2 CS2 CS ADSP ADSC ADV WE OE DQ LH H X L L X X X X HIZ Deselected Cycle Operation LH X L L L X X X X HIZ Deselected Cycle LH H X X X L X X X HIZ Deselected Cycle LH X L X X L X X X HIZ Deselected Cycle LH L H L L X X X L Q Read from External Address, Begin Burst LH L H L L X X X H HIZ Read from External Address, Begin Burst LH L H L H L X H L Q Read from External Address, Begin Burst LH L H L H L X L X D Write to External Address, Begin Burst LH X X X H H L H L Q Read from next Add., Continue Burst LH X X X H H L L X D Write to next Add., Continue Burst LH X X X H H H H L Q Read from Current Add., Suspend Burst LH X X X H H H L X D Write to Current Add., Suspend Burst LH X X H X L X X X HIZ LH X X H X H L H L Q Read from next Add., Continue Burst LH X X H X H L L X D Write to next Add., Continue Burst LH X X H X H H H L Q Read from current Add., Suspend Burst LH X X H X H H L X D Write to current Add., Suspend Burst Deselect Cycle 1. For a write operation preceded by a read cycle, OE must be HIGH early enough to allow Input Data Setup, and must be kept HIGH through Input Data Hold Time. 2. WE refers to WEa, WEb, WEc, WEd. 3. ADSP is gated by CS, and CS is used to block ADSP when CS = VIH, as required in applications using Processor Address Pipelining. 4. All Addresses, Data In and Control signals are registered on the rising edge of CLK. Burst Sequence Truth Table (A1,A0) External Address A14-A2 (0,1) (1,0) (1,1) 1st Access A14-A2 (0,0) (0,1) (1,0) (1,1) 2nd Access A14-A2 (0,1) (1,0) (1,1) (0,0) 3rd Access A14-A2 (1,0) (1,1) (0,0) (0,1) 4th Access A14-A2 (1,1) (0,0) (0,1) (1,0) (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 12 Notes (0,0) 8190747 SA14-4652-02 Revised 07/95 IBM043614PQK 32K X 36 BURST SRAM Write Enable Truth Table WEa WEb WEc WEd H H H H L L L L Write All Bytes Notes Byte Written Read All Bytes L H H H Write Byte A (DIN 0 - 8) H L H H Write Byte B (DIN 9 - 17) H H L H Write Byte C (DIN 18 - 26) H H H L Write Byte D (DIN 27 - 35) Absolute Maximum Ratings Parameter Symbol Rating Units Notes Power Supply Voltage VDD -0.5 to 4.6 V 1 Input Voltage VIN -0.5 to 6.0 V 1 Output Voltage VOUT -0.5 to VDD+0.5 V 1 Operating Temperature TOPR 0 to +70 C 1 Storage Temperature TSTG -55 to +125 C 1 Power Dissipation PD 2.0 W 1 Short Circuit Output Current IOUT 50 mA 1 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (TA=0 to 70C) Parameter Symbol Min. Typ. Max. Units Notes Supply Voltage VDD 3.135 3.3 3.465 V 1,4 Input High Voltage VIH 2.2 -- 5.5 V 1,2,4 Input Low Voltage VIL -0.3 -- 0.8 V 1,3,4 Output Current IOUT -- 5 8 mA 4 1. 2. 3. 4. All voltages referenced to GND. All VDD(Q) and VSS(Q) pins must be connected. VIH(Max)DC = 5.5 V, VIH(Max)AC = 6.0 V (pulse width 4.0ns) VIL(Min)DC = - 0.3 V, VIL(Min)AC= -1.5 V (pulse width 4.0ns) Input voltage levels are tested to the following DC conditions: 1 microsecond cycle and 200 ns set-up and hold times. Capacitance (TA=0 to +70C, VDD=3.3V 5%, f=1MHz) Parameter Input Capacitance Data I/O Capacitance (DQ0-DQ35) 8190747 SA14-4652-02 Revised 07/95 Symbol Test Condition Max Units CIN VIN = 0V 5 pF COUT VOUT = 0V 5 pF Notes (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 12 IBM043614PQK 32K X 36 BURST SRAM DC Electrical Characteristics (TA= 0 to +70C, VDD=3.3V 5%) Parameter Symbol Min. Max. Units Notes IDD15 -- 275 mA 2,3 Standby Current Power Supply Standby Current (CS2 = VIH or CS2 = VIL or CS = VIH All other inputs = VIH or VIL, IOUT. = 0, Clock @ 66 MHz)) ISB -- 25 mA 1,3 Input Leakage Current Input Leakage Current, any input (VIN = 0 &VDD) ILI -- +1 A 4 Output Leakage Current (VOUT =0 &VDD, OE = VIH) ILO -- +1 A Output High Level Output "H" Level Voltage (IOH=-8mA @ 2.4V) VOH 2.4 -- V Output Low Level Output "L" Level Voltage (IOL=+8mA @ 0.4V) VOL -- 0.4 V Operating Current Average Power Supply Operating Current (OE = VIH, IOUT = 0) 1. 2. 3. 4. ISB = Stand-by Current IDD = Selected Current IOUT = Chip Output Current The input leakage current for 5.5V inputs is 200 A for Clk, Chip Selects, and Output Enable. Other inputs have100 A of leakage current at 5.5V AC Test Conditions (TA=0 to +70C, VDD=3.3V 5%) Parameter Symbol Conditions Units Input Pulse High Level VIH 3.0 V Input Pulse Low Level VIL 0.0 V Input Rise Time TR 2.0 ns Input Fall Time TF 2.0 ns 1.5 V Input and Output Timing Reference Level Output Load Conditions Notes 1 1. See AC Test Loading figure 1 on page 8. (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 12 8190747 SA14-4652-02 Revised 07/95 IBM043614PQK 32K X 36 BURST SRAM AC Characteristics (TA=0 to +70C, VDD=3.3V 5%, Units in nsec) -8 Parameter -9 -10 -11 Symbol Notes Min. Max. Min. Max. Min. Max. Min. Max. tCYCLE 15.0 -- 15.0 -- 15.0 -- 15.0 -- Clock Pulse High tCH 3.0 -- 3.0 -- 3.0 -- 3.0 -- Clock Pulse Low tCL 3.0 -- 3.0 -- 3.0 -- 3.0 -- Clock to Output Valid tCQ -- 8.0 -- 9.0 -- 10.0 -- 11.0 Address Status Controller Setup Time tADSCS 2.5 -- 2.5 -- 2.5 -- 2.5 -- Address Status Controller Hold Time tADSCH 0.5 -- 0.5 -- 0.5 -- 0.5 -- Address Status Processor Setup Time tADSPS 2.5 -- 2.5 -- 2.5 -- 2.5 -- Address Status Processor Hold Time tADSPH 0.5 -- 0.5 -- 0.5 -- 0.5 -- Advance Setup Time tADVS 2.5 -- 2.5 -- 2.5 -- 2.5 -- Advance Hold Time tADVH 0.5 -- 0.5 -- 0.5 -- 0.5 -- Address Setup Time tAS 2.5 -- 2.5 -- 2.5 -- 2.5 -- Address Hold Time tAH 0.5 -- 0.5 -- 0.5 -- 0.5 -- Chip Selects Setup Time tCSS 2.5 -- 2.5 -- 2.5 -- 2.5 -- Chip Selects Hold Time tCSH 0.5 -- 0.5 -- 0.5 -- 0.5 -- Write Enables Setup Time tWES 2.5 -- 2.5 -- 2.5 -- 2.5 -- Write Enables Hold Time tWEH 0.5 -- 0.5 -- 0.5 -- 0.5 -- Data In Setup Time tDS 2.5 -- 2.5 -- 2.5 -- 2.5 -- Data In Hold Time tDH 0.5 -- 0.5 -- 0.5 -- 0.5 -- Data Out Hold Time tCQX 3.0 -- 3.0 -- 3.0 -- 3.0 -- 3 Clock High to Output High Z tCHZ -- 5.0 -- 5.0 -- 5.5 -- 5.5 1,2,4 Clock High to Output Active tCLZ 2.5 -- 2.5 -- 2.5 -- 2.5 -- 1,2,4 Output Enable to High Z tOHZ 2.0 5.0 2.0 5.5 2.0 6.0 2.0 6.5 1,4 Output Enable to Low Z tOLZ 0.25 -- 0.25 -- 0.25 -- 0.25 -- 1,4 Output Enable to Output Valid tOQ -- 4.0 -- 5.0 -- 5.0 -- 6.0 3 Cycle Time 3 1. Transitions are measured 200 mV from steady state voltage. 2. At any given voltage and temperature, Tchz (max) is always less than Tclz (min) for a given device and from device to device. For any read cycle preceded by a write or deselect cycle, the data bus will transition glitch-free from HIZ to new RAM data. 3. See AC Test Loading figure 1 on page 8. 4. See AC Test Loading figure 2 on page 8. 8190747 SA14-4652-02 Revised 07/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 12 IBM043614PQK 32K X 36 BURST SRAM AC Test Loading + 3.3 V 317 50 DQ DQ 50 30 pF 351 5 pF VL = 1.5 V Fig. 1 Test Equivalent Load Fig. 2 Test Equivalent Load Output Capacitive Load Derating Curve 3.0 2.5 nanoseconds 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 0 15 30 45 60 75 90 105 picoFarads The derating curve above is for a purely capacitive load on the output driver. For example, a part specified at 8 ns access time will behave as though it has an 8.5 ns access time if a 30 pF load with no DC component was attached to the output driver. The access times guaranteed in the datasheets are based on a 50 ohm terminated test load. For unterminated loads the derating curve should be used. This curve is based on nominal process conditions with worst case parameters Vdd = 3.14 V, Ta = 70 C. (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 12 8190747 SA14-4652-02 Revised 07/95 IBM043614PQK 32K X 36 BURST SRAM Timing Diagram (Burst Read) tcycle tCH tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tADVS tADVH ADV tAS tAH ADDR tAS A1 tAH A2 tWES tWEH WEa, WEb WEc, WEd tCSS tCSH CS2 CS2 CS tCSS OE tCSH tOHZ tOQ DQ Q1(A) tCQ tCQ tCQ tOLZ Q2(A) Q2(B) Q2(D) Q2(C) tCQX tCQX Notes: 1. Q1(A) and Q2(A) refer to data read from address A1 and A2. 2. Q2(B), Q2(C) and Q2(D) refer to read from subsequent internal burst counter addresses. 8190747 SA14-4652-02 Revised 07/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 12 IBM043614PQK 32K X 36 BURST SRAM Timing Diagram (Burst Write) tcycle tCH tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tADVS tADVH tADVH ADV tAS tAH tAS A1 ADDR tAH tADVS A2 tWES tWEH WEa, WEb WEc, WEd tCSS tCSH CS2 CS2 tCSS tCSH CS OE tOHZ tCHZ DQ tDS tDH tDS tDH D2(A) D1(A) tDS tDH tDS tDH D2(B) D2(B) tCLZ Notes: 1. D1(A) and D2(A) refer to data written to address A1 and A2. 2. D2(B) refers to data written to a subsequent internal burst counter address. 3. WEa, WEb, WEc and WEd are don't cares when ADSP is sampled LOW. (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 12 8190747 SA14-4652-02 Revised 07/95 IBM043614PQK 32K X 36 BURST SRAM 100 Pin TQFP Package Diagram Pin 1 I.D. 22.00 0.20 20.00 0.10 14.00 0.10 16.00 0.20 1.40 0.10 12 Typ 1.60 Max 0.05/0.15 (Min/Max) 12 Typ 0.30 0.05 0.65 Basic 1.60 MAX 6 4 0.25 Seating Plane 0.10 Max Standoff 0.05/0.15(Min/Max) Lead Coplanarity 0- 7 Rad 0.20 Typ 0.60 +0.15/-0.10 Note: All dimensions in Millimeters 8190747 SA14-4652-02 Revised 07/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 12 IBM043614PQK 32K X 36 BURST SRAM Revision Log Rev Contents of Modification 5/94 Initial Release of the 32K x 36 (8/9/11) TQFP BURST MODE Application Spec. 3/95 Updated -8, -9, -11; Added -10 Specifications 7/95 Removed Preliminary classification. (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 12 8190747 SA14-4652-02 Revised 07/95