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FEATURES
APPLICATIONS
DESCRIPTION
1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
D or P PACKAGE
(TOP VIEW)
LOGIC DIAGRAM (Positive Logic)
DA
DE
RE
R
B
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
WIDE SUPPLY RANGE RS-485 TRANSCEIVER
The driver differential outputs and receiverdifferential inputs connect internally to form a•Operates With a 3-V to 5.5-V Supply
differential input/output (I/O) bus port that is designed•Consumes Less Than 90 mW Quiescent
to offer minimum loading to the bus whenever thePower
driver is disabled or not powered. The drivers andreceivers have active-high and active-low enables•Open-Circuit, Short Circuit, and Idle-Bus
respectively, which can be externally connectedFailsafe Receiver
together to function as a direction control.•1/8
th
Unit-Load (up to 256 nodes on the bus)•Bus-Pin ESD Protection Exceeds 16 kV HBM•Driver Output Voltage Slew-Rate Limited forOptimum Signal Quality at 10 Mbps•Electrically Compatible With ANSITIA/EIA-485 Standard
•Data Transmission With Remote StationsPowered From the Host•Isolated Multipoint Data Buses•Industrial Process Control Networks•Point-of-Sale Networks•Electric Utility Metering
The SN65HVD08 combines a 3-state differential linedriver and differential line receiver designed forbalanced data transmission and interoperation withANSI TIA/EIA-485-A and ISO-8482Estandard-compliant devices.
The wide supply voltage range and low quiescentcurrent requirements allow the SN65HVD08s tooperate from a 5-V power bus in the cable with asmuch as a 2-V line voltage drop. Busing power in thecable can alleviate the need for isolated power to begenerated at each connection of a ground-isolatedbus.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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Host
SN65HVD08
Power Bus and Return Resistance
Isolation
Barrier
Remote
(One of n Shown)
5 V Power
Direct
Connection
to Host
5 V Return
PACKAGE DISSIPATION RATINGS
ABSOLUTE MAXIMUM RATINGS
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
SPECIFIED TEMPERATUREPART NUMBER PACKAGE PACKAGE MARKINGRANGE
SN65HVD08D –40°C to 85°C SOIC VP08SN65HVD08P –40°C to 85°C PDIP 65HVD08SN75HVD08D 0°C to 70°C SOIC VN08SN75HVD08P 0°C to 70°C PDIP 75HVD08
PACKAGE T
A
≤25°C POWER RATING DERATING FACTOR ABOVE T
A
= 25°C T
A
= 85°C POWER RATING
SOIC (D) 710 mW 5.7 mW/°C 369 mWPDIP (P) 1000 mW 8 mW/°C 520 mW
over operating free-air temperature range unless otherwise noted
(1) (2)
UNIT
Supply voltage, V
CC
-0.3 V to 6 VVoltage range at A or B -9 V to 14 VInput voltage range at D, DE, R or RE -0.5 V to V
CC
+ 0.5 VVoltage input range, transient pulse, A and B, through 100 Ω-25 V to 25 VReceiver ouput current, I
O
–11 mA to 11 mAA, B, and GND 16 kVHuman Body Model
(3)Electrostatic discharge All pins 4 kVCharged-Device Model
(4)
All pins 1 kVContinuous total power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
MIN NOM MAX UNIT
Supply voltage, V
CC
3 5.5 VInput voltage at any bus terminal (separately or common mode), V
I
(1)
–7 12 VHigh-level input voltage, V
IH
2.25 V
CCDriver, driver enable, and receiver enable inputs VLow-level input voltage, V
IL
0 0.8Differential input voltage, V
ID
–12 12Driver –60High-level output current, I
OH
mAReceiver –8Driver 60Low-level output current, I
OL
mAReceiver 8SN75HVD08 0 70Operating free-air temperature, T
A
°CSN65HVD08 –40 85
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R
L
= 60 Ω, 375 Ωon each output to|V
OD
| Driver differential output voltage magnitude 1.5 V
CC
V-7 V to 12 V, See Figure 1Change in magnitude of driver differential∆|V
OD
| R
L
= 54 Ω–0.2 0.2 Voutput voltagePeak-to-peak driver common-mode output Center of two 27- ΩloadV
OC(PP)
0.5 Vvoltage resistors, See Figure 2Positive-going receiver differential inputV
IT+
–10 mVvoltage threshold
Negative-going receiver differential inputV
IT-
–200 mVvoltage threshold
Receiver differential input voltage thresholdV
hys
35 mVhysteresis(V
IT+
- V
IT-
)V
OH
Receiver high-level output voltage I
OH
= -8 mA 2.4 VV
OL
Receiver low-level output voltage I
OL
= 8 mA 0.4 VDriver input, driver enable, and receiverI
IH
–100 100 µAenable high-level input currentDriver input, driver enable, and receiverI
IL
–100 100 µAenable low-level input currentI
OS
Driver short-circuit output current 7 V < V
O
< 12 V –265 265 mAV
I
= 12 V 130V
I
= -7 V –100I
I
Bus input current (disabled driver) µAV
I
= 12 V, V
CC
= 0 V 130V
I
= -7 V. V
CC
= 0 V –100Receiver enabled, driver
10disabled, no load
mADriver enabled, receiver
16I
CC
Supply current
disabled, no loadBoth disabled 5 µABoth enabled, no load 16 mA
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DRIVER SWITCHING CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
60 Ω ±1%
VOD
0 or 3 V
_
+–7 V < V(test) < 12 V
DE
VCC
A
B
D
375 Ω ±1%
375 Ω ±1%
VOC
27 Ω ± 1%
Input
A
B
VA
VB
VOC(PP) ∆VOC(SS)
VOC
27 Ω ± 1%
CL = 50 pF ±20%
DA
B
DE
VCC
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
CL Includes Fixture and
Instrumentation Capacitance
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PHL
Driver high-to-low propagation delay time 18 40t
PLH
Driver low-to-high propagation delay time 18 40t
r
Driver 10%-to-90% differential output rise time R
L
= 54 Ω, C
L
= 50 pF,See Figure 3 10 55 nst
f
Driver 90%-to-10% differential output fall time 10 55t
SK(P)
Driver differential output pulse skew, |t
PHL
- t
PLH
| 2.5Receiver enabled, See Figures 4 and 5 55 nst
en
Driver enable time
Receiver disabled, See Figures 4 and 5 6 µst
dis
Driver disable time Receiver enabled, See Figures 4 and 5 90 ns
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PHL
Receiver high-to-low propagation delay time 70t
PLH
Receiver low-to-high propagation delay time 70t
r
Receiver 10%-to-90% differential output rise time C
L
= 15 pF, See Figure 6 5 nst
f
Receiver 90%-to-10% differential output fall time 5t
SK(P)
Receiver differential output pulse skew, |t
PHL
- t
PLH
| 4.5Driver enabled, See Figure 7 15 nst
en
Receiver enable time
Driver disabled, See Figure 8 6 µst
dis
Receiver disable time Driver enabled, See Figure 7 20 ns
Figure 1. Driver V
OD
With Common-Mode Loading Test Circuit
Figure 2. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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VOD
RL = 54 Ω
± 1%
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
tPLH tPHL
1.5 V 1.5 V
3 V
≈ 2 V
≈ –2 V
90%
10%
0 V
VI
VOD
trtf
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
DA
B
DE
VCC
VI
Input
Generator 90% 0 V
10%
RL = 110 Ω
± 1%
Input
Generator 50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3 V S1
0.5 V
3 V
0 V
VOH
≈ 0 V
tPHZ
tPZH
1.5 V 1.5 V
VI
VO
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
DA
B
DE
VO
VI
2.3 V
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Driver Switching Test Circuit and Voltage Waveforms
Figure 4. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 5. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
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Input
Generator 50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
1.5 V
0 V
1.5 V 1.5 V
3 V
VOH
VOL
1.5 V
10%
1.5 V
tPLH tPHL
trtf
90%
VI
VO
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
A
B
RE
VI
R
0 V
90%
10%
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
RE
R
A
B
3 V
0 V or 3 V
VCC
1.5 V 1.5 V
tPZH tPHZ
1.5 V VOH –0.5 V
3 V
0 V
VOH
≈ 0 V
VO
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VI
DE
D1 kΩ ± 1%
VI
A
B
S1
D at 3 V
S1 to B
tPZL tPLZ
1.5 V VOL +0.5 V
≈ VCC
VOL
VO
D at 0 V
S1 to A
Input
Generator
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Receiver Switching Test Circuit and Voltage Waveforms
Figure 7. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
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Input
Generator 50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
RE
R
A
B
VCC
1.5 V
tPZH
1.5 V
3 V
0 V
VOH
GND
VI
VO
0 V or 1.5 V
1.5 V or 0 V CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VI
1 kΩ ± 1% A
B
S1
A at 1.5 V
B at 0 V
S1 to B
tPZL
1.5 V
VOL
VO
A at 0 V
B at 1.5 V
S1 to A
≈ VCC
DEVICE INFORMATION
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Receiver Enable Time From Standby (Driver Disabled)
Function Tables
DRIVER
INPUT ENABLE OUTPUTS
D DE A B
H H H LL H L HX L Z ZOpen H H L
RECEIVER
DIFFERENTIAL INPUTS ENABLE
(1)
OUTPUT
(1)
V
ID
= V
A
- V
B
RE R
V
ID
≤-0.2 V L L-0.2 V < V
ID
< -0.01 V L ?-0.01 V ≤V
ID
L HX H ZOpen Circuit L HShort Circuit L H
(1) H = high level; L = low level; Z = high impedance; X = irrelevant;? = indeterminate
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
9 V
1 kΩ
100 kΩ
Input
VCC
D and RE Inputs
9 V
1 kΩ
100 kΩ
Input
VCC
DE Input
16 V
16 V
100 kΩ
Input
A Input
16 V
16 V
100 kΩ
Input
B Input
16 V
16 V
VCC
A and B Outputs
9 V
VCC
R Output
5 ΩOutput
VCC
VCC
Output
180 kΩ36 kΩ
36 kΩ
180 kΩ
36 kΩ
36 kΩ
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
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TYPICAL CHARACTERISTICS
2.5
2
1.5
12.5 3 3.5 4 4.5
Differential Output Voltage – V
3
3.5
DIFFERENTIAL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
4
5 5.5 6
VCC – Supply V oltage – V
D and DE at VCC
RL = 54 ΩTA = –40°C
TA = 25°C
TA = 85°C
0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4
0
10
20
30
40
50
60
70
IO– Driver Output Current – mA
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
VCC – Supply V oltage – V
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
1
0.5
02.5 3.5 4.5
Logic Input Threshold Voltage – V
1.5
2
LOGIC INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
2.5
5.5 6.5
VCC – Supply V oltage – V
Positive Going
Negative Going
TA = 25°C
D, DE or RE input
40
60
80
100
120
0 2.5 5 7.5 10
Signaling Rate – Mbps
RMS SUPPLY CURRENT
vs
SIGNALING RATE
ICC– RMS Supply Current – mA
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
VCC = 5 V
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
Figure 9. Figure 10.
Figure 11. Figure 12.
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3.3V
5V
50
150
350
450
500
-7 -2 3 8 13
EnableTime − ns
V −
(TEST) Common-ModeVoltage − V
250
300
400
200
100
0
60 W
1%±
50 W
375 W1%±
-7V<V <12V
(TEST)
VOD
V (low)
OD
t (diff)
pZL
t (diff)
pZH
V
0or3V
375 W1%±
50%
0V
1.5V
D
Z
DE
Y
-1.5V
V (high)
OD
Input
Generator
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
ENABLE TIME
vsCOMMON-MODE VOLTAGE (SEE Figure 14 )
Figure 13.
Figure 14. Driver Enable Time From DE to V
OD
The time t
pZL
(x) is the measure from DE to V
OD
(x). V
OD
is valid when it is greater than 1.5 V.
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APPLICATION INFORMATION
OPTO-ISOLATED DATA BUSES
SUPPLY SOURCE IMPEDANCE
+
–
+
–
VS
RS
RS
IL
RL
VL = VS – 2RSIL
DC-to-DC
Converter
Opto
Isolators
DC-to-DC
Converter
Opto
Isolators
Local Power
Source
Rest of
Board
Local Power
Source
Rest of
Board
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
As electrical loads are physically distanced from their not be ignored and decoupling capacitance at thepower source, the effects of supply and return line load is required. The amount depends upon theimpedance and the resultant voltage drop must be magnitude and frequency of the load current changeaccounted. If the supply regulation at the load cannot but, if only powering the SN65HVD08, a 0.1 µFbe maintained to the circuit requirements, it forces ceramic capacitor is usually sufficient.the use of remote sensing, additional regulation atthe load, bigger or shorter cables, or a combinationof these. The SN65HVD08 eases this problem by
Long RS-485 circuits can create large ground loopsrelaxing the supply requirements to allow for more
and pick up common-mode noise voltages in excessvariation in the supply voltage over typical RS-485
of the range tolerated by standard RS-485 circuits. Atransceivers.
common remedy is to provide galvanic isolation ofthe data circuit from earth or local grounds.
Transformers, capacitors, or phototransistors mostIn the steady state, the voltage drop from the source
often provide isolation of the bus and the local node.to the load is simply the wire resistance times the
Transformers and capacitors require changingload current as modeled in Figure 15 .
signals to transfer the information over the isolationbarrier and phototransistors (opto-isolators) can passsteady-state signals. Each of these methods incursadditional costs and complexity, the former in clockencoding and decoding of the data stream and thelatter in requiring an isolated power supply.
Quite often, the cost of isolated power is repeated ateach node connected to the bus as shown inFigure 16 . The possibly lower-cost solution is togenerate this supply once within the system and thenFigure 15. Steady-State Circuit Model
distribute it along with the data line(s) as shown inFigure 17 .For example, if you were to provide 5-V ±5% supplypower to a remote circuit with a maximum loadrequirement of 0.1 A (one SN65HVD08), the voltageat the load would fall below the 4.5-V minimum ofmost 5-V circuits with as little as 5.8 m of 28-GAconductors. Table 1 summarizes wire resistance andthe length for 4.5 V and 3 V at the load with 0.1 A ofload current. The maximum lengths would scalelinearly for higher or lower load currents.
Table 1. Maximum Cable Lengths for MinimumLoad Voltages at 0.1 A Load
WIRE RESISTANCE 4.5 V LENGTH 3-v LENGTHSIZE AT 0.1 A AT 0.1 A
28 Gage 0.213 Ω/m 5.8 m 41.1 m24 Gage 0.079 Ω/m 15.8 m 110.7 m22 Gage 0.054 Ω/m 23.1 m 162.0 m20 Gage 0.034 Ω/m 36.8 m 257.3 m18 Gage 0.021 Ω/m 59.5 m 416.7 m
Figure 16. Isolated Power at Each NodeUnder dynamic load requirements, the distributedinductance and capacitance of the power lines may
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AN OPTO ALTERNATIVE
SN65HVD08
Local Power
Source
Rest of
Board
Opto
Isolators
Local Power
Source
Rest of
Board
Opto
Isolators
+5 V
–5 V
Bus
+5 V “1”
+5 V
DE/RE
Data
(I/O)
Side A Side B
Channel 1
Channel 2
D2A GAVSB D2B
D1B
GA
D1A VSA
R/T1A R/T1B
R/T2B
R/T2A
DA
DE
RE
R
B
SN65HVD08
ISO150
SN75HVD08 , SN65HVD08
SLLS550C – NOVEMBER 2002 – REVISED JULY 2006
The features of the SN65HVD08 are particularlygood for the application of Figure 17 . Due to addedsupply source impedance, the low quiescent currentrequirements and wide supply voltage toleranceallow for the poorer load regulation.
The ISO150 is a two-channel, galvanically isolateddata coupler capable of data rates of 80 Mbps. Eachchannel can be individually programmed to transmitdata in either direction.
Data is transmitted across the isolation barrier bycoupling complementary pulses through high-voltage0.4-pF capacitors. Receiver circuitry restores thepulses to standard logic levels. Differential signaltransmission rejects isolation-mode voltagetransients up to 1.6 kV/ms.
ISO150 avoids the problems commonly associatedwith opto-couplers. Optically-isolated couplersFigure 17. Distribution of Isolated Power
require high current pulses and allowance must bemade for LED aging. The ISO150's Bi-CMOScircuitry operates at 25 mW per channel with supplyvoltage range matching that of the SN65HVD08 of 3V to 5.5 V.
Figure 18 shows a typical circuit.
Figure 18. Isolated RS-485 Interface
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65HVD08D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD08DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD08DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD08DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD08P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65HVD08PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD08D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD08DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD08DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD08DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75HVD08P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75HVD08PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVD08DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75HVD08DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD08DR SOIC D 8 2500 340.5 338.1 20.6
SN75HVD08DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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