© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 7
1Publication Order Number:
MC14532B/D
MC14532B
8-Bit Priority Encoder
The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority
encoder is to provide a binary address for the active input with the
highest priority. Eight data inputs (D0 thru D7) and an enable input
(Ein) are provided. Five outputs are available, three are address outputs
(Q0 thru Q2), one group select (GS) and one enable output (Eout).
Features
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating Symbol Value Unit
DC Supply Voltage Range VDD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
Vin,
Vout
−0.5 to VDD + 0.5 V
Input or Output Current
(DC or Transient) per Pin
Iin, Iout ±10 mA
Power Dissipation, per Package (Note 1) PD500 mW
Ambient Temperature Range TA−55 to +125 °C
Storage Temperature Range Tstg −65 to +150 °C
Lead Temperature (8 Sec Soldering) TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
TRUTH TABLE
Input Output
Ein D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 Eout
0 X X X X X X X X 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 1
1 1 X X X X X X X 1 1 1 1 0
1 0 1 X X X X X X 1 1 1 0 0
1 0 0 1 X X X X X 1 1 0 1 0
1 0 0 0 1 X X X X 1 1 0 0 0
1 0 0 0 0 1 X X X 1 0 1 1 0
1 0 0 0 0 0 1 X X 1 0 1 0 0
1 0 0 0 0 0 0 1 X 1 0 0 1 0
1 0 0 0 0 0 0 0 1 1 0 0 0 0
X = Don’t Care
SOIC−16
D SUFFIX
CASE 751B
MARKING
DIAGRAMS
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See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G = Pb−Free Package
14532BG
AWLYWW
PDIP−16
P SUFFIX
CASE 648
1
1
MC14532BCP
AWLYYWWG
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
D2
D3
GS
Eout
VDD
Q0
D0
D1
D7
D6
D5
D4
VSS
Q1
Q2
Ein
PIN ASSIGNMENT
1
1
MC14532B
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2
ORDERING INFORMATION
Device Package Shipping†
MC14532BCPG PDIP−16
(Pb−Free) 500 Units / Rail
MC14532BDG SOIC−16
(Pb−Free) 48 Units / Rail
MC14532BDR2G SOIC−16
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min
Typ
(Note 2) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
“1” Level
Vin = 0 or VDD
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIL 5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
VIH 5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
–3.0
– 0.64
–1.6
– 4.2
−
−
−
−
–2.4
– 0.51
–1.3
–3.4
–4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
–1.7
– 0.36
–0.9
–2.4
−
−
−
−
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current Iin 15 −±0.1 −±0.00001 ±0.1 −±1.0 mAdc
Input Capacitance
(Vin = 0)
Cin − − − − 5.0 7.5 − − pF
Quiescent Current
(Per Package)
IDD 5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (1.74 mA/kHz) f + IDD
IT = (3.65 mA/kHz) f + IDD
IT = (5.73 mA/kHz) f + IDD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.
MC14532B
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3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) (Note 5)
Characteristic Symbol VDD Min Typ
(Note 6)
Max Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Propagation Delay Time — Ein to Eout
tPLH, tPHL = (1.7 ns/pF) CL + 120 ns
tPLH, tPHL = (0.66 ns/pF) CL + 77 ns
tPLH, tPHL = (0.5 ns/pF) CL + 55 ns
tPLH,
tPHL 5.0
10
15
−
−
−
205
110
80
410
220
160
ns
Propagation Delay Time — Ein to GS
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL 57 ns
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns
tPLH,
tPHL 5.0
10
15
−
−
−
175
90
65
350
180
130
ns
Propagation Delay Time — Ein to Qn
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns
tPLH, tPHL = (0.66 ns/pF) CL + 107 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPHL,
tPLH 5.0
10
15
−
−
−
280
140
100
560
280
200
ns
Propagation Delay Time — Dn to Qn
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns
tPLH, tPHL = (0.66 ns/pF) CL + 137 ns
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns
tPLH,
tPHL 5.0
10
15
−
−
−
300
170
110
600
340
220
ns
Propagation Delay Time — Dn to GS
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns
tPLH, tPHL = (0.66 ns/pF) CL + 107 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL 5.0
10
15
−
−
−
280
140
100
560
280
200
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Output
Under
Test
VGS = VDD
VDS = Vout
Sink Current
VGS = – VDD
VDS = Vout – VDD
Source Current
D0 thru D7 Ein D0 thru D6 D7 Ein
Eout
Q0
Q1
Q2
GS
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Figure 1. Typical Sink and Source
Current Characteristics Figure 2. Typical Power Dissipation Test Circuit
SWITCH
MATRIX
EXTERNAL
POWER
SUPPLY
ID
Ein
D0
D1
D2
D3
D4
D5
D6
D7
GS
Q2
Q1
Q0
Eout
Vout
PULSE
GENERATOR
(fo)
Ein
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
ID
CL
CL
CL
CL
CL
GS
Q2
Q1
Q0
Eout
0.01 mF
500 mF
MC14532B
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4
Figure 3. AC Test Circuit and Waveforms
PROGRAMMABLE
PULSE
GENERATOR
Ein
D0
D1
D2
D3
D4
D5
D6
D7 GS
Q2
Q1
Q0
Eout
VDD
VSS
CL
CL
CL
CL
CL
NOTE: Input rise and fall times are 20 ns
50%
50%
50%
50%
50%
50%
50%
50%
90%
50%
10%
90%
50%
10%
90%
50%
10%
90%
50%
10%
tPHL
tPHL
tPHL
tPHL
tPHL
tTHL
tTHL
tTHL
tTHL
tPLH
tPLH
tPLH
tPLH
tPLH
tPLH
tPLH
tTLH
tTLH
tTLH
tTLH
tTLH
tPHL
tPLH
tTHL
90%
50%
10%
tPLH
tPHL tPHL tPHL
D0
D1
D2
D3
D4
D5
D6
D7
Ein
Eout
GS
Q0
Q1
Q2
10
11
12
13
1
2
3
4
5
15
14
9
7
6
PIN
NO.
50%
MC14532B
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5
LOGIC EQUATIONS
Eout = Ein D0 D1 D2 D3 D4 D5 D6 D7
10
11
12
13
1
2
3
4
5
D0
D1
D2
D3
D4
D5
D6
D7
Ein
9
7
6
14
15
Q0
Q1
Q2
GS
Eout
Q0 = Ein (D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7)
Q1 = Ein (D2 D4 D5 + D3 D4 D5 + D6 + D7)
Q2 = Ein (D4 + D5 + D6 + D7)
GS = Ein (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)
Figure 4. Logic Diagram
(Positive Logic)
MC14532B
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6
Figure 5. Two MC14532B’s Cascaded for 4−Bit Output
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Q1 Q0Q2 Q1 Q0Q2
Q1 Q0Q2Q3
GS
3/4 MC14071B
VDD Ein Eout Ein Eout Eout = “1"
WITH Din = “0"
Figure 6. Digital to Analog and Analog to Digital Converter
DIGITAL TO ANALOG CONVERSION
The digital eight−bit word to be converted is applied to the
inputs of the MC14512 with the most significant bit at X7
and the least significant bit at X0. A clock input of up to
2.5 MHz (at VDD = 10 V) is applied to the MC14520B.
A compromise between Ibias for the MC1710 and DR
between N and P−channel outputs gives a value of R of
33 kW. In order to filter out the switching frequencies, RC
should be about 1.0 ms (if R = 33 kW, C [ 0.03 mF). The
analog 3.0 dB bandwidth would then be dc to 1.0 kHz.
ANALOG TO DIGITAL CONVERSION
An analog signal is applied to the analog input of the
MC1710. A digital eight−bit word known to represent a di-
gitized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is incre-
mented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.
ANALOG
OUTPUT
CLOCK
INPUT
ANALOG
INPUT
VDD
X7 X6 X5 X4 X3 X2 X1 X0
MC14512
A
B
C
MC1710 R
C
Z
VDD VSS
Ein
D0 D1 D2 D3 D4 D5 D6 D7
Q2 Q0Q1
STOP
WORD
INCREMENTATION
Q2 Q4Q3Q1 Q2 Q4Q3Q1
CE RCE R
1/2 MC14520B 1/2 MC14520B
DIGITAL INPUT/OUTPUT
8-BIT WORD
TO BE CONVERTED
MC14532B
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PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
CASE 648−08
ISSUE T
MC14532B
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8
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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