2100 MHz to 2600 MHz Rx Mixer with
Integrated Fractional-N PLL and VCO
ADRF6603
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
FEATURES
Rx mixer with integrated fractional-N PLL
RF input frequency range: 1100 MHz to 3200 MHz
Internal LO frequency range: 2100 MHz to 2600 MHz
Input P1dB: 14.8 dBm
Input IP3: 28.5 dBm
IIP3 optimization via external pin
SSB noise figure
IP3SET pin open: 14.3 dB
IP3SET pin at 3.3 V: 15.6 dB
Voltage conversion gain: 6.7 dB
Matched 200 Ω IF output impedance
IF 3 dB bandwidth: 500 MHz
Programmable via 3-wire SPI interface
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Cellular base stations
GENERAL DESCRIPTION
The ADRF6603 is a high dynamic range active mixer with
integrated phase-locked loop (PLL) and voltage controlled
oscillator (VCO). The PLL/synthesizer uses a fractional-N
PLL to generate a fLO input to the mixer. The reference input
can be divided or multiplied and then applied to the PLL phase
frequency detector (PFD).
The PLL can support input reference frequencies from 12 MHz
to 160 MHz. The PFD output controls a charge pump whose
output drives an off-chip loop filter.
The loop filter output is then applied to an integrated VCO. The
VCO output at 2 × fLO is applied to an LO divider, as well as to a
programmable PLL divider. The programmable PLL divider is
controlled by a sigma-delta (Σ-) modulator (SDM). The modulus
of the SDM can be programmed from 1 to 2047.
The active mixer converts the single-ended 50 RF input to
a 200 Ω differential IF output. The IF output can operate up
to 500 MHz.
The ADRF6603 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP with an exposed paddle. Performance is
specified over the −40°C to +85°C temperature range.
Table 1.
Part No.
Internal LO
Range
±3 dB RFIN
Balun Range
±1 dB RFIN
Balun Range
ADRF6601 750 MHz 300 MHz 450 MHz
1160 MHz 2500 MHz 1600 MHz
ADRF6602 1550 MHz 1000 MHz 1350 MHz
2150 MHz 3100 MHz 2750 MHz
ADRF6603 2100 MHz 1100 MHz 1450 MHz
2600 MHz 3200 MHz 2850 MHz
ADRF6604 2500 MHz 1200 MHz 1600 MHz
2900 MHz 3600 MHz 3200 MHz
FUNCTIONAL BLOCK DIAGRAM
MUX
RSET CP VTUNE
LODRV_EN
LON
LOP
IP3SET
V
CC1
2:1
MUX
VCO
CORE
RFIN
TEMP
SENSOR
DECLVCO
DECL2P5
DECL3P3
IFP
BUFFER
BUFFER
IFN
V
CC2
V
CC_LO
V
CC_MIX
V
CC_V2I
V
CC_LO NC
–
+
CHARGE P UMP
250µA,
500µA (DEFAULT ),
750µA,
1000µA
PRESCALER
÷2
LE
CLK SPI
INTERFACE
DATA
MUXOUT
NC
3.3V
LDO
2.5V
LDO
VCO
LDO
DIV
BY
2, 1
PLL_EN
REF_IN
GND
ADRF6603
INT E RNAL LO RANGE
2100MHz TO 2600 M Hz
34
191839
3
54
8
6
14
13
12
16
38
37
36
711 15 20 21 23 24 25 28 30 31 35
32 33
2
9
40
26
29
271710122
PHASE
FREQUENCY
DETECTOR
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG MODULUS INTEGER
REG
N COUNT E R
21 TO 123
×2
÷2
÷4
08547-001
Figure 1.
ADRF6603
Rev. A | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
RF Specifications .......................................................................... 3
Synthesizer/PLL Specifications ................................................... 4
Logic Input and Power Specifications ....................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
RF Frequency Sweep .................................................................... 9
IF Frequency Sweep ................................................................... 10
Spurious Performance................................................................ 15
Register Structure ........................................................................... 16
Register 0—Integer Divide Control (Default: 0x0001C0)..... 16
Register 1—Modulus Divide Control (Default: 0x003001) .. 16
Register 2—Fractional Divide Control
(Default: 0x001802) .................................................................... 17
Register 3—Σ-Δ Modulator Dither Control
(Default: 0x10000B) ................................................................... 17
Register 4—PLL Charge Pump, PFD, and Reference Path
Control (Default: 0x0AA7E4) ................................................... 18
Register 5—PLL Enable and LO Path Control
(Default: 0x0000E5) ................................................................... 19
Register 6—VCO Control and VCO Enable
(Default: 0x1E2106) ................................................................... 19
Register 7—Mixer Bias Enable and External VCO Enable
(Default: 0x000007) .................................................................... 19
Theory of Operation ...................................................................... 20
Programming the ADRF6603 ................................................... 20
Initialization Sequence .............................................................. 20
LO Selection Logic ..................................................................... 21
Applications Information .............................................................. 22
Basic Connections for Operation ............................................. 22
AC Test Fixture ............................................................................... 23
Evaluation Board ............................................................................ 24
Evaluation Board Control Software ......................................... 24
Schematic and Artwork ............................................................. 26
Evaluation Board Configuration Options ............................... 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
11/10—Rev. 0 to Rev. A
Changes to Features and General Description ............................. 1
Changes to Table 1 ............................................................................ 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 and Table 4 ....................................................... 4
Changes to Table 6 ............................................................................ 6
Change to Table 7, Pin 36 Description .......................................... 8
Changes to Typical Performance Characteristics Section ........... 9
Added Spurious Performance Section ......................................... 15
Changes to Programming the ADRF6603 Section .................... 20
Changes to Figure 46 ...................................................................... 22
Added AC Test Fixture Section and Figure 47;
Renumbered Sequentially ............................................................. 23
Changes to Evaluation Board Control Software Section;
Changes to Figure 48 ...................................................................... 24
Changes to Figure 49 ...................................................................... 25
Changes to Figure 50 ...................................................................... 26
1/10—Revision 0: Initial Version
ADRF6603
Rev. A | Page 3 of 32
SPECIFICATIONS
RF SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; fREF = 153.6 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized
using CDAC (0x1) and IP3SET (3.3 V), unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
INTERNAL LO FREQUENCY RANGE 2100 2600 MHz
RF INPUT FREQUENCY RANGE ±3 dB RF input range 1100 3200 MHz
RF INPUT AT 2140 MHz
Input Return Loss Relative to 50 Ω (can be improved with external match) <(−20) dB
Input P1dB 14.9 dBm
Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 55.3 dBm
Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 29.3 dBm
Single-Side Band Noise Figure IP3SET = 3.3 V 15.6 dB
IP3SET = open 14.4 dB
LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −43 dBm
RF INPUT AT 2400 MHz
Input Return Loss Relative to 50 Ω (can be improved with external match) −16 dB
Input P1dB 14.9 dBm
Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 55.1 dBm
Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 28.6 dBm
Single-Side Band Noise Figure IP3SET = 3.3 V 15.8 dB
IP3SET = open 14.2 dB
LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −43 dBm
RF INPUT AT 2650 MHz
Input Return Loss Relative to 50 Ω (can be improved with external match) −11 dB
Input P1dB 14.7 dBm
Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 52.1 dBm
Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 28.1 dBm
Single-Side Band Noise Figure IP3SET = 3.3 V 15.8 dB
IP3SET = open 14.5 dB
LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −44 dBm
IF OUTPUT
Voltage Conversion Gain Differential 200 Ω load 6.7 dB
IF Bandwidth Small signal 3 dB bandwidth 500 MHz
Output Common-Mode Voltage External pull-up balun or inductors required 5 V
Gain Flatness Over frequency range, any 5 MHz/50 MHz 0.2/1.0 dB
Gain Variation Over full temperature range 1.2 dB
Output Swing Differential 200 Ω load 2 V p-p
Differential Output Return Loss Measured through 4:1 balun −15 dB
LO INPUT/OUTPUT (LOP, LON) Externally applied 1× LO input, internal PLL disabled
Frequency Range 250 6000 MHz
Output Level (LO as Output) 1× LO into a 50 Ω load, LO output buffer enabled −7 dBm
Input Level (LO as Input) −6 0 +6 dBm
Input Impedance 50 Ω
ADRF6603
Rev. A | Page 4 of 32
SYNTHESIZER/PLL SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; fREF = 153.6 MHz; fREF power = 4 dBm; fPFD = 38.4 MHz; high-side LO injection;
fIF = 140 MHz; IIP3 optimized using CDAC (0x1) and IP3SET (3.3 V), unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1× LO
Frequency Range Internally generated LO 2100 2600 MHz
Figure of Merit1 P
REF_IN = 0 dBm −222 dBc/Hz/Hz
Reference Spurs fPFD = 38.4 MHz
f
PFD/4 −107 dBc
f
PFD −82 dBc
>fPFD −85 dBc
PHASE NOISE fLO = 2100 MHz to 2600 MHz, fPFD = 38.4 MHz
1 kHz to 10 kHz offset −88 dBc/Hz
100 kHz offset −99.5 dBc/Hz
500 kHz offset −120 dBc/Hz
1 MHz offset −128 dBc/Hz
5 MHz offset −142 dBc/Hz
10 MHz offset −148 dBc/Hz
20 MHz offset −150 dBc/Hz
Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.42 °rms
PFD Frequency 20 40 MHz
REFERENCE CHARACTERISTICS REF_IN, MUXOUT pins
REF_IN Input Frequency 12 160 MHz
REF_IN Input Capacitance 4 pF
MUXOUT Output Level VOL (lock detect output selected) 0.25 V
V
OH (lock detect output selected) 2.7 V
MUXOUT Duty Cycle 50 %
CHARGE PUMP
Pump Current Programmable to 250 μA, 500 μA, 750 μA, 1 mA 500 μA
Output Compliance Range 1 2.8 V
1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10Log10(fPFD) – 20Log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz,
and fREF power = 10 dBm (500 V/μs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.
LOGIC INPUT AND POWER SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; fREF = 153.6 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized
using CDAC (0x1) and IP3SET (3.3 V), unless otherwise noted.
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS CLK, DATA, LE
Input High Voltage, VINH 1.4 3.3 V
Input Low Voltage, VINL 0 0.7 V
Input Current, IINH/IINL 0.1 μA
Input Capacitance, CIN 5 pF
POWER SUPPLIES VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins
Voltage Range 4.75 5 5.25 V
Supply Current PLL only 97 mA
External LO mode (internal PLL disabled, LO output buffer off, IP3SET pin = 3.3 V) 164 mA
Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on) 274 mA
Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off) 261 mA
Power-down mode 30 mA
ADRF6603
Rev. A | Page 5 of 32
TIMING CHARACTERISTICS
VCC2 = 5 V ± 5%.
Table 5.
Parameter Limit Unit Description
t1 20 ns min LE setup time
t2 10 ns min DATA-to-CLK setup time
t3 10 ns min DATA-to-CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK-to-LE setup time
t7 20 ns min LE pulse width
Timing Diagram
CLK
DATA
LE
DB23 (MSB) DB22 DB2 DB1
(CONTROL BIT C2)(CONTROL BIT C3) DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
08547-002
Figure 2. Timing Diagram
ADRF6603
Rev. A | Page 6 of 32
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Supply Voltage, VCC1, VCC2, VCC_LO,
VCC_MIX, VCC_V2I
−0.5 V to +5.5 V
Digital I/O, CLK, DATA, LE, LODRV_EN,
PLL_EN
−0.3 V to +3.6 V
VTUNE 0 V to 3.3 V
IFP, IFN −0.3 V to VCC_V2I + 0.3 V
RFIN 16 dBm
LOP, LON, REF_IN 13 dBm
θJA (Exposed Paddle Soldered Down) 35°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADRF6603
Rev. A | Page 7 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PI N 1
INDICATOR
NOTES
1. NC = NO CO NNE CT.
2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A
LO W IMPEDANCE GROUND PLANE.
1VCC1 2DECL3P3 3CP 4
GND 5
R
SET
6
REF_IN 7
GND 8
MUXOUT 9
DECL2P5 10
VCC2
23 GND
24 GND
25 GND
26 RF
IN
27 VCC_V2I
28 GND
29 IP3SET
30 GND
22 VCC_MIX
21 GND
11
GND 12
DATA 13
CLK
15
GND
17
VCC_LO 16
PLL_EN
18
IFP 19
IFN 20
GND
14
LE
33 NC
34 VCC_LO
35 GND
36 LODRV_EN
37 LON
38 LOP
39 VTUNE
40 DECLVCO
32 NC
31 GND
TOP VIEW
(No t to Scale)
ADRF6603
08547-003
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCC1
Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.
2 DECL3P3 Decoupling Node for 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
3 CP Charge Pump Output Pin. Connect to VTUNE through the loop filter.
4, 7, 11, 15, 20,
21, 23, 24, 25,
28, 30, 31, 35
GND Ground. Connect these pins to a low impedance ground plane.
5 RSET Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using
Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In
this mode, no external RSET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL)
can be externally adjusted according to the following equation:
37.8
4.217 −
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛×
=
NOMINAL
CP
SET I
I
R
6 REF_IN
Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dc-
biased and should be ac-coupled.
8 MUXOUT
Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect
signal. The output is selected by programming the appropriate register.
9 DECL2P5 Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
10 VCC2
Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.
12 DATA Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits.
13 CLK
Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
14 LE
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the
eight registers. The relevant latch is selected by the three control bits of the 24-bit word.
16 PLL_EN
PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is
automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the
internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be
used to switch modes.
ADRF6603
Rev. A | Page 8 of 32
Pin No. Mnemonic Description
17, 34 VCC_LO Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.
18, 19 IFP, IFN Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes.
22 VCC_MIX
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.
26 RFIN RF Input (Single-Ended, 50 Ω).
27 VCC_V2I
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.
29 IP3SET Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open.
32, 33 NC No Connection.
36 LODRV_EN
LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON
pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin
is set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN
pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. External LO drive frequency
must be 1× LO. This pin has an internal 100 kΩ pull down resistor.
37, 38 LON, LOP Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO
generation is disabled, an external 1× LO can be applied to these pins.
39 VTUNE
VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on
this pin is 1.5 V to 2.5 V.
40 DECLVCO Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground.
EPAD Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
ADRF6603
Rev. A | Page 9 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
RF FREQUENCY SWEEP
CDAC = 0x1, internally generated high-side LO, RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted.
5
–5
–4
–3
–2
–1
0
1
2
3
4
1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460
GAIN (dB)
RF F REQUENCY (MHz)
IP3SET = O PEN
IP3SET = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-104
Figure 4. Gain vs. RF Frequency
90
80
70
60
50
40
30
1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460
INPUT IP2 (dBm)
RF F REQUE NCY ( MHz)
IP3SET = OPEN
IP3SET = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-105
Figure 5. Input IP2 vs. RF Frequency
20
18
16
14
12
10
8
6
4
2
0
1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460
NOI S E FIGURE (d B)
RF F REQUE NCY ( MHz)
IP3SET = OPEN
IP3SET = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-106
Figure 6. Noise Figure vs. RF Frequency
40
35
30
25
20
15
1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460
INPUT IP3 (dBm)
RF F REQUE NCY ( MHz)
IP3SET = OPEN
IP3SET = 3.3V TA = –40°C
TA = +25°C
TA = +85°C
08547-107
Figure 7. Input IP3 vs. RF Frequency
20
19
18
17
16
15
14
13
12
11
10
1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460
INPUT P1dB (dBm)
RF F REQ UE NCY (M Hz)
IP3SET = O P EN
IP3SET = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-108
Figure 8. Input P1dB vs. RF Frequency
ADRF6603
Rev. A | Page 10 of 32
IF FREQUENCY SWEEP
CDAC = 0x1, internally generated swept low-side LO, fRF = 1960 MHz, RFIN = −5 dBm, unless otherwise noted.
5
–5
–4
–3
–2
–1
0
1
2
3
4
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
GAIN (dB)
IP3SET = O P EN
IP3SET = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
IF FREQUEN CY (MHz)
08547-109
Figure 9. Gain vs. IF Frequency
90
80
70
60
50
40
3025 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
INPUT IP2 (dBm)
IP3SET = O P EN
IP3SET = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
IF FREQUEN CY (MHz)
08547-110
Figure 10. Input IP2 vs. IF Frequency, RFIN = −5 dBm
20
18
16
14
12
10
8
6
4
2
025 4003753503253002752502252001751501257550 100
NOI S E F I GURE (d B)
IF FRE QUENCY ( MHz)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
IP3SET = OPEN
IP 3 S E T = 3.3V
08547-111
Figure 11. Noise Figure vs. IF Frequency
45
40
35
30
25
20
15
10
525 4003753503253002752502252001751501257550 100
INPUT IP3 (dBm)
IF FRE QUENCY ( MHz)
IP3SET = OPEN
IP 3 S E T = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-112
Figure 12. Input IP3 vs. IF Frequency, RFIN = −5 dBm
25 4003753503253002752502252001751501257550 100
20
18
16
14
12
10
8
6
4
2
0
INPUT P1dB (dBm)
IF FRE QUENCY ( MHz)
IP3SET = OPEN
IP 3 S E T = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-113
Figure 13. Input P1dB vs. IF Frequency
ADRF6603
Rev. A | Page 11 of 32
0
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
LO-TO - IF F EEDTHRO UGH ( dBm)
LO FREQ UE NCY (MHz )
IP3SET = OPEN
IP3SET = 3.3V TA = –40°C
TA = +25°C
TA = +85°C
08547-114
Figure 14. LO-to-IF Feedthrough vs. LO Frequency,
LO Output Turned Off, CDAC = 0x0
–
20
–90
–85
–80
–75
–70
–65
–55
–60
–50
–45
–40
–35
–30
–25
2100 26002500240023002200
LO-TO -RF LEA KAGE ( dBm)
LO FREQ UE NCY (MHz )
IP3SET = OPEN
IP3SE T = 3.3V TA = –40° C
TA = +25°C
TA = +85°C
08547-115
Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off
0
–45
–35
–40
–30
–25
–20
–15
–10
–5
1900 280027002600250024002300220021002000
RETURN LO S S ( dB)
RF F REQUENCY ( MHz )
08547-116
Figure 16. RF Input Return Loss vs. RF Frequency
0
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
1900 280027002600250024002300220021002000
RETURN LO S S ( dB)
LO FREQ UENCY (MHz)
08547-117
Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun)
350
0
50
100
150
200
250
300
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
50 500450400350300250200150100
RESI S T ANCE ( Ω)
CAPACITANCE (p F)
IF F R E Q UENC Y (M Hz )
CAPACITANCE
RESISTANCE
08547-118
Figure 18. IF Differential Output Impedance (R Parallel C Equivalent)
35
10
15
20
25
30
–60 –50 –40 –30 –20 –10 0
NOISE FIGURE ( dB)
CW BLOCKER LE VE L (dBm)
IP3SET = OPEN
IP3SET = 3.3V
08547-119
Figure 19. SSB Noise Figure vs. 5 MHz Offset Blocker Level,
LO Frequency = 2105 MHz, RF Frequency = 1965 MHz
ADRF6603
Rev. A | Page 12 of 32
0
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
1900 280027002600250024002300220021002000
RF- TO - IF ISOL ATI ON (dB)
LO FRE QUENCY ( MHz)
IP3SET = OP EN
IP 3SET = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-120
Figure 20. RF-to-IF Isolation vs. RF Frequency, High-Side LO, IF = 140 MHz,
LO Output Turned Off
–
2
–12
–3
–4
–5
–6
–7
–8
–9
–11
–10
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
LO OUTP UT AMP LI TUDE ( dBm)
LO FRE QUENCY ( MHz)
IP3SET = OP EN
IP 3SET = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-121
Figure 21. LO Output Amplitude vs. LO Frequency
20
15
10
5
0
–5
–10
–15
–20 0 50 100 150 200 250
FREQUENCY DEVIATIO N FRO M 2 140M Hz (MHz)
TIME (µs)
08547-122
Figure 22. Frequency Deviation from 2140 MHz vs Time
(Demonstrates LO Frequency Settling Time from 2150 MHz to 2140 MHz)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2100 2200 2300 2400 2500 2600
VTUNE VO LT AGE (V)
LO FRE QUENCY ( MHz)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-123
Figure 23. VTUNE vs. LO Frequency
350
100
150
200
250
300
2100 2600255025002450240023502300225022002150
SUPP LY CURRENT (mA)
LO FRE QUENCY ( MHz)
IP3SET = OP EN
IP 3SET = 3.3V T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-124
Figure 24. Supply Current vs. LO Frequency
2.0
2.1
2.2
2.3
2.4
2.5
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
–55 –35 –15 5 25 45 65 85 105
VPTAT VOLTAGE (V)
TE M PERATURE (°C)
IP3SET = OPEN
IP 3 S ET = 3.3V
08547-125
Figure 25. VPTAT Voltage vs. Temperature (IP3SET = Optimized, Open)
ADRF6603
Rev. A | Page 13 of 32
Complementary cumulative distribution function (CCDF), fRF = 2140 MHz, fIF = 140 MHz.
100
0
10
20
30
40
50
60
70
80
90
–1.0 –0.5 0 0.5 1.0 1.5 2.0
DIS TRI BU T IO N P E RCE NTAG E ( %)
GAIN (dB)
IP3SET = OPEN
IP3SET = 3.3V
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-126
Figure 26. Gain
100
0
10
20
30
40
50
60
70
80
90
40 45 50 55 60 65 70
DISTRIBUTION PERCENTAGE ( %)
INPUT IP2 (dBm)
IP3SET = OPEN
IP 3SE T = 3.3V
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-127
Figure 27. Input IP2
100
0
10
20
30
40
50
60
70
80
90
11 12 13 14 15 16 17 18
DISTRIBUTION PERCENTAGE ( %)
NOI SE FIGURE (dB)
IP3SET = OPEN
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08547-128
Figure 28. Noise Figure
100
0
10
20
30
40
50
60
70
80
90
20 22 24 26 28 30 32 34 36
DISTRIBUTION PERCENTAGE ( %)
INPUT IP3 (dBm)
IP3SET = OPEN
IP 3SE T = 3.3V
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08547-129
Figure 29. Input IP3
100
0
10
20
30
40
50
60
70
80
90
9 10111213141516 1817
DISTRIBUTION PERCENTAGE ( %)
INPUT P1dB (dBm)
IP3SET = OPEN
IP 3S E T = 3.3V
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08547-130
Figure 30. Input P1dB
100
0
10
20
30
40
50
60
70
80
90
–55 –53 –51 –49 –47 –45 –43 –41 –39 –37 –35
DISTRI BUTI ON PERCENTAGE ( %)
LO FEEDT HROUGH (dBm)
IP3SET = OPEN
IP 3 S ET = 3.3V
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-131
Figure 31. LO Feedthrough to IF, LO Output Turned Off
ADRF6603
Rev. A | Page 14 of 32
Measured at IF output, CDAC = 0x1, IP3SET = open, internally generated high-side LO, fREF = 153.6 MHz, fPFD = 38.4 MHz,
RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted.
–
80
–160
–150
–140
–130
–120
–110
–100
–90
1k 10k 100k 1M 10M 100M
PHASE NOISE (dBc/Hz)
OFF SET FREQUENCY (Hz)
LO FREQUENCY = 2595.2MHz
LO FREQUENCY = 2115.2MHz
TA = –40°C
TA = +25°C
TA = +85°C
08547-132
Figure 32. Phase Noise vs. Offset Frequency
–
75
–110
–105
–100
–95
–90
–85
–80
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
SPURRS LEVEL (d Bc)
LO FRE QUENCY ( MHz)
2× PFD FREQUE NCY
4× PFD FREQUE NCY T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-133
Figure 33. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD)
–
75
–110
–105
–100
–95
–90
–85
–80
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
SPURRS LEVEL (d Bc)
LO FRE QUENCY ( MHz)
3× PFD FREQUE NCY
1× PFD FREQUE NCY T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
0.25× PF D FRE QUENCY
08547-134
Figure 34. PLL Reference Spurs vs. LO Frequency (0.25× PFD, 1× PFD, and 3× PFD)
1.0
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.1
0.2
2100 2600255025002450240023502300225022002150
INTEGRATED PHASE NOISE (°rms)
LO FRE QUENCY ( MHz)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
08547-135
Figure 35. Integrated Phase Noise vs. LO Frequency
–
80
–90
–100
–110
–120
–130
–140
–150
–160
PHASE NOISE ( dBc/Hz)
LO FRE QUENCY ( MHz)
OFFSET = 5MHz
OFF SET = 100kHz
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
2100 2600255025002450240023502300225022002150
OFFSET = 1kHz
08547-136
Figure 36. Phase Noise vs. LO Frequency (1 kHz, 100 kHz, and 5 MHz Steps)
–
80
–90
–100
–110
–120
–130
–140
–150
–160
PHASE NOISE (d Bc/Hz)
LO FRE QUENCY ( MHz)
OFFSET = 1MHz
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
2100 2600255025002450240023502300225022002150
OF FSE T = 10kHz
08547-137
Figure 37. Phase Noise vs. LO Frequency (10 kHz, 1 MHz Steps)
ADRF6603
Rev. A | Page 15 of 32
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spurious
products were measured in dB relative to the carrier (dBc) from the IF output power level. All spurious components greater than −125 dBc
are shown.
LO = 2280 MHz, RF = 2140 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm.
M
0 1 2 3 4
0 −114.35 −45.19 −36.94
1 −20.79 0.0 −67.43 −52.11
2 −58.20 −61.95 −78.15 −85.93 −93.10
3 −71.79 −91.89 −67.46 −105.88
4 −107.79 −110.27 −107.87
5 −107.88 −112.41
6 −107.71
N
7 −108.62
LO = 2540 MHz, RF = 2400 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm.
M
0 1 2 3 4
0 −113.65 −47.04 −36.36
1 −18.91 0.0 −65.01 −56.24
2 −59.08 −60.49 −69.27 −89.85 −94.25
3 −77.54 −89.56 −68.39 −109.30
4 −108.79 −110.65 −111.94
5 −108.85 −111.54
6 −108.89
N
7
LO = 2650 MHz, RF = 2510 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm.
M
0 1 2 3 4
0 −111.38 −46.57 −36.03
1 −17.70 0.0 −65.70 −54.37
2 −58.49 −75.49 −72.27 −71.05 −95.32
3 −81.35 −89.18 −68.23 −103.38
4 −106.13 −106.74 −112.72
5 −107.26 −105.45
6 −110.74
N
7
ADRF6603
Rev. A | Page 16 of 32
REGISTER STRUCTURE
This section provides the register maps for the ADRF6603. The three LSBs determine the register that is programmed.
REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)
DIVIDE
MODE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000000000000DMID6ID5ID4ID3ID2ID1ID0C3(0)C2(0)C1(0)
DM
0
1
ID6 ID5 ID4 ID3 ID2 ID1 ID0
0010101
0010110
0010111
0011000
... ... ... ... ... ... ...
... ... ... ... ... ... ...
0111000
... ... ... ... ... ... ...
... ... ... ... ... ... ...
1110111
1111000
1111001
1111010
1111011
...
...
119
120 (INT E GE R M ODE ONLY)
INTEGER DIVIDE RATI O
21 (I NTEGE R M ODE ONL Y )
22 (I NTEGE R M ODE ONL Y )
23 (I NTEGE R M ODE ONL Y )
24
...
...
56 (DE FAULT )
INTEGER
INTEGE R DIVIDE RATI O CONTRO L BI TS
DIV IDE M ODE
FRACTIO NAL (DEF AULT)
121 (INT E GE R M ODE ONLY)
122 (INT E GE R M ODE ONLY)
123 (INT E GE R M ODE ONLY)
RESERVED
08547-004
Figure 38. Register 0—Integer Divide Control Register Map
REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)
MODULUS VALUE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)
MD10MD9MD8MD7MD6MD5MD4MD3MD2MD1MD0
0 0000000001
0 0000000010
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1000000000
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1111111111
MODULUS VALUE
...
...
2047
CONT ROL BITS
1
1536 (DEFAULT)
2
...
...
RESERVED
0
8547-005
Figure 39. Register 1—Modulus Divide Control Register Map
ADRF6603
Rev. A | Page 17 of 32
REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)
FD10FD9FD8FD7FD6FD5FD4FD3FD2FD1FD0
0 0000000000
0 0000000001
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
0 1100000000
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
FRACT IONAL VAL UE M US T BE LESS THAN MODULUS
FRACT I ONAL V ALUE
0
1
...
...
768 (DEFAUL T)
...
...
<MDR
FRACT IONAL VAL UERESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CONT ROL BITS
0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0)
08547-006
Figure 40. Register 2—Fractional Divide Control Register Map
REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)
DITHER
ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 DITH1 DITH0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)
DITH1 DITH0
00
01
10
11
DEN
0
1
DITHER
MAGNITUDE DITHER RESTART V ALUE CONT ROL BITS
DITHER MAGNITUDE
15 (DEFAUL T)
7
3
1 (RECO M MENDED)
DIT HE R E NABLE
DISABLE
ENABLE (DEF AULT, RECO M M E NDE D)
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
00000000000000001
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
11111111111111111
0x00001 (DE FAULT)
...
...
0x1FFFF
DITHER RES T ART
VALUE
08547-007
Figure 41. Register 3—Σ-Δ Modulator Dither Control Register Map
ADRF6603
Rev. A | Page 18 of 32
REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)
CP
CURRENT
REF
SOURCE
PFD
POL CP
SRC
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)
CPC1 CPC0
00
01
10
11
CPS
0
1
CPP1 CPP0
00
01
10
11
CPB4 CPB3 CPB2 CPB1 CPB0
00000
00001
00110
01010
10000
11111
CPBD
0
1
CPM
0
1
RS0 RS1
00
01
10
11
RMS2 RMS1 RMS0
000
001
010
011
100
101
110
111
10 × 22. 5°/I
CPMULT
(DEFAULT)
16 × 22. 5°/I
CPMULT
31 × 22. 5°/I
CPMULT
PFD PHAS E O F F S ET M UL T I P L I ER
0 × 22. 5°/I
CPMULT
1 × 22. 5°/I
CPMULT
6 × 22. 5°/I
CPMULT
(RECOMMENDED)
BOTH ON
PUMP DOWN
PUMP UP
TRISTATE (DEFAULT)
REF O U P U T
MUX SELECT INPUT REF
PATH PFD PHASE OFFSET
MULTIPLIER CP
CURRENT CP
CONTROL P F D EDG E CONT RO L BI T S
PFD ANTI
BACKLASH
DELAY
PE0
0
1
REFE RE NCE PATH EDG E
SENSITIVITY
FALLING EDGE
RISING EDGE ( DEFAULT)
PAB0 PAB1
00
01
10
11
PFD ANTI BACKL AS H
DELAY
0ns ( DE FAULT)
0.5ns
0.75ns
0.9ns
CHARGE P UMP CONTROL
0.5× REFI N ( BUFFE RE D)
CHARGE P UMP CONT ROL SOURCE
CONT ROL BASED ON STAT E OF DB7/DB8 (CP CONTROL)
CONT RO L F RO M PFD (DEF AUL T)
REF OUTPUT MUX SELECT
LO CK DE TECT ( DE FAULT)
VPTAT
REFIN (BUF FERED)
PFD PHASE OFF SET PO L ARITY
NEGATIVE
POSITI VE (DEFAULT)
CHARGE P UMP CURRENT
REFERENCE SO URCE
INT E RNAL (DEFAULT)
EXTERNAL
0.25× RE FI N
CHARGE P UMP CURRENT
250µA
500 µ A ( DE FAUL T)
750µA
1000µA
INPUT REF ERENCE
PATH SO URCE
2× REF IN
REFIN (DEFAULT)
0.5× RE FI N
2× REF IN (BUFF ERE D)
TRISTATE
RESERVED
RESERVED
PE1
0
1
DIVIDER PATH EDG E
SENSITIVITY
FALLING EDGE
RISING EDGE ( DE FAULT)
08547-008
Figure 42. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map
ADRF6603
Rev. A | Page 19 of 32
REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)
08547-009
RESERVED RES PLL
EN LO
DIV1 LO
EXT LO
DRV
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
LDV2 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CD3 CD2 CD1 CD0 PLEN LDV1 LXL LDRV C3(1) C2(0) C1(1)
LDRV
0
1
LXL
0
1
LDV1
0
1DIVIDE BY 1
DIVIDE BY 2 ( DE FAULT)
LO OUTPUT DRIVER
ENABLE
DRIV ER OF F (DE FAUL T)
DRIVE R ON
PLEN
0
1DISABLE
ENABLE (DEFAUL T)
PL L ENABLE
EXTERNAL LO DRIVE
ENABLE (P I N 37, P I N 38)
INTERNAL LO OUT PUT (DE FAUL T)
EXTERNAL LO INPUT
DIVIDE-BY-2 I N LO CHAIN ENABL E
CAP DAC CONTROL BI TS
CD3 CD2 CD1 CD0
0000
... ... ... ... MIN
...
CAPACITO R DAC
CONTROL F OR I IP3
OPTIMIZATION
1111MAX
00000000000 0
Figure 43. Register 5—PLL Enable and LO Path Control Register Map
REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)
CHARGE
PUMP
ENABLE
3.3V
LDO
ENABLE VCO
ENABLE VCO
SWITCH VCO
BW SW
CTRL
VBSRC
0
1
VCO EN
VCO LDO
ENABLE VCO AMPL I T UDERESERVED VCO BAND SE LECT FROM SPI
VBS[5:0] VCO BAND SELECT FROM S P I
0x00
DEF AULT 0x 20
CHARGE P UM P E NABLE
0x01
….
0x00 0
…. ….
0x18 24 (DEFAUL T)
…. ….
0x2B 43
…. ….
0x3F 63 (RECOMM E NDE D)
0x3F
VCO BW CAL AND S W SO URCE CONTROL
BAND CAL (DE F AULT )
VCO SW
0
1
VCO SWITCH CONTRO L F ROM S PI
REGULAR (DEFAULT)
BAND CAL
SPI
VCO ENABL E
DISABLE
ENABLE ( DE FAUL T)
DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CONT ROL BITS
DB23 CPEN L3EN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
LVEN
VC[5:0] VCO AMPLI TUDE
0
1
LVEN VCO LDO ENABLE
DISABLE
ENABLE (DEFAULT)
0
1
L3EN 3.3V LDO ENABLE
DISABLE
ENABLE ( DE FAULT)
0
1
CPEN
DISABLE
ENABLE ( DE FAULT)
0
1
000
08547-010
Figure 44. Register 6—VCO Control and VCO Enable Register Map
REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0XVCO
XVCORES
MBE000000000000000000C3(1)C2(1)C1(1)
MIXER
B_EN RE SE RV ED CONT ROL BIT S
MBE
0
1
XVCO
0
1INTERNAL V CO (DE FAULT)
EXT ERNAL V CO
MIX ER BI AS E NABLE
ENABLE (DEFAULT)
DISABLE
EXT ERNAL V CO
08547-011
Figure 45. Register 7—Mixer Bias Enable and External VCO Enable Register Map
ADRF6603
Rev. A | Page 20 of 32
THEORY OF OPERATION
The ADRF6603 integrates a high performance downconverting
mixer with a state-of-the-art fractional-N PLL. The PLL also
integrates a low noise VCO. The SPI port allows the user to control
the fractional-N PLL functions and the mixer optimization
functions, as well as allowing for an externally applied LO or VCO.
The mixer core within the ADRF6603 is the next generation of
an industry-leading family of mixers from Analog Devices, Inc.
The RF input is converted to a current and then mixed down to IF
using high performance NPN transistors. The mixer output currents
are transformed to a differential output. The high performance active
mixer core results in an exceptional IIP3 and IP1dB, with a very
low output noise floor for excellent dynamic range. Over the
specified frequency range, the ADRF6603 typically provides IF
input P1dB of 14.6 dBm and IIP3 of 27 dBm.
Improved performance at specific frequencies can be achieved
with the use of the internal capacitor DAC (CDAC), which is
programmable via the SPI port, and by using a resistor to a 5 V
supply from the IP3SET pin (Pin 29). Adjustment of the capacitor
DAC allows increments in phase shift at internal nodes in the
ADRF6603, thus allowing cancellation of third-order distortion
with no change in supply current. Connecting a resistor to a 5 V
supply from the IP3SET pin increases the internal mixer core current,
thereby improving overall IIP2 and IIP3, as well as IP1dB. Using
the IP3SET pin for this purpose increases the overall supply current.
The fractional divide function of the PLL allows the frequency
multiplication value from REF_IN to LO output to be a fractional
value rather than be restricted to an integer value as in traditional
PLLs. In operation, this multiplication value is INT + (FRAC/MOD),
where INT is the integer value, FRAC is the fractional value,
and MOD is the modulus value, all programmable via the SPI
port. In other fractional-N PLL designs, fractional multiplication
is achieved by periodically changing the fractional value in a
deterministic way. The disadvantage of this approach is often
spurious components close to the fundamental signal. In the
ADRF6603, a Σ- modulator is used to distribute the fractional
value randomly, thus significantly reducing the spurious content
due to the fractional function.
PROGRAMMING THE ADRF6603
The ADRF6603 is programmed via a 3-pin SPI port. The timing
requirements for the SPI port are shown in Figure 2. Eight pro-
grammable registers, each with 24 bits, control the operation of
the device. The register functions are listed in Table 8.
Table 8. ADRF6603 Register Functions
Register Function
Register 0 Integer divide control for the PLL
Register 1 Modulus divide control for the PLL
Register 2 Fractional divide control for the PLL
Register 3 Σ-Δ modulator dither control
Register 4 PLL charge pump, PFD, reference path control
Register 5 PLL enable and LO path control
Register 6 VCO control and VCO enable
Register 7 Mixer bias enable and external VCO enable
Note that internal calibration for the PLL must be run when the
ADRF6603 is initialized at a given frequency. This calibration is
run automatically whenever Register 0, Register 1, or Register 2 is
programmed. Because the other registers affect PLL performance,
Register 0, Register 1, and Register 2 should always be programmed
last and in this order: Register 0, Register 1, Register 2.
To program the frequency of the ADRF6603, the user typically
programs only Register 0, Register 1, and Register 2. However,
if registers other than these are programmed first, a short delay
should be inserted before programming Register 0. This delay
ensures that the VCO band calibration has sufficient time to
complete before the final band calibration for Register 0 is initiated.
Software is available on the ADRF6603 product page under the
Evaluation Boards & Development Kits section that allows easy
programming from a PC running Windows XP or Vista.
INITIALIZATION SEQUENCE
To ensure proper power-up of the ADRF6603, it is important to
reset the PLL circuitry after the VCC supply rail settles to 5 V ±
0.25 V. Resetting the PLL ensures that the internal bias cells are
properly configured, even under poor supply start-up conditions.
To ensure that the PLL is reset after power-up, follow this procedure:
1. Disable the PLL by setting the PLEN bit to 0 (Register 5,
Bit DB6).
2. After a delay of >100 ms, set the PLEN bit to 1 (Register 5,
Bit DB6).
After this procedure is followed, the other registers should be
programmed in this order: Register 7, Register 6, Register 4,
Register 3, Register 2, Register 1. Then, after a delay of >100 ms,
Register 0 should be programmed.
ADRF6603
Rev. A | Page 21 of 32
LO SELECTION LOGIC
The downconverting mixer in the ADRF6603 can be used
without the internal PLL by applying an external differential
LO to Pin 37 and Pin 38 (LON and LOP). In addition, when
using an LO generated by the internal PLL, the LO signal can
be accessed directly at these same pins. This function can be
used for debugging purposes, or the internally generated LO
can be used as the LO for a separate mixer.
The operation of the LO generation and whether LOP and LON
are inputs or outputs are determined by the logic levels applied
at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3
(LDRV) and Bit DB6 (PLEN) in Register 5. The combination of
externally applied logic and internal bits required for particular
LO functions is given in Table 9 .
Table 9. LO Selection Logic
Pins1 Register 5 Bits1 Outputs
Pin 16 (PLL_EN) Pin 36 (LODRV_EN) Bit DB6 (PLEN) Bit DB3 (LDRV) Output Buffer LO
0 X 0 X Disabled External
0 X 1 X Disabled External
1 X 0 X Disabled External
1 0 1 0 Disabled Internal
1 X 1 1 Enabled Internal
1 1 1 X Enabled Internal
1 X = don’t care.
ADRF6603
Rev. A | Page 22 of 32
APPLICATIONS INFORMATION
BASIC CONNECTIONS FOR OPERATION
Figure 46 shows the schematic for the ADRF6603 evaluation
board. The six power supply pins should be individually decoupled
using 100 pF and 0.1 µF capacitors located as close as possible
to the device. In addition, the internal decoupling nodes
(DECL3P3, DECL2P5, and DECLVCO) should be decoupled
with the capacitor values shown in Figure 46.
The RF input is internally ac-coupled and needs no external
bias. The IF outputs are open collector, and a bias inductor is
required from these outputs to VCC.
A peak-to-peak differential swing on RFIN of 1 V (0.353 V rms
for a sine wave input) results in an IF output power of 4.7 dBm.
The reference frequency for the PLL should be from 12 MHz to
160 MHz and should be applied to the REF_IN pin, which should
be ac-coupled and terminated with a 50 Ω resistor as shown in
Figure 46. The reference signal, or a divided-down version of
the reference signal, can be brought back off chip at the multiplexer
output pin (MUXOUT). A lock detect signal and a voltage
proportional to the ambient temperature can also be selected
on the multiplexer output pin.
The loop filter is connected between the CP and VTUNE pins.
When connected in this way, the internal VCO is operational.
For information about the loop filter components, see the
Evaluation Board Configuration Options section.
Operation with an external VCO is also possible. In this case,
the loop filter components should be referred to ground. The
output of the loop filter is connected to the input voltage pin of
the external VCO. The output of the VCO is brought back into
the device on the LOP and LON pins, using a balun if necessary.
R28
0Ω
(0402)
RFIN
MUX
R
SET
CP VTUNE
LODRV_EN
LON
LOP
2:1
MUX
VCO
CORE
TEMP
SENSOR
DECL2P5
DECL3P3
DECLVCO
BUFFER
BUFFER
IFNIFP
2
14
5
3
IP3SET
RF
IN
–
+
CHARGE P UMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
PRESCALER
÷2
MUXOUT
REF_IN
ADRF6603
195
8
36
1174 2015 2321 2524 3038 3531
26
PHASE
FREQUENCY
DETECTOR
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG MODULUS INTEGER
REG
N COUNTE R
21 TO 123
×2
÷2
÷4
DIVIDER
÷2
SPI
INTERFACE
C43
10µF
(0603)
C14
22pF
(0603)
CP
TEST
POINT
(ORANGE) C13
6.8pF
(0603)
C40
22pF
(0603)
C7
0.1µF
(0402)
VCC
RED
+5V
VCC
VTUNE
C15
2.7nF
(1206)
C2
OPEN
(0402)
C1
100pF
(0402)
R1
0Ω
(0402)
R38
0Ω
(0402)
R37
0Ω
(0402)
R2
OPEN
(0402)
C42
10µF
(0603)
C17
0.1µF
(0402)
R63
OPEN
(0402)
R65 10kΩ
(0402)
R9 10kΩ
(0402)
R12
0Ω
(0402)
R10
3kΩ
(0603)
R62
0Ω
(0402)
R11
OPEN
(0402)
RFOUT
C16
100pF
(0402)
R18
0Ω
(0402)
C41
OPEN
(0603)
C11
0.1µF
(0402)
C27
0.1µF
(0402)
C29
0.1µF
(0402)
C12
100pF
(0402)
R8
0Ω
(0402)
R16
0Ω
(0402)
C31
1nF
(0402)
C6
1nF
(0402)
R55
OPEN
(0402)
VCC1
RED
S1
OPEN
R56
0Ω
(0402)
C5
1nF
(0402)
R70
49.9Ω
(0402)
4
LO IN/OUT
REF_IN
REFOUT
3
51
T8
TC1-1-13+
R20
0Ω
(0402)
R54
10kΩ
(0402)
R19
0Ω
(0402)
S2 R53
10kΩ
(0402)
R35
0Ω
(0402)
R30
0Ω
(0402)
R50
OPEN
(0402)
R57
0Ω
(0402)
R36
0Ω
(0402)
P1
9-PIN
DSUB
VCC_LO VCC2 VCC1
PLL_EN
CLK
DATA
LE
27 13 12
C8
100pF
(0402)
R6
0Ω
(0402)
C25
0.1µF
(0402)
C24
100pF
(0402)
R26
0Ω
(0402)
C23
0.1µF
(0402)
C22
100pF
(0402)
R25
0Ω
(0402)
C20
0.1µF
(0402)
C21
100pF
(0402)
R24
0Ω
(0402)
C19
0.1µF
(0402)
C18
100pF
(0402)
R17
0Ω
(0402)
C9
0.1µF
(0402)
C10
100pF
(0402)
R7
0Ω
(0402)
2 4 61357
C32
OPEN
(0402)
R51
OPEN
(0402)
C33
OPEN
(0402)
R52
OPEN
(0402)
C34
OPEN
(0402)
14
DIV
BY
2, 1
VCC_MIXVCC_V2IVCC_LO
R27
0Ω
(0402)
R43
0Ω
(0402)
VCC
+5V R59
0Ω
(0402)
08547-024
16
2
9
29
1840393
6
38
37
34 22 17 10 1
89
Figure 46. Basic Connections for Operation of the ADRF6603
ADRF6603
Rev. A | Page 23 of 32
AC TEST FIXTURE
Characterization data for the ADRF6603 was taken under very
strict test conditions. All possible techniques were used to
achieve optimum accuracy and to remove degrading effects of
the signal generation and measurement equipment. Figure 47
shows the typical AC test set up used in the characterization of
the ADRF6603.
ROHDE & SCHWART Z
FSEA30
IF_OUT
AGIL ENT 344 01A S E T TO IDC
(SET FOR SUPPLY CURRENT)
RF1 A GI LEN T N5181A
RF2 A GI LEN T N5181A
REF_I N AGIL ENT N 5181A
HP 11636A
PO WE R DIVIDE R
AGIL E NT 34980A WI TH T HRE E 34921 MO D UL E S
AND O NE 34950 MO DULE
A
DRF6603 CHARACTERIZATION RACK DIAGRAM.
ALL I NSTRUMENTS AR E CO NTROLL ED BY A LAB
COMP U T ER V IA A US B TO GPIB CONTROLLE R, DAI SY
CHAIN ED TO EACH INDI VI DUA L INS T R UMENT.
REF_IN
RF
IN
5V d c VIA
10-PIN DC HEAD E R
5V dc MEASURED FOR SUPPLY CURRENT AGI L E NT E3631A 25V SE T T O
3.3V, 6V SET TO 5V .
RETURNS ARE
JUMPERED TOG ET HER
ADRF6603
EVALUAT IO N BO A RD
GND VIA
10-PIN DC HEADER
3.3V d c VIA
10-PIN DC HEADER
9-PIN CONTRO LLER DS U B AND
10-PIN DC HEADER
08547-047
Figure 47. ADRF6603 AC Test Setup
ADRF6603
Rev. A | Page 24 of 32
EVALUATION BOARD
Figure 50 shows the schematic of the RoHS-compliant evaluation
board for the ADRF6603. This board has four layers and was
designed using Rogers 4350 hybrid material to minimize high
frequency losses. FR4 material is also adequate if the design can
accept the slightly higher trace loss of this material.
The evaluation board is designed to operate using the internal
VCO of the device (the default configuration) or with an external
VCO. To use an external VCO, R62 and R12 should be removed.
Place 0 Ω resistors in R63 and R11. The input of the external
VCO should be connected to the VTUNE SMA connector, and
the external VCO output should be connected to the LO IN/OUT
SMA connector. In addition to these hardware changes, internal
register settings must also be changed to enable operation with
an external VCO (see the Register 6—VCO Control and VCO
Enable (Default: 0x1E2106) section).
Additional configuration options for the evaluation board are
described in Table 10.
EVALUATION BOARD CONTROL SOFTWARE
Software to program the ADRF6603 is available for download
on the ADRF6603 product page under the Evaluation Boards &
Development Kits section. To install the software
1. Download and extract the zip file:
ADRF6x0x_3p0p0_XP_install.exe file.
2. Follow the instructions in the read me file.
The evaluation board can be connected to the PC using a PC
parallel port or a USB port. These options are selectable from the
opening menu of the software interface (see Figure 48). The
evaluation board is shipped with a 25-pin parallel port cable
for connection to the PC parallel port.
To connect the evaluation board to a USB port, a USB adapter board
(EVAL-ADF4XXXZ-USB) must be purchased from Analog Devices.
This board connects to the PC using a standard USB cable with a
USB mini-connector at one end. An additional 25-pin male to 9-pin
female adapter is required to mate the ADF4XXXZ-USB board
to the 9-pin D-Sub connector on the ADRF6603 evaluation board.
0
8547-048
Figure 48. Control Software Opening Menu
Figure 49 shows the main menu of the control software with the
default settings displayed.
ADRF6603
Rev. A | Page 25 of 32
0
8547-049
Figure 49. Main Screen of the ADRF6603 Evaluation Board Software
ADRF6603
Rev. A | Page 26 of 32
SCHEMATIC AND ARTWORK
08547-050
AGND
AGND
AGND
AGND
AGND
NC
AGND
AGND
AGNDAGND
AGND
AGND
AGND
AGND
AGND
AGND AGND
AGND
AGND AGND
AGNDAGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGND
AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
E-PAD
VCC
CPOUT
GNDCP
RSET
REFGND
VCC
GNDDIG
DATA
CLK
LE
GNDDIG
OUTPUTEN
GNDBB
GNDRF
VCCBB
RFRTN
NC
GNDRF
VCCRF
GNDRF
GNDRF
INBB
IPBB
GNDBB
GND
LOEXTEN
LON
REFIN
VCC_LO VCC_LO
VCO_LDO
3P3_LDO
2P5_LDO
LOP
VCO_IN
RFIN
IP3SET
IFP
IFN
REFOUT/LOCK
AGND
AGND
AGND
AGND
AGND
AGND
AGND
1
VCC
1
VCC2
1
VCC5
1
VCC_LO1
1
VCC_BB1
1
VCC_RF
1
VCC1
1
VCC_LO
1
VCC4
1
VCO_LDO
1
CP
1
DATA
1
IP3SET
1
LE
1
CLK
1
2P5V
1
OSC_3P3V
1
3P3V1
R10
3K
R63
100K
R37
0
DNI
R11
R12
0
0
R62
10K
R65R9
10K
22PF
C40
C14
22PF C13
6.8PF
C15
2.7NF
L2
TBD
L1
TBD
C36
DNI
C35
DNI
0
R66
R67
0
R68
0 DNI
C41
10UF
0.1UF
C9
10UF
C42
10UF
C43
P1-6
P1-1
1
2
3
4
5
6
7
8
9
P1
AMP745781-4
TBD
R27
IP3SET
C34
100PF DNI
100PF DNI
C33
C32
100PF DNI
1K DNI
R52
R51
1K DNI
1K DNI
R50
C28
10UF
R47
0
0
R48
VCC
VCC
1
2
3
4
5
6
7
8
9
10
11 12 15 16 18 20
22
23
24
25
26
27
28
29
30
31323334353637383940
21
13 14 17 19
PAD
Z1
VCC_BB
R60
TBD
R44
DNI
VCC
4
6
1
3
2
T3
TC4-1W
R59
0
0
R43
0.1UF
C29
C25
0.1UF
DNI
R58
1
DIG_GND
R36 0
0
R57
12
3
S2
R53
10K 10K
R54
R56
10K
VCC
C31
1000PF
R49
DNI
1NF
C6 C5
1NF
LO_EXTERN
0
R33
10K
R55
VCC
3
2
1S1
OUTPUT_EN
0
R30
R19
0
100PF
C10
R18
0
DNI
R2
C12
100PF
0
R25
R26
0
0
R38
R8
0
0
R35
1
GND
0
R29
VCC
1J1
Y1
R1
0
VCC_SENSE
SNS1
SNS
VCO_LDO
LO_EXTERN
2P5V_LDO
3P3V_LDO
AGND
VCC_SENSE
AGND
VCC
10J1
8J1
R20
0
VCC_BB
VCC_LO
VCC_RF
VCC_BB
VCC_LO
VCC_LO
0
R28
R14
DNI
R15
0
C3
10PF
C4
22000PF
0.1UF
C7
0
R6
C2
0.1UF C1
100PF
100PF
C8
0
R7
C11
0.1UF
REFIN
REFOUT R16
0
0.1UF
C19 100PF
C18
C17
0.1UF C16
100PF
0
R17
OUT
C21
100PF
R24
0C20
0.1UF
0.1UF
C23
100PF
C22
C24
100PF
0.1UF
C27
RFIN
VCC
0
R31
R32
0
0
R34
2J1
3J1
4J1
5J1
6J1
7J1
9J1
1
GND1 1
GND2
VCC_RF
IFN
IFP
OSC_3P3V
VCC
P4-T7
P4-T7
P3-T7
P3-T7
P1-T7
P1-T7
P1-T7 LO
0
R69
1
1A
2
2A
3
3A 4
4A
5
5A
6
6A
T7
15
34
2
T8
P3-T7
P4-T7
OUTPUT_EN
IP3SET
R70
49.9
3P3V_LDO
VCO_LDO
2P5V_LDO
VTUNE
P1-6
R72
0
P1-1
R71
TBD
Figure 50. Evaluation Board Schematic
ADRF6603
Rev. A | Page 27 of 32
08547-013
Figure 51. Evaluation Board Layout (Bottom)
08547-012
Figure 52. Evaluation Board Layout (Top)
ADRF6603
Rev. A | Page 28 of 32
EVALUATION BOARD CONFIGURATION OPTIONS
Table 10.
Component Description
Default Condition/
Option Settings
S1, R55, R56, R33 LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in
combination with internal register settings, determines whether the LOP and LON pins
function as inputs or outputs (see the LO Selection Logic section for more information).
S1 = R55 = open
(not installed),
R56 = R33 = 0 Ω,
LODRV_EN = 0 V
LO IN/OUT
SMA Connector
LO input/output. An external 1× LO or 2× LO can be applied to this single-ended input
connector.
LO input
REFIN
SMA Connector
Reference input. The input reference frequency for the PLL is applied to this connector.
Input impedance is 50 Ω.
REFOUT
SMA Connector
Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The
on-board multiplexer can be programmed to bring out the following signals: REFIN, 2×
REFIN, REFIN/2, and REFIN/4; temperature sensor output voltage; and lock detect indicator.
Lock detect
CP Test Point Charge pump test point. The unfiltered charge pump signal can be probed at this test
point. Note that the CP pin should not be probed during critical measurements such as
phase noise.
R37, C14, R9, R10,
C15, C13, R65, C40
Loop filter. Loop filter components.
R11, R12 Loop filter return. When the internal VCO is used, the loop filter components should be
returned to Pin 40 (DECLVCO) by installing a 0 Ω resistor in R12. When an external VCO is used,
the loop filter components can be returned to ground by installing a 0 Ω resistor in R11.
R12 = 0 Ω (0402),
R11 = open (0402)
R62, R63, VTUNE
SMA Connector
Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are
connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an
external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the
voltage input of the VCO should be connected to the VTUNE SMA connector. The output of
the VCO is brought back into the PLL via the LO IN/OUT SMA connector.
R62 = 0 Ω (0402),
R63 = open (0402)
R2 RSET pin. This pin is unused and should be left open. R2 = open (0402)
RFIN SMA Connector RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of
the ADRF6603 is ac-coupled, so no bias is necessary.
R3 = R23 = open (0402)
T3 IF output. The differential IF output signals from the ADRF6603 (IFP and IFN) are converted
to a single-ended signal by T3.
ADRF6603
Rev. A | Page 29 of 32
OUTLINE DIMENSIONS
1
40
10
11
31
30
21
20
4.25
4.10 SQ
3.95
TOP
VIEW
6.00
BSC SQ
PIN 1
INDICATOR 5.75
BSC SQ
12° MAX
0.30
0.23
0.18 0 .20 REF
SEATING
PLANE
1.00
0.85
0.80
0.05 M A X
0.02 NOM
COPLANARITY
0.08
0.80 M A X
0.65 TYP
4.50
REF
0.50
0.40
0.30
0.50
BSC
PIN 1
INDICATOR
0.60 M A X
0.60 M AX
0.25 M IN
EXPOSED
PAD
(BOTTOM VIEW)
COMP LIANT TO JEDEC S TANDARDS M O-220- V JJD- 2
072108-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATION AND
FUNCT ION DE S CRIPT IONS
SECT ION OF THIS DATA SHEE T.
Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADRF6603ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1
ADRF6603-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
ADRF6603
Rev. A | Page 30 of 32
NOTES
ADRF6603
Rev. A | Page 31 of 32
NOTES
ADRF6603
Rev. A | Page 32 of 32
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08547-0-11/10(A)
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08547-0-11/10(A)
