Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync AD9558 Data Sheet FEATURES Pin program function for easy frequency translation configuration Software controlled power-down 64-lead, 9 mm x 9 mm, LFCSP package Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, G.824, G.825, and G.8261 Auto/manual holdover and reference switchover 4 reference inputs (single-ended or differential) Input reference frequencies: 2 kHz to 1250 MHz Reference validation and frequency monitoring (1 ppm) Programmable input reference switchover priority 20-bit programmable input reference divider 6 pairs of clock output pins with each pair configurable as a single differential LVDS/HSTL output or as 2 single-ended CMOS outputs Output frequencies: 352 Hz to 1250 MHz Programmable 17-bit integer and 24-bit fractional feedback divider in digital PLL Programmable digital loop filter covering loop bandwidths from 0.1 Hz to 5 kHz (2 kHz maximum for <0.1 dB of peaking) Low noise system clock multiplier Frame sync support Adaptive clocking Optional crystal resonator for system clock input On-chip EEPROM to store multiple power-up profiles APPLICATIONS Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Wireless base station controllers Cable infrastructure Data communications GENERAL DESCRIPTION The AD9558 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9558 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9558 continuously generates a low jitter output clock even when all reference inputs have failed. The AD9558 operates over an industrial temperature range of -40C to +85C. If a smaller package is required, refer to the AD9557 for the two-input/two-output version of the same part. FUNCTIONAL BLOCK DIAGRAM STABLE SOURCE AD9558 CHANNEL 0 DIVIDER CLOCK MULTIPLIER CHANNEL 1 DIVIDER /3 TO /11 HF DIVIDER 0 DIGITAL PLL ANALOG PLL /3 TO /11 HF DIVIDER 1 REFERENCE INPUT AND MONITOR MUX CHANNEL 3 DIVIDER FRAME SYNC EEPROM STATUS AND CONTROL PINS 09758-001 SERIAL INTERFACE (SPI OR I2C) CHANNEL 2 DIVIDER Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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Technical Support www.analog.com AD9558 Data Sheet TABLE OF CONTENTS Features ........................................................................................................ 1 Digital PLL (DPLL) Core ...................................................................31 Applications ................................................................................................ 1 Loop Control State Machine .............................................................34 General Description .................................................................................. 1 System Clock (SYSCLK) .........................................................................35 Functional Block Diagram ....................................................................... 1 System Clock Inputs............................................................................35 Revision History......................................................................................... 3 System Clock Multiplier .....................................................................35 Specifications .............................................................................................. 4 Output PLL (APLL).................................................................................37 Supply Voltage ........................................................................................ 4 Clock Distribution ...................................................................................38 Supply Current ....................................................................................... 4 Clock Dividers......................................................................................38 Power Dissipation.................................................................................. 5 Output Power-Down ..........................................................................38 Logic Inputs (SYNC, RESET, PINCONTROL, M7 to M0).......... 5 Output Enable ......................................................................................38 Logic Outputs (M7 to M0, IRQ) ........................................................ 6 Output Mode........................................................................................38 System Clock Inputs (XOA, XOB) ..................................................... 6 Clock Distribution Synchronization................................................38 Reference Inputs .................................................................................... 7 Frame Synchronization ...........................................................................40 Reference Monitors ............................................................................... 8 Reference Configuration in Frame Synchronization Mode ........40 Reference Switchover Specifications.................................................. 8 Clock Outputs in Frame Synchronization Mode ..........................40 Distribution Clock Outputs................................................................. 9 Control Registers for Frame Synchronization Mode....................40 Time Duration of Digital Functions ................................................ 10 Level Sensitive Mode and One-Shot Mode ....................................40 Digital PLL ............................................................................................ 11 M3b Divider/OUT5 Programming in Frame Synchronization Mode .......................................................................41 E Digital PLL Lock Detection............................................................... 11 Holdover Specifications...................................................................... 11 Serial Port Specifications--SPI Mode ............................................. 12 Serial Port Specifications--I2C Mode .............................................. 13 Jitter Generation .................................................................................. 13 Absolute Maximum Ratings .................................................................. 16 ESD Caution ......................................................................................... 16 Pin Configuration and Function Descriptions .................................. 17 Typical Performance Characteristics.................................................... 20 Input/Output Termination Recommendations ................................. 25 Getting Started.......................................................................................... 26 Chip Power Monitor and Startup ..................................................... 26 Multifunction Pins at Reset/Power-Up ........................................... 26 Device Register Programming When Using a Register Setup File ............................................................................................... 26 Status and Control ...................................................................................42 Multifunction Pins (M7 to M0)........................................................42 Watchdog Timer ..................................................................................43 EEPROM...............................................................................................43 Serial Control Port ...................................................................................49 SPI/I2C Port Selection.........................................................................49 SPI Serial Port Operation...................................................................49 I2C Serial Port Operation ...................................................................53 Programming the I/O Registers ............................................................56 Buffered/Active Registers...................................................................56 Autoclear Registers..............................................................................56 Register Access Restrictions ..............................................................56 Thermal Performance .............................................................................57 Power Supply Partitions ..........................................................................58 Register Programming Overview .................................................... 26 Recommended Configuration for 3.3 V Switching Supply.........58 Theory of Operation ............................................................................... 29 Configuration for 1.8 V Supply.........................................................58 Overview ............................................................................................... 29 Pin Program Function Description ......................................................59 Reference Clock Inputs ...................................................................... 30 Overview of On-Chip ROM Features .............................................59 Reference Monitors ............................................................................. 30 Hard Pin Programming Mode..........................................................60 Reference Profiles ................................................................................ 30 Soft Pin Programming Overview .....................................................61 Reference Switchover .......................................................................... 30 Register Map .............................................................................................62 Rev. B | Page 2 of 104 Data Sheet AD9558 Register Map Bit Descriptions............................................................... 72 Serial Port Configuration (Register 0x0000 to Register 0x0005)72 Silicon Revision (Register 0x000A) ................................................. 72 Clock Part Serial ID (Register 0x000C to Register 0x000D) ...... 72 System Clock (Register 0x0100 to Register 0x0108) .................... 73 General Configuration (Register 0x0200 to Register 0x0214) ... 74 Frame Synchronization (Register 0x0640 to Register 0x0641) .......................................................................... 86 DPLL Profile Registers (Register 0x0700 to Register 0x07E6) ......................................................................... 87 Operational Controls (Register 0x0A00 to Register 0x0A10) ........................................................................................ 89 IRQ Mask (Register 0x020A to Register 0x020F) ...................75 Quick In/Out Frequency Soft Pin Configuration (Register 0x0C00 to Register 0x0C08) ...................................................... 92 DPLL Configuration (Register 0x0300 to Register 0x032E) .76 Status ReadBack (Register 0x0D00 to Register 0x0D14)....... 93 Output PLL Configuration (Register 0x0400 to Register 0x0408) ..........................................................................79 EEPROM Control (Register 0x0E00 to Register 0x0E03) ..... 97 EEPROM Storage Sequence (Register 0x0E10 to Register 0x0E3C)......................................................................... 98 Output Clock Distribution (Register 0x0500 to Register 0x0515) ..........................................................................81 Outline Dimensions ......................................................................104 Reference Inputs (Register 0x0500 to Register 0x0507) ........85 Ordering Guide .........................................................................104 REVISION HISTORY 6/13--Rev. A to Rev. B Changes to Multifunction Pins (M7 to M0) Section .................. 42 Change to Address 0x0101, Table 35 ............................................ 62 Changes to Bit 4, Table 43 .............................................................. 73 Updated Outline Dimensions ...................................................... 104 4/12--Rev 0 to Rev. A Changed 3 Hz to 352 kHz in Output Frequencies List Item, Features Section ................................................................................. 1 Change to Output Frequency Range Parameter, Min; and System Clock Input Doubler Duty Cycle Parameter Description, Table 6... 6 Changes to Test Conditions/Comments Column, Table 9 .......... 8 Changes to Output Frequency Parameters, Min, Table 10 .......... 9 Changes to Pin 4 and Pin 42, Table 20 ......................................... 17 Changes to Device Register Programming When Using a Register Setup File and Register Programming Overview Sections ............. 26 Changed APLL VCO Lower Frequency and OUT5 Frequency Range, Figure 35; Changed 225 MHz to 200 MHz and 3.45 GHz to 3.35 GHz in Overview Section................................................... 29 Changes to Reference Profiles Section ......................................... 30 Changes to Programmable Digital Loop Filter Section ............. 32 Changes to System Clock Inputs Section ..................................... 35 Changes to Output PLL (APLL) Section; Changes to Figure 39 .... 37 Changes to Figure 40; Changed 1024 to 1023 in Clock Dividers Section; Changes to Clock Distribution Synchronization Section .............................................................................................. 38 Changes to Multifunction Pins (M7 to M0) and IRQ Pin Sections ............................................................................................. 42 Changes to Figure 44 ...................................................................... 43 Changes to EEPROM Conditional Processing Section and Figure 45 ............................................................................................ 46 Added Programming the EEPROM to Configure an M Pin to Control Synchronization of Clock Distribution Section ......... 48 Changes to the Power Supply Partitions Section ........................ 58 Changed 89.5 to 88.5 in DPLL Phase Margin Section ............ 59 Changes to Address 0x0006, Address 0x0007, and Address 0x000A, Table 35 .............................................................. 62 Changes to Address 0x0304, Table 35 .......................................... 63 Changes to Address 0x0405, Table 35 .......................................... 64 Changes to Address 0x071A and Address 0x071D, Table 35 .... 65 Changes to Address 0x0780, Address 0x0785 to Address 0x078A, Address 0x079A, Address 0x079D, Table 35 ... 67 Changes to Address 0x07C0, Address 0x07DA, and Address 0x07DD, Table 35 ............................................................. 68 Change to Address 0x0A01, Bit 7, Table 35 ................................. 69 Added Address 0x0E3D to Address 0x0E45, Table 35 ............... 71 Change to Table 38; Added Table 40, Renumbered Sequentially; Changes to Table 41 ........................................................................ 72 Change to Bit 0, Address 0x0101, Table 43 .................................. 73 Changes to Address 0x0304, Table 55 .......................................... 76 Deleted Address 0x0305, Table 55 ................................................ 76 Changes to Table Title, Table 63; Changes to Address 0x0400 and Address 0x0403, Table 64........................................................ 79 Changes to Address 0x0405, Table 64 .......................................... 80 Changes to Descriptions, Address 0x0500, Table 67 .................. 81 Changes to Bit 0, Address 0x0501, Table 68 ................................ 82 Changes to Bits[6:4], Address 0x0505 and Changes to Address 0x0506, Table 70 ............................................................... 83 Changes to Bits[6:4] and Bit 0, Address 0x050F, Table 73 ......... 84 Change to Address 0x0704, Table 78; Changes to Bits[3:0] in Address 0x0707 and Address 070A, Table 79; and Changes to Address 0x070E, Table 82................................................................ 87 Changes to Address 0x0710, Table 83; and Changes to Bits[3:0], Address 0x0714, Table 84 ................................................................. 88 Changes to Bits[1:0], Address 0x0A01, Table 90........................... 89 Changes to Descriptions, Address 0x0A0B, Table 99................. 91 Changes to Bit 4, Address 0x0C06, Table 100 ............................. 93 Changes to Bit 6 and Bit 1, Address 0x0D01, Table 102 ............ 94 Changes to Table Summary, Table 114 ......................................... 98 Added Table 128 ............................................................................ 101 Changes to Table 129 .................................................................... 102 Changes to Table 130 .................................................................... 103 10/11--Revision 0: Initial Version Rev. B | Page 3 of 104 AD9558 Data Sheet SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1.8 V; TA= 25C, unless otherwise noted. SUPPLY VOLTAGE Table 1. Parameter SUPPLY VOLTAGE DVDD3 DVDD AVDD3 AVDD Min Typ Max Unit 3.135 1.71 3.135 1.71 3.30 1.80 3.30 1.80 3.465 1.89 3.465 1.89 V V V V Test Conditions/Comments SUPPLY CURRENT The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of Table 3. The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter of Table 3. Table 2. Parameter SUPPLY CURRENT FOR TYPICAL CONFIGURATION IDVDD3 IDVDD IAVDD3 IAVDD Min Typ Max Unit 12 12 50 152 19 20 70 230 26 28 92 305 mA mA mA mA SUPPLY CURRENT FOR THE ALL BLOCKS RUNNING CONFIGURATION IDVDD3 IDVDD IAVDD3 IAVDD 23 11 73 168 34 22 108 250 46 32 143 331 mA mA mA mA Rev. B | Page 4 of 104 Test Conditions/Comments Typical numbers are for the typical configuration listed in Table 3 Pin 45, Pin 46, Pin 51, Pin 52, Pin 64 Pin 6, Pin 55, Pin 56 Pin 25, Pin 26, Pin 31 Pin 7, Pin 10, Pin 12, Pin 17, Pin 22, Pin 29, Pin 30, Pin 35, Pin 37, Pin 38 Maximum numbers are for all blocks running configuration in Table 3 Pin 45, Pin 46, Pin 51, Pin 52, Pin 64 Pin 6, Pin 55, Pin 56 Pin 25, Pin 26, Pin 31 Pin 7, Pin 10, Pin 12, Pin 17, Pin 22, Pin 29, Pin 30, Pin 35, Pin 37, Pin 38 Data Sheet AD9558 POWER DISSIPATION Table 3. Parameter POWER DISSIPATION Typical Configuration Min Typ Max Unit Test Conditions/Comments 0.47 0.74 1.02 W All Blocks Running 0.6 1.0 1.32 W 44 125 mW System clock: 49.152 MHz crystal; DPLL active; both 19.44 MHz input references in differential mode; one HSTL driver at 644.53125 MHz; one 3.3 V CMOS driver at 161.1328125 MHz and 80 pF capacitive load on CMOS output System clock: 49.152 MHz crystal; DPLL active; both input references in differential mode; four HSTL drivers at 750 MHz; four 3.3 V CMOS drivers at 250 MHz and 80 pF capacitive load on CMOS outputs Typical configuration with no external pull-up or pulldown resistors; about 2/3 of this power is on AVDD3 Conditions = typical configuration; table values show the change in power due to the indicated operation 20 26 5 25 32 7 32 40 9 mW mW mW Additional current draw is in the DVDD3 domain only Additional current draw is in the DVDD3 domain only Additional current draw is in the DVDD3 domain only 12 14 14 18 17 21 21 27 22 28 28 36 mW mW mW mW Additional current draw is in the AVDD domain only Additional current draw is in the AVDD domain only A single 1.8 V CMOS output with an 80 pF load A single 3.3 V CMOS output with an 80 pF load 36 10 51 17 64 23 mW mW Additional current draw is in the AVDD domain only Additional current draw is in the AVDD domain only Max Unit Test Conditions/Comments 0.8 100 V V A pF 2.2 0.6 100 V V V A pF Full Power-Down Incremental Power Dissipation Input Reference On/Off Differential Without Divide-by-2 Differential With Divide-by-2 Single-Ended (Without Divide-by-2) Output Distribution Driver On/Off LVDS (at 750 MHz) HSTL (at 750 MHz) 1.8 V CMOS (at 250 MHz) 3.3 V CMOS (at 250 MHz) Other Blocks On/Off Second RF Divider Channel Divider Bypassed LOGIC INPUTS (SYNC, RESET, PINCONTROL, M7 TO M0) E A A Table 4. Parameter LOGIC INPUTS (SYNC, RESET, PINCONTROL) Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IINH, IINL) Input Capacitance (CIN) LOGIC INPUTS (M7 to M0) Input High Voltage (VIH) Input 1/2 Level Voltage (VIM) Input Low Voltage (VIL) Input Current (IINH, IINL) Input Capacitance (CIN) Min Typ E A EA A A 2.1 50 3 2.5 1.0 60 3 Rev. B | Page 5 of 104 AD9558 Data Sheet LOGIC OUTPUTS (M7 TO M0, IRQ) Table 5. Parameter LOGIC OUTPUTS (M7 to M0, IRQ) Output High Voltage (VOH) Output Low Voltage (VOL) IRQ Leakage Current Active Low Output Mode Active High Output Mode Min Typ Max Unit Test Conditions/Comments 0.4 V V -200 100 A A IOH = 1 mA IOL = 1 mA Open-drain mode VOH = 3.3 V VOL = 0 V Max Unit Test Conditions/Comments 750 805 MHz The VCO range may place limitations on nonstandard system clock input frequencies 150 255 MHz 2 600 MHz V/s DVDD3 - 0.4 SYSTEM CLOCK INPUTS (XOA, XOB) Table 6. Parameter SYSTEM CLOCK MULTIPLIER Output Frequency Range Phase Frequency Detector (PFD) Rate Frequency Multiplication Range SYSTEM CLOCK REFERENCE INPUT PATH Input Frequency Range Minimum Input Slew Rate Common-Mode Voltage Differential Input Voltage Sensitivity Min Typ 10 20 Assumes valid system clock and PFD rates 1.05 250 1.16 1.25 V mV p-p 45 46 47 50 50 50 3 4.2 55 54 53 % % % pF k System Clock Input Doubler Duty Cycle System Clock Input = 50 MHz System Clock Input = 20 MHz System Clock Input = 16 MHz to 20 MHz Input Capacitance Input Resistance CRYSTAL RESONATOR PATH Crystal Resonator Frequency Range Maximum Crystal Motional Resistance 10 50 100 Rev. B | Page 6 of 104 MHz Minimum limit imposed for jitter performance Internally generated Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding of complementary input; 1 V p-p recommended for optimal jitter performance This is the amount of duty cycle variation that can be tolerated on the system clock input to use the doubler Single-ended, each pin Fundamental mode, AT cut crystal Data Sheet AD9558 REFERENCE INPUTS Table 7. Parameter DIFFERENTIAL OPERATION Frequency Range Sinusoidal Input LVPECL Input LVDS Input Min Max Unit 10 0.002 750 1250 MHz MHz 0.002 750 MHz Minimum Input Slew Rate Common-Mode Input Voltage AC-Coupled DC-Coupled Differential Input Voltage Sensitivity 40 fIN < 800 MHz fIN = 800 to 1050 MHz fIN = 1050 to 1250 MHz Differential Input Voltage Hysteresis Input Resistance Input Capacitance 240 320 400 Minimum Pulse Width High LVPECL LVDS Minimum Pulse Width Low LVPECL LVDS SINGLE-ENDED OPERATION Frequency Range (CMOS) Minimum Input Slew Rate Input Voltage High (VIH) 1.2 V to 1.5 V Threshold Setting 1.8 V to 2.5 V Threshold Setting 3.0 V to 3.3 V Threshold Setting Input Voltage Low (VIL) 1.2 V to 1.5 V Threshold Setting 1.8 V to 2.5 V Threshold Setting 3.0 V to 3.3 V Threshold Setting Input Resistance Input Capacitance Minimum Pulse Width High Minimum Pulse Width Low 1.9 1.0 Typ V/s 2 58 21 3 2.2 2.4 100 V V mV ps ps 390 640 ps ps 300 1.0 1.4 2.0 47 3 1.5 1.5 MHz V/s V V V 0.35 0.5 1.0 The reference input divide-by-2 block must be engaged for fIN > 705 MHz The reference input divide-by-2 block must be engaged for fIN > 705 MHz Minimum limit imposed for jitter performance Internally generated Minimum differential voltage across pins is required to ensure switching between logic levels; instantaneous voltage on either pin must not exceed the supply rails mV mV mV mV k pF 390 640 0.002 40 Test Conditions/Comments V V V k pF ns ns Rev. B | Page 7 of 104 Minimum limit imposed for jitter performance AD9558 Data Sheet REFERENCE MONITORS Table 8. Parameter REFERENCE MONITORS Reference Monitor Loss of Reference Detection Time Frequency Out-of-Range Limits Validation Timer 1 Min Typ Max Unit Test Conditions/Comments 1.1 DPLL PFD period f/fREF (ppm) Nominal phase detector period = R/fREF 1 <2 105 0.001 65.535 sec 0F0F Programmable (lower bound is subject to quality of the system clock (SYSCLK)); SYSCLK accuracy must be better than the lower bound Programmable in 1 ms increments fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider. REFERENCE SWITCHOVER SPECIFICATIONS Table 9. Parameter REFERENCE SWITCHOVER SPECIFICATIONS Maximum Output Phase Perturbation (Phase Build-Out Switchover) 50 Hz DPLL Loop Bandwidth Peak Steady State 2 kHz DPLL Loop Bandwidth Peak Steady State Time Required to Switch to a New Reference Phase Build-Out Switchover Min Typ Max Unit 0 0 100 100 ps ps 0 0 250 100 ps ps 1.1 DPLL PFD period Test Conditions/Comments Assumes a jitter-free reference; satisfies Telcordia GR-1244-CORE requirements; select high PM base loop filter bit (Register 0x070E, Bit 0) is set to 1 for all active references Valid for automatic and manual reference switching Valid for automatic and manual reference switching Rev. B | Page 8 of 104 Calculated using the nominal phase detector period (NPDP = R/fREF); the total time required is equal to the time plus the reference validation time and the time required to lock to the new reference Data Sheet AD9558 DISTRIBUTION CLOCK OUTPUTS Table 10. Parameter HSTL MODE Output Frequency Min Typ Max Unit Test Conditions/Comments 1250 MHz 140 250 ps OUT5 only; OUT0 to OUT4 minimum output frequency is 360 kHz 100 termination across output pins 48 48 43 950 870 52 53 1200 960 % % % mV mV Magnitude of voltage across pins; output driver static Output driver static 1250 MHz 185 280 ps 48 47 43 53 53 % % % 454 mV 50 mV 1.375 50 24 V mV mA Output driver static Voltage difference between pins; output driver static Output driver static 0.000352 Rise/Fall Time (20% to 80%) 1 Duty Cycle Up to fOUT = 700 MHz Up to fOUT = 750 MHz Up to fOUT = 1250 MHz Differential Output Voltage Swing Common-Mode Output Voltage LVDS MODE Output Frequency 1F Rise/Fall Time (20% to 80%)1 Duty Cycle Up to fOUT = 750 MHz Up to fOUT = 800 MHz Up to fOUT = 1250 MHz Differential Output Voltage Swing Balanced, VOD 45 42 700 700 0.000352 44 43 247 Unbalanced, VOD Offset Voltage Common-Mode, VOS Common-Mode Difference, VOS Short-Circuit Output Current CMOS MODE Output Frequency 1.8 V Supply 3.3 V Supply (OUT0 and OUT5) Strong Drive Strength Setting Weak Drive Strength Setting Rise/Fall Time (20% to 80%)1 1.8 V Supply 3.3 V Supply Strong Drive Strength Setting Weak Drive Strength Setting Duty Cycle 1.8 V Mode 3.3 V Strong Mode 3.3 V Weak Mode Output Voltage High (VOH) AVDD3 = 3.3 V, IOH = 10 mA AVDD3 = 3.3 V, IOH = 1 mA AVDD3 = 1.8 V, IOH = 1 mA Output Voltage Low (VOL) AVDD3 = 3.3 V, IOL = 10 mA AVDD3 = 3.3 V, IOL = 1 mA AVDD3 = 1.8 V, IOL = 1 mA 1.125 1.26 13 OUT5 only; OUT0 to OUT4 minimum output frequency is 360 kHz 100 termination across the output pair Voltage swing between output pins; output driver static Absolute difference between voltage swing of normal pin and inverted pin; output driver static 0.000352 150 MHz OUT5 only; OUT0 to OUT4 minimum output frequency is 360 kHz 10 pF load 0.000352 0.000352 250 25 MHz MHz 10 pF load 10 pF load 1.5 3 ns 10 pF load 0.4 8 0.6 ns ns 10 pF load 10 pF load % % % 10 pF load 10 pF load 10 pF load Output driver static; strong drive strength 50 47 51 AVDD3 - 0.3 AVDD3 - 0.1 AVDD - 0.2 V V V Output driver static; strong drive strength 0.3 0.1 0.1 Rev. B | Page 9 of 104 V V V AD9558 Parameter OUTPUT TIMING SKEW Between OUT0 and OUT1 Data Sheet Typ Max Unit 10 70 ps Between OUT0 and OUT3 105 222 ps Between OUT0 and OUT5 1.39 1.76 ns Between OUT1 and OUT2 (OUT1 and OUT2 Share the Same Divider) Between OUT3 and OUT4 (OUT3 and OUT4 Share the Same Divider) Across All OUT0 to OUT4 HSTL 1 12 ps 1 24 ps HSTL mode on both drivers; rising edge only; any divide value 105 235 ps Across All OUT0 to OUT4 LVDS 100 235 ps HSTL mode on all drivers; rising edge only; any divide value LVDS mode on all drivers; rising edge only; any divide value -5 +1 +5 ps -5 0 +5 ps 3.53 3.55 3.56 4.84 3.59 3.65 3.68 5.1 ns ns ns ns Typ Max Unit Test Conditions/Comments 13 20 ms 138 145 ms Using default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E3F) Using default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E3F) Time from power-down exit to system clock lock detect Additional Delay on One Driver by Changing Its Logic Type HSTL to LVDS HSTL to 1.8 V CMOS Min HSTL to 3.3 V CMOS, Strong Mode OUT0 CMOS to OUT1 HSTL OUT0 CMOS to OUT3 HSTL OUT0 CMOS to OUT4 HSTL OUT0 CMOS to OUT5 HSTL 1 Test Conditions/Comments 10 pF load HSTL mode on both drivers; rising edge only; any divide value HSTL mode on both drivers; rising edge only; any divide value HSTL mode on both drivers; rising edge only; any divide value HSTL mode on both drivers; rising edge only; any divide value Positive value indicates that the LVDS edge is delayed relative to HSTL Positive value indicates that the CMOS edge is delayed relative to HSTL The CMOS edge is delayed relative to HSTL The listed values are for the slower edge (rise or fall). TIME DURATION OF DIGITAL FUNCTIONS Table 11. Parameter TIME DURATION OF DIGITAL FUNCTIONS EEPROM-to-Register Download Time Register-to-EEPROM Upload Time Minimum Power-Down Exit Time Min 1 ms Rev. B | Page 10 of 104 Data Sheet AD9558 DIGITAL PLL Table 12. Parameter DIGITAL PLL Phase-Frequency Detector (PFD) Input Frequency Range Loop Bandwidth Phase Margin Closed-Loop Peaking Reference Input (R) Division Factor Integer Feedback (N1) Division Factor Fractional Feedback Divide Ratio Min Typ Max Unit 2 100 kHz 0.1 30 <0.1 2000 89 Hz Degrees dB 1 180 0 220 217 0.999 Test Conditions/Comments Programmable design parameter Programmable design parameter Programmable design parameter ; part can be programmed for <0.1 dB peaking in accordance with Telcordia GR-253 jitter transfer 1, 2, ..., 1,048,576 180, 181, ..., 131,072 Maximum value: 16,777,215/16,777,216 DIGITAL PLL LOCK DETECTION Table 13. Parameter PHASE LOCK DETECTOR Threshold Programming Range Threshold Resolution FREQUENCY LOCK DETECTOR Threshold Programming Range Threshold Resolution Min Typ 0.001 Max Unit 65.5 ns ps 16,700 ns ps Reference-to-feedback period difference Max Unit Test Conditions/Comments ppm Excludes frequency drift of SYSCLK source; excludes frequency drift of input reference prior to entering holdover; compliant with GR-1244 Stratum 3 1 0.001 1 Test Conditions/Comments HOLDOVER SPECIFICATIONS Table 14. Parameter HOLDOVER SPECIFICATIONS Initial Frequency Accuracy Min Typ <0.01 Rev. B | Page 11 of 104 AD9558 Data Sheet SERIAL PORT SPECIFICATIONS--SPI MODE Table 15. Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO As an Input Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance As an Output Output Logic 1 Voltage Output Logic 0 Voltage SDO Output Logic 1 Voltage Output Logic 0 Voltage TIMING SCLK Clock Rate, 1/tCLK Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup (tS) CS to SCLK Hold (tC) CS Minimum Pulse Width High Min Typ Max Unit Test Conditions/Comments E A E A A E A A E A A 2.0 0.8 60 100 2 V V A A pF 2.0 0.8 200 1 2 V V A A pF 2.0 0.8 1 1 2 V V A A pF Internal 30 k pull-down resistor DVDD3 - 0.6 0.4 V V 1 mA load current 1 mA load current 0.4 V V 1 mA load current 1 mA load current DVDD3 - 0.6 40 10 13 3 6 10 10 0 6 Rev. B | Page 12 of 104 MHz ns ns ns ns ns ns ns ns Data Sheet AD9558 SERIAL PORT SPECIFICATIONS--I2C MODE Table 16. Parameter SDA, SCL (AS INPUT) Input Logic 1 Voltage Min Typ Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSP SDA (AS OUTPUT) Output Logic 0 Voltage Output Fall Time from VIHmin to VILmax TIMING SCL Clock Rate Bus-Free Time Between a Stop and Start Condition, tBUF Repeated Start Condition Setup Time, tSU; STA Repeated Hold Time Start Condition, tHD; STA Stop Condition Setup Time, tSU; STO Low Period of the SCL Clock, tLOW High Period of the SCL Clock, tHIGH SCL/SDA Rise Time, tR SCL/SDA Fall Time, tF Data Setup Time, tSU; DAT Data Hold Time, tHD; DAT Capacitive Load for Each Bus Line, Cb1 1 Unit Test Conditions/Comments V 0.7 x DVDD3 Input Logic 0 Voltage Input Current Hysteresis of Schmitt Trigger Inputs Max V 0.3 x DVDD3 +10 A 50 ns 0.4 250 V ns 400 1.3 kHz s 0.6 0.6 s s 0.6 1.3 0.6 20 + 0.1 Cb1 20 + 0.1 Cb1 100 100 s s s ns ns ns ns pF -10 0.015 x DVDD3 20 + 0.1 Cb 1 2F 300 300 400 For VIN = 10% to 90% DVDD3 IO = 3 mA 10 pF Cb 400 pF After this period, the first clock pulse is generated Cb is the capacitance (pF) of a single bus line. JITTER GENERATION Jitter generation (random jitter) uses 49.152 MHz crystal for system clock input. Table 17. Parameter JITTER GENERATION fREF = 19.44 MHz; fOUT = 622.08 MHz; fLOOP = 50 Hz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz Min Typ Max 304 296 300 266 185 Rev. B | Page 13 of 104 Unit fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments System clock doubler enabled; high phase margin mode enabled; Register 0x0405 = 0x20; Register 0x0403 = 0x07; Register 0x0400 = 0x81; in cases where multiple driver types are listed, both driver types were tested at those conditions, and the one with higher jitter is quoted, although there is usually not a significant jitter difference between the driver types AD9558 Parameter fREF = 19.44 MHz; fOUT = 644.53 MHz; fLOOP = 50 Hz HSTL and/or LVDS Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz fREF = 19.44 MHz; fOUT = 693.48 MHz; fLOOP = 50 Hz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz fREF = 19.44 MHz; fOUT = 174.703 MHz; fLOOP = 1 kHz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz fREF = 19.44 MHz; fOUT = 174.703 MHz; fLOOP = 100 Hz LVDS and/or 3.3 V CMOS Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz fREF = 25 MHz; fOUT = 161.1328 MHz; fLOOP = 100 Hz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz fREF = 2 kHz; fOUT = 70.656 MHz; fLOOP = 100 Hz; HSTL and/or 3.3 V CMOS Driver Bandwidth: 10 Hz to 30 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 10 kHz to 400 kHz Bandwidth: 100 kHz to 10 MHz fREF = 25 MHz; fOUT = 1 GHz; fLOOP = 500 Hz HSTL Driver Bandwidth: 100 Hz to 500 MHz (Broadband) Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Data Sheet Min Typ Max Unit 334 321 319 277 185 fs rms fs rms fs rms fs rms fs rms 298 285 286 252 183 fs rms fs rms fs rms fs rms fs rms 354 301 321 290 177 fs rms fs rms fs rms fs rms fs rms 306 293 313 283 166 fs rms fs rms fs rms fs rms fs rms 316 302 324 292 171 fs rms fs rms fs rms fs rms fs rms 3.22 ps rms fs rms fs rms fs rms fs rms 338 324 278 210 1.71 343 338 Rev. B | Page 14 of 104 ps rms fs rms fs rms Test Conditions/Comments Data Sheet AD9558 Jitter generation (random jitter) uses 19.2 MHz TCXO for system clock input. Table 18. Parameter JITTER GENERATION fREF = 19.44 MHz; fOUT = 644.53 MHz; fLOOP = 0.1 Hz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz fREF = 19.44 MHz; fOUT = 693.48 MHz; fLOOP = 0.1 Hz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz fREF = 19.44 MHz; fOUT = 312.5 MHz; fLOOP = 0.1 Hz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz fREF = 25 MHz; fOUT = 161.1328 MHz; fLOOP = 0.1 Hz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz fREF = 2 kHz; fOUT = 70.656 MHz; fLOOP = 0.1 Hz HSTL and/or 3.3 V CMOS Driver Bandwidth: 10 Hz to 30 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 10 kHz to 400 kHz Bandwidth: 100 kHz to 10 MHz Min Typ Max Unit 402 393 391 347 179 fs rms fs rms fs rms fs rms fs rms 379 371 371 335 175 fs rms fs rms fs rms fs rms fs rms 413 404 407 358 142 fs rms fs rms fs rms fs rms fs rms 399 391 414 376 190 fs rms fs rms fs rms fs rms fs rms 970 404 374 281 fs rms fs rms fs rms fs rms Rev. B | Page 15 of 104 Test Conditions/Comments System clock doubler enabled; high phase margin mode enabled; Register 0x0405 = 0x20; Register 0x0403 = 0x07; Register 0x0400 = 0x81; in cases where multiple driver types are listed, both driver types were tested at those conditions, and the one with higher jitter is quoted, although there is usually not a significant jitter difference between the driver types AD9558 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 19. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD3) Analog Supply Voltage (AVDD3) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 2V 2V 3.6 V 3.6 V -0.5 V to DVDD3 + 0.5 V -65C to +150C -40C to +85C 300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 150C Rev. B | Page 16 of 104 Data Sheet AD9558 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVDD3 M6 M5 M4 M3 M2 M1 M0 DVDD DVDD REFB REFB DVDD3 DVDD3 REFD REFD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD9558 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 REFC REFC DVDD3 DVDD3 REFA REFA SYNC M7 PINCONTROL RESET AVDD AVDD NC AVDD NC LF_VCO2 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS). 09758-002 AVDD OUT2 OUT2 OUT1 OUT1 AVDD OUT5 OUT5 AVDD3 AVDD3 OUT0 OUT0 AVDD AVDD AVDD3 LDO_VCO2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IRQ SCLK/SCL SDIO/SDA SDO CS DVDD AVDD XOA XOB AVDD NC AVDD OUT4 OUT4 OUT3 OUT3 Figure 2. Pin Configuration Table 20. Pin Function Descriptions Pin No. 1 2 Mnemonic IRQ SCLK/SCL Input/ Output O I Pin Type 3.3 V CMOS 3.3 V CMOS 3 SDIO/SDA I/O 3.3 V CMOS 4 SDO O 3.3 V CMOS CS I 3.3 V CMOS 5 E A 6, 55, 56 7 8 DVDD AVDD XOA I I I Power Power Differential input 9 XOB I Differential input 10 11 12, 17, 22, 29, 30 AVDD NC AVDD I I I Power Power Description Interrupt Request Line. Serial Programming Clock (SCLK) in SPI Mode. Data clock for serial programming. Open-Collector Serial Clock Pin (SCL) in I2C Mode. Requires a pull-up resistor, usually 2.2 k; the resistor size depends on the number of I2C devices on the bus. Serial Data Input/Output (SDIO) in SPI Mode. When the device is in 4-wire SPI mode, data is written via this pin. In 3-wire SPI mode, both data reads and writes occur on this pin. There is no internal pull-up/pull-down resistor on this pin. Open-Collector Serial Data Pin (SDA) in I2C Mode. Requires a pull-up resistor, usually 2.2 k; the resistor size depends on the number of I2C devices on the bus. Serial Data Output. Use this pin to read data in 4-wire mode. There is no internal pull-up/ pull-down resistor on this pin. This pin is high impedance in the default 3-wire mode. Chip Select (SPI), Active Low. When programming a device, this pin must be held low. In systems where more than one AD9558 is present, this pin enables individual programming of each AD9558. This pin has an internal 10 k pull-up resistor. 1.8 V Digital Supply. 1.8 V Analog (SYSCLK) Power Supply. System Clock Input. XOA contains internal dc biasing and should be ac-coupled with a 0.01 F capacitor, except when using a crystal. If a crystal is used, connect the crystal across XOA and XOB. Single-ended 1.8 V CMOS is also an option but can introduce a spur if the duty cycle is not 50%. When using XOA as a single-ended input, connect a 0.01 F capacitor from XOB to ground. Complementary System Clock Input. Complementary signal to XOA. XOB contains internal dc biasing and should be ac-coupled with a 0.01 F capacitor, except when using a crystal. If a crystal is used, connect the crystal across XOA and XOB. 1.8 V Analog (VCO) Power Supply. No Connection. Do not connect to this pin. 1.8 V Analog (Output Driver) Power Supply. Rev. B | Page 17 of 104 AD9558 Data Sheet Pin No. 13 Mnemonic OUT4 Input/ Output O 14 OUT4 O OUT3 O OUT3 O OUT2 O OUT2 O OUT1 O OUT1 O OUT5 O 24 OUT5 O 25, 26 27 AVDD3 OUT0 I O 28 OUT0 O 31 32 AVDD3 LDO_VCO2 I I Power LDO bypass 33 LF_VCO2 I/O Loop filter 34 35 36 37, 38 39 NC AVDD NC AVDD RESET I Power I I Power 3.3 V CMOS 40 PINCONTROL I 3.3 V CMOS 41 M7 I/O 3.3 V CMOS I 3.3 V CMOS E 15 A E 16 A 18 E 19 A 20 E 21 A 23 42 A E A E A E SYNC A E Pin Type HSTL, LVDS, or 1.8 V CMOS HSTL, LVDS, or 1.8 V CMOS HSTL, LVDS, or 1.8 V CMOS HSTL, LVDS, or 1.8 V CMOS HSTL, LVDS, or 1.8 V CMOS HSTL, LVDS, or 1.8 V CMOS HSTL, LVDS, or 1.8 V CMOS HSTL, LVDS, or 1.8 V CMOS HSTL, LVDS, 1.8 V CMOS, 3.3 V CMOS HSTL, LVDS, 1.8 V CMOS, 3.3 V CMOS Power HSTL, LVDS, 1.8 V CMOS, 3.3 V CMOS HSTL, LVDS, 1.8 V CMOS, 3.3 V CMOS Description Complementary Output 4. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. Output 4. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section. Complementary Output 3. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. Output 3. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section. Complementary Output 2. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. Output 2. This output can be HSTL, LVDS, or single-ended 1.8 V CMOS. LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section. Complementary Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section. Complementary Output 5. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V CMOS. Output 5. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V CMOS. LVPECL levels can be achieved by ac coupling and by using the Theveninequivalent termination as described in the Input/Output Termination Recommendations section. 3.3 V Analog (Output Driver) Power Supply. Complementary Output 0. This output can be configured as HSTL, LVDS, or singleended 1.8 V or 3.3 V CMOS. Output 0. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V CMOS. LVPECL levels can be achieved by ac coupling and by using the Theveninequivalent termination as described in the Input/Output Termination Recommendations section. 3.3V Analog (VCO 2) Power Supply. Output PLL Loop Filter Voltage Regulator. Connect a 0.47 F capacitor from this pin to ground. This pin is also the ac ground reference for the integrated output PLL external loop filter. Loop Filter Node for the Output PLL. Connect an external 6.8 nF capacitor from this pin to Pin 32 (LDO_VCO2). No Connect. There is no internal connection for this pin. 1.8 V Analog (APLL) Power Supply. No Connect. There is no internal connection for this pin. 1.8 V Analog (DCO and TDC) Power Supplies. Chip Reset. When this active low pin is asserted, the chip goes into reset. This pin has an internal 50 k pull-up resistor. Pin Program Mode Enable Pin. When pulled high during startup, this pin enables pin programming of the AD9558 configuration during startup. If this pin is low during startup, the user must program the part via the serial port, or use values that are stored in the EEPROM. Configurable I/O Pin. Along with pins M6 through M0, this pin is configured through the AD9558 register space. Clock Distribution Synchronization Pin. When this pin is activated, output drivers are held static and then synchronized on a low-to-high transition of this pin. This pin is used to arm the frame sync function when frame sync mode is enabled and has an internal 60 k pull-up resistor. Rev. B | Page 18 of 104 Data Sheet Pin No. 43 Mnemonic REFA Input/ Output I REFA I 44 A Differential input Power I REFC I Differential input I Differential input Differential input 48 REFC A E REFD I REFD I REFB I REFB I M0, M1, M2, M3, M4, M5, M6 I/O Differential input 3.3 V CMOS DVDD3 VSS I O Power Exposed pad 49 50 A E 53 57, 58, 59, 60, 61, 62, 63 64 EP E Pin Type Differential input DVDD3 45, 46, 51, 52 47 54 AD9558 A E Differential input Differential input Description Reference A Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS. Complementary Reference A Input. This pin is the complementary input to Pin 43. 3.3 V Digital (Reference Input) Power Supply. Reference C Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS. Complementary Reference C Input. This pin is the complementary input to Pin 47. Reference D Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS. Complementary Reference D Input. This pin is the complementary input to Pin 49. Reference B Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS. Complementary Reference B Input. This pin is the complementary input to Pin 53. Configurable I/O Pins. These pins are configured under program control. The M7 pin (Pin 41) is the last pin of this group. 3.3 V Digital Supply. The exposed pad must be connected to ground (VSS). Rev. B | Page 19 of 104 AD9558 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS fR = input reference clock frequency; fOUT = output clock frequency; fSYS = SYSCLK input frequency; fS = internal system clock frequency; LF = SYSCLK PLL internal loop filter used. AVDD, AVDD3, and DVDD at nominal supply voltage; fS = 786.432 MHz, unless otherwise noted. -60 -60 INTEGRATED RMS JITTER (12kHz TO 20MHz): 285fs -70 -80 -80 -90 -100 -110 -120 -130 -90 -100 -110 -120 -130 -140 -140 -150 -150 -160 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) -160 100 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 3. Absolute Phase Noise (Output Driver = HSTL), fR = 19.44 MHz, fOUT = 622.08 MHz, DPLL Loop BW = 50 Hz, fSYS = 49.152 MHz Crystal Figure 5. Absolute Phase Noise (Output Driver = HSTL), fR = 19.44 MHz, fOUT = 693.482991 MHz, DPLL Loop BW = 50 Hz, fSYS = 49.152 MHz Crystal -60 -70 INTEGRATED RMS JITTER (12kHz TO 20MHz): 301fs INTEGRATED RMS JITTER (12kHz TO 20MHz): 320fs -70 -80 -80 PHASE NOISE (dBc/Hz) -90 -90 -100 -110 -120 -130 -100 -110 -120 -130 -140 -140 -160 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 4. Absolute Phase Noise (Output Driver = HSTL), fR = 19.44 MHz, fOUT = 644.53125 MHz, DPLL Loop BW = 50 Hz, fSYS = 49.152 MHz Crystal -160 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 6. Absolute Phase Noise (Output Driver = HSTL), fR = 19.44 MHz, fOUT = 174.703 MHz, DPLL Loop BW = 1 kHz, fSYS = 49.152 MHz Crystal Rev. B | Page 20 of 104 09758-006 -150 -150 09758-004 PHASE NOISE (dBc/Hz) 1k 09758-005 PHASE NOISE (dBc/Hz) -70 09758-003 PHASE NOISE (dBc/Hz) INTEGRATED RMS JITTER (12kHz TO 20MHz): 296fs Data Sheet AD9558 -80 -60 INTEGRATED RMS JITTER (12kHz TO 20MHz): 302fs INTEGRATED RMS JITTER (12kHz TO 20MHz): 393fs -70 -90 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) -80 -100 -110 -120 -130 -140 -90 -100 -110 -120 -130 -140 -150 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) -160 09758-007 1k 10 1M 10M 100M INTEGRATED RMS JITTER (12kHz TO 20MHz): 371s -70 -80 -80 -100 -110 -120 -130 -90 -100 -110 -120 -130 -140 -140 -150 -150 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) -160 09758-008 1k 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 8. Absolute Phase Noise (Output Driver = HSTL), fR = 2 kHz, fOUT = 125 MHz, DPLL Loop BW = 100 Hz, fSYS = 49.152 MHz Crystal 09758-011 PHASE NOISE (dBc/Hz) -90 Figure 11. Absolute Phase Noise (Output Driver = HSTL), fR = 19.44 MHz, fOUT = 693.482991 MHz, DPLL Loop BW = 0.1 Hz, fSYS = 19.2 MHz TCXO -70 -60 INTEGRATED RMS JITTER (12kHz TO 20MHz): 404fs INTEGRATED RMS JITTER (12kHz TO 20MHz): 343fs -70 -80 -80 PHASE NOISE (dBc/Hz) -90 -90 -100 -110 -120 -130 -100 -110 -120 -130 -140 -140 -150 1k 10k 100k 1M 10M FREQUENCY OFFSET (Hz) 100M 09758-009 -150 -160 Figure 9. Absolute Phase Noise (Output Driver = HSTL), fR = 25 MHz, fOUT = 1 GHz, DPLL Loop BW = 500 Hz, fSYS = 49.152 MHz Crystal 10 100 1k 10k 100k 1M 10M FREQUENCY OFFSET (Hz) Figure 12. Absolute Phase Noise (Output Driver = HSTL), fR = 19.44 MHz, fOUT = 312.5 MHz, DPLL Loop BW = 0.1 Hz, fSYS = 19.2 MHz TCXO Rev. B | Page 21 of 104 100M 09758-012 PHASE NOISE (dBc/Hz) 100k -60 INTEGRATED RMS JITTER (12kHz TO 20MHz): 308fs PHASE NOISE (dBc/Hz) 10k Figure 10. Absolute Phase Noise (Output Driver = HSTL), fR = 19.44 MHz, fOUT = 644.53 MHz, DPLL Loop BW = 0.1 Hz, fSYS = 19.2 MHz TCXO -70 -160 100 1k FREQUENCY OFFSET (Hz) Figure 7. Absolute Phase Noise (Output Driver = 3.3.V CMOS), fR = 19.44 MHz, fOUT = 161.1328125 MHz, DPLL Loop BW = 100 Hz, fSYS = 49.152 MHz Crystal -160 100 100 09758-010 -150 -160 100 AD9558 Data Sheet DIFFERENTIAL PEAK-TO-PEAK AMPLITUDE (V) -70 INTEGRATED RMS JITTER (12kHz TO 20MHz): 391fs -80 -100 -110 -120 -130 -140 -150 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) 1300 09758-116 0.9 LVDS BOOST MODE 0.8 0.7 LVDS DEFAULT 0.6 0.5 0.4 09758-014 -150 1.0 0 100 200 300 400 500 600 700 800 FREQUENCY (MHz) 09758-117 DIFFERENTIAL PEAK-TO-PEAK AMPLITUDE (V) INTEGRATED RMS JITTER (12kHz TO 20MHz): 395fs 100 1100 Figure 16. Amplitude vs. Toggle Rate, HSTL Mode (LVPECL-Compatible Mode) -70 10 1200 FREQUENCY (MHz) Figure 13. Absolute Phase Noise (Output Driver = 3.3 V CMOS), fR = 19.44 MHz, fOUT =161.1328125 MHz, DPLL Loop BW = 0.1 Hz, fSYS = 19.2 MHz TCXO -160 900 1.0 1000 FREQUENCY OFFSET (Hz) 1.1 800 100M 1.2 700 10M 1.3 600 1M 1.4 500 100k 1.5 300 10k 1.6 400 1k 1.7 200 100 1.8 0 10 09758-013 -160 1.9 100 PHASE NOISE (dBc/Hz) -90 2.0 Figure 17. Amplitude vs. Toggle Rate, LVDS Figure 14. Absolute Phase Noise (Output Driver = 1.8 V CMOS), fR = 2 kHz, fOUT = 70.656 MHz, DPLL Loop BW = 0.1 Hz, fSYS = 19.2 MHz TCXO 3.5 -60 INTEGRATED RMS JITTER (12kHz TO 20MHz): 388fs 3.3V CMOS PEAK-TO-PEAK AMPLITUDE (V) -70 -90 -100 -110 -120 -130 -140 3.0 2.5 2.0 1.8V CMOS 1.5 -160 10 100 1k 10k 100k 1M 10M FREQUENCY OFFSET (Hz) 100M Figure 15. Absolute Phase Noise (Output Driver = HSTL), fR = 19.44 MHz, fOUT = 644.53 MHz, fSYS = 19.2 MHz TCXO Holdover Mode 1.0 0 50 100 150 200 250 FREQUENCY (MHz) Figure 18. Amplitude vs. Toggle Rate with 10 pF Load, 3.3 V (Strong Mode) and 1.8 V CMOS Rev. B | Page 22 of 104 300 09758-118 -150 09758-016 PHASE NOISE (dBc/Hz) -80 AD9558 70 3.0 60 2.5 50 2.0 1.5 30 20 0.5 10 0 20 10 30 40 50 60 70 80 FREQUENCY (MHz) Figure 19. Amplitude vs. Toggle Rate with 10 pF Load, 3.3 V (Weak Mode) CMOS 0 0 50 100 150 200 FREQUENCY (MHz) Figure 22. Power Consumption vs. Frequency, One CMOS Driver on Output Driver Power Supply Only (Pin 12, Pin 17, Pin 22, and Pin 29) for 1.8 V CMOS Mode, or on Pin 25 and Pin 26 for 3.3 V CMOS Mode 1.0 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 DIFFERENTIAL AMPLITUDE (V) 0.8 OUTPUT CHANNEL 1 OR 2: BOTH HSTL DRIVERS ENABLED OUTPUT CHANNEL 1 OR 2: ONE HSTL DRIVER ENABLED OUTPUT CHANNEL 0 OR 3: HSTL DRIVER ENABLED 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 250 500 750 FREQUENCY (MHz) 1000 1250 -1.0 -1 0 1 3 2 4 5 TIME (ns) 09758-123 -0.8 09758-120 POWER (mW) 40 1.0 0 1.8V CMOS MODE 3.3V CMOS STRONG MODE 3.3V CMOS WEAK MODE 09758-122 POWER (mW) 3.5 09758-119 PEAK-TO-PEAK AMPLITUDE (V) Data Sheet Figure 23. Output Waveform, HSTL (400 MHz) Figure 20. Power Consumption vs. Frequency, HSTL Mode (Single Channel) on 1.8 V Output Driver Power Supply Only (Pin 12, Pin 17, Pin 22, and Pin29) 0.4 65 60 0.3 DIFFERENTIAL AMPLITUDE (V) OUTPUT CHANNEL 1 OR 2: BOTH LVDS DRIVERS ENABLED 55 50 POWER (mW) 45 40 35 OUTPUT CHANNEL 1 OR 2: ONE LVDS DRIVER ENABLED 30 25 OUTPUT CHANNEL 0 OR 3: LVDS DRIVER ENABLED 20 15 10 0.2 0.1 0 -0.1 -0.2 -0.3 0 100 200 300 400 500 FREQUENCY (MHz) 600 700 800 Figure 21. LVDS Power Consumption vs. Frequency on 1.8 V Output Driver Power Supply Only (Pin 12, Pin 17, Pin 22, and Pin 29) Rev. B | Page 23 of 104 -0.4 -1 0 1 2 3 TIME (ns) Figure 24. Output Waveform, LVDS (400 MHz) 4 09758-124 0 09758-121 5 AD9558 Data Sheet 3 3.4 0 3.0 -3 2.6 -6 1.8 1.4 1.0 0.2 0 1 2 3 4 5 6 7 8 TIME (ns) 9 10 11 12 13 14 15 1.9 LOOP BW = 2kHz; HIGH PHASE MARGIN; PEAKING: 0.097dB; -3dB: 1.23kHz -27 LOOP BW = 5kHz; HIGH PHASE MARGIN; PEAKING: 0.14dB; -3dB: 4.27kHz 100 1k 10k FREQUENCY OFFSET (Hz) 100k 3 0 1.5 -3 -6 LOOP GAIN (dB) 1.3 1.1 0.9 0.7 0.5 -9 -12 -15 -18 -21 2pF LOAD 10pF LOAD 0.3 LOOP BW = 100Hz; NORMAL PHASE MARGIN; PEAKING: 0.09dB; -3dB: 117Hz LOOP BW = 2kHz; NORMAL PHASE MARGIN; PEAKING: 1.6dB; -3dB: 2.69kHz -24 0.1 -27 0 1 2 3 4 5 6 7 8 TIME (ns) 9 10 11 12 13 14 15 -30 09758-127 -0.1 -1 10 Figure 26. Output Waveform, 1.8 V CMOS (100 MHz) 3.2 2.8 2.4 2.0 1.6 1.2 0.8 25 35 45 55 65 75 85 TIME (ns) 95 09758-128 0.4 15 1k 10k FREQUENCY OFFSET (Hz) 100k Figure 29. Closed-Loop Transfer Function for 100 Hz and 2 kHz Loop Bandwidth Settings; Normal Phase Margin Loop Filter Setting 2pF LOAD 10pF LOAD 5 100 09758-230 AMPLITUDE (V) -24 1.7 0 -5 LOOP BW = 100Hz; HIGH PHASE MARGIN; PEAKING: 0.06dB; -3dB: 69Hz Figure 28. Closed-Loop Transfer Function for 100 Hz, 2 kHz, and 5 kHz Loop Bandwidth Settings; High Phase Margin Loop Filter Setting (This is compliant with Telcordia GR-253 jitter transfer test for loop bandwidths < 2 kHz.) Figure 25. Output Waveform, 3.3 V CMOS (100 MHz, Strong Mode) AMPLITUDE (V) -18 -30 10 09758-126 -0.2 -1 -15 -21 2pF LOAD 10pF LOAD 0.6 -9 -12 09758-129 LOOP GAIN (dB) AMPLITUDE (V) 2.2 Figure 27. Output Waveform, 3.3 V CMOS (20 MHz, Weak Mode) Rev. B | Page 24 of 104 Data Sheet AD9558 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 10pF 0.1F XOA 0.1F XOB 10pF Figure 30. AC-Coupled LVDS or HSTL Output Driver (100 resistor can go on either side of decoupling capacitors and should be as close as possible to the destination receiver.) Figure 33. System Clock Input (XOA, XOB) in Crystal Mode (The recommended CLOAD = 10 pF is shown. The values of the 10 pF shunt capacitors shown here should equal the CLOAD of the crystal.) Z0 = 50 SINGLE-ENDED (NOT COUPLED) HSTL OR LVDS 100 3.3V CMOS TCXO LVDS OR 1.8V HSTL HIGH IMPEDANCE DIFFERENTIAL RECEIVER 82 82 3.3V LVPECL SINGLE-ENDED (NOT COUPLED) 1.8V HSTL 0.1F Z0 = 50 127 127 09758-132 AD9557/ AD9558 XOA 150 AD9557/ AD9558 XOB VS = 3.3V Z0 = 50 0.1F Figure 34. System Clock Input (XOA, XOB) When Using a TCXO/OCXO with 3.3 V CMOS Output Figure 31. DC-Coupled LVDS or HSTL Output Driver 0.1F 300 0.1F Z0 = 50 09758-131 AD9557/ AD9558 AD9557/ AD9558 09758-134 HSTL OR LVDS 10MHz TO 50MHz FUNDAMENTAL AT CUT CRYSTAL WITH 10pF LOAD CAPACITANCE 09758-133 100 09758-130 AD9557/ AD9558 DOWNSTREAM DEVICE WITH HIGH IMPEDANCE INPUT AND INTERNAL DC BIAS Figure 32. Interfacing the HSTL Driver to a 3.3 V LVPECL Input (This method incorporates impedance matching and dc biasing for bipolar LVPECL receivers. If the receiver is self-biased, the termination scheme shown in Figure 30 is recommended.) Rev. B | Page 25 of 104 AD9558 Data Sheet GETTING STARTED CHIP POWER MONITOR AND STARTUP The AD9558 monitors the voltage on the power supplies at power-up. When DVDD3 is greater than 2.35 V 0.1 V and DVDD and AVDD are greater than 1.4 V 0.05 V, the device generates a 20 ms reset pulse. The power-up reset pulse is internal and independent of the RESET pin. This internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing. Within 45 ns after the leading edge of the internal reset pulse, the M7 to M0 multifunction pins behave as high impedance digital inputs and continue to do so until programmed otherwise. The delay on the M7 to M0 pin function change is 45 ns for pin reset or soft reset. E A A During a device reset (either via the power-up reset pulse or the RESET pin), the multifunction pins (M7 to M0) behave as high impedance inputs, but upon removal of the reset condition, level-sensitive latches capture the logic pattern present on the multifunction pins. E A A MULTIFUNCTION PINS AT RESET/POWER-UP The AD9558 requires the user to supply the desired logic state to the PINCONTROL pin, as well as to the M7 to M0 pins. If PINCONTROL is high, the part is in hard pin programming mode. See the Pin Program Function Description section for details on hard pin programming. At startup, there are three choices for the M7 to M0 pins: pullup, pull-down, and floating. If the PINCONTROL pin is low, the M7 to M0 pins determine the following configurations: * * Following a reset, the M1 and M0 pins determine whether the serial port interface behaves according to the SPI or I2C protocol. Specifically, M0 = M1 = low selects the SPI interface, and any other value selects the I2C port. The 3level logic of M1 and M0 allows the user to select eight possible I2C addresses (see Table 24). The M3 and M2 pins select which of the eight possible EEPROM profiles are loaded, or if the EEPROM loading is bypassed. Leaving M3 and M2 floating at startup bypasses the EEPROM loading, and the factory defaults are used instead (see Table 22). DEVICE REGISTER PROGRAMMING WHEN USING A REGISTER SETUP FILE The evaluation software contains a programming wizard and a convenient graphical user interface that assists the user in determining the optimal configuration for the DPLL, APLL, and SYSCLK based on the desired input and output frequencies. It generates a register setup file with a .STP extension that is easily readable using a text editor. After using the evaluation software to create the setup file, use the following sequence to program the AD9557 once: 1. 2. Register 0x0A01 = 0x20 (set user free run mode). Register 0x0A02 = 0x02 (hold outputs in static SYNC). (Skip this step if using SYNC on DPLL phase lock or SYNC on DPLL frequency lock. See Register 0x0500[1:0].) 3. Register 0x0405 = 0x20 (clear APLL VCO calibration). 4. Write the register values in the STP file from Address 0x0000 to Address 0x032E. 5. Register 0x0005 = 0x01 (update all registers). 6. Write the rest of the registers in the STP file, starting at Address 0x0400. 7. Register 0x0405 = 0x21 (calibrate APLLon next I/O update). 8. Register 0x0403 = 0x07 (configure APLL). 9. Register 0x0400 = 0x81 (configure APLL). 10. Register 0x0005 = 0x01 (update all registers). 11. Register 0x0A01[5] = 0b (clear user free run mode). 12. Register 0x0005 = 0x01 (update all registers). REGISTER PROGRAMMING OVERVIEW This section provides an overview of the register blocks in the AD9558, describing what they do and why they are important. Registers Differing from Defaults for Optimal Performance Ensure that the following registers are programmed to the listed values for optimal performance: * * * Register 0x0405[7:4] = 0x2 Register 0x0403 = 0x07 Register 0x0400 = 0x81 If the silicon revision (Register 0x000A) equals 0x21 or higher, the values listed here are already the default values. Rev. B | Page 26 of 104 Data Sheet AD9558 Program the System Clock and Free Run Tuning Word Program the Clock Distribution Outputs The system clock multiplier (SYSCLK) parameters are at Register 0x0100 to Register 0x0108, and the free run tuning word is at Register 0x0300 to Register 0x0303. Use the following steps for optimal performance: The APLL output goes to the clock distribution block. The clock distribution parameters reside in Register 0x0500 to Register 0x0509. They include the following: 1. 2. 3. 4. 5. Set the system clock PLL input type and divider values. Set the system clock period. It is essential to program the system clock period because many of the AD9558 subsystems rely on this value. Set the system clock stability timer. It is highly recommended that the system clock stability timer be programmed. This is especially important when using the system clock multiplier and also applies when using an external system clock source, especially if the external source is not expected to be completely stable when power is applied to the AD9558. The system clock stability timer specifies the amount of time that the system clock PLL must be locked before the part declares that the system clock is stable. The default value is 50 ms. Program the free run tuning word. The free run frequency of the digital PLL (DPLL) determines the frequency appearing at the APLL input when free run mode is selected. The free run tuning word is at Register 0x0300 to Register 0x0303. The correct free run frequency is required for the APLL to calibrate and lock correctly. Set user free run mode (Register 0x0A01[5] = 1b). Initialize and Calibrate the Output PLL (APLL) The registers controlling the APLL are at Register 0x0400 to Register 0x0408. This low noise, integer-N PLL multiplies the DPLL output (which is usually 175 MHz to 200 MHz) to a frequency in the 3.35 GHz to 4.05 GHz range. After the system clock is configured and the free run tuning word is set in Register 0x0300 to Register 0x0303, the user can set the manual APLL VCO calibration bit (Register 0x0405[0]) and issue an I/O update (Register 0x0005[0]). This process performs the APLL VCO calibration. VCO calibration ensures that, at the time of calibration, the dc control voltage of the APLL VCO is centered in the middle of its operating range. It is important to remember the following points when calibrating the APLL VCO: * * * * * The system clock must be stable. The APLL VCO must have the correct frequency from the 30-bit DCO (digitally controlled oscillator) during calibration. The APLL VCO must be recalibrated any time the APLL frequency changes. APLL VCO calibration occurs on the low-to-high transition of the manual APLL VCO calibration bit, and this bit is not autoclearing. Therefore, this bit must be cleared (and an I/O update issued) before another APLL calibration is started. The best way to monitor successful APLL calibration is to monitor Bit 2 in Register 0x0D01 (APLL lock). * * * * * Output power-down control Output enable (disabled by default) Output synchronization Output mode control Output divider functionality See the Clock Distribution section for more information. Generate the Output Clock If Register 0x0500[1:0] is programmed for automatic clock distribution synchronization via the DPLL phase or frequency lock, the synthesized output signal appears at the clock distribution outputs. Otherwise, set and then clear the soft sync clock distribution bit (Register 0x0A02, Bit 1), or use a multifunction pin input (if programmed for use) to generate a clock distribution sync pulse, which causes the synthesized output signal to appear at the clock distribution outputs. Program the Multifunction Pins (Optional) This step is required only if the user intends to use any of the multifunction pins for status or control. The multifunction pin parameters are at Register 0x0200 to Register 0x0208. Program the IRQ Functionality (Optional) This step is required only if the user intends to use the IRQ feature. The IRQ monitor registers are at Register 0x0D02 to Register 0x0D09. If the desired bits in the IRQ mask registers at Register 0x020A to Register 0x020F are set high, the appropriate IRQ monitor bit at Register 0x0D02 to Register 0x0D07 is set high when the indicated event occurs. Individual IRQ events are cleared by using the IRQ clearing registers at Register 0x0A04 to Register 0x0A09, or by setting the clear all IRQs bit (Register 0x0A03[1]) to 1b. The default values of the IRQ mask registers are such that interrupts are not generated. The IRQ pin mode default is opendrain NMOS. Program the Watchdog Timer (Optional) This step is required only if the user intends to use the watchdog timer. The watchdog timer control is in Register 0x0210 and Register 0x0211 and is disabled by default. The watchdog timer is useful for generating an IRQ after a fixed amount of time. The timer is reset by setting the clear watchdog timer bit (Register 0x0A03[0]) to 1b. Rev. B | Page 27 of 104 AD9558 Data Sheet Program the Digital Phase-Locked Loop (DPLL) Program the Reference Profiles The DPLL parameters reside in Register 0x0300 to Register 0x032E. They include the following: The reference profile parameters reside in Register 0x0700 to Register 0x07E6. The AD9558 evaluation software contains a wizard that calculates these values based on the user's input frequency. See the Reference Profiles section for details on programming these functions. They include the following: * * * * * Free run frequency DPLL pull-in range limits DPLL closed-loop phase offset Phase slew control (for hitless reference switching) Tuning word history control (for holdover operation) Program the Reference Inputs The reference input parameters reside in Register 0x0600 to Register 0x0602. See the Reference Clock Input section for details on programming these functions. They include the following: * * * Reference power-down Reference logic family Reference priority * * * * * * * * Reference period Reference period tolerance Reference validation timer Selection of high phase margin loop filter coefficients DPLL loop bandwidth Reference prescaler (R divider) Feedback dividers (N1, N2, N3, FRAC1, and MOD1) Phase and frequency lock detector controls Generate the Reference Acquisition After the registers are programmed, the user can clear the user freerun bit (Register 0x0A01[5]) and issue an I/O update, using Register 0x0005[0] to invoke all of the register settings that are programmed up to this point. After the registers are programmed, the DPLL locks to the first available valid reference that has the highest priority. Rev. B | Page 28 of 104 Data Sheet AD9558 THEORY OF OPERATION XO OR XTAL SYNC RESET PINCONTROL M0 M1 M2 M3 M4 M5 M6 M7 IRQ XO FREQUENCIES 10MHz TO 180MHz XTAL: 10MHz TO 50MHz /M0 TO /M3b ARE 10-BIT INTEGER DIVIDERS 1 2kHz TO 1.25GHz SPI/I2C SPI/I2C SERIAL PORT EEPROM REFA REFA /2 REFB REFB /2 REFC REFC /2 REFD REFD /2 REGISTER SPACE ROM AND FSM /M0 MULTIFUNCTION I/O PINS (CONTROL AND STATUS READBACK) /2 RF DIVIDER 1 /3 TO /11 R DIVIDER (20-BIT) 17-BIT INTEGER FRAC1/ /N1 MOD1 DIGITAL LOOP FILTER OUT31 /M2 /M3 FRAME SYNC PULSE OUT31 OUT41 OUT41 /M3b 30-BIT NCO DIGITAL PLL (DPLL) OUT11 OUT11 OUT21 x2 TUNING WORD CLAMP AND HISTORY OUT01 OUT21 MAX 1.25GHz RF DIVIDER 2 /3 TO /11 FREE RUN TW DPFD FRAME SYNC MODE ONLY /M1 SYSTEM PFD/CP /N3 CLOCK MULTIPLIER LF 24b/24b RESOLUTION x2 OUT51 OUT51 /N2 OUTPUT PLL (APLL) REF MONITORING AUTOMATIC SWITCHING AD9558 x2 OUT0 PFD/CP LF 3.35GHz TO 4.05GHz 2kHz TO 8kHz FRAME SYNC SIGNAL LF_VCO2 09758-135 APLL STATUS 1OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz TO 1.25GHz; OUT5: 352Hz TO 1.25GHz Figure 35. Detailed Block Diagram OVERVIEW The AD9558 provides clocking outputs that are directly related in phase and frequency to the selected (active) reference, but with jitter characteristics that are governed by the system clock, the DCO, and the output PLL (APLL). The AD9558 supports up to four reference inputs and input frequencies ranging from 2 kHz to 1250 MHz. The core of this product is a digital phaselocked loop (DPLL). The DPLL has a programmable digital loop filter that greatly reduces jitter that is transferred from the active reference to the output. The AD9558 supports both manual and automatic holdover. While in holdover, the AD9558 continues to provide an output as long as the system clock is present. The holdover output frequency is a time average of the output frequency history just prior to the transition to the holdover condition. The device offers manual and automatic reference switchover capability if the active reference is degraded or fails completely. The AD9558 also has adaptive clocking capability that allows the DPLL divider ratios to be changed while the DPLL is locked. The AD9558 has a system clock multiplier, a digital PLL (DPLL), and an analog PLL (APLL). The input signal goes first to the DPLL, which performs the jitter cleaning and most of the frequency translation. The DPLL features a 30-bit digitally controlled oscillator (DCO) output that generates a signal in the 175 MHz to 200 MHz range. The DPLL output goes to an analog integer-N PLL (APLL), which multiplies the signal up to the 3.35 GHz to 4.05 GHz range. That signal is then sent to the clock distribution section, which has two divide-by-3 to divide-by-11 RF dividers that are cascaded with 10-bit integer (divide-by-1 to divide-by1024) channel dividers. The XOA and XOB pins provide the input for the system clock. These pins accept a reference clock in the 10 MHz to 600 MHz range, or a 10 MHz to 50 MHz crystal connected directly across the XOA and XOB pins. The system clock provides the clocks to the frequency monitors, the DPLL, and internal switching logic. The AD9558 has six output drivers, arranged into four channels. Each channel has a dedicated 10-bit programmable post divider. Channel 0 and Channel 3 have one driver each, and Channel 1 and Channel 2 have two drivers each. Each driver is programmable either as a single differential or dual single-ended CMOS output. The clock distribution section operates at up to 1250 MHz. In differential mode, the output drivers run on a 1.8 V power supply to offer very high performance with minimal power consumption. There are two differential modes: LVDS and 1.8 V HSTL. In 1.8 V HSTL mode, the voltage swing is compatible with LVPECL. If LVPECL signal levels are required, the designer can ac-couple the AD9558 output and use Thevenin-equivalent termination at the destination to drive the LVPECL inputs. In single-ended mode, each differential output driver can operate as two single-ended CMOS outputs. OUT0 and OUT5 support either 1.8 V or 3.3 V CMOS operation. OUT1 through OUT4 support only 1.8 V operation. Rev. B | Page 29 of 104 AD9558 Data Sheet REFERENCE CLOCK INPUTS Reference Validation Timer Four pairs of pins provide access to the reference clock receivers. To accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. Hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate. Each reference input has a dedicated validation timer. The validation timer establishes the amount of time that a previously faulted reference must remain unfaulted before the AD9558 declares it valid. The timeout period of the validation timer is programmable via a 16-bit register. The 16-bit number stored in the validation register represents units of milliseconds (ms), which yields a maximum timeout period of 65,535 ms. When configured for differential operation, the input receivers accommodate either ac- or dc-coupled input signals. The input receivers are capable of accepting dc-coupled LVDS and 2.5 V and 3.3 V LVPECL signals. The receiver is internally dc biased to handle ac-coupled operation, but there is no internal 50 or 100 termination. When configured for single-ended operation, the input receivers exhibit a pull-down load of 45 k (typical). Three user-programmable threshold voltage ranges are available for each single-ended receiver. REFERENCE MONITORS The accuracy of the input reference monitors depends on a known and accurate system clock period. Therefore, the functioning of the reference monitors is not operable until the system clock is stable. Reference Period Monitor Each reference input has a dedicated monitor that repeatedly measures the reference period. The AD9558 uses the reference period measurements to determine the validity of the reference based on a set of user-provided parameters in the profile register area of the register map. The monitor works by comparing the measured period of a particular reference input with the parameters stored in the profile register assigned to that same reference input. The parameters include the reference period, an inner tolerance, and an outer tolerance. A 40-bit number defines the reference period in units of femtoseconds (fs). The 40-bit range allows for a reference period entry of up to 1.1 ms. A 20-bit number defines the inner and outer tolerances. The value stored in the register is the reciprocal of the tolerance specification. For example, a tolerance specification of 50 ppm yields a register value of 1/(50 ppm) = 1/0.000050 = 20,000 (0x04E20). The use of two tolerance values provides hysteresis for the monitor decision logic. The inner tolerance applies to a previously faulted reference and specifies the largest period tolerance that a previously faulted reference can exhibit before it qualifies as nonfaulted. The outer tolerance applies to an already nonfaulted reference. It specifies the largest period tolerance that a nonfaulted reference can exhibit before being faulted. To produce decision hysteresis, the inner tolerance must be less than the outer tolerance. That is, a faulted reference must meet tighter requirements to become nonfaulted than a nonfaulted reference must meet to become faulted. It is possible to disable the validation timer by programming the validation timer to 0b. With the validation timer disabled, the user must validate a reference manually via the manual reference validation override controls register (Address 0x0A0B). Reference Validation Override Control The user also has the ability to override the reference validation logic and can either force an invalid reference to be treated as valid, or force a valid reference to be treated as an invalid reference. These controls are in Register 0x0A0B to Register 0x0A0D. REFERENCE PROFILES The AD9558 has an independent profile for each reference input. A profile consists of a set of device parameters such as the R divider and N divider, among others The profiles allow the user to prescribe the specific device functionality that should take effect when one of the input references becomes the active reference. The AD9558 evaluation software includes a frequency planning wizard that can configure the profile parameters, given the input and output frequencies. The user should not change a profile that is currently in use because unpredictable behavior may result. The user can either select free run or holdover mode or invalidate the reference input prior to changing it. REFERENCE SWITCHOVER An attractive feature of the AD9558 is its versatile reference switchover capability. The flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm that is coupled with register-based controls. This scheme provides the user with maximum control over the state machine that handles reference switchover. The main reference switchover control resides in the loop mode register (Address 0x0A01). The REF switchover mode bits (Register 0x0A01, Bits[4:2]) allow the user to select one of the five operating modes of the reference switchover state machine, as follows: * * * * * Rev. B | Page 30 of 104 Automatic revertive mode Automatic non-revertive mode Manual with automatic fallback mode Manual with holdover mode Full manual mode (without auto-holdover) Data Sheet AD9558 In the automatic modes, a fully automatic priority-based algorithm selects which reference is the active reference. When programmed for an automatic mode, the device chooses the highest priority valid reference. When both references have the same priority, REFA gets preference over REFB. However, the reference position is used only as a tie-breaker and does not initiate a reference switch. The following list gives an overview of the five operating modes: Automatic revertive mode. The device selects the highest priority valid reference and switches to a higher priority reference if it becomes available, even if the reference in use is still valid. In this mode, the user reference is ignored. Automatic non-revertive mode. The device stays with the currently selected reference as long as it is valid, even if a higher priority reference becomes available. The user reference is ignored in this mode. Manual with automatic fallback mode. The device uses the user reference for as long as it is valid. If it becomes invalid, the reference input with the highest priority is chosen in accordance with the priority-based algorithm. Manual with holdover mode. The user reference is the active reference until it becomes invalid. At that point, the device automatically goes into holdover. Manual mode without holdover. The user reference is the active reference, regardless of whether or not it is valid. The user also has the option to force the device directly into holdover or free run operation via the user holdover and user freerun bits. In free run mode, the free run frequency tuning word register defines the free run output frequency. In holdover mode, the output frequency depends on the holdover control settings (see the Holdover section). Phase Build-Out Reference Switching The AD9558 supports phase build-out reference switching, which is the term given to a reference switchover that completely masks any phase difference between the previous reference and the new reference. That is, there is virtually no phase change detectable at the output when a phase build-out switchover occurs. A diagram of the DPLL core of the AD9558 appears in Figure 36. The phase/frequency detector, feedback path, lock detectors, phase offset, and phase slew rate limiting that comprise this second generation DPLL are all digital implementations. The start of the DPLL signal chain is the reference signal, fR, which is the frequency of the reference input. A reference prescaler reduces the frequency of this signal by an integer factor, R + 1, where R is the 20-bit value stored in the appropriate profile register and 0 R 1,048,575. Therefore, the frequency at the output of the R-divider (or the input to the time-to-digital converter (TDC)) is fTDC A TDC samples the output of the R-divider. The TDC/PFD produces a time series of digital words and delivers them to the digital loop filter. The digital loop filter offers the following advantages: The DPLL includes a feedback divider that causes the digital loop to operate at an integer-plus-fractional multiple. The output of the DPLL is FRAC1 f OUT _ DPLL f TDC (N1 1) MOD1 where N1 is the 17-bit value stored in the appropriate profile registers (Register 0x0715 to Register 0x0717 for REFA). FRAC1 and MOD1 are the 24-bit numerators and denominators of the fractional feedback divider block. The fractional portion of the feedback divider can be bypassed by setting FRAC1 to 0, but MOD1 should never be 0. DPLL Overview SYSTEM CLOCK + TUNING WORD CLAMP AND HISTORY 17-BIT 24-BIT/24-BIT INTEGER RESOLUTION The DPLL output frequency is usually 175 MHz to 200 MHz for optimal performance. TO APLL FROM APLL 09758-136 DIGITAL LOOP FILTER x2 30-BIT NCO FRAC1/ MOD1 DPFD /N1 FREE RUN TW R DIVIDER (20-BIT) Determination of the filter response by numeric coefficients rather than by discrete component values The absence of analog components (R/L/C), which eliminates tolerance variations due to aging The absence of thermal noise associated with analog components The absence of control node leakage current associated with analog components (a source of reference feedthrough spurs in the output spectrum of a traditional analog PLL) The digital loop filter produces a time series of digital words at its output and delivers them to the frequency tuning input of a sigma-delta (-) modulator (SDM). The digital words from the loop filter steer the DCO frequency toward frequency and phase lock with the input signal (fTDC). DIGITAL PLL (DPLL) CORE FROM REF INPUT MUX fR R 1 Figure 36. Digital PLL Core Rev. B | Page 31 of 104 AD9558 Data Sheet TDC/PFD DPLL Digitally Controlled Oscillator Free Run Frequency The phase-frequency detector (PFD) is an all-digital block. It compares the digital output from the TDC (which relates to the active reference edge) with the digital word from the feedback block. It uses a digital code pump and digital integrator (rather than a conventional charge pump and capacitor) to generate the error signal that steers the DCO frequency toward phase lock. The AD9558 uses a - modulator (SDM) as a digitally controlled oscillator (DCO). The DCO free run frequency can be calculated from the following equation: Programmable Digital Loop Filter where FTW0 is the value in Register 0x0300 to Register 0x0303, and fSYS is the system clock frequency. See the System Clock section for information on calculating the system clock frequency. The AD9558 loop filter is a third order digital IIR filter that is analogous to the third order analog loop shown in Figure 37. C2 C3 09758-015 R2 2 FTW0 8 30 2 Adaptive Clocking R3 C1 f dco _ freerun f SYS Figure 37. Third Order Analog Loop Filter The AD9558 loop filter block features a simplified architecture in which the user enters the desired loop characteristics directly into the profile registers. This architecture makes the calculation of individual coefficients unnecessary in most cases, while still offering complete flexibility. The AD9558 has two preset digital loop filters: high (88.5) phase margin and normal (70) phase margin. The loop filter coefficients are stored in Register 0x0317 to Register 0x0322 for high phase margin and Register 0x0323 to Register 0x032E for normal phase margin. The high phase margin loop filter is intended for applications in which the closed-loop transfer function must not have greater than 0.1 dB of peaking. Bit 0 of the following registers selects which filter is used for each profile: Register 0x070E for Profile A, Register 0x074E for Profile B, Register 0x078E for Profile C, and Register 0x07CE for Profile D. The loop bandwidth for each profile is set in the following registers: Register 0x070F to Register 0x0711 for Profile A, Register 0x074F to Register 0x0751 for Profile B, Register 0x078F to Register 0x0791 for Profile C, and Register 0x07CF to Register 0x07D1 for Profile D. The two preset conditions should cover all of the intended applications for the AD9558. For special cases where these conditions must be modified, the tools for calculating these coefficients are available by contacting Analog Devices directly. The AD9558 can support adaptive clocking applications such as asynchronous mapping and demapping. In these applications, the output frequency can be dynamically adjusted by up to 100 ppm from the nominal output frequency without manually breaking the DPLL loop and reprogramming the part. This function is supported for REFA only, not REFB. The following registers are used in this function: Register 0x0717 (DPLL N1 divider) Register 0x0718 to Register 0x071A (DPLL FRAC1 divider) Register 0x071B to Register 0x071D (DPLL MOD1 divider) Writing to these registers requires an I/O update by writing 0x01 to Register 0x0005 before the new values take effect. To make small adjustments to the output frequency, the user can vary the FRAC1 and issue an I/O update. The advantage to using only FRAC1 to adjust the output frequency is that the DPLL does not briefly enter holdover. Therefore, the FRAC1 bit can be updated as fast as the phase detector frequency of the DPLL. Writing to the N1 and MOD1 dividers allows for larger changes to the output frequency. When the AD9558 detects that the N1 or MOD1 values have changed, it automatically enters and exits holdover for a brief instant without any disturbance in the output frequency. This limits how quickly the output frequency can be adapted. It is important to realize that the amount of frequency adjustment is limited to 100 ppm before the output PLL (APLL) needs a recalibration. Variations that are larger than 100 ppm are possible, but the ability of the AD9558 to maintain lock over temperature extremes may be compromised. It is also important to remember that the rate of change in output frequency depends on the DPLL loop bandwidth. Rev. B | Page 32 of 104 Data Sheet AD9558 DPLL Phase Lock Detector The DPLL contains an all-digital phase lock detector. The user controls the threshold sensitivity and hysteresis of the phase detector via the profile registers. The phase lock detector behaves in a manner analogous to water in a tub (see Figure 38). The total capacity of the tub is 4096 units with -2048 denoting empty, 0 denoting the 50% point, and +2048 denoting full. The tub also has a safeguard to prevent overflow. Furthermore, the tub has a low water mark at -1024 and a high water mark at +1024. To change the water level, the user adds water with a fill bucket or removes water with a drain bucket. The user specifies the size of the fill and drain buckets via the 8-bit fill rate and drain rate values in the profile registers. PREVIOUS STATE LOCKED UNLOCKED 2048 DRAIN RATE UNLOCK LEVEL -1024 09758-017 0 FILL RATE -2048 Figure 38. Lock Detector Diagram The water level in the tub is what the lock detector uses to determine the lock and unlock conditions. When the water level is below the low water mark (-1024), the detector indicates an unlock condition. Conversely, when the water level is above the high water mark (+1024), the detector indicates a lock condition. When the water level is between the marks, the detector simply holds its last condition. This concept appears graphically in Figure 38, with an overlay of an example of the instantaneous water level (vertical) vs. time (horizontal) and the resulting lock/unlock states. During any given PFD cycle, the detector either adds water with the fill bucket or removes water with the drain bucket (one or the other but not both). The decision of whether to add or remove water depends on the threshold level specified by the user. The phase lock threshold value is a 16-bit number stored in the profile registers and is expressed in picoseconds (ps). Thus, the phase lock threshold extends from 0 ns to 65.535 ns and represents the magnitude of the phase error at the output of the PFD. The phase lock detector compares each phase error sample at the output of the PFD to the programmed phase threshold value. If the absolute value of the phase error sample is less than or equal to the programmed phase threshold value, the detector control logic dumps one fill bucket into the tub. Otherwise, Note that when the AD9558 enters the free run or holdover mode, the DPLL phase lock detector indicates an unlocked state. However, when the AD9558 performs a reference switch, the lock detector state prior to the switch is preserved during the transition period. DPLL Frequency Lock Detector LOCK LEVEL 1024 it removes one drain bucket from the tub. Note that it is not the polarity of the phase error sample, but its magnitude relative to the phase threshold value, that determines whether to fill or drain. If more filling is taking place than draining, the water level in the tub eventually rises above the high water mark (+1024), which causes the phase lock detector to indicate lock. If more draining is taking place than filling, then the water level in the tub eventually falls below the low water mark (-1024), which causes the phase lock detector to indicate unlock. The ability to specify the threshold level, fill rate, and drain rate enables the user to tailor the operation of the phase lock detector to the statistics of the timing jitter associated with the input reference signal. The operation of the frequency lock detector is identical to that of the phase lock detector. The only difference is that the fill or drain decision is based on the period deviation between the reference and feedback signals of the DPLL instead of the phase error at the output of the PFD. The frequency lock detector uses a 24-bit frequency threshold register specified in units of picoseconds (ps). Thus, the frequency threshold value extends from 0 s to 16.777215 s. It represents the magnitude of the difference in period between the reference and feedback signals at the input to the DPLL. For example, if the reference signal is 1.25 MHz and the feedback signal is 1.38 MHz, the period difference is approximately 75.36 ns (|1/1,250,000 - 1/1,380,000| 75.36 ns). Frequency Clamp The AD9558 DPLL features a digital tuning word clamp that ensures that the DPLL output frequency stays within a defined range. This feature is very useful to eliminate undesirable behavior in cases where the reference input clocks may be unpredictable. The tuning word clamp is also useful to guarantee that the APLL never loses lock by ensuring that the APLL VCO frequency stays within its tuning range. Frequency Tuning Word History The AD9558 has the ability to track the history of the tuning word samples generated by the DPLL digital loop filter output. It does so by periodically computing the average tuning word value over a user-specified interval. This average tuning word is used during holdover mode to maintain the average frequency when no input references are present. Rev. B | Page 33 of 104 AD9558 Data Sheet LOOP CONTROL STATE MACHINE Switchover Switchover occurs when the loop controller switches directly from one input reference to another. The AD9558 handles a reference switchover by briefly entering holdover mode, loading the new DPLL parameters, and then immediately recovering. During the switchover event, however, the AD9558 preserves the status of the lock detectors to avoid phantom unlock indications. Holdover The holdover state of the DPLL is typically used when none of the input references are present, although the user can also manually engage holdover mode. In holdover mode, the output frequency remains constant. The accuracy of the AD9558 in holdover mode is dependent on the device programming and availability of tuning word history. Recovery from Holdover When in holdover mode and a valid reference becomes available, the device exits holdover operation. The loop state machine restores the DPLL to closed-loop operation, locks to the selected reference, and sequences the recovery of all the loop parameters based on the profile settings for the active reference. Note that, if the user holdover bit is set, the device does not automatically exit holdover when a valid reference is available. However, automatic recovery can occur after clearing the user holdover bit (Bit 6 in Register 0x0A01). Rev. B | Page 34 of 104 Data Sheet AD9558 SYSTEM CLOCK (SYSCLK) SYSTEM CLOCK INPUTS Functional Description The SYSCLK circuit provides a low jitter, stable, high frequency clock for use by the rest of the chip. The XOA and XOB pins connect to the internal SYSCLK multiplier. The SYSCLK multiplier can synthesize the system clock by connecting a crystal resonator across the XOA and XOB input pins or by connecting a low frequency clock source. The optimal signal for the system clock input is either a crystal in the 50 MHz range or an ac-coupled square wave with a 1 V p-p amplitude. System Clock Period For the AD9558 to accurately measure the frequency of incoming reference signals, the user must enter the system clock period into the nominal system clock period registers (Register 0x0103 to Register 0x0105). The SYSCLK period is entered in units of nanoseconds (ns). System Clock Details There are two internal paths for the SYSCLK input signal: low frequency non-xtal (LF) and crystal resonator (XTAL). Using a TCXO for the system clock is a common use for the LF path. Applications requiring DPLL loop bandwidths of less than 50 Hz or high stability in holdover require a TCXO. As an alternative to the 49.152 MHz crystal for these applications, the AD9558 reference design uses a 19.2 MHz TCXO, which offers excellent holdover stability and a good combination of low jitter and low spurious content. The 1.8 V differential receiver connected to the XOA and XOB pins is self-biased to a dc level of ~1 V, and ac coupling is strongly recommended. When a 3.3 V CMOS oscillator is in use, it is important to use a voltage divider to reduce the input high voltage to a maximum of 1.8 V. See Figure 34 for details on connecting a 3.3 V CMOS TCXO to the system clock input. The non-xtal input path permits the user to provide an LVPECL, LVDS, 1.8 V CMOS, or sinusoidal low frequency clock for multiplication by the integrated SYSCLK PLL. The LF path handles input frequencies from 3.5 MHz up to 100 MHz. However, when using a sinusoidal input signal, it is best to use a frequency that is in excess of 20 MHz. Otherwise, the resulting low slew rate can lead to substandard noise performance. Note that the non-xtal path includes an optional 2x frequency multiplier to double the rate at the input to the SYSCLK PLL and potentially reduce the PLL in-band noise. However, to avoid exceeding the maximum PFD rate of 150 MHz, the 2x frequency multiplier is only for input frequencies that are below 75 MHz. The XTAL path enables the connection of a crystal resonator (typically 10 MHz to 50 MHz) across the XOA and XOB input pins. An internal amplifier provides the negative resistance required to induce oscillation. The internal amplifier expects an AT cut, fundamental mode crystal with a maximum motional resistance of 100 . The following crystals, listed in alphabetical order, may meet these criteria. Analog Devices, Inc., does not guarantee their operation with the AD9558 nor does Analog Devices endorse one crystal supplier over another. The AD9558 reference design uses a 49.152 MHz crystal, which is high performance, low spurious content, and readily available. AVX/Kyocera CX3225SB ECS ECX-32 Epson/Toyocom TSX-3225 Fox FX3225BS NDK NX3225SA Siward SX-3225 Suntsu SCM10B48-49.152 MHz SYSTEM CLOCK MULTIPLIER The SYSCLK PLL multiplier is an integer-N design with an integrated VCO. It provides a means to convert a low frequency clock input to the desired system clock frequency, fSYS (750 MHz to 805 MHz). The SYSCLK PLL multiplier accepts input signals of between 3.5 MHz and 600 MHz, but frequencies that are in excess of 150 MHz require the system clock P-divider to ensure compliance with the maximum PFD rate (150 MHz). The PLL contains a feedback divider (N) that is programmable for divide values between 4 and 255. f SYS f OSC sysclk _ Ndiv sysclk _ Pdiv where: fOSC is the frequency at the XOA and XOB pins. sysclk_Ndiv is the value stored in Register 0x0100. sysclk_Pdiv is the system clock P divider that is determined by the setting of Register 0x0101[2:1]. If the system clock doubler is used, the value of sysclk_Ndiv should be half of its original value. The system clock multiplier features a simple lock detector that compares the time difference between the reference and feedback edges. The most common cause of the SYSCLK multiplier not locking is a non-50% duty cycle at the SYSCLK input while the system clock doubler is enabled. The non-xtal path also includes an input divider (M) that is programmable for divide-by-1, -2, -4, or -8. The purpose of the divider is to limit the frequency at the input to the PLL to less than 150 MHz (the maximum PFD rate). Rev. B | Page 35 of 104 AD9558 Data Sheet System Clock Stability Timer Because the reference monitors depend on the system clock being at a known frequency, it is important that the system clock be stable before activating the monitors. At initial powerup, the system clock status is not known, and, therefore, it is reported as being unstable. After the part has been programmed, the system clock PLL (if enabled) eventually locks. When a stable operating condition is detected, a timer is run for the duration that is stored in the system clock stability period registers. If at any time during this waiting period, the condition is violated, the timer is reset and halted until a stable condition is reestablished. After the specified period elapses, the AD9558 reports the system clock as stable. Rev. B | Page 36 of 104 Data Sheet AD9558 OUTPUT PLL (APLL) A diagram of the output PLL (APLL) is shown in Figure 39. Calibration of the APLL must be performed at startup and when the nominal input frequency to the APLL changes by more than 100 ppm, although the APLL maintains lock over voltage and temperature extremes without recalibration. Calibration centers the dc operating voltage at the input to the APLL VCO. INTEGER DIVIDER /N2 OUTPUT PLL DIVIDER (APLL) FROM DPLL PFD CP LF TO CLOCK DISTRIBUTION VCO2 3.35GHz TO 4.05GHz LF CAP 09758-138 LF_VCO2 Figure 39. Output PLL Block Diagram The APLL provides the frequency upconversion from the DPLL output to the 3.35 GHz to 4.05 GHz range, while also providing noise filtering on the DPLL output. The APLL reference input is the output of the DPLL. The feedback divider is an integer divider. The loop filter is partially integrated with the one external 6.8 nF capacitor. The nominal loop bandwidth for this PLL is 250 kHz, with 68 degrees of phase margin. The frequency wizard that is included in the evaluation software configures the APLL, and the user should not need to make changes to the APLL settings. However, there may be special cases where the user may wish to adjust the APLL loop bandwidth to meet a specific phase noise requirement. The easiest way to change the APLL loop BW is to adjust the APLL charge pump current in Register 0x0400. There is sufficient stability (68 of phase margin) in the APLL default settings to permit a broad range of adjustment without causing the APLL to be unstable. The user should contact Analog Devices directly if more detail is needed. APLL calibration at startup can be accomplished during initial register loading by following the instructions in the Device Register Programming When Using a Register Setup File section of this datasheet. To recalibrate the APLL VCO after the chip has been running, the user should first input the new settings (if any). Ensure that the system clock is still locked and stable, and that the DPLL is in free run mode with the free run tuning word set to the same output frequency that is used when the DPLL is locked. Use the following steps to calibrate the APLL VCO: 1. 2. 3. 4. 5. 6. Ensure that the system clock is locked and stable. Ensure that the DPLL is in user free run mode (Register 0x0A01[5] = 1b), and the free run tuning word is set. Write Register 0x0405 = 0x20. Write Register 0x0005 = 0x01. Write Register 0x0405 = 0x21. Write Register 0x0005 = 0x01. Monitor the APLL status using Bit 2 in Register 0x0D01. Rev. B | Page 37 of 104 AD9558 Data Sheet CLOCK DISTRIBUTION /M0 RF DIVIDER 1 /3 TO /11 MAX 1.25GHz FRAME SYNC MODE ONLY /M1 OUT01 OUT01 OUT11 OUT11 OUT21 FROM APLL (3.35GHz TO 4.05GHz) OUT21 RF DIVIDER 2 /3 TO /11 MAX 1.25GHz /M2 OUT31 OUT31 OUT41 OUT41 SYNC SIGNAL TO M0 TO M3 DIVIDERS CHANNEL SYNC BLOCK /M3 FRAME SYNC FRAME SYNC ENGAGED SIGNAL Fsync_ALIGN_METHOD SELECTED INPUT FRAME PULSE /M3b FRAME SYNC BLOCK x2 OUT51 OUT51 FRAME SYNC MONITOR OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz TO 1.25GHz; OUT5: 352Hz TO 1.25GHz. 09758-139 CHIP RESET SYNC/SOFT_SYNC Figure 40. Clock Distribution Block Diagram CLOCK DIVIDERS The channel divider blocks, M0, M1, M2, M3, and M3b, are 10-bit integer dividers with a divide range of 1 to 1023. The channel divider block contains duty cycle correction that guarantees 50% duty cycle for both even and odd divide ratios. All CMOS drivers feature a CMOS drive strength that allows the user to choose between a strong, high performance CMOS driver, or a lower power setting with less EMI and crosstalk. The best setting is application dependent. The output drivers can be individually powered down. For applications where LVPECL levels are required, the user should choose the HSTL mode, and ac-couple the output signal. See the Input/Output Termination Recommendations section for recommended termination schemes. OUTPUT ENABLE CLOCK DISTRIBUTION SYNCHRONIZATION Each of the output channels offers independent control of enable/ disable functionality via the distribution enable register. The distribution outputs use synchronization logic to control enable/disable activity to avoid the production of runt pulses and ensure that outputs with the same divide ratios become active/inactive in unison. Divider Synchronization OUTPUT POWER-DOWN OUTPUT MODE The user has independent control of the operating mode of each of the four output channels via the output clock distribution registers (Address 0x0500 to Address 0x0515). The operating mode control includes * * * * * Logic family and pin functionality Output drive strength Output polarity Divide ratio Phase of each output channel Channel 0 and Channel 3 provide 3.3 V CMOS, in addition to 1.8 V CMOS modes. Channel 1 and Channel 2 have 1.8 V CMOS, LVDS, and HSTL modes. The dividers in the clock distribution channels can be synchronized with each other. At power-up, the clock dividers are held static until a sync signal is initiated by the channel SYNC block. The following are possible sources of a SYNC signal, and these settings are found in Register 0x0500: * * * * * * Direct sync via Bit 2 of Register 0x0500 Direct sync via a sync op code (0xA1) in the EEPROM storage sequence during EEPROM loading DPLL phase or frequency lock A rising edge of the selected reference input The SYNC pin A multifunction pin configured for the SYNC signal E A A The APLL lock detect signal gates the SYNC signal from the channel sync block shown in Figure 40. The channel dividers receive a SYNC signal from the channel SYNC block only if the APLL is calibrated and locked, unless the APLL locked controlled sync bit (Register 0x0405[3]) is set. Rev. B | Page 38 of 104 Data Sheet AD9558 A channel can be programmed to ignore the sync function by setting the mask Channel x sync bits in Register 0x0500[7:4]. When programmed to ignore the sync, the channel ignores both the user initiated sync signal and the zero delay initiated sync signals, and the channel divider starts toggling, provided that the APLL is calibrated and locked, or if the APLL locked controlled sync bit (Register 0x0405[3]) is set. If the output SYNC function is to be controlled using an M pin, use the following steps: 1. 2. 3. First, enable the M pins by writing Register 0x0200 = 0x01. Issue an I/O update (Register 0x0005 = 0x01). Set the appropriate M pin function. If this process is not followed, a SYNC pulse is issued automatically. Rev. B | Page 39 of 104 AD9558 Data Sheet FRAME SYNCHRONIZATION The AD9558 provides frame synchronization function/mode. With this function, the AD9558 can take a pair consisting of a reference clock and a 2 kHz or 8 kHz frame pulse as input signals and generate a pair consisting of a synchronized output clock and an output frame pulse while the output frame pulse is synchronized with the input frame pulse also. The reference clock is used to synthesize the output clock and output frame pulse through DPLL/output PLL/distribution and the input frame pulse is used to control the phase of the output frame pulse. CLOCK OUTPUTS IN FRAME SYNCHRONIZATION MODE Frame synchronization is not supported in the soft or hard pin control mode. The AD9558 has six outputs (OUT0 to OUT5). In frame sync mode, the OUT0 and OUT5 form the pair of output clock (OUT0) and output frame pulse (OUT5). The frequency of OUT0 is required to have the integer relation with the frequency of the OUT5 (fOUT0 = M x fOUT5). The rest of the outputs (OUT1 to OUT4) do not participate in frame synchronization mode and are programmed and synchronized with each other the same as in normal mode (except for SYNC function). However, OUT1 to OUT4 should not be synchronized with the OUT0/OUT5. REFERENCE CONFIGURATION IN FRAME SYNCHRONIZATION MODE CONTROL REGISTERS FOR FRAME SYNCHRONIZATION MODE In frame synchronization mode, four AD9558 reference inputs (REFA/REFB/REFC/REFD) are arranged into two pairs of signals: REFA and REFC form a pair of input clock/input frame pulse with REFA as the input clock, and REFC as the frame pulse. REFB and REFD form the second pair of input clock/ input frame pulse with REFB as the input clock and REFD is the frame pulse. During reference switchover, only two input clocks, REFA and REFB, are assigned with a priority index. The two frame pulses, REFC and REFD, are not assigned with the priority index (the priority register bits in the profiles associated with input frame pulse are ignored). Each pair of input clock/ frame pulse participates in the reference selection as a group, and the valid state and priority of the pair are used in determining the reference selection. The priority of the pair is indicated by the priority index of the input clock in the pair. The frame synchronization function is enabled by setting Register 0x0640[0] to 1b. When Register 0x0640[0] = 1b, the following occurs: Users have the option to either include or exclude the valid state of input frame pulse in the reference selection by programming the validate Fsync reference bit (Register 0x0641[3]). When Register 0x0641[3] is programmed to 1b, the valid state of the input frame pulse and the valid state of the paired input clock are logically ANDed and the result is used to indicate the valid state of the pair. When validate Fsync ref is programmed to 0b, the valid state of the input frame pulse is excluded in reference selection and only the valid state of the input clock in the pair is used to indicate the valid state of the pair. The valid pair with the higher priority index is selected as the DPLL reference and input frame pulse to control the phase of the output frame pulse. If no pair is valid, the selection does not change and DPLL is switched to either holdover or free run mode, and the phase of the output frame pulse is not controlled by any of the input frame pulses. The five reference switchover modes for frame synchronization mode is the same as for normal mode. E A A * The frame synchronization control bits (Register 0x0641[3:0]) are enabled. The SYNC pin switches from SYNC function to frame SYNC function. In frame synchronization mode, SYNC cannot be used as clock distribution synchronization function as it is in normal mode. Instead it is used as the frame synchronization arm function. * E E A A A A E E A A A A When the AD9558 is in frame synchronization mode, the frame synchronization function can be armed by either the SYNC pin or the arm soft Fsync bit (Register 0x0641[0]), which is selected by the Fsync arm method bit (Register 0x0641[1]. A value of 0b (which is the default) selects the SYNC pin as the arm method. If SYNC is selected as arm method, SYNC = low means armed; if the register is selected as arm method, Register 0x0641[0] = 1b means armed. ARM means that once armed, the output frame pulse is edge aligned with the paired output clock edge after the rising edge of the input frame pulse. E A A E A A E A E A A A LEVEL SENSITIVE MODE AND ONE-SHOT MODE The frame synchronization can operate in level sensitive or oneshot mode as determined by the Fsync one shot bit (Register 0x0641[2]). When in level sensitive mode (Register 0x0641[2] = 0b) and the frame sync ARM signal is high, each rising edge of the selected input frame pulse signal is used to control the phase of the output frame pulse. When in one-shot mode, after the frame sync ARM signal is high, only the immediate next rising edge of the selected input frame pulse signal is used to control the phase of the output frame pulse (one time phase alignment). After that, the phase of the output frame pulse is not controlled by the selected input frame pulse. Instead, it follows the phase of the input clock of M3 divider. In either alignment control mode, the resolution of the phase realignment between the input frame pulse and the output frame pulse is one clock cycle of the paired clock output. Rev. B | Page 40 of 104 Data Sheet AD9558 M3b DIVIDER/OUT5 PROGRAMMING IN FRAME SYNCHRONIZATION MODE This means that in frame synchronization mode, the total divide ratio between the RF divider and OUT5 is M0 x M3 x M3b. In frame synchronization mode, the clock distribution signal path for OUT5 is changed, as follows: the OUT5 signal goes from the RF divider to the M0 divider, and then to the M3 and M3b dividers. The other important change is that the sync signal for the M3b divider is no longer the standard clock distribution sync. It is controlled by a signal derived from the input frame pulse. ACTIVE SYNC ACTIVE SYNC OUPUT CLOCK (OUT0) FRAME CLOCK INPUT (REFC/REFD) ENABLE Fsync (REGISTER 0x0640[0] = 1b) FRAME SYNC ARM (REGISTER OR SYNC PIN) NOTES 1. AFTER THE FRAME SYNC IS ARMED, THE FRAME CLOCK OUTPUT IS SYNCHRONIZED TO THE FRAME CLOCK INPUT. THE SKEW BETWEEN THE FRAME CLOCK INPUT AND FRAME CLOCK OUTPUT IS 15ns (NOMINAL) PLUS A DELAY OF 0.5 TO 1.5 OUTPUT CLOCK CYCLES. 09758-141 FRAME CLOCK (OUT5) Figure 41. Frame Synchronization in Level Sensitive Mode ACTIVE SYNC OUPUT CLOCK (OUT0) FRAME CLOCK INPUT (REFC/REFD) ENABLE Fsync (REGISTER 0x0640[0] = 1b) FRAME SYNC ARM (REGISTER OR SYNC PIN) NOTES 1. AFTER THE FRAME SYNC IS ARMED, THE FRAME CLOCK OUTPUT IS SYNCHRONIZED TO THE FRAME CLOCK INPUT. THE SKEW BETWEEN THE FRAME CLOCK INPUT AND FRAME CLOCK OUTPUT IS 15ns (NOMINAL) PLUS 0.5 TO 1.5 OUTPUT CLOCK CYCLES. Figure 42. Frame Synchronization in One Shot Mode ENABLE Fsync M3 DIVIDER FROM APLL M3b DIVIDER OUT5 ENABLE Fsync RF DIVIDER 1 LOGIC 0 OUT0 M0 DIVIDER ENABLE Fsync CLOCK DISTRIBUTION SYNC LOGIC DELAY OUTPUT SYNC LEVEL (RETIMED) ENABLE Fsync OUTPUT SYNC PULSE FRAME SYNC PULSE GENERATOR FRAME SYNC PULSE INPUT (ON REFC OR REFD) NOTES 1. THE ENABLE Fsync FUNCTION IN THE DIAGRAM IS CONTROLLED BY REGISTER 0x0640[0]. Figure 43. Frame Synchronization Implementation Rev. B | Page 41 of 104 09758-143 Fsync_arm (FROM EITHER THE SYNC PIN OR THE Arm Soft Fsync BIT IN REGISTER 0x0641[0]) 09758-142 FRAME CLOCK (OUT5) AD9558 Data Sheet STATUS AND CONTROL MULTIFUNCTION PINS (M7 TO M0) The AD9558 has eight digital CMOS I/O pins (M7 to M0) that are configurable for a variety of uses. To use these functions, the user must enable them by writing a 0x01 to Register 0x0200. The function of these pins is programmable via the register map. Each pin can control or monitor an assortment of internal functions based on the contents of Register 0x0201 to Register 0x0208. To monitor an internal function with a multifunction pin, write a Logic 1 to the most significant bit of the register associated with the desired multifunction pin. The value of the seven least significant bits of the register defines the control function, as shown in Table 129. To control an internal function with a multifunction pin, write a Logic 0 to the most significant bit of the register associated with the desired multifunction pin. The monitored function depends on the value of the seven least significant bits of the register, as shown in Table 130. If more than one multifunction pin operates on the same control signal, then internal priority logic ensures that only one multifunction pin serves as the signal source. The selected pin is the one with the lowest numeric suffix. For example, if both M0 and M3 operate on the same control signal, then M0 is used as the signal source and the redundant pins are ignored. At power-up, the multifunction pins can be used to force the device into certain configurations as defined in the initial pin programming section. This functionality, however, is valid only during power-up or following a reset, after which the pins can be reconfigured via the serial programming port or via the EEPROM. If the output SYNC function is to be controlled using an M pin, 1. 2. 3. First, enable the M pins by writing Register 0x0200 = 0x01. Issue an I/O update (Register 0x0005 = 0x01). Set the appropriate M pin function. If this process is not followed, a SYNC pulse is issued automatically. IRQ Pin The AD9558 has a dedicated interrupt request (IRQ) pin. Bits[1:0] of the IRQ pin output mode register (Register 0x0209) control how the IRQ pin asserts an interrupt based on the value of the two bits, as follows: 00--The IRQ pin is high impedance when deasserted and active low when asserted and requires an external pull-up resistor. 01--The IRQ pin is high impedance when deasserted and active high when asserted and requires an external pull-down resistor. 10--The IRQ pin is Logic 0 when deasserted and Logic 1 when asserted. 11--The IRQ pin is Logic 1 when deasserted and Logic 0 when asserted. (This is the default operating mode.) The AD9558 asserts the IRQ pin when any bit in the IRQ monitor register (Address 0x0D02 to Address 0x0D07) is a Logic 1. Each bit in this register is associated with an internal function that is capable of producing an interrupt. Furthermore, each bit of the IRQ monitor register is the result of a logical AND of the associated internal interrupt signal and the corresponding bit in the IRQ mask register (Address 0x020A to Address 0x020E). That is, the bits in the IRQ mask register have a one-to-one correspondence with the bits in the IRQ monitor register. When an internal function produces an interrupt signal and the associated IRQ mask bit is set, the corresponding bit in the IRQ monitor register is set. The user should be aware that clearing a bit in the IRQ mask register removes only the mask associated with the internal interrupt signal. It does not clear the corresponding bit in the IRQ monitor register. Note that the IRQ function detects a state change in the function that is being monitored. However, if IRQs are cleared (or if they are enabled for the first time), they do not generate for a preexisting condition. The state must change after the IRQs are enabled. For example, if REFA is already invalid before the REFA invalid IRQ is enabled, the IRQ does not generate. The IRQ pin is the result of a logical OR of all the IRQ monitor register bits. Thus, the AD9558 asserts the IRQ pin as long as any IRQ monitor register bit is a Logic 1. Note that it is possible to have multiple bits set in the IRQ monitor register. Therefore, when the AD9558 asserts the IRQ pin, it may indicate an interrupt from several different internal functions. The IRQ monitor register provides the user with a means to interrogate the AD9558 to determine which internal function produced the interrupt. Typically, when the IRQ pin is asserted, the user interrogates the IRQ monitor register to identify the source of the interrupt request. After servicing an indicated interrupt, the user should clear the associated IRQ monitor register bit via the IRQ clearing register (Address 0x0A04 to Address 0x0A09). The bits in the IRQ clearing register have a one-to-one correspondence with the bits in the IRQ monitor register. Note that the IRQ clearing register is autoclearing. The IRQ pin remains asserted until the user clears all of the bits in the IRQ monitor register that indicate an interrupt. It is also possible to collectively clear all of the IRQ monitor register bits by setting the clear all IRQs bit in the reset function register (Register 0x0A03, Bit 1). Note that this is an autoclearing bit. Setting this bit results in deassertion of the IRQ pin. Alternatively, the user can program any of the multifunction pins to clear all IRQs. This allows the user to clear all IRQs by means of a hardware pin rather than by using a serial I/O port operation. Rev. B | Page 42 of 104 Data Sheet AD9558 WATCHDOG TIMER EEPROM The watchdog timer is a general purpose programmable timer. To set the timeout period, the user writes to the 16-bit watchdog timer register (Address 0x0210 to Address 0x0211). A value of 0b in this register disables the timer. A nonzero value sets the timeout period in milliseconds (ms), giving the watchdog timer a range of 1 ms to 65.535 sec. The relative accuracy of the timer is approximately 0.1% with an uncertainty of 0.5 ms. EEPROM Overview If enabled, the timer runs continuously and generates a timeout event when the timeout period expires. The user has access to the watchdog timer status via the IRQ mechanism and the multifunction pins (M7 to M0). In the case of the multifunction pins, the timeout event of the watchdog timer is a pulse that lasts 32 system clock periods. There are two ways to reset the watchdog timer (thereby preventing it from causing a timeout event). The first is by writing a Logic 1 to the autoclearing clear watchdog bit in the reset functions register (Register 0x0A03, Bit 0). Alternatively, the user can program any of the multifunction pins to reset the watchdog timer. This allows the user to reset the timer by means of a hardware pin rather than by using a serial I/O port operation. The AD9558 contains an integrated 2048-byte, electrically erasable, programmable read-only memory (EEPROM). The AD9558 can be configured to perform a download at power-up via the multifunction pins (M3 and M2), but uploads and downloads can also be done on demand via the EEPROM control registers (Address 0x0E00 to Address 0x0E03). The EEPROM provides the ability to upload and download configuration settings to and from the register map. Figure 44 shows a functional diagram of the EEPROM. Register 0x0E10 to Register 0x0E3F represent a 53-byte EEPROM storage sequence area (referred to as the "scratch pad" in this section) that enables the user to store a sequence of instructions for transferring data to the EEPROM from the device settings portion of the register map. Note that the default values for these registers provide a sample sequence for saving/retrieving all of the AD9558 EEPROM-accessible registers. Figure 44 shows the connectivity between the EEPROM and the controller that manages data transfer between the EEPROM and the register map. The controller oversees the process of transferring EEPROM data to and from the register map. There are two modes of operation handled by the controller: saving data to the EEPROM (upload mode) or retrieving data from the EEPROM (download mode). In either case, the controller relies on a specific instruction set. DATA DATA EEPROM (0x000 TO 0x1FF) SCRATCH PAD ADDRESS POINTER SCRATCH PAD (EEPROM STORAGE SEQUENCE) (0x0E10 TO 0x0E45) REGISTER MAP Figure 44. EEPROM Functional Diagram Rev. B | Page 43 of 104 SERIAL INPUT/OUTPUT PORT 09758-024 DEVICE SETTINGS (0x0004 TO 0x0A0D) CONDITION (0E01 [3:0]) DATA DEVICE SETTINGS ADDRESS POINTER EEPROM ADDRESS POINTER EEPROM CONTROLLER M3 M2 AD9558 Data Sheet Table 21. EEPROM Controller Instruction Set Instruction Value (Hex) 0x00 to 0x7F Instruction Type Data Bytes Required 3 0x80 I/O update 1 0xA0 Calibrate 1 0xA1 Distribution sync 1 0xB0 to 0xCF Condition 1 0xFE Pause 1 0xFF End 1 Description A data instruction tells the controller to transfer data to or from the device settings part of the register map. A data instruction requires two additional bytes that together, indicate a starting address in the register map. Encoded in the data instruction is the number of bytes to transfer, which is one more than the instruction value. When the controller encounters this instruction while downloading from the EEPROM, it issues a soft I/O update. When the controller encounters this instruction while downloading from the EEPROM, it initiates a system clock calibration sequence. When the controller encounters this instruction while downloading from the EEPROM, it issues a sync pulse to the output distribution synchronization. B1 to CF are condition instructions and correspond to Condition 1 through Condition 31, respectively. B0 is the null condition instruction. See the EEPROM Conditional Processing section for details. When the controller encounters this instruction in the EEPROM storage sequence area while uploading to the EEPROM, it holds both the scratch pad address pointer and the EEPROM address pointer at its last value. This allows storage of more than one instruction sequence in the EEPROM. Note that the controller does not copy this instruction to the EEPROM during upload. When the controller encounters this instruction in the the EEPROM storage sequence area while uploading to the EEPROM, it resets both the register area address pointer and the EEPROM address pointer and then enters an idle state. When the controller encounters this instruction while downloading from the EEPROM, it resets the EEPROM address pointer and then enters an idle state. EEPROM Instructions Table 21 lists the EEPROM controller instruction set. The controller recognizes all instruction types whether it is in upload or download mode, except for the pause instruction, which is recognized only in upload mode. The I/O update, calibrate, distribution sync, and end instructions are mostly self-explanatory. The others, however, warrant further detail, as described in the following paragraphs. Data instructions are those that have a value from 0x000 to 0x7FF. A data instruction tells the controller to transfer data between the EEPROM and the register map. The controller requires the following two parameters to carry out the data transfer: * * The number of bytes to transfer The register map target address The controller decodes the number of bytes to transfer directly from the data instruction itself by adding one to the value of the instruction. For example, the 1A data instruction has a decimal value of 26; therefore, the controller knows to transfer 27 bytes (one more than the value of the instruction). When the controller encounters a data instruction, it knows to read the next two bytes in the scratch pad because these contain the register map target address. Note that, in the EEPROM scratch pad, the two registers that comprise the address portion of a data instruction have the MSB of the address in the D7 position of the lower register address. The bit weight increases from left to right, from the lower register address to the higher register address. Furthermore, the starting address always indicates the lowest numbered register map address in the range of bytes to transfer. That is, the controller always starts at the register map target address and counts upward regardless of whether the serial I/O port is operating in I2C, SPI LSB-first, or SPI MSB-first mode. As part of the data transfer process during an EEPROM upload, the controller calculates a 1-byte checksum and stores it as the final byte of the data transfer. As part of the data transfer process during an EEPROM download, however, the controller again calculates a 1-byte checksum value but compares the newly calculated checksum with the one that was stored during the upload process. If an upload/download checksum pair does not match, the controller sets the EEPROM fault status bit. If the upload/download checksums match for all data instructions encountered during a download sequence, the controller sets the EEPROM complete status bit. Condition instructions are those that have a value from B0 to CF. The B1 to CF condition instructions represent Condition 1 to Condition 31, respectively. The B0 condition instruction is special because it represents the null condition (see the EEPROM Conditional Processing section). Rev. B | Page 44 of 104 Data Sheet AD9558 A pause instruction, like an end instruction, is stored at the end of a sequence of instructions in the scratch pad. When the controller encounters a pause instruction during an upload sequence, it keeps the EEPROM address pointer at its last value. This way the user can store a new instruction sequence in the scratch pad and upload the new sequence to the EEPROM. The new sequence is stored in the EEPROM address locations immediately following the previously saved sequence. This process is repeatable until an upload sequence contains an end instruction. The pause instruction is also useful when used in conjunction with condition processing. It allows the EEPROM to contain multiple occurrences of the same registers, with each occurrence linked to a set of conditions (see the EEPROM Conditional Processing section). EEPROM Upload To upload data to the EEPROM, the user must first ensure that the write enable bit (Register 0x0E00, Bit 0) is set. Then, on setting the autoclearing save to EEPROM bit (Register 0x0E02, Bit 0), the controller initiates the EEPROM data storage process. Uploading EEPROM data requires that the user first write an instruction sequence into the scratch pad registers. During the upload process, the controller reads the scratch pad data byteby-byte, starting at Register 0x0E10 and incrementing the scratch pad address pointer, as it goes, until it reaches a pause or end instruction. As the controller reads the scratch pad data, it transfers the data from the scratch pad to the EEPROM (byte-by-byte) and increments the EEPROM address pointer accordingly, unless it encounters a data instruction. A data instruction tells the controller to transfer data from the device settings portion of the register map to the EEPROM. The number of bytes to transfer is encoded within the data instruction, and the starting address for the transfer appears in the next two bytes in the scratch pad. When the controller encounters a data instruction, it stores the instruction in the EEPROM, increments the EEPROM address pointer, decodes the number of bytes to be transferred, and increments the scratch pad address pointer. Then it retrieves the next two bytes from the scratch pad (the target address) and increments the scratch pad address pointer by 2. Next, the controller transfers the specified number of bytes from the register map (beginning at the target address) to the EEPROM. When it completes the data transfer, the controller stores an extra byte in the EEPROM to serve as a checksum for the transferred block of data. To account for the checksum byte, the controller increments the EEPROM address pointer by one more than the number of bytes transferred. Note that, when the controller transfers data associated with an active register, it actually transfers the buffered contents of the register (refer to the Buffered/Active Registers section for details on the difference between buffered and active registers). This allows for the transfer of nonzero autoclearing register contents. Note that conditional processing (see the EEPROM Conditional Processing section) does not occur during an upload sequence. EEPROM Download An EEPROM download results in data transfer from the EEPROM to the device register map. To download data, the user sets the autoclearing load from the EEPROM bit (Register 0x0E03, Bit 1). This commands the controller to initiate the EEPROM download process. During download, the controller reads the EEPROM data byte-by-byte, incrementing the EEPROM address pointer as it goes, until it reaches an end instruction. As the controller reads the EEPROM data, it executes the stored instructions, which includes transferring stored data to the device settings portion of the register map when it encounters a data instruction. Note that conditional processing (see the EEPROM Conditional Processing section) is applicable only when downloading. Automatic EEPROM Download Following a power-up, an assertion of the RESET pin, or a soft reset (Register 0x0000, Bit 5 = 1), if the PINCONTROL pin is low, and M3 and M2 are either high or low (see Table 22), the instruction sequence stored in the EEPROM executes automatically with one of eight conditions. If M3 and M2 are left floating and the PINCONTROL pin is low, the EEPROM is bypassed and the factory defaults are used. In this way, a previously stored set of register values downloads automatically on power-up or with a hard or soft reset. See the EEPROM Conditional Processing section for details regarding conditional processing and the way it modifies the download process. Table 22. EEPROM Setup M3 Low Low Low Open Open Open High High High Rev. B | Page 45 of 104 M2 Low Open High Low Open High Low Open High ID 1 2 3 4 0 5 6 7 8 EEPROM Download? Yes, EEPROM Condition 1 Yes, EEPROM Condition 2 Yes, EEPROM Condition 3 Yes, EEPROM Condition 4 No Yes, EEPROM Condition 5 Yes, EEPROM Condition 6 Yes, EEPROM Condition 7 Yes, EEPROM Condition 8 AD9558 Data Sheet EEPROM Conditional Processing The condition tag board is a table maintained by the EEPROM controller. When the controller encounters a condition instruction, it decodes the B1 through CF instructions as Condition = 1 through Condition = 8, respectively, and tags that particular condition in the condition tag board. However, the B0 condition instruction decodes as the null condition, for which the controller clears the condition tag board; and subsequent download instructions execute unconditionally (until the controller encounters a new condition instruction). The condition instructions allow conditional execution of EEPROM instructions during a download sequence. During an upload sequence, however, they are stored as is and have no effect on the upload process. Note that, during EEPROM downloads, the condition instructions themselves and the end instruction always execute unconditionally. Conditional processing makes use of two elements: the condition (from Condition 1 to Condition 8) and the condition tag board. The relationships among the condition, the condition tag board, and the EEPROM controller appear schematically in Figure 45. During download, the EEPROM controller executes or skips instructions depending on the value of the condition and the contents of the condition tag board. Note, however, that the condition instructions and the end instruction always execute unconditionally during download. If condition = 0, then all instructions during download execute unconditionally. If Condition 0 and there are any tagged conditions in the condition tag board, then the controller executes instructions only if the condition is tagged. If the condition is not tagged, then the controller skips instructions until it encounters a condition instruction that decodes as a tagged condition. Note that the condition tag board allows for multiple conditions to be tagged at any given moment. This conditional processing mechanism enables the user to have one download instruction sequence with many possible outcomes depending on the value of the condition and the order in which the controller encounters condition instructions. The condition is a 4-bit value with 16 possibilities. Condition = 0 is the null condition. When the null condition is in effect, the EEPROM controller executes all instructions unconditionally. Condition 9 through Condition 15 are not accessible using the M pins. The remaining eight possibilities (that is, Condition = 1 through Condition = 8) modify the EEPROM controller's handling of a download sequence. The condition originates from one of two sources (see Figure 45), as follows: * FncInit, Bits[3:0], which is the state of the M2 and M3 multifunction pins at power-up (see Table 22) Register 0x0E01, Bits[3:0] If Register 0x0E01, Bits[3:0] 0, then the condition is the value that is stored in Register 0x0E01, Bits[3:0]; otherwise, the condition is FncInit, Bits[3:0]. Note that a nonzero condition that is present in Register 0x0E01, Bits[3:0] takes precedence over FncInit, Bits[3:0]. M3 AND M2 PINS (3-LEVEL LOGIC) CONDITION TAG BOARD EXAMPLE CONDITION 3 AND CONDITION 13 ARE TAGGED 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 4 IF B1 INSTRUCTION CF, THEN TAG DECODED CONDITION WATCH FOR OCCURRENCE OF CONDITION INSTRUCTIONS DURING DOWNLOAD. UPLOAD PROCEDURE 4 4 COND ITION CONDITION HANDLER SCRATCH PAD FncInit, BITS[3:0] IF {0E01, BITS[3:0] 0} CONDITION = 0E01, BITS[3:0] ELSE CONDITION = FncInit, BITS[3:0] ENDIF IF INSTRUCTION = B0, THEN CLEAR ALL TAGS EEPROM STORE CONDITION INSTRUCTIONS AS THEY ARE READ FROM THE SCRATCH PAD. REGISTER 0x0E01, BITS[3:0] EXECUTE/SKIP INSTRUCTION(S) DOWNLOAD PROCEDURE IF {NO TAGS} OR {CONDITION = 0} EXECUTE INSTRUCTIONS ELSE IF {CONDITION IS TAGGED} EXECUTE INSTRUCTIONS ELSE SKIP INSTRUCTIONS ENDIF ENDIF EEPROM CONTROLLER Figure 45. EEPROM Conditional Processing Rev. B | Page 46 of 104 09758-025 * Data Sheet AD9558 Table 23 lists a sample EEPROM download instruction sequence. It illustrates the use of condition instructions and how they alter the download sequence. The table begins with the assumption that no conditions are in effect. That is, the most recently executed condition instruction is either B0 or no conditional instructions have been processed. Table 23. EEPROM Conditional Processing Example Instruction 0x08 0x01 0x00 0xB1 0x19 0x04 0x00 0xB2 0xB3 0x07 0x05 0x00 0x0A 0xB0 0x80 0x0A 4. Tag Condition 1. Transfer the clock distribution register contents only if tag condition = 1. Tag Condition 2. Tag Condition 3. Transfer the reference input register contents only if tag condition = 1, 2, or 3. Calibrate the system clock only if tag condition = 1, 2, or 3. Clear the tag condition board. Execute an I/O update, regardless of the value of the tag condition. Calibrate the system clock, regardless of the value of the tag condition. Conditional processing makes it possible to create a number of different device setups, store them in EEPROM, and download a specific setup on demand. To do so, first program the device control registers for a specific setup. Then, store an upload sequence in the EEPROM scratch pad with the following general form: 2. 3. 1. 2. 3. Action Transfer the system clock register contents, regardless of the current condition. Storing Multiple Device Setups in EEPROM 1. Reprogram the device control registers for the next desired setup. Then store a new upload sequence in the EEPROM scratch pad with the following general form: Condition instruction (B1 to CF) to identify the setup with a specific condition (1 to 31) Data instructions (to save the register contents) along with any required calibrate and/or I/O update instructions Pause instruction (FE) Condition instruction (B0) The next desired condition instruction (B1 to CF, but different from the one used during the previous upload to identify a new setup) Data instructions (to save the register contents) along with any required calibrate and/or I/O update instructions Pause instruction (FE) With the upload sequence written to the scratch pad, perform an EEPROM upload (Register 0x0E02, Bit 0). Repeat the process of programming the device control registers for a new setup, storing a new upload sequence in the EEPROM scratch pad (Step 1 through Step 4), and executing an EEPROM upload (Register 0x0E02, Bit 0) until all of the desired setups have been uploaded to the EEPROM. Note that, on the final upload sequence stored in the scratch pad, the pause instruction (FE) must be replaced with an end instruction (FF). To download a specific setup on demand, first store the condition associated with the desired setup in Register 0x0E01, Bits[4:0]. Then perform an EEPROM download (Register 0x0E03, Bit 1). Alternatively, to download a specific setup at power-up, apply the required logic levels necessary to encode the desired condition on the M2 and M3 multifunction pins. Then power up the device; an automatic EEPROM download occurs. The condition (as established by the M2 and M3 multifunction pins) guides the download sequence and results in a specific setup. Keep in mind that the number of setups that can be stored in the EEPROM is limited. The EEPROM can hold a total of 2048 bytes. Each nondata instruction requires one byte of storage. Each data instruction, however, requires N + 4 bytes of storage, where N is the number of transferred register bytes and the other four bytes include the data instruction itself (one byte), the target address (two bytes), and the checksum calculated by the EEPROM controller during the upload sequence (one byte). With the upload sequence written to the scratch pad, perform an EEPROM upload (Register 0x0E02, Bit 0). Rev. B | Page 47 of 104 AD9558 Data Sheet Programming the EEPROM to Configure an M Pin to Control Synchronization of Clock Distribution The default EEPROM loading sequence from Register 0x0E10 to Register 0x0E16 is unchanged. The following steps must be inserted into the EEPROM storage sequence: A special EEPROM loading sequence is required to use the EEPROM to load the registers and to use an M pin to enable/disable outputs. To control the output sync function by using an M pin, perform the following steps: 1. 2. 3. Enable the M pins by writing Register 0x0200 = 0x01. Issue an I/O update (Register 0x0005 = 0x01). Set the appropriate M pin function (see the Clock Distribution Synchronization section for details). 1. 2. 3. 4. 5. 6. If this sequence is not performed, a SYNC pulse is issued automatically. The following changes write Register 0x0200 first and then issue an I/O update before writing the remaining M pin configuration registers in Register 0x0201 to Register 0x0208. R0x0E17 = 0x00 # Write one byte R0x0E18 = 0x02 # at Register 0x0200 R0x0E19 = 0x00 # R0x0E1A = 0x80 # Op code for I/O Update R0x0E1B = 0x10 # Transfer 17 instead of 18 bytes R0x0E1C = 0x02 # Transfer starts at Register address R0x0E1D = 0x01 # 0x0201 instead of 0x0200 The rest of the EEPROM loading sequence is the same as the default EEPROM loading sequence, except that the register address of the EEPROM storage sequence is shifted down four bytes from the default. For example, * * * * * Rev. B | Page 48 of 104 R0x0E1E = default value of Register 0x0E1A = 0x2E R0x0E1F = default value of Register 0x0E1B = 0x03 R0x0E20 = default value of Register 0x0E1C = 0x00 ... R0x0E40 = default value of Register 0x0E1C = 0x3C = 0xFF (end of data) Data Sheet AD9558 SERIAL CONTROL PORT The AD9558 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9558 serial control port is compatible with most synchronous transfer formats, including IC, Motorola SPI, and Intel SSR protocols. The serial control port allows read/write access to the AD9558 register map. In SPI mode, single or multiple byte transfers are supported. The SPI port configuration is programmable via Register 0x0000. This register is integrated into the SPI control logic rather than in the register map and is distinct from the I2C Register 0x0000. It is also inaccessible to the EEPROM controller. Although the AD9558 supports both the SPI and I2C serial port protocols, only one or the other is active following power-up (as determined by the M0 and M1 multifunction pins during the startup sequence). That is, the only way to change the serial port protocol is to reset the device (or cycle the device power supply). The CS (chip select) pin is an active low control that gates read and write operations. This pin is internally connected to a 30 k pull-up resistor. When CS is high, the SDO and SDIO pins go into a high impedance state. E A E A SPI Mode Operation The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration and data format features are programmable. By default, the AD9558 uses the bidirectional MSB-first mode. The reason that bidirectional is the default mode is so that the user can still write to the device, if it is wired for unidirectional operation, to switch to unidirectional mode. Assertion (active low) of the CS pin initiates a write or read operation to the AD9558 SPI port. For data transfers of three bytes or fewer (excluding the instruction word), the device supports the CS stalled high mode (see Table 25). In this mode, the CS pin can be temporarily deasserted on any byte boundary, allowing time for the system controller to process the next byte. CS can be deasserted only on byte boundaries, however. This applies to both the instruction and data portions of the transfer. E E Table 24. SPI/IC Serial Port Setup M0 Low Open High Low Open High Low Open High A E A Because the AD9558 supports both SPI and IC protocols, the active serial port protocol depends on the logic state of the PINCONTROL, M1, and M0 pins. The PINCONTROL pin must be low, and the state of the M0 and M1 pins determines the I2C address, or if SPI mode is enabled. See Table 24 for the I2C address assignments. M1 Low Low Low Open Open Open High High High A A A SPI/IC PORT SELECTION A A E A A During stall high periods, the serial control port state machine enters a wait state until all data is sent. If the system controller decides to abort a transfer midstream, then the state machine must be reset either by completing the transfer or by asserting the CS pin for at least one complete SCLK cycle (but less than eight SCLK cycles). Deasserting the CS pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. E A A SPI/IC SPI IC, 1101000 IC, 1101001 IC, 1101010 IC, 1101011 IC, 1101100 IC, 1101101 IC, 1101110 IC, 1101111 E A A In streaming mode (see Table 25), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented. CS must be deasserted at the end of the last byte that is transferred, thereby ending the streaming mode. E A A Table 25. Byte Transfer Count SPI SERIAL PORT OPERATION Pin Descriptions The SCLK (serial clock) pin serves as the serial shift clock. This pin is an input. SCLK synchronizes serial control port read and write operations. The rising edge SCLK registers write data bits, and the falling edge registers read data bits. The SCLK pin supports a maximum clock rate of 40 MHz. The SDIO (serial data input/output) pin is a dual-purpose pin and acts as either an input only (unidirectional mode) or as both an input and an output (bidirectional mode). The AD9558 default SPI mode is bidirectional. The SDO (serial data output) pin is useful only in unidirectional I/O mode. It serves as the data output pin for read operations. W1 0 0 1 1 W0 0 1 0 1 Bytes to Transfer 1 2 3 Streaming mode Communication Cycle--Instruction Plus Data The SPI protocol consists of a two-part communication cycle. The first part is a 16-bit instruction word that is coincident with the first 16 SCLK rising edges and a payload. The instruction word provides the AD9558 serial control port with information regarding the payload. The instruction word includes the R/W bit that indicates the direction of the payload transfer (that is, a read or write operation). The instruction word also indicates the number of bytes in the payload and the starting register address of the first payload byte. Rev. B | Page 49 of 104 E A A AD9558 Data Sheet Write SPI Instruction Word (16 Bits) If the instruction word indicates a write operation, the payload is written into the serial control port buffer of the AD9558. Data bits are registered on the rising edge of SCLK. The length of the transfer (1, 2, or 3 bytes or streaming mode) depends on the W0 and W1 bits (see Table 25) in the instruction byte. When not streaming, CS can be deasserted after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is stalled, the serial transfer resumes when CS is asserted. Deasserting the CS pin on a nonbyte boundary resets the serial control port. Reserved or blank registers are not skipped over automatically during a write sequence. Therefore, the user must know what bit pattern to write to the reserved registers to preserve proper operation of the part. Generally, it does not matter what data is written to blank registers, but it is customary to write 0s. The MSB of the 16-bit instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits, W1 and W0, indicate the number of bytes in the transfer (see Table 25). E A The final 13 bits are the register address (A12 to A0), which indicates the starting register address of the read/write operation (see Table 27). E A A E SPI MSB-/LSB-First Transfers The AD9558 instruction word and payload can be MSB first or LSB first. The default for the AD9558 is MSB first. The LSB-first mode can be set by writing a 1 to Register 0x0000, Bit 6. Immediately after the LSB-first bit is set, subsequent serial control port operations are LSB first. E A A A A A When MSB-first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant payload byte. Subsequent data bytes must follow in order from high address to low address. In MSB-first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. Most of the serial port registers are buffered (refer to the Buffered/Active Registers section for details on the difference between buffered and active registers). Therefore, data written into buffered registers does not take effect immediately. An additional operation is required to transfer buffered serial control port contents to the registers that actually control the device. This is accomplished with an I/O update operation, which is performed in one of two ways. One is by writing a Logic 1 to Register 0x0005, Bit 0 (this bit is autoclearing). The other is to use an external signal via an appropriately programmed multifunction pin. The user can change as many register bits as desired before executing an I/O update. The I/O update operation transfers the buffer register contents to their active register counterparts. When Register 0x0000, Bit 6 = 1 (LSB first), the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant payload byte followed by multiple data bytes. The serial control port internal byte address generator increments for each byte of the multibyte transfer cycle. For multibyte MSB-first (default) I/O operations, the serial control port register address decrements from the specified starting address toward Address 0x0000. For multibyte LSB-first I/O operations, the serial control port register address increments from the starting address toward Address 0x1FFF. Reserved addresses are not skipped during multibyte I/O operations; therefore, the user should write the default value to a reserved register and 0s to unmapped registers. Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers. Read The AD9558 supports the long instruction mode only. If the instruction word indicates a read operation, the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word. N is the number of data bytes read and depends on the W0 and W1 bits of the instruction word. The readback data is valid on the falling edge of SCLK. Blank registers are not skipped over during readback. A readback operation takes data from either the serial control port buffer registers or the active registers, as determined by Register 0x0004, Bit 0. Table 26. Streaming Mode (No Addresses Are Skipped) Write Mode LSB First MSB First Address Direction Increment Decrement Stop Sequence 0x0000 ... 0x1FFF 0x1FFF ... 0x0000 Table 27. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A E Rev. B | Page 50 of 104 Data Sheet AD9558 CS SCLK DON'T CARE R/W W1 W0 A12 A11 A10 A9 SDIO DON'T CARE A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N - 1) DATA 09758-029 DON'T CARE Figure 46. Serial Control Port Write--MSB First, 16-Bit Instruction, Two Bytes of Data CS SCLK DON'T CARE SDIO DON'T CARE SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 REGISTER (N) DATA 16-BIT INSTRUCTION HEADER REGISTER (N - 1) DATA REGISTER (N - 2) DATA REGISTER (N - 3) DATA DON'T CARE 09758-030 R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 47. Serial Control Port Read--MSB First, 16-Bit Instruction, Four Bytes of Data tDS tHIGH tS tLOW CS DON'T CARE SDIO DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 09758-031 SCLK tC tCLK tDH Figure 48. Serial Control Port Write--MSB First, 16-Bit Instruction, Timing Measurements CS SCLK DATA BIT N 09758-032 tDV SDIO SDO DATA BIT N - 1 Figure 49. Timing Diagram for Serial Control Port Register Read CS SCLK DON'T CARE A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 16-BIT INSTRUCTION HEADER D5 D6 REGISTER (N) DATA D7 D0 D1 D2 D6 REGISTER (N + 1) DATA Figure 50. Serial Control Port Write--LSB First, 16-Bit Instruction, Two Bytes of Data Rev. B | Page 51 of 104 D3 D4 D5 D7 DON'T CARE 09758-033 SDIO DON'T CARE DON'T CARE A0 A1 A2 A3 AD9558 Data Sheet CS tS tC tCLK tHIGH tLOW tDS SCLK SDIO BIT N BIT N + 1 Figure 51. Serial Control Port Timing--Write Table 28. Serial Control Port Timing Parameter tDS tDH tCLK tS tC tHIGH tLOW tDV Description Setup time between data and the rising edge of SCLK Hold time between data and the rising edge of SCLK Period of the clock Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle) Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle) Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state SCLK to valid SDIO and SDO (see Figure 49) E A A E A A Rev. B | Page 52 of 104 09758-034 tDH Data Sheet AD9558 The transfer of data is shown in Figure 52. One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. IC SERIAL PORT OPERATION The I2C interface has the advantage of requiring only two control pins and is a de facto standard throughout the I2C industry. However, its disadvantage is programming speed, which is 400 kbps maximum. The AD9558 IC port design is based on the IC fast mode standard; therefore, it supports both the 100 kHz standard mode and 400 kHz fast mode. Fast mode imposes a glitch tolerance requirement on the control signals. That is, the input receivers ignore pulses of less than 50 ns duration. SDA SCL DATA LINE STABLE; DATA VALID Figure 52. Valid Bit Transfer Start/stop functionality is shown in Figure 53. The start condition is characterized by a high-to-low transition on the SDA line while SCL is high. The start condition is always generated by the master to initialize a data transfer. The stop condition is characterized by a low-to-high transition on the SDA line while SCL is high. The stop condition is always generated by the master to terminate a data transfer. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit; bytes are sent MSB first. The AD9558 allows up to seven unique slave devices to occupy the I2C bus. These are accessed via a 7-bit slave address that is transmitted as part of an I2C packet. Only the device that has a matching slave address responds to subsequent I2C commands. Table 24 lists the supported device slave addresses. I2C Bus Characteristics A summary of the various I2C protocols appears in Table 29. The acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. It is done by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte. Table 29. I2C Bus Abbreviation Definitions Abbreviation S Sr P A A W R Definition Start Repeated start Stop Acknowledge Nonacknowledge Write Read E E A The nonacknowledge bit (A) is the ninth bit attached to any 8bit data byte. A nonacknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. It is done by leaving the SDA line high during the ninth clock pulse after each 8-bit data byte. E A A SDA SCL S P START CONDITION 09758-036 STOP CONDITION Figure 53. Start and Stop Conditions MSB SDA ACK FROM SLAVE RECEIVER 1 SCL 2 3 TO 7 8 9 ACK FROM SLAVE RECEIVER 1 S Figure 54. Acknowledge Bit Rev. B | Page 53 of 104 2 3 TO 7 8 9 10 P 09758-037 A CHANGE OF DATA ALLOWED 09758-035 The AD9558 IC port consists of a serial data line (SDA) and a serial clock line (SCL). In an IC bus system, the AD9558 is connected to the serial bus (data bus SDA and clock bus SCL) as a slave device; that is, no clock is generated by the AD9558. The AD9558 uses direct 16-bit memory addressing instead of traditional 8-bit memory addressing. AD9558 Data Sheet Data Transfer Process per transfer is unrestricted. In write mode, the first two data The master initiates data transfer by asserting a start condition. This indicates that a data stream follows. All IC slave devices connected to the serial bus respond to the start condition. bytes immediately after the slave address byte are the internal memory (control registers) address bytes, with the high address byte first. This addressing scheme gives a memory address of up to 216 - 1 = 65,535. The data bytes after these two memory address bytes are register data written to or read from the control registers. In read mode, the data bytes after the slave address byte are register data written to or read from the control registers. The master then sends an 8-bit address byte over the SDA line, consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). E A A When all data bytes are read or written, stop conditions are established. In write mode, the master (transmitter) asserts a stop condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). In read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull SDA low during the ninth clock pulse. This is known as a nonacknowledge bit. By receiving the nonacknowledge bit, the slave device knows that the data transfer is finished and enters idle mode. The master then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. The peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master (transmitter) writes to the slave device (receiver). If the R/W bit is 1, the master (receiver) reads from the slave device (transmitter). E A A E A The format for these commands is described in the Data Transfer Format section. Data is then sent over the serial bus in the format of nine clock pulses, one data byte (eight bits) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. The number of bytes that can be transmitted A start condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. MSB ACK FROM SLAVE RECEIVER 1 SCL 2 3 TO 7 8 9 ACK FROM SLAVE RECEIVER 1 2 3 TO 7 8 9 S 10 P 09758-038 SDA Figure 55. Data Transfer Process (Master Write Mode, 2-Byte Transfer) SDA ACK FROM MASTER RECEIVER SCL 1 2 3 TO 7 8 9 NON-ACK FROM MASTER RECEIVER 1 2 3 TO 7 S 8 9 10 P Figure 56. Data Transfer Process (Master Read Mode, 2-Byte Transfer) Rev. B | Page 54 of 104 09758-039 A Data Sheet AD9558 Data Transfer Format Write byte format--the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. S Slave address A W E A RAM address high byte A RAM address low byte A RAM Data 0 A RAM Data 1 A RAM Data 2 A P Send byte format--the send byte protocol is used to set up the register address for subsequent reads. S Slave address A W E A RAM address high byte A RAM address low byte A P Receive byte format--the receive byte protocol is used to read the data byte(s) from RAM starting from the current address. S Slave address R A RAM Data 0 A RAM Data 1 A RAM Data 2 P A A E Read byte format--the combined format of the send byte and the receive byte. S Slave Address W E A A RAM Address High Byte A RAM Address Low Byte A Sr Slave Address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A A IC Serial Port Timing SDA tLOW tF tSU; DAT tR tHD; STA tSP tBUF tR tF tHD; STA S tHD; DAT tHIGH tSU; STO tSU; STA Sr Figure 57. IC Serial Port Timing Table 30. IC Timing Definitions Parameter fSCL tBUF tHD; STA tSU; STA tSU; STO tHD; DAT tSU; DAT tLOW tHIGH tR tF tSP Description Serial clock Bus free time between stop and start conditions Repeated hold time start condition Repeated start condition setup time Stop condition setup time Data hold time Date setup time SCL clock low period SCL clock high period Minimum/maximum receive SCL and SDA rise time Minimum/maximum receive SCL and SDA fall time Pulse width of voltage spikes that must be suppressed by the input filter Rev. B | Page 55 of 104 P S 09758-040 SCL E P AD9558 Data Sheet PROGRAMMING THE I/O REGISTERS The register map spans an address range from 0x0000 through 0x0E3C. Each address provides access to 1 byte (eight bits) of data. Each individual register is identified by its four-digit hexadecimal address (for example, Register 0x0A10). In some cases, a group of addresses collectively defines a register. In general, when a group of registers defines a control parameter, the LSB of the value resides in the D0 position of the register with the lowest address. The bit weight increases right to left, from the lowest register address to the highest register address. Note that the EEPROM storage sequence registers (Address 0x0E10 to Address 0x0E3C) are an exception to the above convention (see the EEPROM Instructions section). REGISTER ACCESS RESTRICTIONS Read and write access to the register map may be restricted depending on the register in question, the source and direction of access, and the current state of the device. Each register can be classified into one or more access types. When more than one type applies, the most restrictive condition is the one that applies. When access is denied to a register, all attempts to read the register return a 0 byte, and all attempts to write to the register are ignored. Access to nonexistent registers is handled in the same way as for a denied register. Regular Access BUFFERED/ACTIVE REGISTERS There are two copies of most registers: buffered and active. The value in the active registers is the one that is in use. The buffered registers are the ones that take effect the next time the user writes 0x01 to the I/O update register (Register 0x0005). Buffering the registers allows the user to update a group of registers (like the digital loop filter coefficients) at the same time, which avoids the potential of unpredictable behavior in the part. Registers with an L in the option column are live, meaning that they take effect the moment the serial port transfers that data byte. AUTOCLEAR REGISTERS An A in the option column of the register map identifies an autoclear register. Typically, the active value for an autoclear register takes effect following an I/O update. The bit is cleared by the internal device logic upon completion of the prescribed action. Registers with regular access do not fall into any other category. Both read and write access to registers of this type can be from either the serial ports or the EEPROM controller. However, only one of these sources can have access to a register at any given time (access is mutually exclusive). When the EEPROM controller is active, in either load or store mode, it has exclusive access to these registers. Read-Only Access An R in the option column of the register map identifies readonly registers. Access is available at all times, including when the EEPROM controller is active. Note that read-only registers (R) are inaccessible to the EEPROM, as well. Exclusion from EEPROM Access An E in the option column of the register map identifies a register with contents that are inaccessible to the EEPROM. That is, the contents of this type of register cannot be transferred directly to the EEPROM or vice versa. Note that read-only registers (R) are inaccessible to the EEPROM, as well. Rev. B | Page 56 of 104 Data Sheet AD9558 THERMAL PERFORMANCE Table 31. Thermal Parameters for the 64-Lead LFCSP Package Symbol JA JMA JMA JB JC JT 1 2 Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board1 Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-board thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-8 (still air) Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) Value2 21.7 18.9 16.9 11.3 1.2 0.1 Unit C/W C/W C/W C/W C/W C/W The exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance. Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. The AD9558 is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, an airflow source can be used. Use the following equation to determine the junction temperature on the application PCB: TJ = TCASE + (JT x PD) Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first order approximation of TJ by the equation TJ = TA + (JA x PD) where TA is the ambient temperature (C). where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the customer at the top center of the package. JT is the value as indicated in Table 31. PD is the power dissipation (see Table 3). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations. Rev. B | Page 57 of 104 AD9558 Data Sheet POWER SUPPLY PARTITIONS The AD9558 power supplies are divided into four groups: DVDD3, DVDD, AVDD3, and AVDD. All power and ground pins should be connected, even if certain blocks of the chip are powered down. RECOMMENDED CONFIGURATION FOR 3.3 V SWITCHING SUPPLY The ADP7104 is another good choice for converting 3.3 V to 1.8 V. The close-in noise of the ADP7104 is lower than that of the ADP222; therefore, it may be better suited for applications where close-in phase noise is critical and the AD9557 DPLL loop bandwidth is <50 Hz. In such cases, all 1.8 V supplies can be connected to one ADP7104. Use of Ferrite Beads on 1.8 V Supplies A popular power supply arrangement is to power the AD9558 with the output of a 3.3 V switching power supply. CONFIGURATION FOR 1.8 V SUPPLY To ensure the very best output-to-output isolation, one ferrite bead should be used instead of a bypass capacitor for each of the following AVDD pins: Pin 12, Pin 22, Pin 29, and Pin 30. The ferrite beads should be placed in between the 1.8 V LDO output and each pin listed above. Ferrite beads that have low (<0.7 ) dc resistance and approximately 600 impedance at 100 MHz are suitable for this application. When 1.8 V supplies are preferred, it is recommended that an LDO regulator, such as the ADP222, be used to generate the 1.8 V supply from the 3.3 V supply. See Table 2 for the current consumed by each group. Refer to Figure 20, Figure 21, and Figure 22 for information on the power consumption vs. output frequency. When the AD9558 is powered using 3.3 V switching power supplies, all of the 3.3 V supplies can be connected to the 3.3 V switcher output, and a 0.1 F bypass capacitor should be placed adjacent to each 3.3 V power supply pin. The ADP222 offers excellent power supply rejection in a small (2 mm x 2 mm) package. It has two 1.8 V outputs. One output can be used for the DVDD pins (Pin 6, Pin 34, and Pin 35), and the other output can drive the AVDD pins. Rev. B | Page 58 of 104 Data Sheet AD9558 PIN PROGRAM FUNCTION DESCRIPTION The AD9558 supports both hard pin and soft pin program function with the on-chip ROM containing the predefined configurations. When a pin program function is enabled and initiated, the selected predefined configuration is transferred from the ROM to the corresponding registers to configure the part into the desired state. OVERVIEW OF ON-CHIP ROM FEATURES Input/Output Frequency Translation Configuration The AD9558 has one on-chip ROM that contains a total of 256 different input-output frequency translation configurations for independent selection of 16 input frequencies and 16 output frequencies. Each input/output frequency translation configuration assumes that all input frequencies are the same and all the output frequencies are the same. Each configuration reprograms the following registers/parameters: * * * * * Reference input period register Reference divider R register Digital PLL feedback divider register (Fractional Part FRAC1, Modulus Part MOD1 and Integer Part N1) free run Tuning word register Output PLL feedback divider N2 register * * RF divider register Clock distribution channel divider register All configurations are set to support one single system clock frequency as 786.432 MHz (16x the default 49.152 MHz system clock reference frequency). Four Different System Clock PLL Configurations * * * * REF = 49.152 MHz XO (x2 on, N = 8) REF = 49.152 MHz XTAL (x2 on, N = 8) REF = 24.756 MHz XTAL (x2 on, N = 16) REF = 98.304 MHz XO (x2 off, N = 8) Four Different DPLL Loop Bandwidths * 1 Hz, 10 Hz, 50 Hz, 100 Hz DPLL Phase Margin * * Normal phase margin (70) High phase margin (88.5) The ROM also contains an APLL VCO calibration bit. This bit is used to program Register 0x0405[0] (from 0) to 1 to generate a low-high transition to automatically initiate APLL VCO cal. Table 32. Preset Input Frequencies for Hard Pin and Soft Pin Programming Freq ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frequency (MHz) 0.008 19.44 25 125 156.7072 622.08 625 644.53125 657.421875 660.184152 669.3266 672.1627 690.569 693.48299 693.482991 698.81236 Frequency Description 8 kHz 19.44 MHz 25 MHz 125 MHz 156..25 MHz x 1027/1024 622.08 MHz 625 MHz 625 MHz x 33/32 657.421875 MHz 657.421875 MHz x 239/238 622.08 MHz x 255/238 622.08 MHz x 255/236 622.08 MHz x 255/236 644.53125 MHz x 255/238 644.53125 MHz x 255/237 622.08 x 255/237 Hard Pin Program PINCONTROL = High M4 Pin M0 Pin M5 Pin 0 0 0 0 0 1/2 0 0 1 0 1/2 0 0 1/2 1/2 0 1/2 1 0 1 0 0 1 1/2 0 1 1 1/2 0 0 1/2 0 1/2 1/2 0 1 1/2 1/2 0 1/2 1/2 1/2 1/2 1/2 1 1/2 1 0 Rev. B | Page 59 of 104 Soft Pin Program PINCONTROL = Low Register 0x0C01[3:0] B3 B2 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 1 0 AD9558 Data Sheet Table 33. Preset Output Frequencies for Hard Pin and Soft Pin Programming Freq ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frequency (MHz) 19.44 25 125 156.7071 622.08 625 644.53125 657.421875 660.184152 666.5143 669.3266 672.1627 690.5692 693.4830 698.8124 704.380580 Hard Pin Program PINCONTROL = High M3 M2 M1 0 0 0 0 0 1/2 0 0 1 0 1/2 0 0 1/2 1/2 0 1/2 1 0 1 0 0 1 1/2 0 1 1 1/2 0 0 1/2 0 1/2 1/2 0 1 1/2 1/2 0 1/2 1/2 1/2 1/2 1/2 1 1/2 1 0 Frequency Description 19.44 MHz 25 MHz 125 MHz 156.25 MHz x 1027/1024 622.08 MHz 625 MHz 625 MHz x 33/32 657.421875 MHz 657.421875 MHz x 239/238 622.08 MHz x 255/238 622.08 MHz x 255/237 622.08 MHz x 255/236 644.53125 MHz x 255/238 644.53125 MHz x 255/237 622.08 MHz x 255/237 657.421875 MHz x 255/238 B7 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Soft Pin Program PINCONTROL = Low, Register 0x0C01[3:0] B6 B5 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 B4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 34. System Clock Configuration in Hard Pin and Soft Pin Programming Modes Freq ID 0 1 2 3 Frequency (MHz) 49.152 49.152 24.576 98.304 System Clock Configuration XTAL mode, doubler on, N = 8 XTAL mode off, doubler on, N = 8 XTAL mode, doubler on, N = 16 XTAL mode off, doubler off, N = 8 HARD PIN PROGRAMMING MODE The state of the PINCONTROL pin at power-up controls whether or not the chip is in hard pin programming mode. Setting the PINCONTROL pin high disables the I2C protocol, although the register map can be accessed via the SPI protocol. The M0, M5, and M4 pins select one of 16 input frequencies, and the M3 to M1 pins select one of 16 possible output frequencies. See Table 32 and Table 33 for details. Hard Pin Program PINCONTROL = High, IRQ Pin IRQ Pin 0 1/2 1 N/A Soft Pin Program PINCONTROL = Low, Register 0x0C02[1:0] Bit 1 Bit 0 0 0 0 1 1 0 1 1 Equivalent System Clock PLL Register Settings 0001, 0000, 1000 The system clock configuration is controlled by the state of the IRQ pin at startup (see Table 34 for details). The digital PLL loop bandwidth, reference input frequency accuracy tolerance ranges, and DPLL phase margin selection are not available in hard pin programming mode unless the user uses the serial port to change their default values. When in hard pin programming mode, the user must set Register 0x0200[0] = 1 to activate the IRQ, REF status, and PLL lock status signals at the multifunction pins. Rev. B | Page 60 of 104 Data Sheet AD9558 * SOFT PIN PROGRAMMING OVERVIEW The soft pin program function is controlled by a dedicated register section (Address 0x0C00 to Address 0x0C08). The purpose of soft pin program is to use the register bits to mimic the hard pins for the configuration section. When in soft pin program mode, both SPI and I2C port are available. * * * * * * Address 0x0C00[0] enables accessibility to Address 0x0C01 and Address 0x0C02 (Soft Pin Section 1). This bit must be set in soft pin mode. Address 0x0C03[0] enables accessibility to Address 0x0C04 to Address 0x0C06 (Soft Pin Section 2). This bit must be set in soft pin mode. Address 0x0C01[3:0] select one of 16 input frequencies. Address 0x0C01[7:4] select one of 16 output frequencies. Address 0x0C02[1:0] select the system clock configuration. Address 0x0C06[1:0] select one of four input frequency tolerance ranges. * * * Rev. B | Page 61 of 104 Address 0x0C06[3:2] select one of four DPLL loop bandwidths. Address 0x0C06[4] selects the DPLL phase margin. Address 0x0C04[3:0] scales the REFA/REFB/REFC/REFD input frequency down by divide-by-1, divide-by-4, divideby-8, divide-by-16 independently. For example, when Address 0x0C01[3:0] = 0101 to select input frequency as 622.08 MHz for all REFA/REFB/REFC/REFD, setting Address 0x0C04[1:0] = 0x01 scales down the REFA input frequency to 155.52 MHz (= 622.08 MHz/4). This is done by internally scaling the R divider for REFA up by 4x and the REFA period up by 4x. Address 0x0C05[3:0] scales the Channel 0/1/2/3 output frequency down by divide-by-1, divide-by-4, divide-by-8, or divide-by-16. (Channel 2 and Channel 3 are available only for the AD9558). AD9558 Data Sheet REGISTER MAP Register addresses that are not listed in Table 35 are not used, and writing to those registers has no effect. The user should write the default value to sections of registers marked reserved. R = read-only. A = autoclear. E = excluded from EEPROM loading. L = live (I/O update not required for register to take effect or for a read-only register to be updated). Table 35. Register Map Reg Addr (Hex) Opt Name D7 D6 Serial Control Port Configuration and Part Identification 0x0000 L, E SPI control SDO enable LSB first/ increment address 0x0000 L IC control Reserved 0x0004 0x0005 A, L 0x0006 L 0x0007 L 0x000A R, L 0x000B R, L 0x000C R, L 0x000D R, L System Clock 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 Readback control I/O update User scratch pad D5 D4 D3 D2 Reserved Reserved SYSCLK period Reserved SYSCLK stability A Reserved General Configuration 0x0200 EN_MPIN Def Reserved 00 Soft reset Reserved 00 Reserved User scratch pad[7:0] User scratch pad[15:8] Silicon revision[7:0] Reserved Clock part family ID[7:0] Clock part family ID[15:8] SYSCLK config PLL feedback divider D0 Soft reset Reserved Silicon rev Reserved Part ID D1 Read buffer register I/O update System clock N divider[7:0] Load from SYSCLK XTAL SYSCLK P divider[1:0] SYSCLK ROM (readenable doubler only) enable Reserved Nominal system clock period (fs), Bits[7:0] (1 ns at 1 ppm accuracy) Nominal system clock period (fs), Bits[15:8] (1 ns at 1 ppm accuracy) Nominal system clock period (fs), Bits[20:16] System clock stability period (ms), Bits[7:0] System clock stability period (ms), Bits[15:8] Reset System clock stability period (ms), Bits[19:16] SYSCLK (not autoclearing) stab timer (autoclear) Reserved Enable M pins and IRQ pin function 00 00 00 00 21 0F 01 00 08 09 or 19 00 0E 67 13 32 00 00 00 0x0201 M0FUNC Output/inputE Function[6:0] B0 0x0202 M1FUNC Output/AinputE Function[6:0] B1 0x0203 M2FUNC Output/AinputE Function[6:0] C0 0x0204 M3FUNC Output/AinputE Function[6:0] C1 0x0205 M4FUNC Output/AinputE Function[6:0] B2 0x0206 M5func Output/AinputE Function[6:0] B3 0x0207 M6FUNC Output/AinputE Function[6:0] C2 0x0208 M7FUNC Output/AinputE Function[6:0] C3 A E A E A E A E A E A E A A E E Rev. B | Page 62 of 104 Data Sheet Reg Addr (Hex) 0x0209 Opt 0x020A Name IRQ pin output mode AD9558 D7 IRQ mask D6 Reserved Reserved 0x020B D4 SYSCLK unlocked SYSCLK locked Freerun Pin program end Holdover Reserved 0x020C Switching 0x020D Closed Reserved 0x020E Reserved REFB validated 0x020F Reserved REFD validated 0x0210 0x0211 0x0300 0x0301 0x0302 0x0303 0x0304 REFB fault cleared REFD fault cleared Watchdog Timer 1 Freerun frequency TW Reserved Reserved Digital oscillator control 0x0305 0x0306 0x0307 0x0308 0x0309 0x030A 0x030B 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 0x0312 0x0313 0x0314 0x0315 0x0316 0x0317 0x0318 0x0319 0x031A 0x031B 0x031C 0x031D 0x031E 0x031F 0x0320 0x0321 0x0322 D5 DCO 4-level output D3 Status signal at IRQ pin[1:0] History updated REFB fault REFD fault D1 APLL unlocked D2 Use IRQ pin for status signal APLL locked D0 IRQ pin driver type[1:0] APLL cal complete APLL cal started 00 Sync distribution Watchdog timer EEPROM fault EEPROM complete 00 Frequency unlocked Frequency unclamped Reserved Frequency locked Frequency clamped REFA validated Phase unlocked Phase locked 00 Phase slew unlimited REFA fault cleared Phase slew limited REFA fault 00 Reserved REFC validated REFC fault cleared REFC fault 00 Reset SDM 00 00 11 15 64 1B 10 Watchdog timer (ms), Bits[7:0] Watchdog timer (ms), Bits[15:8] 30-bit free run frequency tuning word[7:0] 30-bit free run frequency tuning word[15:8] 30-bit free run frequency tuning word[23:16] 30-bit free run frequency tuning word[29:24] Reserved Reserved Reserved Lower limit of pull-in range[19:16] Upper limit of pull-in range[7:0] Upper limit of pull-in range[15:8] Reserved Closed-loop phase lock offset [0.5 ms] Phase slew rate limit Holdover history History mode L L L L L L L L L L L L Base Loop Filter A coefficient set (high phase margin) Reserved Reserved Reserved Reserved 00 (must be 1b) Reserved Lower limit of pull-in range[7:0] Lower limit of pull-in range[15:8] DPLL frequency clamp Def 1F Upper limit of pull-in range[19:16] Fixed phase lock offset (signed; ps), Bits[7:0] Fixed phase lock offset (signed; ps), Bits[15:8] Fixed phase lock offset (signed; ps), Bits[23:16] Reserved Fixed phase lock offset (signed; ps), Bits[29:24] Incremental phase lock offset step size (ps/step), Bits[7:0] (up to 65.5 ns/step) Incremental phase lock offset step size (ps/step), Bits[15:8] (up to 65.5 ns/step) Phase slew rate limit (s/sec), Bits[7:0] (315 s/sec up to 65.536 ms/sec) Phase slew rate limit (s/sec), Bits[15:8] (315 s/sec up to 65.536 ms/sec) History accumulation timer (ms), Bits[7:0] (up to 65 seconds) History accumulation timer (ms), Bits[15:8] (up to 65 seconds) Reserved Single Persistent Incremental average sample history fallback HPM Alpha-0[7:0] HPM Alpha-0[15:8] HPM Alpha-1[6:0] HPM Beta-0[7:0] HPM Beta-0[15:8] HPM Beta-1[6:0] HPM Gamma-0[7:0] HPM Gamma-0[15:8] HPM Gamma-1[6:0] HPM Delta-0[7:0] HPM Delta-0[15:8] HPM Delta-1[6:0] Rev. B | Page 63 of 104 00 51 B8 02 3E 0A 0B 00 00 00 00 00 00 00 00 0A 00 00 8C AD 4C F5 CB 73 24 D8 59 D2 8D 5A AD9558 Reg Addr (Hex) 0x0323 0x0324 0x0325 0x0326 0x0327 0x0328 0x0329 0x032A 0x032B 0x032C 0x032D 0x032E Opt L L L L L L L L L L L L Data Sheet Name Base loop Filter A coefficient set (normal phase margin of 70) D7 D6 D5 D4 Reserved Reserved Reserved Reserved Output PLL (APLL) 0x0400 APLL charge pump 0x0401 APLL N divider 0x0402 0x0403 APLL loop filter control 0x0404 0x0405 0x0406 0x0407 0x0408 APLL VCO control 0x0501 Channel 0 0x0502 0x0503 0x0504 0x0505 Channel 1 0x0507 0x0508 Channel 2 0x050B 0x050C 0x050D 0x050E 0x050F 0x0510 0x0511 0x0512 0x0513 0x0514 0x0515 Mask Channel 3 sync Enable 3.3 V CMOS driver Mask Channel 2 sync Channel 3 D0 Def 24 8C 49 55 C9 7B 9C FA 55 EA E2 57 81 Output PLL (APLL) feedback N divider[7:0] Reserved APLL loop filter control[7:0] Reserved 14 00 07 00 APLL locked controlled sync disable Reserved RF divider startup mode Mask Mask Channel 1 Channel 0 sync sync OUT0 format[2:0] Reserved Reserved Bypass internal Rzero Manual APLL VCO (not autoclearing) Reserved RF Divider 1[3:0] PD RF Divider 2 Sync source selection OUT0 polarity[1:0] PD RF Divider 1 Automatic sync mode OUT0 drive strength Enable OUT0 Channel 0 (M0) division ratio[7:0] Channel 0 PD Select RF Channel 0 (M0) division ratio[9:8] Divider 2 Reserved Channel 0 divider phase[5:0] Reserved OUT1 format[2:0] OUT1 polarity[1:0] OUT1 drive Enable OUT1 strength Reserved OUT2 format[2:0] OUT2 polarity[1:0] OUT2 drive Enable OUT2 strength Channel 1 (M1) division ratio[7:0] Reserved Channel 1 PD Select RF Channel 1 (M1) division ratio[9:8] Divider 2 Reserved Channel 1 divider phase[5:0] Reserved OUT3 format[2:0] OUT3 polarity[1:0] OUT3 drive Enable OUT3 strength Reserved OUT4 format[2:0] OUT4 polarity[1:0] OUT4 drive Enable OUT4 strength Channel 2 (M2) division ratio[7:0] Reserved Channel 2 PD Select RF Channel 2 (M2) division ratio[9:8] Divider 2 Reserved Channel 2 divider phase[5:0] Enable 3.3 V OUT5 format[2:0] OUT5 polarity[1:0] OUT5 drive Enable OUT5 CMOS driver strength Channel 3, Divider 1 (M3) division ratio[7:0] Reserved Channel 3, Divider 1 (M3) division ratio[9:8] Channel 3, Divider 2 (M3b) division ratio[7:0] Reserved Enable Channnel 3 Select RF Channel 3, Divider 2 (M3b) Channel 3 PD Divider 2 division ratio[9:8] doubler Reserved Channel 3, Divider 1 phase[5:0] Reserved Channel 3, Divider 2 phase[5:0] Reserved 0x0506 0x0509 0x050A RF Divider 2[3:0] Reserved D1 Output PLL (APLL) charge pump[7:0] Reserved (default: 0x2) RF divider Output Clock Distribution 0x0500 Distribution output sync D3 D2 NPM Alpha-0[7:0] NPM Alpha-0[15:8] NPM Alpha-1[6:0] NPM Beta-0[7:0] NPM Beta-0[15:8] NPM Beta-1[6:0] NPM Gamma-0[7:0] NPM Gamma-0[15:8] NPM Gamma-1[6:0] NPM Delta-0[7:0] NPM Delta-0[15:8] NPM Delta-1[6:0] Rev. B | Page 64 of 104 20 00 44 02 02 10 00 00 00 10 10 03 00 00 10 10 00 00 00 10 03 00 00 00 00 00 Data Sheet Reg Addr (Hex) Opt Name Reference Inputs 0x0600 Reference power-down 0x0601 Reference logic type 0x0602 Reference priority 0x0603 Frame Synchronization Mode 0x0640 En frame sync 0x0641 Frame sync options Profile A (for REFA) 0x0700 L Reference period (up to 0x0701 L 1.1 ms) 0x0702 L 0x0703 L 0x0704 L 0x0705 L Frequency tolerance 0x0706 L 0x0707 0x0708 L L 0x0709 L 0x070A 0x070B 0x070C 0x070D 0x070E L L L L L 0x070F 0x0710 0x0711 L L L DPLL loop BW 0x0712 0x0713 0x0714 L L L DPLL R divider (20 bits) 0x071D 0x071E 0x071F 0x0720 0x0721 0x0722 0x0723 0x0724 0x0725 0x0726 L L L L L L L L L D4 D3 D2 Reserved D1 D0 Reference power-down[3:0] REFD logic type[1:0] REFC logic type[1:0] REFD priority[1:0] REFC priority[1:0] REFB logic type[1:0] Fsync one shot 00 00 REFA priority[1:0] 00 00 Reserved Validate Fsync ref Fsync arm method Enable Fsync Arm soft Fsync Nominal reference period (fs), Bits[7:0] (default: 51.44 ns =1/(19.44 MHz) for default system clock setting) Nominal period (fs), Bits[15:8] Nominal period (fs), Bits[23:16] Nominal period (fs), Bits[31:24] Nominal period (fs), Bits[39:32] 00 Inner tolerance, Bits[19:16] Outer tolerance, Bits[19:16] Validation timer (ms), Bits[7:0] (up to 65.5 seconds) Validation timer (ms), Bits[15:8] (up to 65.5 seconds) Reserved Reserved Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz) Digital PLL loop BW scaling factor[15:8] Reserved Reserved R divider[7:0] R divider[15:8] Enable REFA R divider[19:16] divide-by-2 Digital PLL feedback divider--Integer Part N1[7:0] Digital PLL feedback divider--Integer Part N1[15:8] Reserved 00 00 C9 EA 10 03 00 14 Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%) Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm) Select base loop filter Def REFA logic type[1:0] REFB priority[1:0] Reserved Reserved Validation DPLL fractional feedback divider (24 bits) DPLL fractional feedback divider modulus (24 bits) Lock detectors 0x071C D5 Reserved 0x0718 0x071B D6 00 0A Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm) (default: 10%) Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm) DPLL N divider (17 bits) 0x071A D7 Reserved 0x0715 0x0716 0x0717 0x0719 AD9558 00 Sel high PM base loop filter BW scaling factor[16] 00 0A 00 00 00 F4 01 00 C5 00 00 Digital PLL feedback divider-- Integer Part N1[16] 6B 07 00 Digital PLL fractional feedback divider--FRAC1[7:0] 04 Digital PLL fractional feedback divider--FRAC1[15:8] 00 Digital PLL fractional feedback divider--FRAC1[23:16] 00 Digital PLL feedback divider modulus--MOD1[7:0] 05 Digital PLL feedback divider modulus--MOD1[15:8] 00 Digital PLL feedback divider modulus--MOD1[23:16] 00 Phase lock threshold (ps), Bits[7:0] Phase lock threshold (ps), Bits[15:8] Phase lock fill rate[7:0] Phase lock drain rate[7:0] Frequency lock threshold[7:0] Frequency lock threshold[15:8] Frequency lock threshold[23:16] Frequency lock fill rate[7:0] Frequency lock drain rate[7:0] BC 02 0A 0A BC 02 00 0A 0A Rev. B | Page 65 of 104 AD9558 Data Sheet Reg Addr (Hex) Opt Name Profile B (for REFB) 0x0740 L Reference period (up to 0x0741 L 1.1 ms) 0x0742 L 0x0743 L 0x0744 L 0x0745 L Frequency tolerance 0x0746 L 0x0747 L 0x0748 L 0x0749 L 0x074A L 0x074B L 0x074C L 0x074D 0x074E L L 0x074F L 0x0750 0x0751 L L 0x0752 0x0753 0x0754 L L L Validation 0x075D 0x075E 0x075F 0x0760 0x0761 0x0762 0x0763 0x0764 0x0765 0x0766 L L L L L L L L L D3 D2 D1 D0 Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%) Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm) Reserved Inner tolerance, Bits[19:16] Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm] (default: 10%) Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm) Reserved Outer tolerance, Bits[19:16] Validation timer (ms), Bits[7:0] (up to 65.5 seconds) Validation timer (ms), Bits[15:8] (up to 65.5 seconds) Reserved DPLL R divider (20 bits) Sel high PM base loop filter Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz) Digital PLL loop BW scaling factor[15:8] Reserved DPLL fractional feedback divider (24 bits) DPLL fractional feedback divider modulus (24 bits) Lock detectors 0x075C D4 Nominal period (fs), Bits[7:0] (default: 125 s = 1/(8 kHz) for default system clock setting) Nominal period (fs), Bits[15:8] Nominal period (fs), Bits[23:16] Nominal period (fs), Bits[31:24] Nominal period (fs), Bits[39:32] DPLL loop BW 0x0758 0x075B D5 Select base loop filter DPLL N divider (17 bits) 0x075A D6 Reserved 0x0755 0x0756 0x0757 0x0759 D7 Reserved R divider[7:0] R divider[15:8] Enable REFB R divider[19:16] divide-by-2 Digital PLL feedback divider--Integer Part N1[7:0] Digital PLL feedback divider--Integer Part N1[15:8] Reserved Def 00 A2 94 1A 1D 14 00 00 0A 00 00 0A 00 00 00 F4 BW scaling factor[16] 01 00 00 00 00 Digital PLL feedback divider-- Integer Part N1[16] 1F 5B 00 Digital PLL fractional feedback divider--FRAC1[7:0] 00 Digital PLL fractional feedback divider--FRAC1[15:8] 00 Digital PLL fractional feedback divider--FRAC1[23:16] 00 Digital PLL feedback divider modulus--MOD1[7:0] 01 Digital PLL feedback divider modulus--MOD1[15:8] 00 Digital PLL feedback divider modulus--MOD1[23:16] 00 Phase lock threshold (ps), Bits[7:0] Phase lock threshold(ps), Bits[15:8] Phase lock fill rate[7:0] Phase lock drain rate[7:0] Frequency lock threshold[7:0] Frequency lock threshold[15:8] Frequency lock threshold[23:16] Frequency lock fill rate[7:0] Frequency lock drain rate[7:0] BC 02 0A 0A BC 02 00 0A 0A Rev. B | Page 66 of 104 Data Sheet Reg Addr (Hex) Opt Name Profile C (for REFC) 0x0780 L Reference period (up to 0x0781 L 1.1 ms) 0x0782 L 0x0783 L 0x0784 L 0x0785 L 0x0786 L 0x0787 L 0x0788 L 0x0789 L 0x078A L 0x078B L 0x078C L 0x078D 0x078E L L 0x078F 0x0790 0x0791 L L L DPLL loop BW 0x0792 0x0793 0x0794 L L L DPLL R divider (20 bits) Frequency tolerance Validation DPLL N divider (17 bits) 0x0798 0x0799 0x079A DPLL fractional feedback divider (24 bits) DPLL fractional feedback divider modulus (24 bits) Lock detectors 0x079E 0x079F 0x07A0 0x07A1 0x07A2 0x07A3 0x07A4 0x07A5 0x07A6 L L L L L L L L L D7 D6 D5 D4 D3 D2 D1 D0 Def Nominal period (fs), Bits[7:0] (default: 125 s = 1/(8 kHz) for default system clock setting) Nominal period (fs), Bits[15:8] Nominal period (fs), Bits[23:16] Nominal period (fs), Bits[31:24] Nominal period (fs), Bits[39:32] Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%) Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm) Reserved Inner tolerance, Bits[19:16] Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm] (default: 10%) Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm) Reserved Outer tolerance, Bits[19:16] Validation timer (ms), Bits[7:0] (up to 65.5 seconds) Validation timer (ms), Bits[15:8] (up to 65.5 seconds) C9 Reserved 00 00 Select base loop filter 0x0795 0x0796 0x0797 0x079B 0x079C 0x079D AD9558 Reserved Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz) Digital PLL loop BW scaling factor[15:8] Reserved Reserved R divider[7:0] R divider[15:8] Enable REFC R divider[19:16] divide-by-2 Digital PLL feedback divider--Integer Part N1[7:0] Digital PLL feedback divider--Integer Part N1[15:8] Reserved Sel high PM base loop filt BW scaling factor[16] EA 10 03 00 14 00 00 0A 00 00 0A 00 F4 01 00 C5 00 00 Digital PLL feedback divider-- Integer Part N1[16] 6B 07 00 Digital PLL fractional feedback divider--FRAC1[7:0] Digital PLL fractional feedback divider--FRAC1[15:8] Digital PLL fractional feedback divider--FRAC1[23:16] 04 00 00 Digital PLL feedback divider modulus--MOD1[7:0] Digital PLL feedback divider modulus--MOD1[15:8] Digital PLL feedback divider modulus--MOD1[23:16] 05 00 00 Phase lock threshold (ps), Bits[7:0] Phase lock threshold (ps), Bits[15:8] Phase lock fill rate[7:0] Phase lock drain rate[7:0] Frequency lock threshold[7:0] Frequency lock threshold[15:8] Frequency lock threshold[23:16] Frequency lock fill rate[7:0] Frequency lock drain rate[7:0] BC 02 0A 0A BC 02 00 0A 0A Rev. B | Page 67 of 104 AD9558 Data Sheet Reg Addr (Hex) Opt Name DPLL Profile D (for REFD) 0x07C0 L Reference period (up to 0x07C1 L 1.1 ms) 0x07C2 L 0x07C3 L 0x07C4 L 0x07C5 L 0x07C6 L 0x07C7 L 0x07C8 L 0x07C9 L 0x07CA L 0x07CB L 0x07CC L 0x07CD 0x07CE L L 0x07CF 0x07D0 0x07D1 L L L DPLL loop BW 0x07D2 0x07D3 0x07D4 L L L DPLL R divider (20 bits) Tolerance Validation DPLL N divider (17 bits) 0x07D8 0x07D9 0x07DA DPLL fractional feedback divider (24 bits) DPLL fractional feedback divider modulus (24 bits) Lock detectors 0x07DE 0x07DF 0x07E0 0x07E1 0x07E2 0x07E3 0x07E4 0x07E5 0x07E6 L L L L L L L L L D6 D5 D4 D3 D2 D1 D0 Def Nominal reference period (fs), Bits[7:0] (default: 51.44 ns =1/(19.44 MHz) for default system clock setting) Nominal period (fs), Bits[15:8] Nominal period (fs), Bits[23:16] Nominal period (fs), Bits[31:24] Nominal period (fs), Bits[39:32] Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%) Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm) Reserved Inner tolerance, Bits[19:16] Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm) (default: 10%) Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm) Reserved Outer tolerance, Bits[19:16] Validation timer (ms), Bits[7:0] (up to 65.5 seconds) Validation timer (ms), Bits[15:8] (up to 65.5 seconds] 00 Reserved 00 00 Select base loop filter 0x07D5 0x07D6 0x07D7 0x07DB 0x07DC 0x07DD D7 Reserved Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz) Digital PLL loop bandwidth BW scaling factor[15:8] Reserved Sel high PM base loop filter BW scaling factor[16] R divider[7:0] R divider[15:8] Reserved Enable R divider[19:16] REFD divide-by-2 Digital PLL feedback divider--Integer Part N1[7:0] Digital PLL feedback divider--Integer Part N1[15:8] Reserved A2 94 1A 1D 14 00 00 0A 00 00 0A 00 F4 01 00 00 00 00 Digital PLL feedback divider-- Integer Part N1[16] 1F 5B 00 Digital PLL fractional feedback divider--FRAC1[7:0] Digital PLL fractional feedback divider--FRAC1[15:8] Digital PLL fractional feedback divider--FRAC1[23:16] 00 00 00 Digital PLL feedback divider modulus--MOD1[7:0] Digital PLL feedback divider modulus--MOD1[15:8] Digital PLL feedback divider modulus--MOD1[23:16] 01 00 00 Phase lock threshold (ps), Bits[7:0] Phase lock threshold(ps), Bits[15:8] Phase lock fill rate[7:0] Phase lock drain rate[7:0] Frequency lock threshold[7:0] Frequency lock threshold[15:8] Frequency lock threshold[23:16] Frequency lock fill rate[7:0] Frequency lock drain rate[7:0] BC 02 0A 0A BC 02 00 0A 0A Rev. B | Page 68 of 104 Data Sheet AD9558 Reg Addr (Hex) D7 D6 D5 D4 D3 D2 D1 D0 Def DCO PD SYSCLK PD Ref input PD TDC PD APLL PD Clock dist PD Full PD 00 0x0A01 Loop mode Soft reset exclude regmap Reserved User holdover User freerun User ref in manual switchover mode 00 0x0A02 Cal/sync Opt Name Operational Controls 0x0A00 Power-down Reserved 0x0A03 A 0x0A04 A 0x0A05 A 0x0A06 A 0x0A07 A 0x0A08 A Reserved 0x0A09 A Reserved 0x0A0A A Increment phase offset 0x0A0B A Manual reference validation Manual reference invalidation Static reference validation 0x0A0C 0x0A0D Clear/reset functions IRQ clearing Reserved Clear LF Clear CCI Reserved Reserved Reserved SYSCLK unlocked SYSCLK locked Pin program end Holdover Reserved Switching L, E 0x0C04 L, E 0x0C05 L, E 0x0C06 L, E 0x0C07 L, A, E L, E 0x0C08 Closed Freerun Reserved Quick In-Out Frequency Soft Pin Configuration 0x0C00 L, E Enable Soft Pin Section 1 0x0C01 L, E Soft Pin Section 1 0x0C02 L, E 0x0C03 Enable Soft Pin Section 2 Soft Pin Section 2 REF switchover mode[2:0] REFB validated REFD validated REFB fault cleared REFD fault cleared Reserved Soft sync clock dist Clear all IRQs Reserved 00 Clear watchdog 00 APLL cal started EEPROM complete 00 Clear auto sync APLL unlocked Sync clock dist Clear TW history APLL locked Watchdog timer Reserved Phase unlocked Phase slew unlimited REFA fault cleared REFC fault cleared Phase locked Phase slew limited REFA fault REFD fault Frequency locked Frequency clamped REFA validated REFC validated 00 History updated REFB fault Frequency unlocked Frequency unclamped Reserved REFC fault 00 Decrement phase offset Increment phase offset 00 Force Timeout B Force Timeout A 00 APLL cal ended EEPROM fault 00 00 00 Reserved Force Timeout D Reset phase offset Force Timeout C Reserved REF Mon Override D REF Mon Override C REF Mon Override B REF Mon Override A 00 Reserved REF Mon Bypass D REF Mon Bypass C REF Mon Bypass B REF Mon Bypass A 00 En Soft Pin Section 1 00 Reserved Output frequency selection[3:0] Reserved Reserved REFD frequency scale[1:0] Channel 3 output frequency scale[1:0] Reserved REFC frequency scale[1:0] Channel 2 output frequency scale[1:0] Sel high PM base loop filter Reserved Reserved Rev. B | Page 69 of 104 Input frequency selection[3:0] SYSCLK PLL REF selection[1:0] En Soft Pin Section 2 00 00 00 REFB frequency scale[1:0] REFA frequency scale[1:0] 00 Channel 1 output frequency scale[1:0] DPLL BW[1:0] Channel 0 output frequency scale[1:0] REF tolerance[1:0] 00 Soft pin start transfer Soft pin reset 00 00 00 AD9558 Data Sheet Reg Addr (Hex) Opt Name D7 D6 D5 Read-Only Status (Accessible During EEPROM Transactions) 0x0D00 R, L EEPROM Reserved D4 D3 D2 D1 D0 Def Fault detected Load in progress Save in progress N/A 0x0D01 R, L SYSCLK and PLL status All PLLs locked APLL VCO status Pin program ROM load process APLL cal in progress APLL lock SYSCLK stable SYSCLK lock detect N/A 0x0D02 R, L IRQ monitor events SYSCLK unlocked SYSCLK locked APLL unlocked APLL lock detect APLL cal ended APLL cal started N/A 0x0D03 R, L Output dist sync Watchdog timer EEPROM fault EEPROM complete N/A 0x0D04 R, L Freerun Pin program end Holdover R, L 0x0D06 R, L Reserved R, L Reserved Phase unlocked Phase slew unlimited REFA fault cleared REFC fault cleared Phase locked Phase slew limited REFA fault 0x0D07 Frequency locked Frequency clamped REFA validated REFC validated N/A 0x0D05 Frequency unlocked Frequency unclamped Reserved REFC fault N/A 0x0D08 R Holdover Active Freerun N/A 0x0D09 R 0x0D0A 0x0D0B R R REFA/REFB B valid B fault B fast B slow Reserved A valid A fault A fast A slow N/A N/A 0x0D0C R REFC/REFD D valid D fault D fast D slow C valid C fault C fast C slow N/A Reserved DPLL_ APLL_ Lock Reserved Reserved Switching Closed Reserved DPLL Reserved 0x0D0D R Holdover history 0x0D0E R 0x0D0F R 0x0D10 R 0x0D11 R Lock detector phase tub 0x0D12 R 0x0D13 R Lock detector frequency tub 0x0D14 R Nonvolatile Memory (EEPROM) Control 0x0E00 E Write protect 0x0E01 0x0E02 E A,E Condition Save 0x0E03 A,E Load REFB validated REFD validated Offset slew limiting Reserved REFB fault cleared REFD fault cleared Frequency lock Frequency clamped History updated REFB fault REFD fault Reserved Phase lock Loop switching Reserved History available Active reference priority Current active reference Tuning word readback[31:0] Phase tub[11:8] Frequency tub[7:0] Reserved Frequency tub[11:8] Reserved Reserved Write enable Conditional value[3:0] Reserved Reserved Rev. B | Page 70 of 104 Save to EEPROM Load from EEPROM N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Phase tub[7:0] Reserved N/A 00 00 00 00 Data Sheet Reg Addr (Hex) Opt Name EEPROM Storage Sequence 0x0E10 E EEPROM ID 0x0E11 E 0x0E12 E 0x0E13 E System clock 0x0E14 E 0x0E15 E 0x0E16 E I/O update 0x0E17 E General 0x0E18 E 0x0E19 E 0x0E1A E DPLL 0x0E1B E 0x0E1C E 0x0E1D E APLL 0x0E1E E 0x0E1F E 0x0E20 E Clock dist 0x0E21 E 0x0E22 E 0x0E23 E I/O update 0x0E24 E Reference inputs 0x0E25 E 0x0E26 E 0x0E27 E 0x0E28 E 0x0E29 E 0x0E2A E Profile REFA 0x0E2B E 0x0E2C E 0x0E2D E Profile REFB 0x0E2E E 0x0E2F E 0x0E30 E Profile REFC 0x0E31 E 0x0E32 E 0x0E33 E Profile REFD 0x0E34 E 0x0E35 E 0x0E36 E I/O update 0x0E37 E Operational controls 0x0E38 E 0x0E39 E 0x0E3A E Calibrate APLL 0x0E3B E I/O update 0x0E3C E End of data 0x0E3D E Unused to 0xE45 AD9558 D7 D6 D5 D4 D3 D2 Data: two bytes Address: 0x0006 Data: nine bytes Address: 0x0100 Action: I/O update Data: 18 bytes Address: 0x0200 Data: 47 bytes Address: 0x0300 Data: nine bytes Address: 0x0400 Data: 22 bytes Address: 0x0500 Action: I/O update Data: four bytes Address: 0x0600 Data: two bytes Address: 0x0640 Data: 39 bytes Address: 0x0700 Data: 39 bytes Address: 0x0740 Data: 39 bytes Address: 0x0780 Data: 39 bytes Address: 0x07C0 Action: I/O update Data: 14 bytes Address: 0x0A00 Action: calibrate output PLL Action: I/O update Action: End of data Unused (available for additional EEPROM instructions) Rev. B | Page 71 of 104 D1 D0 Def 01 00 06 08 01 00 80 11 02 00 2E 03 00 08 04 00 15 05 00 80 03 06 00 01 06 40 26 07 00 26 07 40 26 07 80 26 07 C0 80 0D 0A 00 A0 80 FF 00 AD9558 Data Sheet REGISTER MAP BIT DESCRIPTIONS SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005) Table 36. Serial Configuration (Note that the contents of Register 0x0000 are not stored to the EEPROM.) Address 0x0000 Bits 7 Bit Name SDO enable 6 LSB first/increment address 5 Soft reset [4:0] Reserved Description Enables SPI port SDO pin. 1 = 4-wire (SDO pin enabled). 0 (default) = 3-wire. Bit order for SPI port. 1 = least significant bit and byte first. Register addresses are automatically incremented in multibyte transfers. 0 (default) = most significant bit and byte first. Register addresses are automatically decremented in multibyte transfers. Device reset (invokes an EEPROM download or pin program ROM download if EEPROM or pin program is enabled. See the EEPROM and Pin Configuration and Function Descriptions sections for details. Reserved. Table 37. Readback Control Address 0x0004 Bits [7:1] Bit Name Reserved Description Reserved. 0 Read buffer register For buffered registers, serial port readback reads from actual (active) registers instead of the buffer. 1 = reads buffered values that take effect on next assertion of I/O update. 0 (default) = reads values currently applied to the device's internal logic. Table 38. Soft I/O Update Address 0x0005 Bits [7:1] 0 Bit Name Reserved I/O update Description Reserved. Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the device's internal control registers. Unless a register is marked as live (as indicated by an L in the Opt column of the register map), the user must write to this bit before any register settings can take effect and before a read-only register can be updated with the most current value. This is an autoclearing bit. Table 39. User Scratch Pad Address 0x0006 0x0007 Bits [7:0] [7:0] Bit Name User scratch pad[7:0] User scratch pad[15:8] Description User programmable EEPROM ID registers. These registers enable users to write a unique code of their choosing to keep track of revisions to the EEPROM register loading. It has no effect on part operation. 0 = default. SILICON REVISION (REGISTER 0x000A) Table 40. Silicon Revision Address 0x000A Bits [7:0] Bit Name Silicon revision Description This read-only register identifies the revision level of the AD9558. CLOCK PART SERIAL ID (REGISTER 0x000C TO REGISTER 0x000D) Table 41. Clock Part Family ID Address 0x000C Bits [7:0] Bit Name Clock part family ID[7:0] 0x000D [7:0] Clock part family ID[15:8] Description This read-only register (along with Register 0x000D) uniquely identifies an AD9557 or AD9558. No other part in the ADI AD95xx family has a value of 0x0001 in these two registers. Default: 0x01 for the AD9557 and AD9558. This register is a continuation of Register 0x000C. Default: 0x00 for the AD9557 and AD9558. Rev. B | Page 72 of 104 Data Sheet AD9558 SYSTEM CLOCK (REGISTER 0x0100 TO REGISTER 0x0108) Table 42. System Clock PLL Feedback Divider (N3 Divider) Address 0x0100 Bits [7:0] Bit Name SYSCLK N3 divider Description System clock PLL feedback divider value: 4 N3 255 (default: 0x08). Table 43. SYSCLK Configuration Address 0x0101 Bits [7:5] 4 Bit Name Reserved Load from ROM (read-only) 3 SYSCLK XTAL enable [2:1] SYSCLK P divider 0 SYSCLK doubler enable Description Reserved. This read-only bit is set if the PINCONTROL pin was high during the last power-on. 0 = The PINCONTROL pin was low at power-on (or reset). 1 = The PINCONTROL pin was high at power-on (or reset). Enables the crystal maintaining amplifier for the system clock input. 1 (default) = crystal mode (crystal maintaining amplifier enabled). 0 = external XO or other system clock source. System clock input divider. 00 (default) = 1. 01 = 2. 10 = 4. 11 = 8. Enable clock doubler on system clock input to reduce noise. 0 = disable. 1 (default) = enable. Table 44. Nominal System Clock Period1 Address 0x0103 Bits [7:0] 0x0104 [7:0] 0x0105 [7:5] [4:0] 1 Bit Name Nominal system clock period (fs) Reserved Nominal system clock period (fs) Description System clock period, Bits[7:0]. Default: 0x0E. System clock period, Bits[15:8]. Default: 0x67. Reserved. System clock period, Bits[20:16]. Default: 0x13. Note that the default setting for system clock period is 1.271566 ns, which is the period of 786.432 MHz (= 49.152 MHz x 16). Table 45. System Clock Stability Period Address 0x0106 Bits [7:0] 0x0107 [7:0] 0x0108 [7:5] 4 [3:0] Bit Name System clock stability period (ms) Reserved Reset SYSCLK stability timer System clock stability period Description System clock period, Bits[7:0]. Default: 0x32 (0x000032 = 50 ms). System clock period, Bits[15:8]. Default: 0x00. Reserved. This autoclearing bit resets the system clock stability timer. System clock period, Bits[19:16]. Default: 0x00. Rev. B | Page 73 of 104 AD9558 Data Sheet GENERAL CONFIGURATION (REGISTER 0x0200 TO REGISTER 0x0214) Multifunction Pin Control (M0 to M7) and IRQ Pin Control (Register 0x0200 to Register 0x0209) Note that the default setting for the M0 to M5 multifunction pins and the IRQ is that of a 3-level logic input; M6 and M7 are unused inputs at startup. After startup, M0 to M7 are 2-level inputs or 2-level outputs, based on the settings of Register 0x0200 to Register 0x0208. Setting Bit 0 in Register 0x0200 to 1 enables M0 to M7 pin functionality. Table 46. Multifunction Pin (M0 to M7) Control Address 0x0200 Bits [7:1] 0 Bit Name Reserved Enable M pins and IRQ pin function 0x0201 7 M0 output/input 0x0202 [6:0] 7 M0 function M1 output/input 0x0203 [6:0] 7 M1 function M2 output/input 0x0204 [6:0] 7 M2 function M3 output/input 0x0205 [6:0] 7 M3 function M4 output/input 0x0206 [6:0] 7 M4 function M5 output/input 0x0207 [6:0] 7 M5 function M6 output/input 0x0208 [6:0] 7 M6 function M7 output/input [6:0] M7 function A A E E See Table 129 and Table 130. Default: 0xB1 = REFB valid. In/out control for M2 pin (same as M0). A E See Table 129 and Table 130. Default: 0xC0 = REFA active. In/out control for M3 pin (same as M0). A E See Table 129 and Table 130. Default: 0xC1 = REFB active. In/out control for M3 pin (same as M0). A E See Table 129 and Table 130. Default: 0xB2 = REFC valid. In/out control for M3 pin (same as M0). A E See Table 129 and Table 130. Default: 0xB3 = REFD valid. In/out control for M3 pin (same as M0). A A Description Reserved. 0 (default) = disables the function of the M pins and IRQ pin control register (Address 0x0201 to Address 0x0209) and the M pins and IRQ pin are in 3-level logic input state. 1 = the M pins and IRQ pin are out of 3-level logic input state. Enables the function of the M pins and IRQ pin control register (Address 0x0201 to Address 0x0209). In/out control for M0 pin. 0 = input (2-level logic control pin). 1 (default) = output (2-level logic status pin). See Table 129 and Table 130. Default: 0xB0 = REFA valid. In/out control for M1 pin (same as M0). E E See Table 129 and Table 130. Default: 0xC2 = REFC active. In/out control for M3 pin (same as M0). See Table 129 and Table 130. Default: 0xC3 = REFD active. Table 47. IRQ Pin Output Mode Address 0x0209 Bits [7:5] [4:3] Bit Name Reserved Status signal at IRQ pin 2 Use IRQ pin for status signal [1:0] IRQ pin driver type Description Default: 000b This selection is valid only when Address 0x0209[2] = 1 00 = DPLL phase locked 01 = DPLL frequency locked 10 = system clock PLL locked 11 (default) = (DPLL phase locked) AND (system clock PLL locked) AND (APLL locked) 0 = uses IRQ pin to monitor IRQ event 1 (default) = uses IRQ pin to monitor internal status signals Select the output mode of the IRQ pin 00 = NMOS, open drain (requires an external pull-up resistor) 01 = PMOS, open drain (requires an external pull-down resistor) 10 = CMOS, active high 11 (default) = CMOS, active low Rev. B | Page 74 of 104 Data Sheet AD9558 IRQ MASK (REGISTER 0x020A TO REGISTER 0x020F) The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (0x0D02 to 0x0D09). When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts. Table 48. IRQ Mask for SYSCLK Address 0x020A Bits [7:6] 5 4 3 2 1 0 Bit Name Reserved SYSCLK unlocked SYSCLK locked APLL unlocked APLL locked APLL cal complete APLL cal started Description Reserved Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked Enables IRQ for indicating an APLL state transition from locked to unlocked Enables IRQ for indicating an APLL state transition from unlocked to locked Enables IRQ for indicating that APLL (LCVCO) calibration has completed Enables IRQ for indicating that APLL (LCVCO) calibration has begun Table 49. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM Address 0x020B Bits [7:5] 4 3 2 1 0 Bit Name Reserved Pin program end Sync distribution Watchdog timer EEPROM fault EEPROM complete Description Reserved Enables IRQ for indicating successful completion of a pin program ROM load Enables IRQ for indicating a distribution sync event Enables IRQ for indicating expiration of the watchdog timer Enables IRQ for indicating a fault during an EEPROM load or save operation Enables IRQ for indicating successful completion of an EEPROM load or save operation Table 50. IRQ Mask for the Digital PLL Address 0x020C Bits 7 6 5 4 3 2 1 0 Bit Name Switching Closed Freerun Holdover Frequency unlocked Frequency locked Phase unlocked Phase locked Description Enables IRQ for indicating that the DPLL is switching to a new reference Enables IRQ for indicating that the DPLL has entered closed-loop operation Enables IRQ for indicating that the DPLL has entered free run mode Enables IRQ for indicating that the DPLL has entered holdover mode Enables IRQ for indicating that the DPLL lost frequency lock Enables IRQ for indicating that the DPLL has acquired frequency lock Enables IRQ for indicating that the DPLL lost phase lock Enables IRQ for indicating that the DPLL has acquired phase lock Table 51. IRQ Mask for History Update, Frequency Limit and Phase Slew Limit Address 0x020D Bits [7:5] 4 3 2 1 Bit Name Reserved History updated Frequency unclamped Frequency clamped Phase slew unlimited 0 Phase slew limited Description Reserved Enables IRQ for indicating the occurrence of a tuning word history update Enables IRQ for indicating a frequency limit state transition from clamped to unclamped Enables IRQ for indicating a state transition of the frequency limiter from unclamped to clamped Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to not slew limiting Enables IRQ for indicating a state transition of the phase slew limiter from not slew limiting to slew limiting Rev. B | Page 75 of 104 AD9558 Data Sheet Table 52. IRQ Mask for Reference Inputs Address 0x020E 0x020F Bits 7 6 5 4 3 2 1 0 [7:0] Bit Name Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault Reserved Description Reserved Enables IRQ for indicating that REFB has been validated Enables IRQ for indicating that REFB has been cleared of a previous fault Enables IRQ for indicating that REFB has been faulted Reserved Enables IRQ for indicating that REFA has been validated Enables IRQ for indicating that REFA has been cleared of a previous fault Enables IRQ for indicating that REFA has been faulted Reserved Table 53. Watchdog Timer 11 Address 0x0210 0x0211 1 Bits [7:0] [7:0] Bit Name Watchdog timer (ms) Description Watchdog timer, Bits[7:0]; default: 0x00 Watchdog timer, Bits[15:8]; default: 0x00 Note that the watchdog timer is expressed in units of milliseconds (ms). The default value is 0 (disabled). DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x032E) Table 54. Free Run Frequency Tuning Word1 Address 0x0300 0x0301 0x0302 0x0303 1 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name 30-bit free run frequency tuning word Reserved 30-bit free run frequency word Description Free run frequency tuning word, Bits[7:0]; default: 0x11 Free run frequency tuning word, Bits[15:8]; default: 0x15 Free run frequency tuning word, Bits[23:9]; default: 0x64 Reserved Free run frequency tuning word, Bits[29:24]; default: 0x1B Note that the default free run tuning word is 0x1B641511, which is used for 8 kHz/19.44 MHz = 622.08 MHz translation. Table 55. Digital Oscillator Control Address 0x0304 Bits [7:6] 5 Bit Name Reserved DCO 4-level output 4 [3:0] Reserved Reserved Description Default: 00b 0 (default) = DCO 3-level output mode 1 = enables DCO 4-level output mode Reserved (must be set to 1b) Reserved (default: 0x0) Table 56. DPLL Frequency Clamp Address 0x0306 Bits [7:0] Bit Name Lower limit of pull-in range (expressed as a 20-bit frequency tuning word) 0x0307 [7:0] 0x0308 [7:4] [3:0] Reserved Lower limit of pull-in range 0x0309 [7:0] 0x030A [7:0] Upper limit of pull-in range (expressed as a 20-bit frequency tuning word) 0x030B [7:4] [3:0] Reserved Upper limit of pull-in range Description Lower limit pull-in range, Bits[7:0]. Default: 0x51. Lower limit pull-in range, Bits[15:8]. Default: 0xB8. Default: 0x0. Lower limit pull-in range, Bits[19:16]. Default: 0x2. Upper limit pull-in range, Bits[7:0]. Default: 0x3E. Upper limit pull-in range, Bits[15:8]. Default: 0x0A. Default: 0x0. Upper limit pull-in range, Bits[19:16]. Default: 0xB. Rev. B | Page 76 of 104 Data Sheet AD9558 Table 57. Fixed Closed-Loop Phase Lock Offset Address 0x030C Bits [7:0] 0x030D [7:0] 0x030E [7:0] 0x030F [7:6] [5:0] Bit Name Fixed phase lock offset (signed; ps) Reserved Fixed phase lock offset (signed; ps) Description Fixed phase lock offset, Bits[7:0]. Default: 0x00. Fixed phase lock offset, Bits[15:8]. Default 0x00. Fixed phase lock offset, Bits[23:16]. Default: 0x00. Reserved; default: 0x0. Fixed phase lock offset, Bits[29:24]. Default: 0x00. Table 58. Incremental Closed-Loop Phase Lock Offset Step Size1 Address 0x0310 Bits [7:0] 0x0311 [7:0] 1 Bit Name Incremental phase lock offset step size (ps) Description Incremental phase lock offset step size, Bits[7:0]. Default: 0x00. This controls the static phase offset of the DPLL while it is locked. Incremental phase lock offset step size, Bits[15:8]. Default: 0x00. This controls the static phase offset of the DPLL while it is locked. Note that the default incremental closed-loop phase lock offset step size value is 0x0000 = 0 (0 ns). Table 59. Phase Slew Rate Limit Address 0x0312 Bits [7:0] 0x0313 [7:0] Bit Name Phase slew rate limit (s/sec) Description Phase slew rate limit, Bits[7:0]. Default: 0x00. This register controls the maximum allowable phase slewing during transients and reference switching. The default phase slew rate limit is 0, or disabled. Minimum useful value is 310 s/sec. Phase slew rate limit, Bits[15:8]. Default: 0x00. Table 60. History Accumulation Timer Address 0x0314 Bits [7:0] 0x0315 [7:0] Bit Name History accumulation timer (ms) Description History accumulation timer bits[7:0]. Default: 0x0A. For Register 0x0314 and Register 0x0315, 0x000A = 10 ms. Maximum is 65 sec. This register controls the amount of tuning word averaging used to determine the tuning word used in holdover. Never program a timer value of zero. The default value is 0x000A = 10 decimal, which equates to 10 ms History accumulation timer bits[15:8]. Default: 0x00. Rev. B | Page 77 of 104 AD9558 Data Sheet Table 61. History Mode Address 0x0316 Bits [7:5] 4 Bit Name Reserved Single sample fallback 3 Persistent history [2:0] Incremental average Description Reserved. Controls holdover history. If tuning word history is not available for the reference that was active just prior to holdover, then: 0 (default) = uses the free run frequency tuning word register value. 1 = uses the last tuning word from the DPLL. Controls holdover history initialization. When switching to a new reference: 0 (default) = clears the tuning word history. 1 = retain the previous tuning word history. History mode value from 0 to 7 (default: 0). When set to non-zero, causes the first history accumulation to update prior to the first complete averaging period. After the first full interval, updates occur only at the full period. 0 (default) = update only after the full interval has elapsed. 1 = update at 1/2 the full interval. 2 = update at 1/4 and 1/2 of the full interval. 3 = update at 1/8, 1/4, and 1/2 of the full interval. ... 7 = update at 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, and 1/2 of the full interval. Table 62. Base Digital Loop Filter with High Phase Margin (PM = 88.5, BW = 0.1 Hz, Third Pole Frequency = 10 Hz, N1 = 1)1 Address 0x0317 0x0318 0x0319 0x031A 0x031B 0x031C 0x031D 0x031E 0x031F 0x0320 0x0321 0x0322 1 Bits [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] Bit Name HPM Alpha-0 linear Reserved HPM Alpha-1 exponent HPM Beta-0 linear Reserved HPM Beta-1 exponent HPM Gamma-0 linear Reserved HPM Gamma-1 exponent HPM Delta-0 linear Reserved HPM Delta-1 exponent Description Alpha-0 coefficient linear bits[7:0]. Default: 0x8C Alpha-0 coefficient linear bits[15:8] Reserved Alpha-1 coefficient exponent bits[6:0] Beta-0 coefficient linear bits[7:0] Beta-0 coefficient linear bits[15:8] Reserved Beta-1 coefficient exponent bits[6:0] Gamma-0 coefficient linear bits[7:0] Gamma-0 coefficient linear bits[15:8] Reserved Gamma-1 coefficient exponent bits[6:0] Delta-0 coefficient linear bits[7:0] Delta-0 coefficient linear bits[15:8] Reserved Delta-1 coefficient exponent bits[6:0] Note that the base digital loop filter coefficients (, , , and ) have the following general form: x(2y), where x is the linear component and y is the exponential component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 x 1. The exponential component (y) is a signed integer. Rev. B | Page 78 of 104 Data Sheet AD9558 Table 63. Base Digital Loop Filter with Normal Phase Margin (PM = 70, BW = 0.1 Hz, Third Pole Frequency = 2 Hz, N1 = 1)1 Address 0x0323 0x0324 0x0325 0x0326 0x0327 0x0328 0x0329 0x032A 0x032B 0x032C 0x032D 0x032E 1 Bits [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] Bit Name NPM Alpha-0 linear Reserved NPM Alpha-1 exponent NPM Beta-0 linear Reserved NPM Beta-1 exponent NPM Gamma-0 linear Reserved NPM Gamma-1 exponent NPM Delta-0 linear Reserved NPM Delta-1 exponent Description Alpha-0 coefficient linear, Bits[7:0] Alpha-0 coefficient linear, Bits[15:8] Reserved Alpha-1 coefficient exponent, Bits[6:0] Beta-0 coefficient linear, Bits[7:0] Beta-0 coefficient linear, Bits[15:8] Reserved Beta-1 coefficient exponent, Bits[6:0] Gamma-0 coefficient linear, Bits[7:0] Gamma-0 coefficient linear, Bits[15:8] Reserved Gamma-1 coefficient exponent, Bits[6:0] Delta-0 coefficient linear, Bits[7:0] Delta-0 coefficient linear, Bits[15:8] Reserved Delta-1 coefficient exponent, Bits[6:0] Note that the digital loop filter base coefficients (, , , and ) have the following general form: x(2y), where x is the linear component and y is the exponential component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 x 1. The exponential component (y) is a signed integer. OUTPUT PLL CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0408) Table 64. Output PLL Setting1 Address 0x0400 Bits [7:0] Bit Name Output PLL (APLL) charge pump current 0x0401 [7:0] APLL N divider 0x0402 0x0403 [7:0] [7:6] Reserved APLL loop filter control [5:3] Description LSB = 3.5 A 00000001b = 1 x LSB; 00000010b = 2 x LSB; 11111111b = 255 x LSB Default: 0x81 = 451 A CP current Division = 14 to 255 Default: 0x14 = divide-by-20 Reserved; default: 0x00 Pole 2 resistor Rp2; default: 0x07 Rp2 () Bit 7 Bit 6 500 (default) 0 0 333 0 1 250 1 0 200 1 1 Zero resistor, Rzero Rzero () Bit 5 Bit 4 Bit 3 1500 (default) 0 0 0 1250 0 0 1 1000 0 1 0 930 0 1 1 1250 1 0 0 1000 1 0 1 750 1 1 0 680 1 1 1 Rev. B | Page 79 of 104 AD9558 Data Sheet Address Bits [2:0] Bit Name 0x0404 [7:1] 0 Reserved Bypass internal Rzero 0x0405 [7:4] 3 Reserved APLL locked controlled sync [2:1] 0 Reserved Manual APLL VCO calibration 1 Description Pole 1 Cp1. Cp1 (pF) Bit 2 Bit 1 Bit 0 0 0 0 0 20 0 0 1 80 0 1 0 100 0 1 1 20 1 0 0 40 1 0 1 100 1 1 0 120 (default) 1 1 1 Default: 0x00. 0 (default) = uses the internal Rzero resistor. 1 = bypasses the internal Rzero resistor (makes Rzero = 0 and requires the use of a series external zero resistor). Default: 0x2. 0 (default) = the clock distribution sync function is not enabled until the output PLL (APLL) is calibrated and locked. After APLL calibration and lock, the output clock distribution sync is armed, and the sync function for the clock outputs is under the control of Register 0x0500. 1 = overrides the lock detector state of the output PLL; allows Register 0x0500 to control the output sync function, regardless of the APLL lock status. Default: 00b. 1 = initiates VCO calibration. (Calibration occurs on low-to-high transition.) 0 (default) = does nothing. This is not an autoclearing bit. Note that the default APLL loop BW is 180 KHz. Table 65. Reserved Address 0x0406 Bits [7:0] Bit Name Reserved Description Default: 0x00 Table 66. RF Divider Setting Address 0x0407 0x0408 Bits [7:4] Bit Name RF Divider 2 division [3:0] RF Divider 1 division [7:5] 4 Reserved RF divider start-up mode [3:2] 1 Reserved PD RF Divider 2 0 PD RF Divider 1 Description 0000/0001 = 3 0010 = 4 0011 = 5 0100 = 6 (default) 0101 = 7 0110 = 8 0111 = 9 1000 = 10 1001 = 11 0000/0001 = 3 0010 = 4 0011 = 5 0100 = 6 (default) 0101 = 7 0110 = 8 0111 = 9 1000 = 10 1001 = 11 Reserved. Default: 000b 0 (default) = RF dividers are held in power-down until the APLL feedback divider is detected, which ensures proper RF divider operation when exiting full power-down 1 = RF dividers are not held in power-down until the APLL feedback divider is detected Reserved. Default: 00b 0 = enables RF Divider 2 1 (default) = powers down RF Divider 2 0 (default) = enables RF Divider 1 1 = powers down RF Divider 1 Rev. B | Page 80 of 104 Data Sheet AD9558 OUTPUT CLOCK DISTRIBUTION (REGISTER 0x0500 TO REGISTER 0x0515) Table 67. Clock Distribution Output Synchronization Settings Address 0x0500 Bits 7 Bit Name Mask Channel 3 sync 6 Mask Channel 2 sync 5 Mask Channel 1 sync 4 Mask Channel 0 sync 3 2 Reserved Sync source selection [1:0] Automatic sync mode Description Masks the synchronous reset to the Channel 3 (M3) divider. 0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs. 1 = masked. Setting this bit asynchronously releases Channel 3 from the static SYNC state, thus allowing the Channel 3 divider to toggle. Channel 3 ignores all SYNC events while this bit is set. Setting this bit does not enable the output drivers connected to this channel. In addition, the output distribution sync also depends on the setting of Register 0x0405[3]. Masks the synchronous reset to the Channel 2 (M2) divider. 0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs. 1 = masked. Setting this bit asynchronously releases Channel 2 from the static SYNC state, thus allowing the Channel 2 divider to toggle. Channel 2 ignores all SYNC events while this bit is set. Setting this bit does not enable the output drivers connected to this channel. In addition, the output distribution sync also depends on the setting of Register 0x0405[3]. Masks the synchronous reset to the Channel 1 (M2) divider. 0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs. 1 = masked. Setting this bit asynchronously releases Channel 1 from the static SYNC state, thus allowing the Channel 1 divider to toggle. Channel 1 ignores all SYNC events while this bit is set. Setting this bit does not enable the output drivers connected to this channel. In addition, the output distribution sync also depends on the setting of Register 0x0405[3]. Masks the synchronous reset to the Channel 0 (M0) divider. 0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs. 1 = masked. Setting this bit asynchronously releases Channel 0 from the static SYNC state, thus allowing the Channel 0 divider to toggle. Channel 0 ignores all SYNC events while this bit is set. Setting this bit does not enable the output drivers connected to this channel. In addition, the output distribution sync also depends on the setting of Register 0x0405[3]. Default: 0b. Selects the sync source for the clock distribution output channels. 0 (default) = direct. The sync pulse happens on the next I/O update. 1 = active reference. Note that the output distribution sync also depends on the APLL being calibrated and locked unless Register 0x0405[3] = 1b. Autosync mode. 00 = disabled. A sync command must be issued manually, or by using the mask sync bits in this register (Bits[7:4]). 01 = sync on DPLL frequency lock. 10 (default) = sync on DPLL phase lock. 11 = reserved. Rev. B | Page 81 of 104 AD9558 Data Sheet Table 68. Distribution OUT0 Setting Address 0x0501 Bits 7 Bit Name Enable 3.3 V CMOS driver [6:4] OUT0 format [3:2] OUT0 polarity 1 OUT0 drive strength 0 Enable OUT0 Description 0 (default) = disables 3.3 V CMOS driver; the OUT5 1.8 V logic is controlled by Register 0x0501[6:4]. 1 = enables 3.3 V CMOS driver as operating mode of OUT0. This bit should be enabled only if Bits[6:4] are in CMOS mode. This control is valid when Register 0x0501[7] = 0. When Register 0x0501[7] = 1, OUT5 is in 3.3 V CMOS mode and these bits are ignored. Select the operating mode of OUT0. 000 = PD, tristate. 001 (default) = HSTL. 010 = LVDS. 011 = reserved. 100 = CMOS, both outputs active. 101 = CMOS, P output active, N output power-down. 110 = CMOS, N output active, P output power-down. 111 = reserved. Control the OUT0 polarity. 00 (default) = positive, negative. 01 = positive, positive. 10 = negative, positive. 11 = negative, nevative. Controls the output drive capability of OUT0. 0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal. 1 = CMOS: normal drive strength; LVDS: 4.5 mA nominal (LVDS boost mode). Note that this is only in 3.3 V CMOS mode for CMOS strength. 1.8 V CMOS has only the low drive strength. Enables/disables (1b/0b) OUT0 1.8 V driver (default is disabled). This bit does not enable/disable OUT0 if Bit 7 of this register is set. Table 69. Distribution Channel 0 Divider Setting Address 0x0502 Bits [7:0] Bit Name Channel 0 (M0) division ratio 0x0503 [7:4] 3 Reserved Channel 0 PD 2 Select RF Divider 2 [1:0] Channel 0 (M0) division ratio Reserved Channel 0 divider phase 0x0504 [7:6] [5:0] Description 10-bit channel divider bits[7:0] (LSB). Division equals channel divider, Bits[9:0] + 1. (Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2...Bits[9:0] = 1023 is divide-by-1024) Reserved. 0 (default) = normal operation. 1 = powers down Channel 0. 1 = selects RF Divider 2 as prescaler for Channel 0 divider. 0 (default) = selects RF Divider 1 as prescaler for Channel 0 divider. 10-bit channel divider, Bits[9:8] (MSB) Reserved. Default: 00b Divider initial phase after sync relative to the divider input clock (from the RF divider output). LSB is 1/2 of a period of the divider input clock. Default: 00000b. Phase = 0 is no phase offset. Phase = 1 is 1/2 a period offset. Rev. B | Page 82 of 104 Data Sheet AD9558 Table 70. Distribution OUT1 Setting Address 0x0505 0x0506 Bits 7 [6:4] Bit Name Reserved OUT1 format [3:2] OUT1 polarity 1 OUT1 drive strength 0 7 [6:4] Enable OUT1 Reserved OUT2 format [3:2] OUT2 polarity 1 OUT2 drive strength 0 Enable OUT2 Description Reserved; default: 0b Select the operating mode of OUT1 000 = PD, tristate 001 (default) = HSTL 010 = LVDS 011 = reserved 100 = CMOS, both outputs active 101 = CMOS, P output active, N output power-down 110 = CMOS, N output active, P output power-down 111 = reserved Configure the OUT1 polarity in CMOS mode and are active in CMOS mode only 00 (default) = positive, negative 01 = positive, positive 10 = negative, positive 11 = negative, negative Controls the output drive capability of OUT1 0 (default) = LVDS: 3.5 mA nominal 1 = LVDS: 4.5 mA nominal (LVDS boost mode) No CMOS control because OUT1 is 1.8 V CMOS only Setting this bit enables the OUT1 driver (default is disabled) Reserved; default: 0b Select the operating mode of OUT2 000 = PD, tristate 001 (default) = HSTL 010 = LVDS 011 = reserved 100 = CMOS, both outputs active 101 = CMOS, P output active, N output power-down 110 = CMOS, N output active, P output power-down 111 = reserved Configure the OUT2 polarity in CMOS mode and are active in CMOS mode only 00 (default) = positive, negative 01 = positive, positive 10 = negative, positive 11 = negative, negative Controls the output drive capability of OUT2 0 (default) = LVDS: 3.5 mA nominal 1 = LVDS: 4.5 mA nominal (LVDS boost mode) No CMOS control because OUT2 is 1.8 V CMOS only Setting this bit enables the OUT2 driver (default is disabled) Table 71. Distribution Channel 1 Divider Setting Address 0x0507 0x0508 0x0509 Bits [7:0] [7:0] [7:0] Bit Name Channel 1 divider Channel 1 divider Channel 1 divider Description The same control for Channel 1 divider as in Register 0x0502 for Channel 0 divider The same control for Channel 1 divider as in Register 0x0503 for Channel 0 divider The same control for Channel 1 divider as in Register 0x0504 for Channel 0 divider Table 72. Clock Distribution Channel 2 and OUT3, OUT4 Driver Settings Address 0x050A 0x050B 0x050C 0x050D 0x050E Bits [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name OUT3 OUT4 Channel 2 divider Channel 2 divider Channel 2 divider Description The same control for OUT3 as in Register 0x0505 for OUT1 The same control for OUT4 as in Register 0x0505 for OUT1 The same control for Channel 2 divider as in Register 0x0502 for Channel 0 divider The same control for Channel 2 divider as in Register 0x0503 for Channel 0 divider The same control for Channel 2 divider as in Register 0x0504 for Channel 0 divider Rev. B | Page 83 of 104 AD9558 Data Sheet Table 73. Clock Distribution Channel 3 and OUT5 Driver Settings Address 0x050F Bits 7 Bit Name Enable 3.3 V CMOS driver [6:4] OUT5 format [3:2] OUT5 polarity 1 OUT5 drive strength 0 OUT5 enable 0x0510 [7:0] Channel 3, Divider 1 (M3) division ratio 0x0511 [7:2] [1:0] 0x0512 [7:0] Reserved Channel 3, Divider 1 (M3) division ratio Channel 3, Divider 2 (M3b) division ratio 0x0513 [7:4] 4 Reserved Channel 3 doubler 3 PD Channel 3 2 Select RF divider for Channel 2 [1:0] Channel 3, Divider 2 (M3b) division ratio Channel 3, Divider 1 (M3) phase Channel 3, Divider 2 (M3b) phase 0x0514 [7:0] 0x0515 [7:0] Description 0 (default) = disable 3.3 V CMOS driver; the OUT5 1.8 V logic is controlled by Register 0x050F[6:4]. 1 = enable 3.3 V CMOS driver as operating mode of OUT5. This bit should be enabled only if Bits[6:4] are in CMOS mode. This control is valid when Register 0x050F[7] = 0; when Register 0x050F[7] = 1, OUT5 is in 3.3 V CMOS mode and these bits are ignored. Select the operating mode of OUT5. 000 = PD, tristate. 001 (default) = HSTL. 010 = LVDS. 011 = reserved. 100 = CMOS, both outputs active. 101 = CMOS, P output active, N output power-down. 110 = CMOS, N output active, P output power-down. 111 = reserved. Control the OUT5 polarity. 00 (default) = positive, negative. 01 = positive, positive. 10 = negative, positive. 11 = negative, negative. Controls the output drive capability of OUT5. 0 (default) = CMOS: low drive strength, LVDS: 3.5 mA nominal. 1 = CMOS: normal drive strength, LVDS: 4.5 mA nominal (LVDS boost mode). Note that this is only in 3.3 V CMOS mode for CMOS strength. 1.8 V CMOS has only the low drive strength. Enables/disables (1b/0b) OUT5 1.8 V driver (default is disabled). This bit does not enable/disable OUT5 if Bit 7 of this register is set. 10-bit channel divider, Bits[7:0] (LSB) (default: 0x03). Division equals channel divider, Bits[9:0] + 1. (Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2...Bits[9:0] = 1023 is divide-by-1024). Reserved. 10-bit channel divider, Bits[9:8] (MSB) (default: 0x00). 10-bit channel divider, Bits[7:0] (LSB). Division equals channel divider bits[9:0] + 1 . (Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2...Bits[9:0] = 1023 is divide-by-1024). Reserved. 0 (default) = normal operation. 1 = enables Channel 3 clock doubler. This bit activates an internal clock doubler that doubles the frequency of the Channel 3 divider. In this mode, Channel 3, Divider 2 is bypassed. 0 (default) = normal operation. 1 = powers down Channel 3. 1 = selects RF Divider 2 as prescaler for the Channel 3 divider. 0 (default) = selects RF Divider 1 as a prescaler for the Channel 3 divider. 10-bit channel divider, Bits[9:8] (MSB). The same control for Channel 3, Divider 1 phase as found in Register 0x0504 for Channel 0 divider phase (default: 0x00). The same control for Channel 3, Divider 2 phase as found in Register 0x0504 for Channel 0 divider phase (default: 0x00). Rev. B | Page 84 of 104 Data Sheet AD9558 REFERENCE INPUTS (REGISTER 0x0500 TO REGISTER 0x0507) Table 74. Reference Power-Down1 Address 0x0600 1 Bits [7:4] 3 2 1 0 Bit Name Reserved REFD power-down REFC power-down REFB power-down REFA power-down Description Default: 0x0 Power down REFD input receiver (default: not powered down). Power down REFC input receiver (default: not powered down). Power down REFB input receiver (default: not powered down). Power down REFA input receiver (default: not powered down). When all bits are set the reference receiver section enters a deep sleep mode. Table 75. Reference Logic Family Address 0x0601 Bits [7:6] Bit Name REFD logic family [5:4] [3:2] [1:0] REFC logic family REFB logic family REFA logic family Description Select logic family for REFD input receiver; only REFD_P is used in CMOS mode 00 (default) = differential 01 = 1.2 V to 1.5 V CMOS 10 = 1.8 V to 2.5 V CMOS 11 = 3.0 V to 3.3 V CMOS Same as Register 0x0601[7:6] for REFC Same as Register 0x0601[7:6] for REFB Same as Register 0x0601[7:6] for REFA Table 76. Reference Priority Setting Address 0x0602 Bits [7:6] Bit Name REFD priority family [5:4] [3:2] [1:0] REFC priority family REFB priority family REFA priority family Description User-assigned priority level (0 to 3) of the reference associated with REFB, which ranks that reference relative to the others. 00 (default) = 0. 01 = 1. 10 = 2. 11 = 3. Same as Register 0x0602[7:6] for REFC. Same as Register 0x0602[7:6] for REFB. Same as Register 0x0602[7:6] for REFA. Rev. B | Page 85 of 104 AD9558 Data Sheet FRAME SYNCHRONIZATION (REGISTER 0x0640 TO REGISTER 0x0641) Table 77. Frame Sync Setting Address 0x0640 Bit(s) [7:1] 0 Bit Name Reserved Enable Fsync 0x0641 [7:4] 3 Reserved Validate Fsync ref 2 Fsync one shot 1 Fsync arm method 0 Arm soft Fsync Description Reserved; default: 0x00. Enable frame synchronization. 0 (default) = frame synchronization disabled. 1 = frame synchronization enabled. Reserved; default: 0x00. Setting this bit forces the reference validation logic to declare REFA valid only if the REFB (the sync pulse) input is also valid. This bit can be thought as a logical AND of REFA VALID and REFB VALID signals. If REFC is selected, this bit requires that REFD (the sync pulse) input also be valid before declaring REFC valid. 0 (default) = only the selected reference input must be valid. 1 = the sync pulse input must also be valid to validate the selected input. Selects one-shot or level-sensitive frame sync function. 0 (default) = use level-sensitive frame sync. Frame sync occurs on every edge of the frame pulse. 1 = use one-shot frame sync. Frame sync occurs only on the first frame sync pulse (on REFB or REFD). User must re-arm by raising the SYNC pin high and then low, or by clearing and resetting the arm soft Fsync bit. As with all buffered registers, an I/O update is required (Register 0x0005[0] = 0x01) after writing this register. Selects which signal is used to arm the frame sync 0 (default) = use SYNC pin. 1 = use arm soft Fsync (Register 0x0641[0]). Arms frame sync after I/O update. Next pulse on REFB or REFD is the sync pulse. The Fsync arm method bit must also be set for this bit to take effect. 0 = (default); frame sync unarmed. 1 = frame sync armed. Rev. B | Page 86 of 104 Data Sheet AD9558 DPLL PROFILE REGISTERS (REGISTER 0x0700 TO REGISTER 0x07E6) Note that the default values of the REFA and REFC profiles are as follows: input frequency=19.44 MHz, output frequency = 622.08 MHz/ 155.52 MHz, loop bandwidth = 400 Hz, normal phase margin, inner tolerance = 5%, and outer tolerance = 10%. The default values of the REFB and REFD profiles are as follows: input frequency = 8 kHz, output frequency = 622.08 MHz/155.52 MHz, loop bandwidth = 100 Hz, normal phase margin, inner tolerance = 5%, and outer tolerance = 10%. REFA Profile (Register 0x0700 to Register 0x0726) Table 78. Reference Period--REFA Profile Address 0x0700 0x0701 0x0702 0x0703 0x0704 Bits [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name Nominal reference period (fs) Description Nominal reference period bits[7:0] (default: 0xC9). Nominal reference period bits[15:8] (default: 0xEA). Nominal reference period bits[23:16] (default: 0x10). Nominal reference period bits[31:24] (default: 0x03). Nominal reference period bits[39:32] (default: 0x00). Default for Register 0x0700 to Register 0x0704 = 0x000310EAC9 = 51.44 ns (1/19.44 MHz). Table 79. Reference Period Tolerance--REFA Profile Address 0x0705 0x0706 0x0707 Bits [7:0] [7:0] [7:4] [3:0] Bit Name Inner tolerance 0x0708 0x0709 0x070A [7:0] [7:0] [7:4] [3:0] Outer tolerance Reserved Inner tolerance Reserved Outer tolerance Description Input reference frequency monitor inner tolerance, Bits[7:0] (default: 0x14). Input reference frequency monitor inner tolerance, Bits[15:8] (default: 0x00). Default: 0x0. Input reference frequency monitor inner tolerance, Bits[19:16]. Default for Register 0x0705 to Register 0x707 = 0x000014 = 20 (5% or 50,000 ppm). The Stratum 3 clock requires inner tolerance of 9.2 ppm and outer tolerance of 12 ppm; an SMC clock requires an outer tolerance of 48 ppm. The allowable range for the inner tolerance is 0x00A (10%) to 0x8FF (1 ppm). The tolerance of the input frequency monitor is only as accurate as the system clock frequency. Input reference frequency monitor outer tolerance, Bits[7:0] (default: 0x0A). Input reference frequency monitor outer tolerance, Bits[15:8] (default: 0x00). Reserved. Input reference frequency monitor outer tolerance, Bits[19:16]. Default for Register 0x0708 to Register 0x70A = 0x00000A = 10 (10% or 100,000 ppm). The Stratum 3 clock requires an inner tolerance of 9.2 ppm and outer tolerance of 12 ppm; an SMC clock requires outer tolerance of 48 ppm. The outer tolerance register setting should always be smaller than the inner tolerance. Table 80. Reference Validation Timer--REFA Profile Address 0x070B Bits [7:0] 0x070C [7:0] Bit Name Validation timer (ms) Description Validation timer, Bits[7:0] (default: 0x0A). This is the amount of time a reference input must be valid before it is declared valid by the reference input monitor (default: 10 ms). Validation timer, Bits[15:8] (default: 0x00). Table 81. Reserved Register Address 0x070D Bits [7:0] Bit Name Reserved Description Reserved. Default: 0x00. Table 82. DPLL Base Loop Filter Selection--REFA Profile Address 0x070E Bits [7:1] 0 Bit Name Reserved Sel high PM base loop filter Description Reserved. Default: 0x00. 0 = base loop filter with normal (70) phase margin (default). 1 = base loop filter with high (88.5) phase margin. (0.1 dB peaking in the closed-loop transfer function for loop BWs 2 kHz. Setting this bit is also recommended for loop BW > 2kHz.) Rev. B | Page 87 of 104 AD9558 Data Sheet Table 83. DPLL Loop BW Scaling Factor--REFA Profile1 Address 0x070F 0x0710 Bits [7:0] [7:0] Bit Name DPLL loop BW scaling factor (unit of 0.1 Hz) 0x0711 [7:1] 0 Reserved BW scaling factor 1 Description Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4). Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01). The default for Register 0x070F to Register 0x0710 = 0x01F4 = 500 (50 Hz loop bandwidth). The loop bandwidth should always be less than the DPLL phase detector frequency divided by 20. Default: 0x00. Digital PLL loop bandwidth scaling factor, Bit 16 (default: 0b). Note that the default DPLL loop BW is 50.4 Hz. Table 84. R-Divider--REFA Profile1 Address 0x0712 0x0713 0x0714 1 Bits [7:0] [7:0] [7:5] 4 Bit Name R divider [3:0] R divider Reserved Enable REFA div2 Description DPLL integer reference divider (minus 1), Bits[7:0] (default: 0xC5) DPLL integer reference divider, Bits[15:8] (default: 0x00) Reserved. Default: 0x0 Enables the reference input divide-by-2 for REFA 0 = bypass the divide-by-2 (default) 1 = enable the divide-by-2 DPLL integer reference divider, Bits[19:16] (default: 0x0). The default for Register 0x0712 to Register 0x0714 = 0x000C5 = 197 (which equals R = 198). Note that the value stored in the R-divider register yields an actual divide ratio of one more than the programmed value. Table 85. Integer Part of Fractional Feedback Divider N1--REFA Profile1 Address 0x0715 0x0716 0x0717 1 Bits [7:0] [7:0] [7:1] 0 Bit Name Integer Part N1 Reserved Integer Part N1 Description DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0x6B). DPLL integer feedback divider, Bits[15:8] (default: 0x07). Reserved. Default: 0x00. DPLL integer feedback divider, Bit 16 (default: 0b). The default for Register 0x0715 to Register 0x717 = 0x0076B (which equals N1 = 1900). Note that the value stored in the N1-divider register yields an actual divide ratio of one more than the programmed value. Table 86. Fractional Part of Fractional Feedback Divider FRAC1--REFA Profile Address 0x0718 0x0719 0x071A Bits [7:0] [7:0] [7:0] Bit Name Digital PLL fractional feedback divider--FRAC1 Description The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04) The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00) The numerator of the fractional-N feedback divider, Bits[23:16] (default: 0x00) Table 87. Modulus of Fractional Feedback Divider MOD1--REFA Profile Address 0x071B 0x071C 0x071D Bits [7:0] [7:0] [7:0] Bit Name Digital PLL feedback divider modulus--MOD1 Description The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05) The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00) The denominator of the fractional-N feedback divider, Bits[23:16] (default: 0x00) Table 88. Phase and Frequency Lock Detector Controls--REFA Profile Address 0x071E 0x071F 0x0720 0x0721 0x0722 0x0723 0x0724 0x0725 0x0726 Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name Phase lock threshold Phase lock fill rate Phase lock drain rate Frequency lock threshold Frequency lock fill rate Frequency lock drain rate Description Phase lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps Phase lock threshold, Bits[15:8] (default: 0x02) Phase lock fill rate, Bits[7:0] (default:0x0A = 10 code/PFD cycle) Phase lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle) Frequency lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps Frequency lock threshold, Bits[15:8] (default: 0x02) Frequency lock threshold, Bits[23:16] (default: 0x00) Frequency lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle) Frequency lock drain rate bits[7:0] (default: 0x0A = 10 code/PFD cycle) Rev. B | Page 88 of 104 Data Sheet AD9558 REFB Profile (Register 0x0740 to Register 0x0766) REFB Profile Register 0x0740 to Register 0x0766 are identical to REFA Profile Register 0x0700 to Register 0x0726. REFC Profile (Register 0x0780 to Register 0x07A6) REFC Profile Register 0x0780 to Register 0x07A6 are identical to REFA Profile Register 0x0700 Register 0x0726. REFD Profile (Register 0x07C0 to Register 0x07E6) REFD Profile Register 0x07C0 to Register 0x07E6 are identical to REFA Profile Register 0x0700 to Register 0x0726. OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10) Table 89. General Power-Down Address 0x0A00 Bits 7 6 5 5 3 2 1 0 Bit Name Soft reset exclude regmap DCO power-down SYSCLK power-down Reference input power-down TDC power-down APLL power-down Clock dist power-down Full power-down Description Resets device but retains programmed register values (default: not reset) Places DCO in deep sleep mode (default: not powered down) Places SYSCLK input and PLL in deep sleep mode (default: not powered down) Places reference clock inputs in deep sleep mode (default: not powered down) Places the time-to-digital converter in deep sleep mode (default: not powered down) Places the output PLL in deep sleep mode (default: not powered down) Places the clock distribution outputs in deep sleep mode (default: not powered down) Places the entire device in deep sleep mode (default: not powered down) Table 90. Loop Mode Address 0x0A01 Bits 7 6 Bit Name Reserved User holdover 5 User freerun [4:2] REF switchover mode [1:0] User reference in manual switchover mode Description Reserved. Forces the device into holdover mode (default: not forced holdover mode). If a tuning word history is available, then the history tuning word specifies the DCO output frequency. Otherwise, the free run frequency tuning word register specifies the DCO output frequency. The phase and frequency lock detectors are forced into the unlocked state. Forces the device into user free run mode (default is not forced user free run mode). The free run frequency tuning word register specifies the DCO output frequency. When the user freerun bit is set, it overrides the user holdover bit (Address 0x0A01, Bit 6). Selects the operating mode of the reference switching state machine. Reference Switchover Mode, Bits[2:0] Register 0x0A01[4:2] Reference Selection Mode 000 (default) Automatic revertive mode 001 Automatic nonrevertive mode 010 Manual reference select (with automatic fallback mode) 011 Manual reference select mode (with auto-holdover) 100 Full manual mode (no auto-holdover) 101 Not used 110 Not used 111 Not used Input reference when REF switchover mode bits (Register 0x0A01, Bits[4:2]) = 010, 011, or 100. 00 (default) = Input Reference A. 01 = Input Reference B. 10 = Input Reference C. 11 = Input Reference D. Table 91. Cal/Sync Distribution Address 0x0A02 Bits [7:2] 1 Bit Name Reserved Soft sync clock distribution 0 Reserved Description Default: 0x00 Setting this bit initiates synchronization of the clock distribution output (default: 0b). Nonmasked outputs stall when value is 1b; restart is initialized on 1b to 0b transition. Default: 0b. Rev. B | Page 89 of 104 AD9558 Data Sheet Reset Functions (Register 0x0A03) Table 92. Reset Functions1 Address 0x0A03 (autoclear) 1 Bits 7 6 5 4 3 2 1 Bit Name Reserved Clear LF Clear CCI Reserved Clear auto sync Clear TW history Clear all IRQs 0 Clear watchdog timer Description Default: 0b. Setting this bit clears the digital loop filter (intended as a debug tool). Setting this bit clears the CCI filter (intended as a debug tool). Default: 0b. Setting this bit resets the automatic synchronization logic (see Register 0x0500). Setting this bit resets the tuning word history logic (part of holdover functionality). Setting this bit clears the entire IRQ monitor register (Register 0x0D02 to Register 0x0D07). It is the equivalent of setting all the bits of the IRQ clearing register (Register 0x0A04 to Register 0x0A0D). Setting this bit resets the watchdog timer (see Register 0x0211 and Register 0x0212). If the timer times out, it starts a new timing cycle. If the timer has not yet timed out, it restarts at time zero without causing a timeout event. Continuously resetting the watchdog timer at intervals less than its timeout period prevents the watchdog timer from generating a timeout event. Note that all bits in this register are autoclearing. IRQ Clearing (Register 0x0A04 to Register 0x0A09) The IRQ clearing registers are identical in format to the IRQ monitor registers (Register 0x0D02 to Register 0x0D09). When set to logic 1, an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ clearing register is an autoclearing register. Table 93. IRQ Clearing for SYSCLK Address 0x0A04 Bits [7:6] 5 4 3 2 1 0 Bit Name Reserved SYSCLK unlocked SYSCLK locked APLL unlocked APLL locked APLL Cal ended APLL Cal started Description Reserved Clears SYSCLK unlocked IRQ Clears SYSCLK locked IRQ Clears Output PLL unlocked IRQ Clears Output PLL locked IRQ Clears APLL calibration complete IRQ Clears APLL calibration started IRQ Table 94. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM Address 0x0A05 Bits [7:5] 4 3 2 1 0 Bit Name Reserved Pin program end Sync clock distribution Watchdog timer EEPROM fault EEPROM complete Description Reserved Clears pin program end IRQ Clears distribution sync IRQ Clears watchdog timer IRQ Clears EEPROM fault IRQ Clears EEPROM complete IRQ Table 95. IRQ Clearing for the Digital PLL Address 0x0A06 Bits 7 6 5 4 3 2 1 0 Bit Name Switching Closed Freerun Holdover Frequency unlocked Frequency locked Phase unlocked Phase locked Description Clears switching IRQ Clears closed IRQ Clears free run IRQ Clears holdover IRQ Clears frequency unlocked IRQ Clears frequency locked IRQ Clears phase unlocked IRQ Clears phase locked IRQ Rev. B | Page 90 of 104 Data Sheet AD9558 Table 96. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit Address 0x0A07 Bits [7:5] 4 3 2 1 0 Bit Name Reserved History updated Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Description Reserved Clears history updated IRQ Clears frequency unclamped IRQ Clears frequency clamped IRQ Clears phase slew unlimited IRQ Clears phase slew limited IRQ Table 97. IRQ Clearing for Reference Inputs Address 0x0A08 0x0A09 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault Description Reserved Clears REFB validated IRQ Clears REFB fault cleared IRQ Clears REFB fault IRQ Reserved Clears REFA validated IRQ Clears REFA fault cleared IRQ Clears REFA fault IRQ Reserved Clears REFD validated IRQ Clears REFD fault cleared IRQ Clears REFD fault IRQ Reserved Clears REFC validated IRQ Clears REFC fault cleared IRQ Clears REFC fault IRQ Table 98. Incremental Phase Offset Control Address 0x0A0A Bits [7:3] 2 Bit Name Reserved Reset phase offset 1 Decrement phase offset 0 Increment phase offset Description Reserved. Resets the incremental phase offset to zero. This is an autoclearing bit. Decrements the incremental phase offset by the amount specified in the incremental phase lock offset step size registers (Register 0x0312 to Register 0x0313). This is an autoclearing bit. Increments the incremental phase offset by the amount specified in the incremental phase lock offset step size registers (Register 0x0312 to Register 0x0313). This is an autoclearing bit. Table 99. Reference Validation Override Controls Address 0x0A0B 0x0A0C Bits [7:4] 3 Bit Name Reserved Force Timeout D 2 Force Timeout C 1 Force Timeout B 0 Force Timeout A [7:4] 3 2 1 0 Reserved Ref Mon Override D Ref Mon Override C Ref Mon Override B Ref Mon Override A Description Reserved. Setting this autoclearing bit emulates timeout of the validation timer for Reference D and allows the user to make REFD valid immediately. Setting this autoclearing bit emulates timeout of the validation timer for Reference C and allows the user to make REFC valid immediately. Setting this autoclearing bit emulates timeout of the validation timer for Reference B and allows the user to make REFB valid immediately. Setting this autoclearing bit emulates timeout of the validation timer for Reference A and allows the user to make REFA valid immediately. Reserved. Overrides the reference monitor REF FAULT signal for Reference D (default: 0). Overrides the reference monitor REF FAULT signal for Reference C (default: 0). Overrides the reference monitor REF FAULT signal for Reference B (default: 0). Overrides the reference monitor REF FAULT signal for Reference A (default: 0). Rev. B | Page 91 of 104 AD9558 Address 0x0A0D Bits [7:4] 3 2 1 0 Data Sheet Bit Name Reserved Ref Mon Bypass D Ref Mon Bypass C Ref Mon Bypass B Ref Mon Bypass A Description Reserved. Bypasses the reference monitor for Reference D (default: 0). Bypasses the reference monitor for Reference C (default: 0). Bypasses the reference monitor for Reference B (default: 0). Bypasses the reference monitor for Reference A (default: 0). QUICK IN/OUT FREQUENCY SOFT PIN CONFIGURATION (REGISTER 0x0C00 TO REGISTER 0x0C08) Table 100. Soft Pin Program Setting1 Address 0x0C00 Bits [7:1] 0 Bit Name Reserved Enable Soft Pin Section 1 0x0C01 [7:4] Output frequency selection [3:0] Input frequency selection 0x0C02 [7:2] [1:0] Reserved System clock PLL ref selection 0x0C03 [7:1] 0 Reserved Enable Soft Pin Section 2 0x0C04 [7:4] [3:2] Reserved REFB frequency scale [1:0] REFA frequency scale Description Reserved. 0 (default) = disables the function of soft pin registers in Soft Pin Section 1 (Register 0x0C01 and Register 0x0C02). 1 = enables the function of soft pin registers in Soft Pin Section 1 (Register 0x0C01 to Register 0x0C02) when the PINCONTROL pin is low at startup and/or reset. The register in Soft Pin Section 1 configures the part into one of 256 preconfigured input-to-output frequency translations stored in the on-chip ROM. The registers in Soft Pin Section 1 (Register 0x0C00 to Register 0x0C02) are ignored when the PINCONTROL pin is high at power-up and/or reset (which means the hard pin program is enabled). Selects one of 16 predefined output frequencies as ouptut freqeuncy of the desired frequency translation and reprograms the free run TW, N2, RF divider, and M0 to M3b dividers with the value stored in the ROM. Selects one of 16 predefined input frequencies as the input frequency of the desired frequency translation and reprograms the reference period, R divider, N1, FRAC1, and MOD1 in four REF profiles with the value stored in the ROM. Reserved. Selects one of the four predefined system PLL references for the desired frequency translation and reprograms the system PLL configuration with the value stored in the ROM. To load values from the ROM, the user must write Register 0x0C07[0] = 1 after writing this. Equivalent System Clock PLL Settings, Register 0x0C02[1:0] Register 0x0100 to Register 0x101[3:0] System PLL Ref Bit 1 Bit 0 12 Bits 1 0 0 24.576 MHz XTAL, x2 on, N = 8 2 0 1 49.152 MHz XTAL, x2 on, N = 8 3 1 0 24.576 MHz XO, x2 off, N = 16 4 1 1 49.152 MHz XO, x2 off, N = 8 Reserved. 0 (default) = disables the function of soft pin registers in Soft Pin Section 2 (Register 0x0C04 to Register 0x0C06). 1 = enables the function of soft pin registers in Soft Pin Section 2 (Register 0x0C04 to Register 0x0C06) when PINCONTROL pin is low. Reserved. Scales the the selected input frequency (defined by Register 0x0C01[3:0]) for REFB. 00 (default) = divide-by-1. 01 = divide-by-4. 10 = divide-by-8. 11 = divide-by-16. For example, if the selected input frequency is 622.08 MHz and Register 0x0C04[3:2] = 11, the new input frequency should be 622.08 MHz/16 = 38.8 MHz Scales the the selected input frequency (defined by Register 0x0C01[3:0]) for REFA. 00 (default) = divide-by-1. 01 = divide-by-4. 10 = divide-by-8. 11 = divide-by-16. Rev. B | Page 92 of 104 Data Sheet Address 0x0C05 AD9558 Bits [7:4] [3:2] Bit Name Reserved Channel 1 output frequency scale [1:0] Channel 0 output frequency scale [7:5] 4 Reserved Sel high PM base loop filter [3:2] DPLL loop BW [1:0] Reference input frequency tolerance 0x0C07 [7:1] 0 Reserved Soft pin start transfer 0x0C08 [7:1] 0 Reserved Soft pin reset 0x0C06 1 Description Reserved. Scales the selected output frequency (defined by Register 0x0C01[7:4]) for the Channel Divider 1 output. 00 (default) = divide-by-1. 01 = divide-by-4. 10 = divide-by-8. 11 = divide-by-16. Scale the selected output frequency (defined by Register 0x0C01[7:4]) for the Channel Divider 0 output. 00 (default) = divide-by-1. 01 = divide-by-4. 10 = divide-by-8. 11 = divide-by-16. Reserved. 0 = base loop filter with normal (70) phase margin (default). 1 = base loop filter with high (88.5) phase margin. (< 0.1 dB peaking in closed-loop transfer function). Scale the DPLL loop BW while in soft pin mode. 00 (default) = 50 Hz. 01 = 1 Hz. 10 = 10 Hz. 11 =100 Hz. Scales the input frequency tolerance while in soft pin mode. 00 (default) = outer tolerance: 10%; inner tolerance: 8% (for general conditions). 01 = outer tolerance: 12 ppm; inner tolerance: 9.6 ppm (for Stratum 3). 10 = outer tolerance: 48 ppm; inner tolerance: 38 ppm (for SMC clock standard). 11 = outer tolerance: 200 ppm; inner tolerance: 160 ppm (for XTAL system clock). Reserved. Autoclearing register. 1 = initiates ROM download without resetting the part/register map. After ROM download is complete, this register is reset. Reserved. Autoclearing register; resets the part like soft reset (Register 0x0000[5]), except that this reset function initiates a soft pin ROM download without resetting the part/register map. After ROM download is complete, this register is pulled back to zero. All bits in Register 0x0C00 to Register 0x0C06 take effect only with either a soft pin start transfer (Register 0x0C07) or soft pin reset (Register 0x0C08). STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D14) All bits in Register 0x0D00 to Register 0x0D14 are read only. To show the latest status, these registers require an I/O update (Register 0x0005 = 0x01) immediately before being read. Table 101. EEPROM Status Address 0x0D00 Bits [7:4] 3 2 1 0 Bit Name Reserved Pin program ROM load process Fault detected Load in progress Save in progress Description Reserved. The control logic sets this bit when data is being read from the ROM. An error occurred while saving data to or loading data from the EEPROM. The control logic sets this bit while data is being read from the EEPROM. The control logic sets this bit while data is being written to the EEPROM. Rev. B | Page 93 of 104 AD9558 Data Sheet Table 102. SYSCLK Status Address 0x0D01 Bits 7 6 Bit Name Reserved DPLL_APLL_Lock 5 All PLLs locked 4 APLL VCO status 3 2 APLL cal in process APLL lock 1 System clock stable 0 SYSCLK lock detect Description Reserved. Indicates the status of the DPLL and APLL. 0 = either the DPLL or the APLL is unlocked. 1 = both the DPLL and APLL are locked. Indicates the status of the system clock PLL, APLL, and DPLL. 0 = system clock PLL or APLL or DPLL is unlocked. 1 = all three PLLs (system clock PLL, APLL, and DPLL) are locked. 1 = OK. 0 = off/clocks are missing. The control logic holds this bit set while the amplitude calibration of the APLL VCO is in progress. Indicates the status of the APLL. 0 = unlocked. 1 = locked. The control logic sets this bit when the device considers the system clock to be stable (see the System Clock Stability Timer section). 0 = not stable (the system clock stability timer has not expired yet). 1 = stable (the system clock stability timer has expired). Indicates the status of the system clock PLL. 0 = unlocked. 1 = locked. IRQ Monitor (Register 0x0D02 to Register 0x0D09) If not masked via the IRQ mask registers (Register 0x0209 to Register 0x020F), the appropriate IRQ monitor bit is set to a Logic 1 when the indicated event occurs. These bits can be cleared only via the IRQ clearing registers (Register 0x0A04 to Register 0x0A09), the reset all IRQs bit (Register 0x0A03[1]), or a device reset. Table 103. IRQ Monitor for SYSCLK Address 0x0D02 Bits [7:6] 5 4 3 2 1 0 Bit Name Reserved SYSCLK unlocked SYSCLK locked APLL unlocked APLL locked APLL cal ended APLL cal started Description Reserved Indicates a SYSCLK PLL state transition from locked to unlocked Indicates a SYSCLK PLL state transition from unlocked to locked Indicates an output PLL state transition from locked to unlocked Indicates an output PLL state transition from unlocked to locked Indicates that APLL calibration is complete Indicates that APLL in APLL calibration has begun Table 104. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM Address 0x0D03 Bit [7:5] 4 3 2 1 0 Bit Name Reserved Pin program end Output distribution sync Watchdog timer EEPROM fault EEPROM complete Description Reserved Indicates successful completion of a ROM load operation Indicates a distribution sync event Indicates expiration of the watchdog timer Indicates a fault during an EEPROM load or save operation Indicates successful completion of an EEPROM load or save operation Rev. B | Page 94 of 104 Data Sheet AD9558 Table 105. IRQ Monitor for the Digital PLL Address 0x0D04 Bits 7 6 5 4 3 2 1 0 Bit Name Switching Closed Freerun Holdover Frequency unlocked Frequency locked Phase unlocked Phase locked Description Indicates that the DPLL is switching to a new reference Indicates that the DPLL has entered closed-loop operation Indicates that the DPLL has entered free run mode Indicates that the DPLL has entered holdover mode Indicates that the DPLL has lost frequency lock Indicates that the DPLL has acquired frequency lock Indicates that the DPLL has lost phase lock Indicates that the DPLL has acquired phase lock Table 106. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit Address 0x0D05 Bits [7:5] 4 3 2 1 0 Bit Name Reserved History updated Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Description Reserved Indicates the occurrence of a tuning word history update Indicates a frequency limiter state transition from clamped to unclamped Indicates a frequency limiter state transition from unclamped to clamped Indicates a phase slew limiter state transition from slew limiting to not slew limiting Indicates a phase slew limiter state transition from not slew limiting to slew limiting Table 107. IRQ Monitor for Reference Inputs Address 0x0D06 0x0D07 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault Description Reserved Indicates that REFB has been validated Indicates that REFB has been cleared of a previous fault Indicates that REFB has been faulted Reserved Indicates that REFA has been validated Indicates that REFA has been cleared of a previous fault Indicates that REFA has been faulted Reserved Indicates that REFD has been validated Indicates that REFD has been cleared of a previous fault Indicates that REFD has been faulted Indicates that REFC has been validated Indicates that REFC has been cleared of a previous fault Indicates that REFC has been faulted Rev. B | Page 95 of 104 AD9558 Data Sheet DPLL Status, Input Reference Status, Holdover History, and DPLL Lock Detect Tub Levels (Register 0x0D08 to Register 0x0D14) Table 108. DPLL Status1 Address 0x0D08 0x0D09 1 Bits 7 6 5 4 3 2 1 0 [7:6] 5 4 [3:2] Bit Name Reserved Offset slew limiting Frequency lock Phase lock Loop switching Holdover Active Freerun Reserved Frequency clamped History available Active reference priority [1:0] Current active reference Description Reserved The current closed-loop phase offset is rate limited The DPLL has achieved frequency lock The DPLL has achieved phase lock The DPLL is in the process of a reference switchover The DPLL is in holdover mode The DPLL is active (that is, operating in a closed-loop condition) The DPLL is free run (that is, operating in an open-loop condition) Default: 0b The upper or lower frequency tuning word clamp is in effect There is sufficient tuning word history available for holdover operation Priority value of the currently active reference 00 = highest priority ... 11 = lowest priority Index of the currently active reference 00 = Reference A 01 = Reference B 10 = Reference C 11 = Reference D Note that the user must issue an I/O update by writing 0x01 to Register 0x0005 to update the status of these registers. Table 109. Reserved Register Address 0x0D0A Bits [7:0] Bit Name Reserved Description Reserved. Table 110. Input Reference Status1 Address 0x0D0B 0x0D0C 1 Bits 7 6 5 4 3 2 1 0 [7:4] [3:0] Bit Name B valid B fault B fast B slow A valid A fault A fast A slow Description REFB is valid for use. (It is unfaulted, and its validation timer has expired.) REFB is not valid for use. This bit indicates that the frequency of REFB is higher than allowed by its profile settings. This bit indicates that the frequency of REFB is lower than allowed by its profile settings. REFA is valid for use. (It is unfaulted, and its validation timer has expired.) REFA is not valid for use. This bit indicates that the frequency of REFA is higher than allowed by its profile settings. This bit indicates that the frequency of REFA is lower than allowed by its profile settings. Same as Register 0xDOB[7:4] but for REFD instead of REFB . Same as Register 0xDOB[3:0] but for REFC instead of REFA. Note that the user must issue an I/O update by writing 0x01 to Register 0x0005 to update the status of these registers. Table 111. Holdover History1 Address 0x0D0D 0x0D0E 0x0D0F 0x0D10 1 Bits [7:0] [7:0] [7:0] [7:0] Bit Name Holdover history Description Tuning word readback bits[7:0] Tuning word readback bits[15:8] Tuning word readback bits[23:9] Tuning word readback bits[29:24] Note that these registers contain the current 30-bit DCO frequency tuning word generated by the tuning word history logic. Rev. B | Page 96 of 104 Data Sheet AD9558 Table 112. Digital PLL Lock Detect Tub Levels1 Address 0x0D11 Bits [7:0] Bit Name Phase tub 0x0D12 [7:4] [3:0] 0x0D13 [7:0] Frequency tub 0x0D14 [7:4] [3:0] Reserved Frequency tub Description Read-only digital PLL lock detect bathtub level, Bits[7:0]; see the DPLL Frequency Lock Detector section for details. Reserved. Read-only digital PLL lock detect bathtub level, Bits[11:8]; see the DPLL Frequency Lock Detector section for details. Read-only digital PLL lock detect bathtub level, Bits[7:0]; see the DPLL Phase Lock Detector section for details. Reserved. Read-only digital PLL lock detect bathtub level, Bits[11:8]; see the DPLL Phase Lock Detector section for details. These registers contain the current digital PLL lock detection bathtub levels. 1 EEPROM CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03) Table 113. EEPROM Control Address 0x0E00 Bits [7:1] 0 Bit Name Reserved Write enable 0x0E01 [7:4] [3:0] [7:1] 0 Reserved Conditional value Reserved Save to EEPROM [7:2] 1 0 Reserved Load from EPROM Reserved 0x0E02 0x0E03 Description Reserved. EEPROM write enable/protect. 0 (default) = EEPROM write protected. 1 = EEPROM write enabled. Reserved. When set to a non-zero value, it establishes the condition for EEPROM downloads. Default: 0b. Reserved. Upload data to the EEPROM based on the EEPROM Storage Sequence (Register 0x0E10 to Register 0x0E3C) section. Reserved. Downloads data from the EEPROM. Reserved. Rev. B | Page 97 of 104 AD9558 Data Sheet EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3C) The default settings of Register 0x0E10 to Register 0x0E3C contain the default EEPROM instruction sequence. The tables in this section provide descriptions of the register defaults, based on the assumption that the controller has been instructed to carry out an EEPROM storage sequence in which all of the registers are stored and loaded by the EEPROM. Table 114. EEPROM Storage Sequence for System Clock Settings Address 0x0E10 Bits [7:0] 0x0E11 [7:0] 0x0E12 [7:0] 0x0E13 [7:0] 0x0E14 [7:0] 0x0E15 [7:0] 0x0E16 [7:0] Bit Name EEPROM ID System clock I/O update Description The default value of this register is 0x01, which the controller interprets as a data instruction. Its decimal value is 1, so this tells the controller to transfer two bytes of data (1 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x01 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0006. Note that Register 0x0E11 and Register 0x0E12 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0006). The controller stores 0x0006 in the EEPROM and increments the EEPROM pointer by 2. It then transfers two bytes from the register map (beginning at Address 0x0006) to the EEPROM and increments the EEPROM address pointer by 3 (two data bytes and one checksum byte). The two bytes transferred correspond to the system clock parameters in the register map. The default value of this register is 0x08, which the controller interprets as a data instruction. Its decimal value is 8, so this tells the controller to transfer nine bytes of data (8 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0100. Note that Register 0x0E14 and Register 0x0E15 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0100). The controller stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2. It then transfers nine bytes from the register map (beginning at Address 0x0100) to the EEPROM and increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The nine bytes transferred correspond to the system clock parameters in the register map. The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer. Table 115. EEPROM Storage Sequence for General Configuration Settings Address 0x0E17 Bits [7:0] 0x0E18 [7:0] 0x0E19 [7:0] Bit Name General Description The default value of this register is 0x11, which the controller interprets as a data instruction. Its decimal value is 17, which tells the controller to transfer 18 bytes of data (17 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x11 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0200. Note that Register 0x0E18 and Register 0x0E19 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0200). The controller stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 18 bytes from the register map (beginning at Address 0x0200) to the EEPROM and increments the EEPROM address pointer by 19 (18 data bytes and one checksum byte). The 18 bytes transferred correspond to the general configuration parameters in the register map. Table 116. EEPROM Storage Sequence for DPLL Settings Address 0x0E1A Bits [7:0] 0x0E1B [7:0] 0x0E1C [7:0] Bit Name DPLL Description The default value of this register is 0x2E, which the controller interprets as a data instruction. Its decimal value is 46, which tells the controller to transfer 47 bytes of data (46 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x2E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x03. Note that Register 0x0E1B and Register 0x0E1C are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0300). The controller stores 0x0300 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 47 bytes from the register map (beginning at Address 0x0300) to the EEPROM and increments the EEPROM address pointer by 48 (47 data bytes and one checksum byte). The 47 bytes transferred correspond to the DPLL parameters in the register map. Rev. B | Page 98 of 104 Data Sheet AD9558 Table 117. EEPROM Storage Sequence for Output PLL Settings Address 0x0E1D Bits [7:0] 0x0E1E [7:0] 0x0E1F [7:0] Bit Name APLL Description The default value of this register is 0x08, which the controller interprets as a data instruction. Its decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0400. Note that Register 0x0E1E and Register 0x0E1F are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0400). The controller stores 0x0400 in the EEPROM and increments the EEPROM pointer by 2. It then transfers nine bytes from the register map (beginning at Address 0x0400) to the EEPROM and increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The nine bytes transferred correspond to APLL parameters in the register map. Table 118. EEPROM Storage Sequence for Clock Distribution Settings Address 0x0E20 Bits [7:0] 0x0E21 [7:0] 0x0E22 [7:0] 0x0E23 [7:0] Bit Name Clock distribution I/O update Description The default value of this register is 0x15, which the controller interprets as a data instruction. Its decimal value is 21, which tells the controller to transfer 22 bytes of data (21+1), beginning at the address that is specified by the next two bytes. The controller stores 0x15 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0500. Note that Register 0x0E21 and Register 0x0E22 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0500). The controller stores 0x0500 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 22 bytes from the register map (beginning at Address 0x0500) to the EEPROM and increments the EEPROM address pointer by 23 (22 data bytes and one checksum byte). The 22 bytes transferred correspond to the clock distribution parameters in the register map. The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer. Table 119. EEPROM Storage Sequence for Reference Input Settings Address 0x0E24 Bits [7:0] 0x0E25 [7:0] 0x0E26 [7:0] Bit Name Reference inputs Description The default value of this register is 0x03, which the controller interprets as a data instruction. Its decimal value is 3, so this tells the controller to transfer four bytes of data (3 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x03 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0600. Note that Register 0x0E25 and Register 0x0E26 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0600). The controller stores 0x0600 in the EEPROM and increments the EEPROM pointer by 2. It then transfers four bytes from the register map (beginning at Address 0x0600) to the EEPROM and increments the EEPROM address pointer by 5 (four data bytes and one checksum byte). The four bytes that are transferred correspond to the reference inputs parameters in the register map. Table 120. EEPROM Storage Sequence for Frame Sync Settings Address 0x0E27 Bit [7:0] 0x0E28 [7:0] 0x0E29 [7:0] Bit Name Frame sync Description The default value of this register is 0x01, which the controller interprets as a data instruction. Its decimal value is 1, which tells the controller to transfer two bytes of data (1 + 1), beginning at the address specified by the next two bytes. The controller stores 0x01 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0640. Note that Register 0x0E28 and Register 0x0E29 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0640). The controller stores 0x0640 in the EEPROM and increments the EEPROM pointer by 2. It then transfers two bytes from the register map (beginning at Address 0x0640) to the EEPROM and increments the EEPROM address pointer by 3 (two data bytes and one checksum byte). The two bytes transferred correspond to the reference inputs parameters in the register map. Rev. B | Page 99 of 104 AD9558 Data Sheet Table 121. EEPROM Storage Sequence for REFA Profile Settings Address 0x0E2A Bits [7:0] 0x0E2B [7:0] 0x0E2C [7:0] Bit Name REFA Profile Description The default value of this register is 0x26, which the controller interprets as a data instruction. Its decimal value is 38, so this tells the controller to transfer 39 bytes of data (38 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x26 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0700. Note that Register 0x0E2B and Register 0x0E2C are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0700). The controller stores 0x0700 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 39 bytes from the register map (beginning at Address 0x0700) to the EEPROM and increments the EEPROM address pointer by 40 (39 data bytes and one checksum byte). The 39 bytes transferred correspond to the REFA profile parameters in the register map. Table 122. EEPROM Storage Sequence for REFB Profile Settings Address 0x0E2D Bits [7:0] 0x0E2E [7:0] 0x0E2F [7:0] Bit Name REFB profile Description The default value of this register is 0x26, which the controller interprets as a data instruction. Its decimal value is 38, so this tells the controller to transfer 39 bytes of data (38 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x26 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0740. Note that Register 0x0E2E and Register 0x0E2F are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0740). The controller stores 0x0740 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 39 bytes from the register map (beginning at Address 0x0740) to the EEPROM and increments the EEPROM address pointer by 40 (39 data bytes and one checksum byte). The 39 bytes transferred correspond to the REFB profile parameters in the register map. Table 123. EEPROM Storage Sequence for REFC Profile Settings Address 0x0E30 Bits [7:0] 0x0E31 [7:0] 0x0E32 [7:0] Bit Name REFC profile Description The default value of this register is 0x26, which the controller interprets as a data instruction. Its decimal value is 38, so this tells the controller to transfer 39 bytes of data (38 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x26 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0780. Note that Register 0x0E31 and Register 0x0E32 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0780). The controller stores 0x0780 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 39 bytes from the register map (beginning at Address 0x0780) to the EEPROM and increments the EEPROM address pointer by 40 (39 data bytes and one checksum byte). The 39 bytes transferred correspond to the REFC profile parameters in the register map. Table 124. EEPROM Storage Sequence for REFD Profile Settings Address 0x0E33 Bits [7:0] 0x0E34 [7:0] 0x0E35 [7:0] Bit Name REFD profile Description The default value of this register is 0x26, which the controller interprets as a data instruction. Its decimal value is 38, so this tells the controller to transfer 39 bytes of data (38 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x26 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x07C0. Note that Register 0x0E34 and Register 0x0E35 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x07C0). The controller stores 0x07C0 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 39 bytes from the register map (beginning at Address 0x07C0) to the EEPROM and increments the EEPROM address pointer by 40 (39 data bytes and one checksum byte). The 39 bytes transferred correspond to the REFD profile parameters in the register map. Rev. B | Page 100 of 104 Data Sheet AD9558 Table 125. EEPROM Storage Sequence for Operational Control Settings Address 0x0E37 Bits [7:0] 0x0E38 [7:0] 0x0E39 [7:0] Bit Name Operational controls Description The default value of this register is 0x0D, which the controller interprets as a data instruction. Its decimal value is 13, so this tells the controller to transfer 14 bytes of data (13 + 1), beginning at the address specified by the next two bytes. The controller stores 0x0D in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0A00. Note that Register 0x0E38 and Register 0x0E39 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0A00). The controller stores 0x0A00 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 14 bytes from the register map (beginning at Address 0x0A00) to the EEPROM and increments the EEPROM address pointer by 15 (14 data bytes and one checksum byte). The 14 bytes transferred correspond to the operational controls parameters in the register map. Table 126. EEPROM Storage Sequence for APLL Calibration Address 0x0E3A Bits [7:0] Bit Name Calibrate APLL 0x0E3B [7:0] I/O update Description The default value of this register is 0xA0, which the controller interprets as a calibrate instruction. The controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer. The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer. Table 127. EEPROM Storage Sequence for End of Data Address 0x0E3C Bits [7:0] Bit Name End of data Description The default value of this register is 0xFF, which the controller interprets as an end instruction. The controller stores this instruction in the EEPROM, resets the EEPROM address pointer, and enters an idle state. Note that if this is a pause rather than an end instruction, the controller actions are the same except that the controller increments the EEPROM address pointer rather than resetting it. Table 128. Available for Additional EEPROM Instructions Address 0x0E3D to 0xE45 Bits [7:0] Bit Name Unused Description This area is available for additional EEPROM instructions. Rev. B | Page 101 of 104 AD9558 Data Sheet Table 129. Multifunction Pin Output Functions (D7 = 1) Register Value 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A to 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 to Ax2F 0xB0 0xB1 0xB2 0xB3 0xB4 to 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 to 0xCF 0xD0 0xD1 0xD2 to 0FF Output Function Static Logic 0 Static Logic 1 System clock divided by 32 Watchdog timer output EEPROM upload in progress EEPROM download in progress EEPROM fault detected SYSCLK PLL lock detected SYSCLK PLL stable Output PLL locked APLL calibration in process APLL input reference present All PLLs locked (DPLL phase lock) and (APLL lock) and (sys PLL lock) (DPLL phase lock) and (APLL lock) Reserved Reserved DPLL free run DPLL active DPLL in holdover DPLL in reference switchover DPLL phase locked DPLL frequency locked DPLL phase slew limited DPLL frequency clamped Tuning word history available Tuning word history updated Reserved Reference A fault Reference B fault Reference C fault Reference D fault Reserved Reference A valid Reference B valid Reference C valid Reference D valid Reserved Reference A active Reference B active Reference C active Reference D active Reserved Clock distribution sync pulse Soft pin configuration in progress Reserved Rev. B | Page 102 of 104 Equivalent Status Register None None None None Register 0x0D00, Bit 0 Register 0x0D00, Bit 1 Register 0x0D00, Bit 2 Register 0x0D01, Bit 0 Register 0x0D01, Bit 1 Register 0x0D01, Bit 2 Register 0x0D01, Bit 3 Register 0x0D01, Bit 4 Register 0x0D01, Bit 5 Register 0x0D01, Bit 6 Register 0x0D08, Bit 0 Register 0x0D08, Bit 1 Register 0x0D08, Bit 2 Register 0x0D08, Bit 3 Register 0x0D08, Bit 4 Register 0x0D08, Bit 5 Register 0x0D08, Bit 6 Register 0x0D09, Bit 5 Register 0x0D09, Bit 4 Register 0x0D05, Bit 4 Register 0x0D0B, Bit 2 Register 0x0D0B, Bit 6 Register 0x0D0C, Bit 2 Register 0x0D0C, Bit 6 Register 0x0D0B, Bit 3 Register 0x0D0B, Bit 7 Register 0x0D0C, Bit 3 Register 0x0D0C, Bit 7 Register 0x0D09, Bits[1:0] Register 0x0D09, Bits[1:0] Register 0x0D09, Bits[1:0] Register 0x0D09, Bits[1:0] Register 0x0D03, Bit 3 Register 0x0D03, Bit 4 Data Sheet AD9558 Table 130. Multifunction Pin Input Functions (D7 = 0) Register Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 to 0x0E 0x10 0x11 0x12 0x13 0x14 0x15 to 0x1F 0x20 0x21 0x22 0x23 0x24 to 0x2F 0x30 0x31 0x32 0x33 0x34 to 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 to 0x7F Input Function Reserved, high-Z input I/O update Full power-down Clear watchdog Clear all IRQs Tuning word history reset Reserved User holdover User free run Reset incremental phase offset Increment incremental phase offset Decrement incremental phase offset Reserved Override Reference Monitor A Override Reference Monitor B Override Reference Monitor C Override Reference Monitor D Reserved Force Validation Timeout A Force Validation Timeout B Force Validation Timeout C Force Validation Timeout D Reserved Enable OUT0 Enable OUT1 Enable OUT2 Enable OUT3 Enable OUT4 Enable OUT5 Enable OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 Soft sync clock distribution outputs Reserved Equivalent Control Register Register 0x0005, Bit 0 Register 0x0A00, Bit 0 Register 0x0A03, Bit 0 Register 0x0A03, Bit 1 Register 0x0A03, Bit 2 Register 0x0A01, Bit 6 Register 0x0A01, Bit 5 Register 0x0A0A, Bit 2 Register 0x0A0A, Bit 0 Register 0x0A0A, Bit 1 Register 0x0A0C, Bit 0 Register 0x0A0C, Bit 1 Register 0x0A0C, Bit 2 Register 0x0A0C, Bit 3 Register 0x0A0B, Bit 0 Register 0x0A0B, Bit 1 Register 0x0A0B, Bit 2 Register 0x0A0B, Bit 3 Register 0x0501, Bit 0 Register 0x0505, Bit 0 Register 0x0506, Bit 0 Register 0x050A, Bit 0 Register 0x050B, Bit 0 Register 0x050F, Bit 0 Register 0x0501/0x0505/0x0506/0x050A/0x050B/0x050F, Bit 0 Register 0x0A02, Bit 1 Rev. B | Page 103 of 104 AD9558 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.23 0.18 0.60 MAX 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 16 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-14-2012-A 12 MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.85 0.80 5.25 5.10 SQ 4.95 EXPOSED PAD Figure 58. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-5) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9558BCPZ AD9558BCPZ-REEL7 AD9558/PCBZ 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2011-2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09758-0-6/13(B) Rev. B | Page 104 of 104 Package Option CP-64-5 CP-64-5 CP-64-5 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD9558BCPZ AD9558/PCBZ AD9558BCPZ-REEL7