NXP Semiconductors 42
20XS4200
6.2.1.15 Reverse voltage protection on VPWR
The device can withstand reverse supply voltages on VPWR down to -28 V. Under these conditions, the outputs are automatically turned
On and the channel’s on-resistance (RDS(on)) is similar to that during positive supply voltages. No additional components are required to
protect the VPWR circuit except series resistors (>8.0 k) between the direct inputs IN[0:1] and VPWR, in case they are connected to VPWR.
The VDD pin needs reverse voltage protection from an externally connected diode (Figure 23).
6.2.1.16 Load and system ground loss
In case of load ground loss, the channel’s state does not change, but the device detects an openload fault. In case of a system GND loss,
the channels are turned off.
6.2.1.17 Device ground loss
In the (improbable) case the device loses all of its three ground connections (pins 14, 17, and 22), the channels’ state (ON/ OFF), depends
on several factors: the values of the series resistors connected to the device pins, the voltage of the direct input signals, the device’s
momentary current consumption (influenced by the SPI settings) and the state of other high side switches on the board when there are
pins in common like FSB, FSOB, and SYNC. In the following description, all voltages are referenced to the system (module) GND.
When series resistors are used, the channel state can be controlled by entering Fail-safe mode. The channels are turned off automatically
when the voltage applied to the IN[x] input(s) through the series resistor(s) is not higher than VDD and be turned on when the IN[x] input(s)
are tied to VPWR. Fail-safe is entered under the following conditions:
• all unused pins are tied to the overall system’s GND connection by resistors > 8.0 k
• any device pin connected to external system components has a series resistors > 8.0 k (except pins Vpwr, VDD, HS[0], HS[1], and
R(CSNS)>2.0 k)
• the FSB, FSOB, and SYNC pins are in the logic high state when they are shared with other devices. This means that none of the
other devices is in Fault or Fail-safe mode, nor should current sensing be performed on any one of them when GND is lost
When no series resistors are employed, the channel state after GND loss is determined by the voltage on pins IN[0:1] and the voltage
shift of the device GND. Device GND shift is determined by the lowest value of the external voltage applied to either pin of the following
list: CLOCK, FSB, IN[0:1], FSOB, SCLK, CS,SI, SO, RSTB, CONF[0:1], SYNC, and CSNS. When the device GND voltage becomes logic
low (V(GND)< VIL), the SPI port continues to operate and the device operates normally. When the GND voltage becomes logic high
(V(GND)> VIH), SPI communication is lost and Fail-safe mode is entered. When the voltage applied to the IN[0:1] input is VPWR, the
channel is turned on when it is VDD, the channel is turned off if (VDD - V(GND)) < VIH.
6.2.2 Supply voltages out of range
6.2.2.1 VDD out of range
If the external VDD supply voltage is lost (or falls outside the authorized range: VDD<VDD(FAIL)), the device enters Fail-safe mode, provided
the VDD_FAIL_en bit had been set. Consequently, the contents of all SPI registers are reset. The channels are controlled by the direct
inputs IN[0 :1] (if VPWR is within the normal range). Since the VPWR pin supplies the circuitry of the SPI, current sense and most of the
protective functions (overtemperature, overcurrent, severe short-circuit, short to VPWR, and OpenLoad detection circuitry), these faults
are still detected and reported at the FSB pin. However, without VDD, the SO pin is no longer functional. The SPI registers can no longer
be read and detailed fault information is unavailable. Current sensing also becomes unavailable. If VDD_FAIL_EN wasn’t set before VDD
was lost, the device remains SPI-controlled, even though the SPI registers can’t be read. No current flows from the VPWR to the VDD pin.
6.2.2.2 VPWR supply voltage out of range
In case VPWR is below the undervoltage threshold VPWR(UV), it is still possible to address the device by the SPI port, provided VDD is within
the normal range. It does not prevent other devices from operating when a device is part of a daisy-chain. To accomplish this, RSTB must
be kept at logic [1]. When the device operates at supply voltages above the maximum supply voltage (VPWR=36 V), SPI communication
is not affected (see Overvoltage detection (enabled by default)). The internal pull-up and pull-down current sources on the SPI pins are
not operational. Executing a Power-on-Reset (POR) sequence is recommended when VPWR re-enters its authorized range. No current
flows from the VDD to the VPWR pin.