Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 ee DESCRIPTION The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry. The 3-State output data lines can be connected directly to the data bus. The differential analog voltage input allows for increased common-mode rejection and provides a means to adjust the zero-scale offset. Additionally, the voltage reference input provides a means of encoding small analog voltages to the full 8 bits of resolution. FEATURES Compatible with most microprocessors Differential inputs 3-State outputs Logic levels TTL and MOS compatible Can be used with internal or external clock Analog input range OV to Vec Single 5V supply Guaranteed specification with 1MHz clock ORDERING INFORMATION PIN CONFIGURATION D N PACKAGES zs[1| ww 2 wr[3| CLK IN | 4 | INTR [5 | Vint) [ 5 | vin 7 | AGND [8 | VREF2|9 | . ~~ 20] veg 19] CLK R 18] Do 16] D2 15] D3 14] Da 13] DS 12] 06 = D GND [10] 11] 07 NOTE: TOP VIEW SOL Released in large SO packaga only. APPLICATIONS Transducer-to-microprocessor interface Digital thermometer Digitally-controlled thermostat Microprocessor-based monitoring and control systems DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 20-Pin Plastic Dual In-Line Package (DIP} -40 to +85C ADC0803/04-1 LCN 0408B 20-Pin Plastic Dual In-Line Package (DIP} 0 to 70C ADC0803/04-1 CN 0408B 20-Pin Plastic Small Outline (SO) Package 0 to 70C ADC0803/04-1 CD 1021B 20-Pin Plastic Small Outline (SO) Package -40 to 85C ADC0803/04-1 LCD 1021B ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT Voc Supply voltage 6.5 Vv Logic control input voltages -0.3 to +16 Vv All other input voltages Veo #03) Vv Ta Operating temperature range ADC0803/04-1 LCD -40 to +85 S ADC0803/04-1 LCN -40 to +85 S ADC0803/04-1 CD Oto +70 S ADC0803/04-1 CN Oto +70 C Ts1 Storage temperature -65 to +150 C Tso_b Lead soldering temperature (10 seconds) 300 C P Maximum power dissipation D Ta=25C (still air)! N package 1690 mW D package 1390 mW NOTES: 1. Derate above 25C, at the following rates: N package at 13.5mW/C; D package at 11.1mW/C August 31, 1994 853-0034 13721Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 BLOCK DIAGRAM VREF/2 LADDER AND a DECODER AGND 20 vec 10 DGND 3 WO B-BIT SHIFT REGISTER 1 ts oO 2 AD 4 CLK IN + AUTO ZERO CoM D7 (MSB) (11) DB (12) Ds (13) OUTPUT D4 (14) LATCHES D3 (15) bB2 (15) Bi (17) Bo (LSB) (18) 19 CLK R August 31, 1994 556Philips Sem iconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 DC ELECTRICAL CHARACTERISTICS Vcc = 5.0, fete = 1MHz, Twin = Ta = Tax, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS Apcomst UNIT Min Typ Max ADC0803 relative accuracy error (adjusted) Full-Scale adjusted 0.50 LSB ADC0804 relative accuracy error (unadjusted) Veerf2 = 2.500Vpc 1 LSB Rin Vrer2 input resistance? Vec = av? 400 680 a Analog input voltage range? 0.05 Vec+0.05 V DC common-mode error Over analog input voltage 1416 1/8 LSB range Power supply sensitivity Veo = BV +10%! 1/16 LSB Control inputs Vin Logical 1 input voltage Vee = 5.25Vpc 2.0 15 Voc Vit Logical 0 input voltage Vee = 4.78Vpc 0.8 Voc NH Logical 1 input current Vin =8Vpc 0.005 1 HApe lit Logical O input current Vin =9Vpc -1 0.005 HApe Clock in and clock R Va+ Clock in positive-going threshold voltage 27 3.1 3.5 Voc Vq- Clock in negative-going threshold voltage 15 1.8 2.1 Vpc Vu Clock in hysteresis (V7+)4V7-) 0.6 1.3 2.0 Voc VoL Logical 0 clock R output voltage lol = 360A, Voc = 4.75Vpc 0.4 Voc Vou Logical 1 clock R output voltage lon = S60HA, Ver = 4.75Vpc 24 Voc Data output and INTR VoL Logical 0 output voltage Data outputs loc = 1.6mA, Vee = 4.75Vpc 0.4 Voc TNTR outputs lot = 1.0mA, Vee = 4.78Vpc 0.4 Voc Vou Logical 1 output voltage Lo = S60HA, Veo = # 7PNoc ef Voc lon =10nHA, Veco = 4.75Vpe 45 loz. 3-state output leakage Vout = OVpc, CS = logical 1 -3 MApe lozH 3-state output leakage Vout = 5Vpc, CS = logical 1 3 HApe Ise +Output short-circuit current Vout = OV, Ta = 25C 45 12 mApc Ise Output short-circuit current Vout = Vee. Ta = 25C 9.0 30 mApc lec Power supply current fouc= Logical he oeC. 3.0 3.5 mA NOTES: 1. Analog inputs must remain within the range: -0.05 < Viy = Vor + 0.05V. 2. See typical performance characteristics for input resistance at Vec = 5V. 3. Vrer/2 and Vin must be applied after the Vcc has been turned on to prevent the possibility of latching. August 31, 1994 557Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TO FROM TEST GONDITIONS - Apeososi4 UNIT Min | Typ Max Conversion time fo. k=1MHz! 66 73 Ls foLk Clock frequency! 0.1 1.0 3.0 MHz Clock duty cyclet 40 60 % CR Free-running conversion rate sei Co 13690 | conv/s tw(WR)L | Start pulse width CS=0 30 ns tacc Access time Output RD CS=0, C.=100pF 75 190 ns tin. to 3-State control Output RD oes et 70 100 ns tw, tr INTR delay INTR Mee 100 150 ns Cin Logic input=capacitance 75 pF Cout 3-State output capacitance 7.5 pF NOTES: 1. Accuracy is guaranteed at fo, ~=1MHz. Accuracy may degrade at higher clock frequencies. FUNCTIONAL DESCRIPTION These devices operate on the Successive Approximation principle. Analog switches are closed sequentially by successive approximation logic until the input to the auto-zero comparator [ Vin(+)-Vin(-) ] matches the voltage from the decoder. After all bits are tested and determined, the 8-bit binary code corresponding to the input voltage is transferred to an output latch. Conversion begins with the arrival of a pulse at the WR input if the CS inputis low. On the High-to-Low transition of the signal at the WR or the CS input, the SAR is initialized, the shift register is reset, and the INTR output is set high. The A/D will remain in the reset state as long as the CS and WR inputs remain low. Conversion will start from one to eight clock periods after one or both of these inputs makes a Low-to-High transition. After the conversion is complete, the INTH pin will make a High-to-Low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion result. A read (RD) operation (with CS low) will clear the TNTR line and enable the output latches. The device may be runin the free-running mode as described later. A conversion in progress can be interrupted by issuing another start command. Digital Control Inputs The digital control inputs (CS, WR, RD) are compatible with standard TTL logic voltage levels. The required signals at these inputs correspond to Chip Select, START Conversion, and Output Enable control signals, respectively. They are active-Low for easy interface to microprocessor and microcontroller control buses. For applications not using microprecessors, the CS input (Pin 1) can be grounded and the A/D START function is achieved by a negative-going pulse to the WH input (Pin 3). The Output Enable function is achieved by a logic low signal at the RD input (Pin 2), which may be grounded to constantly have the latest conversion present at the output. August 31, 1994 558 ANALOG OPERATION Analog Input Current The analog comparisons are performed by a capacitive charge summing circuit. The input capacitor is switched between Vin.)4 and Vic), while reference capacitors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted difference between the input and the most recent total value set by the successive approximation register. The internal switching action causes displacement currents to flow at the analeg inputs. The voltage on the on-chip capacitance is switched through the analog differential input voltage, resulting in proportional currents entering the Ving.) input and leaving the Viney input. These transient currents occur at the leading edge of the internal clock pulses. They decay rapidly so do not inherently cause errors as the on-chip comparator is strobed at the end of the clock period. Input Bypass Capacitors and Source Resistance Bypass capacitors at the input will average the charges mentioned above, causing a DC and an AC current to flow through the output resistance of the analog signal sources. This charge pumping action is worse for continuous conversions with the Vij. input at full scale. This current can be a few microamps, so bypass capacitors should NOT be used at the analog inputs of the Veer/2 input for high resistance sources (> 1k@). If input bypass capacitors are desired for noise filtering and a high source resistance is desired to minimize capacitor size, detrimental effects of the voltage drop across the input resistance can be eliminated by adjusting the full scale with both the input resistance and the input bypass capacitor in place. This is possible because the magnitude of the input current is a precise linear function of the differential voltage.Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 Large values of source resistance where an input bypass capacitor is not used will not cause errors as the input currents settle out prior to the comparison time. If a low pass filter is required in the system, use alow valued series resistor (< 1k) for a passive RC section or add an op amp active filter (low pass). For applications with source resistances at or below 1k, a 0.1u.F bypass capacitor at the inputs will prevent pickup due to series lead inductance or a long wire. A 100 series resistor can be used to isolate this capacitor (both the resistor and capacitor should be placed out of the feedback loop) from the output of the op amp, if used. Analog Differential Voltage Inputs and Common- Mode Rejection These A/D converters have additional flexibility due to the analog differential voltage input. The Vijy_) input (Pin 7) can be used to subtract a fixed voltage from the input reading (tare correction). This is also useful in a 4/20mA current loop conversion. Common-mode noise can also be reduced by the use of the differential input. The time interval between sampling Ving) and Vin) is 4.5 clock periods. The maximum error due to this time difference is given by: Vimax)=(Vp) (2fem) (4.5/feik), where: V=error voltage due to sampling delay Vp=peak value of common-mode voltage feyy=common mode frequency For example, with a 60Hz common-mode frequency, fem, and a 1MHz A/D clock, Fe, , keeping this error to 1/4 LSB (about 5mV) would allow a common-mode voltage, Vp, which is given by: y. Wimax) four) P (2fgyy)t4-5) or (5 x 1073) (104) Vp = (6.28) (60) (4.5) = 2.95V The allowed range of analog input voltages usually places more severe restrictions on input common-mode voltage levels than this, however. An analog input span less than the full SV capability of the device, together with a relatively large zero offset, can be easily handled by use of the differential input. (See Reference Voltage Span Adjust). Noise and Stray Pickup The leads of the analog inputs (Pins 6 and 7) should be kept as short as possible to minimize input noise coupling and stray signal pick-up. Both EMI and undesired digital signal coupling to these inputs can cause system errors. The source resistance for these inputs should generally be below 5k to help avoid undesired noise pickup. Input bypass capacitors at the analog inputs can create errors as described previously. Full scale adjustment with any input bypass capacitors in place will eliminate these errors. Reference Voltage For application flexibility, these A/D converters have been designed to accommodate fixed reference voltages of 5V to Pin 20 or 2.5V to Pin 9, or an adjusted reference voltage at Pin 9. The reference can be set by forcing it at Vaer/2 input, or can be determined by the supply voltage (Pin 20). Figure 1 indicates how this is accomplished. August 31, 1994 559 Reference Voltage Span Adjust Note that the Pin 9 (VpRer/2) voltage is either 1/2 the voltage applied to the Vec supply pin, or is equal to the voltage which is externally forced at the Vper/2 pin. In addition to allowing for flexible references and full span voltages, this also allows for a ratiometric voltage reference. The internal gain of the Vaef/2 input is 2, making the full-scale differential input voltage twice the voltage at Pin 9. For example, a dynamic voltage range of the analog input voltage that extends from 0 to 4V gives aspan of 4 (4-0), so the Vper/2 voltage can be made equal to 2V (half of the 4V span) and full scale output would correspond to 4V at the input. On the other hand, if the dynamic input voltage had a range of 0.5 to 3.5, the span or dynamic input range is 3V (3.5-0.5). To encode this 3V span with 0.5V yielding a code of zero, the minimum expected input (0.5, in this case) is applied to the Vjy(-) pin to account for the offset, and the Vprr/2 pin is set to 1/2 the 3V span, or 1.5V. The A/D converter will now encode the Vin(+) signal between 0.5 and 3.5 with 0.5V at the input corresponding to a code of zero and 3.5V at the input producing a full scale output code. The full 8 bits of resolution are thus applied over this reduced input voltage range. The required connections are shown in Figure 2. Operating Mode These converters can be operated in two modes: 1) absolute mode 2) ratiometric mode In absolute mode applications, both the initial accuracy and the temperature stability of the reference voltage are important factors in the accuracy of the conversion. For Vp_er/2 voltages of 2.5, initial errors of +10mV will cause conversion errors of +1 LSB due to the gain of 2 at the VpeP/2 input. In reduced span applications, the initial value and stability of the Vper/2 input voltage become even more important as the same error is a larger percentage of the Vaer/2 nominal value. See Figure 3. In ratiometric converter applications, the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A/D converter, and, therefore, cancels outin the final digital code. See Figure 4. Generally, the reference voltage will require an initial adjustment. Errors due to an improper reference voltage value appear as full-scale errors in the A/D transfer function. ERRORS AND INPUT SPAN ADJUSTMENTS There are many sources of error in any data converter, some of which can be adjusted out. Inherent errors, such as relative accuracy, cannot be eliminated, but such errors as full-scale and zero scale offset errors can be eliminated quite easily. See Figure 2. Zero Scale Error Zero scale error of an A/D is the difference of potential between the ideal 1/2 LSB value (9.8mV for Vpef/2=2.500V) and that input voltage which just causes an output transition from code 0000 0000 to a code of 0000 0001. If the minimum input value is not ground potential, a zero offset can be made. The converter can be made to output a digital code of 0000 0000 for the minimum expected input voltage by biasing the Vin(-) input to that minimum value expected at the Vin(-) input to that minimum value expected at the Vj,(+) input. This uses thePhilips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 differential mode of the converter. Any offset adjustment should be done prior to full scale adjustment. Full Scale Adjustment Full scale gain is adjusted by applying any desired offset voltage to Vin(-), then applying the Vix(+) a voltage thatis 1-1/2 LSB less than the desired analog full-scale voltage range and then adjusting the magnitude of VRer/2 input voltage (or the Voc supply if there is no Vrer/2 input connection) for a digital output code which just changes from 1111 1110 to 1111 1111. The ideal Vipy(+) voltage for this full-scale adjustmentis given by: Vax Vin Vin( ) = Vin(-) -15x 355. where: Vuiaxehigh end of analog input range (ground referenced) Veinslow end (zero offset) of analog input (ground referenced) CLOCKING OPTION The clock signal for these A/Ds can be derived from external sources, such as a system clock, or self-clocking can be accomplished by adding an external resistor and capacitor, as shown in Figure 6. Heavy capacitive or DC loading of the CLK R pin should be avoided as this will disturb normal converter operation. Loads less than 50pF are allowed. This permits driving up to seven A/D converter CLK IN pins of this family from a single CLK R pin of one converter. For larger loading of the clock line, a CMOS or low power TTL buffer or PNP input logic should be used to minimize the loading on the CLK R pin. Restart During a Conversion A conversion in process can be halted and a new conversion began by bringing the CS and WA inputs low and allowing at least one of them to go high again. The output data latch is not updated if the conversion in progress is not completed; the data from the previously completed conversion will remain in the output data latches until a subsequent conversion is completed. Continuous Conversion To provide continuous conversion of input data, the CS and RD inputs are grounded and TNTR output is tied to the WR input. This INTRAWR connection should be momentarily forced to a logic low upon power-up to insure circuit operation. See Figure 5 for one way to accomplish this. DRIVING THE DATA BUS This CMOS A/D converter, like MOS microprocessors and memories, will require a bus driver when the total capacitance of the data bus gets large. Other circuitry tied to the data bus will add to the total capacitive loading, even in the high impedance mode. There are alternatives in handling this problem. The capacitive loading of the data bus slows down the response time, although DC specifications are still met. For systems with a relatively low CPU clock frequency, more time is available in which to establish proper logic levels on the bus, allowing higher capacitive loads to be driven (see Typical Performance Characteristics). August 31, 1994 560 At higher CPU clock frequencies, time can be extended for /O reads (and/or writes) by inserting wait states (8880) or using clock-extending circuits (6800, 8035). Finally, if time is critical and capacitive loading is high, external bus drivers must be used. These can be 3-State buffers (low power Schottky is recommended, such as the N74LS240 series) or special higher current drive products designed as bus drivers. High current bipolar bus drivers with PNP inputs are recommended as the PNP input offers low loading of the A/D output, allowing better response time. POWER SUPPLIES Noise spikes on the Veg line can cause conversion errors as the internal comparator will respond to them. A low inductance filter capacitor should be used close to the converter Vee pin and values of 1,F or greater are recommended. A separate 5V regulator for the converter (and other 5 linear circuitry) will greatly reduce digital noise on the Vee supply and the attendant problems. WIRING AND LAYOUT PRECAUTIONS Digital wire-wrap sockets and connections are not satisfactory for breadboarding this (or any) A/D converter. Sockets on PC boards can be used. All logic signal wires and leads should be grouped or kept as far as possible from the analog signal leads. Single wire analog input leads may pick up undesired hum and noise, requiring the use of shielded leads to the analog inputs in many applications. A single-point analog ground separate from the logic or digital ground points should be used. The power supply bypass capacitor and the self-clocking capacitor, if used, should be returned to digital ground. Any Vp_er/2 bypass capacitor, analog input filter capacitors, and any input shielding should be returned to the analog ground point. Proper grounding will minimize zero-scale errors which are present in every code. Zero-scale errors can usually be traced to improper board layout and wiring. APPLICATIONS Microprocessor Interfacing This family of A/D converters was designed for easy microprocessor interfacing. These converters can be memory mapped with appropriate memory address decoding for CS (read) input. The active-Low write pulse from the processor is then connected to the WA input of the A/D converter, while the processor active-Low read pulse is fed to the converter RD input to read the converted data. If the clock signal is derived from the microprocessor system clock, the designer/programmer should be sure that there is no attempt to read the converter until 74 converter clock pulses after the start pulse goes high. Alternatively, the INTR pin may be used to interrupt the processor to cause reading of the converted data. Of course, the converter can be connected and addressed as a peripheral (in l/O space), as shown in Figure 7. A bus driver should be used as a buffer to the A/D output in large microprocessor systems where the data leaves the PC board and/or must drive capacitive loads in excess of 100pF. See Figure 9. Interfacing the SCN8048 microcomputer farnily is pretty simple, as shown in Figure 8. Since the SCN8048 family has 24 I/O lines, one of these (shown here as bit 0 or port 1) can be used as the chip select signal to the converter, eliminating the need for an addressPhilips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 decoder. The RD and WR signals are generated by reading from and writing to a dummy address. Digitizing a Transducer Interface Output Circuit Description Figure 10 shows an example of digitizing transducer interface output voltage. In this case, the transducer interface is the NE5521, an LYDT {Linear Variable Differential Transformer) Signal Conditioner. The diode at the A/D inputis used to insure that the input to the A/D does not go excessively beyond the supply voltage of the A/D. See the NE5521 data sheet for a complete description of the operation of that part. Circuit Adjustment To adjust the full scale and zero scale of the A/D, determine the range of voltages that the transducer interface output will take on. Set the LVDT core for null and set the Zero Scale Scale Adjust Potentiometer for a digital output from the A/D of 1000 000. Set the LYDT core for maximum voltage from the interface and set the Full Scale Adjust potentiometer so the A/D output is just barely 1111 1111. August 31, 1994 561 A Digital Thermostat Circuit Description The schematic of a Digital Thermostat is shown in Figure 11. The A/D digitizes the output of the LM35, a temperature transducer IC with an output of 10mV per C. With Vper/2 set for 2.56V, this 10mV corresponds to 1/2 LSB and the circuit resolution is 2C. Reducing Veef/ to 1.28 yields a resolution of 1C. Of course, the lower Vreff2 is, the more sensitive the A/D will be to noise. The desired temperature is set by holding either of the set buttons closed. The SCC80C451 programming could cause the desired (set) temperature to be displayed while either button is depressed and for a short time after itis released. At other times the ambient temperature could be displayed. The set temperature is stored in an SCN8051 internal register. The A/D conversion is started by writing anything at all to the A/D with port pin P10 set high. The desired ternperature is compared with the digitized actual temperature, and the heater is turned on or off by clearing setting port pin P12. If desired, another port pin could be used to turn on or off an air conditioner. The display drivers are NE587s if common anode LED displays are used. Of course, it is possible to interface to LCD displays as well.Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Current vs Clock Frequency vs Input Current vs Temperature Clock Capacitor Applied Voltage at Vag. Pin 10.0 5 =z 3.0 = < = E tCLK = 1MHz 6.0 4 5 ou E cS =H 4.0 3 Ta = 25C ira N 2 5 = 2.0 ~ 5 o < 1 * fe E z % 08 x 2 . Ww te G9 o6 oo ti o 04 -2 3 o2 4 MIN. 0.1 5 -50 -25 oD 25 50 75 100 125 10 20 40 6080100 200 400 6001000 o 1 2 3 4 5 AMBIENT TEMPERATURE (C} CLOCK CAP (pF) APPLIED VREF/2 (V) Logic Input Threshold CLK-IN Threshold Voltage vs Output Current vs Voltage vs Supply Voltage Supply Voltage Temperature 18 | | 1.70 > = = 55C < Ta 125C 46 Voc =5.0 o ~_ eN ~. = 1-60 a VTs E 14 sl = > 2 MN = Ww 5 a fe ~ a o 5 12 ~ Vo=2.5 z x 0 180 ig E N\ PA 8 = a 10 N, g E E NSS z 1.40 5 9 = J me YOroAv | a 8 a 1.30 5 4.50 475 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50 -0 -25 0 25 50 75 100 125 Voc SUPPLY VOLTAGE (V) Veo SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) Delay From RD Falling Full Scale Error vs Edge to Data Valid vs Conversion Time Load Capacitance 4 T T T 350 oc=50V Voo= 300 VREF/2 = on osc A= 3}- 2.6V 250 ao a @ 200 2 > 9S 2 150 tf a Ww a 100 1 N 50 S| Oo 0 o 20 40 60 80 100 120 Ga 200 400 600 800 1000 CONVERSION TIME (us) LOAD CAPACITANCE (pF) August 31, 1994 562Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 3-STATE TEST CIRCUITS AND WAVEFORMS (ADC0801-1) Vec Voc Yec DATA ry TS OUTPUT FRO DATA ad t oy 10K YOu 90% cs OUTPUT 10pF DATA DATA OUTPUT OUTPUT 10% = GN GN LT 10pF it af tH toH TIMING DIAGRAMS (All timing is measured from the 50% voltage points) START CONVERSION cs i wr * tw wR) BUSY y DATA IS VALID IN ACTUAL INTERNAL NOT BUSY OUTPUT LATCHES STATUS OF THE | CONVERTER 1 aST DATA WAS READ) ~ 4T08X%14eLK *'* INTERNAL Te * INTR \ (LAST DATA WAS NOT neaoy INT ASSERTED +| V2 TSLK Win INTR RESET sa trl DATA THREE-STATE OUTPUTS | 14H, toH Output Enable and Reset INTR NOTE: Read strobe must occur 8 clock periods (64) after assertion of interrupt to quarantee reset of INTH. August 31, 1994 563Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 Voc 20| YREF 3 " VREF2 4 DIGITAL CIRCUITS rR | __] ANALOG | CIRCUITS 8 10 NOTE: The VREF/2 voltage is either 1/2 ihe Vee voltage or is that whieh is forced at Pin 9. Figure 1. Internal Reference Design (5V) VREF 330 aM TO VREF2 T 0.1pF 3 : zs OFFSET -) ADJUST TOVING Figure 2. Offsetting the Zero Scale and Adjusting the Input Range (Span) Figure 4. Ratiometric Mode of Operation with Optional Full Scale Adjustment August 31, 1994 +5V +5V A +5V Yee Vint) Lt Voc IN 1OUF . = 2k Vint(+) 10nF AD = = 2k A/D = $ VREF/2 00 VOLTAGE YING) VREF?? | REFERENCE 2k 2k VinG) VREF/2 a. Fixed Reference b. Fixed Reference Derived from Voc . c. Optional Full Scale Adjustment Figure 3. Absolute Mode of Operation Yoo Vin} Yoo TRANSDUCER 4* J te L 10pF $ = A/D = 2k YING) VREF/2 FULL SCALE 100 OPTIONAL 564Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 10k +5V 45 NAA cs 4 20 Voc WO 2 wcLKkR| | + 18 DD = WR 3) aH peo | LKIN | 4 DBI = INTH | 5 16 D2 AID DB2 vin(+) | 1503 bs 47uF TO v 7 14 D4 100,1F 2 INC) _* | pR4 56pFI AGND 8 13 DS 7" = VAREF2 12p5 08 9 REF2 9] DRS DGND 10 11 D7 +# DB7 v= Figure 5. Connection for Continuous Conversion +5V [ o_l R ] KT CLKIN 4 Yoo) 40 Yec| 200 = * CLK 1 Pt.o Do 18 19 CLKR c foLK=117AC 2 Pi D1 17 R= 10K 10k = A/D 3 P12 D2 16 4 PL D3 15 4 CLKIN 5 P14 D4 14 56pF ; ; 6 P15 D5 13 Figure 6. Self-Clocking the Converter seNe0s1 7 PLB De 12 AID = scnsocsi | 8 P1.7 Do? 11 5 Vint) _____[>o__ INT ANALOG Town INPUTS 17 AD FD 2 7 VREF/2 ORD 16 WA WR 3 10k 45 iz INTO INTH 5 12 AGND Ww 39 Poo tS 4 11_DGND csi 1 20 Vcc Ro| 2 19CLKR| | L a Wh | 18 DD pao | ~ CLKIN 4 17 D1 = Figure 8. SCN8051 Interfacing DB1 INTR 16 D2 : A/D 15D DB2 18 Do 5 D3 Vint) & DBS ANALOG 7 14 D4 17 D1 INPUTS ING) DB4 te be + AGND 8 13 DS == S6pF i2pe OBS 15 D3 s-BIT PF | VRE? 91 2 D6 Das BUFFER DATA DGND 10 11 D7 14 D4 | sf Bus - BB? AID 13 DS N74L8241 = 12 De N74LS244 [ = ADDRESS N74LSs41 DECODE |______ 11 D7 Loaic > -. Figure 7. Interfacing to 8080A Microprocessor __6E Figure 9. Buffering the A/D Output to Drive High Capacitance Loads and for Driving Off-Board Loads August 31, 1994 565Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 15k 820 LDT WA NESS521 47k 0.47 uF == ju x , 470 IN4148 man Vin) 3.3k A/D 2k Vin VREF/2 a -_ Figure 10. Digitizing a Transducer Interface Output + on = Voc 2k FULL 100 SCALE ADJUST NAAAA\AA_____4 TH }-2# 2k TE August 31, 1994 566Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 fy 6 2 1 Ness? =| 7 | 1/4 7 HEF4071 3 8 _) > | | RBO| 4 10K RBI| 5 6 2 1 7 NES87 2 14 7 = HEFAor1 _ |) > - 10K LOWER is | 14 Ps 1a | pBo DO 18 as RAISE 17 | DBI D1 17 A oe 16 | DB2 D2 16 20 coc + is | DBs D3 15 ok = 14 | DB4 D4 14 19 CLKR T 13 | DBS Ds 13 | = sccaocs! |i2 | DBs De 12 AID 10K 11_| DB? D7 11 # | oLKIN S56pF 8 AD RD 2 L io | WR WH 3 y 6 6 NT NTA 5 ING) ims] 27 PIO cs 1 7 MING) 29 | P12 mol ewo * 2N3906 1N4148 TO HEATER D enol 8| AGND Figure 11. Digital Thermostat 10nF August 31, 1994 567