ACD2203 CATV/TV/Video Downconverter with Dual Synthesizer PRELIMINARY DATA SHEET - Rev 1.5 FEATURES * * * * * * * * * * Integrated Downconverter Integrated Dual Synthesizer 256 QAM Compatibility Single +5 V Power Supply Operation Low Power Consumption: <0.6 W Low Noise Figure: 8 dB High Conversion Gain: 10 dB Low Distortion: -53 dBc Two-Wire Interface RoHS Compliant Package APPLICATIONS * * * * * Set Top Boxes CATV Video Tuners Digital TV Tuners CATV Data Tuners Cable Modems S8 Package 28 Pin SSOP PRODUCT DESCRIPTION The ACD2203 uses both GaAs and Si technology to provide the downconverter and dual synthesizer functions of a double conversion tuner. The performance of the included local oscillator, balanced mixer and synthesizers meet the requirements for CATV/TV/Video and Cable Modem applications. The ACD2203 is supplied in a RoHS compliant 28 lead SSOP package and requires a single +5 V supply voltage. The IC is well suited for applications where small size, low cost, low auxiliary parts count and a no-compromise performance is important. It provides for cost reduction by lowering the component and packaged IC count and decreasing the amount of labor-intensive production alignment steps, while significantly improving performance and reliability. RF2: 64/65 Prescaler RFD VIF+IFOUT+ RFIN+ RF2 Phase Detector RF2 Charge Pump CPD RF1 Phase Detector RF1 Charge Pump CPU 15 Bit RF2 R Counter RFINLow Noise Amplifier VIF+IFOUT- REFIN REFOUT Mixer Oscillator 15 Bit RF1 R Counter RFU Phase Splitter TCKT 18 Bit RF2 N Counter OSC OUT RF1: 64/65 Prescaler Clock Data AS 18 Bit RF1 N Counter 24 Bit Data Register 2 Bit A/D Figure 2: Dual Synthesizer Block Diagram Figure 1: Downconverter Block Diagram 04/2008 ACD2203 Figure 3: Pinout 2 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 ACD2203 Table 1: Pin Description PIN NAME DESCRIPTION PIN NAME DESCRIPTION VIF+IFOUT+ Downconverter Differential IFOutput Inductively coupled to +VDD 27 VIF+IFOUT - Downconverter Differential IFOutput Inductively coupled to +VDD Downconverter Ground (Must be connected) 26 GND Downconverter Ground (Must be connected) ISET Downconverter Gilbert Cell Current Source Resistor 25 VSUP Oscillator and Phase Splitter Supply (+VDD) TCKT Oscillator Input Port (Tank circuit connection) 24 OSC OUT Oscillator Output (Connected to Synthesizer RF Input) 6 OSCGND Oscillator Tank Circuit Ground (Not to be connected to any other circuit ground) 23 GND Downconverter Ground (Must be connected) 7 OSCGND Same as Pin 6 22 GND Downconverter Ground (Must be connected) 8 VSS Synthesizer Ground (Required) 21 VSS Synthesizer Ground (Required) 9 VSS Synthesizer Ground (Required) 20 VSS Synthesizer Ground (Required) 10 AS Address Select 19 RFD Synthesizer Downconverter RFInput 11 DATA 2-Wire Interface Data 18 CPD Synthesizer Downconverter Charge Pump Output 12 CLK 2-Wire Interface Clock 17 CPU Synthesizer Upconverter Charge Pump Output 13 REFIN Crystal Reference Input 16 RFU Synthesizer Upconverter RFInput 14 REFOUT Crystal Reference Output 15 VSYN Synthesizer Supply (+VDD) RFIN+ Downconverter Differential RFInput 2 RFIN- Downconverter Differential RFInput 3 GND 4 5 1 28 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 3 ACD2203 electrical characteristics Table 2: Absolute Minimum and Maximum Ratings PARAMETER MIN MAX UNIT - +9 +6.5 VDC -0.3 VSYN +0.3 VDC Input Voltages (pins 1, 2 & 5) - 0 VDC Input Power (pins 1& 2) (pin 5) (pins 13, 16 & 19) - +10 +17 +20 dBm Storage Temperature -55 +150 C Soldering Temperature - 260 C Soldering Time - 4 Sec Thermal Impedance, JC - 40 C/W Supply voltage (pins 25, 27 & 28) (pin 15) Voltage on pins 10 through 14, 16 through 19 with VSS = 0 V Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Table 3: Operating Ranges PARAMETER Downconverter Frequencies RF Input (RF) IF Output (IF) Local Oscillator (LO) MIN TYP MAX UNIT 900 35 865 - 1200 150 1350 MHz 400 400 2 - 4 - 2100 1400 20 10 MHz +4.70 +5 +5.25 VDC -40 - +85 C (1) Synthesizer Frequencies Upconverter Synthesizer (RFU) Downconverter Synthesizer (RFD) Reference Oscillator (REFIN) Phase Detector Supply Voltage: VDD (pins 15, 25, 27, 28) Ambient Operating Temperature: TA (2) The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. Notes: (1) Mixer operation is possible beyond these frequencies with slightly reduced performance. (2) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 24-26. 4 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 ACD2203 Table 4: Electrical Specifications - Downconverter Section (TA = +25 C (7), VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz) PARAMETER MIN TYP MAX UNIT Conversion Gain (1) Conversion Gain (2) 8 11 10 13 14 17 dB SSB Noise Figure (2), (3) - 4 7 dB Cross Modulation - -56 -53 dBc - - -53 dBc +12 - - dBm - -90 -85.5 dBc/Hz -10 -5 - dBm Spurious @ IF Output LO Signals and Harmonics Beats Within Output Channel Other Beats from 2 to 200 MHz Other Spurious - -10 -48 -50 -10 - dBm dBc dBm dBm IF Supply Current (pin 27 & 28) (1), (2),(6) - 50 65 mA Osc/Phase Splitter Supply Current (pin 25) - 30 45 mA Power Consumption - 400 550 mW (2), (4), (6) 3rd Order Intermodulation Distortion (IMD3) (2), (5), (6) 2-Tone 3rd Order Input Intercept Point (IIP3) (2), (5), (6) LO Phase Noise (@ 10 KHz Offset) (1), (2) LO Output Power (pin 24) (1), (2) Notes: (1) As measured in ANADIGICS test fixture with single-ended RF input. (2) As measured in ANADIGICS test fixture with differential RF inputs. (3) SSB noise figure will be approximately 3 dB higher with single-ended RF input. (4) Two tones: 1085 and 1091 MHz, -20 dBm each, 1091 MHz tone AM-modulated 99% at 15 kHz. (5) Two tones: 1085 and 1091 MHz, -15 dBm each. (6) R1 = 10 Ohms. (7) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 24-26. PRELIMINARY DATA SHEET - Rev 1.5 04/2008 5 ACD2203 Table 5: Electrical Specifications - Synthesizer Section (TA = +25 C (4), VDD = +5 VDC) PARAMETER MIN TYP MAX UNIT Prescalar Input Sensitivity Upconverter: RFU (pin 16) (1) Downconverter: RFD (pin 19) (2) Upconverter: RFU (pin 16) (1) Downconverter: RFD (pin 19) (2) -7 -13 -6 -11 - +20 +20 - Reference Oscillator Sensitivity (pin 13) - 0.5 - Vp-p Charge Pump Output Current (3) SINK SOURCE - 1.25 -1.25 - mA Supply Current - 35 50 mA Power Consumption - 165 250 mW COMMENTS (over operating frequency) dBm TA = +85 C, VDD = +4.7 V TA = +85 C, VDD = +4.7 V Notes: (1) Measured at 250 kHz comparison frequency. (2) Measured at 62.5 kHz comparison frequency. (3) CPU and CPD = VCC/2. (4) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 24-26. 6 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 ACD2203 Table 6: Digital 2-Wire Interface Specifications (TA = +25 C, VDD = +5 VDC, ref. Figure 4) PARAMETER SYMBOL MIN MAX UNIT CLK Frequency fCLK 1 400 kHz Logic High Input (pins 11, 12) VH 2.0 - V Logic Low Input (pins 11, 12) VL - 0.8 V Logic Input Current Consumption (pins 11, 12) ILOG - 10 A Address Select Input Current Consumption (pin 10) IAS - 10 A Data Sink Current (2) IAK - 4.0 mA Bus Free Time between a STOP and START Condition tBUF 1.3 - s tHD;STA 0.6 - s LOW period of CLK tLOW 1.3 - s HIGH period of CLK tHIGH 0.6 - s Set-up Time for a Repeated START Condition tSU;STA 0.6 - s Data Hold Time (for 2-wire bus devices) tHD;DAT 0.0 0.9 s Data Set-up Time tSU;DAT 100 - ns Rise Time of DATA and CLK Signals tR 20 + 0.1Cb (1) 300 ns Fall Time of Data and CLK Signals tF 20 + 0.1Cb 300 ns Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. Set-up Time for STOP Condition Capacitive Load for Each Bus Line (1) tSU;STO 0.6 - s Cb - 400 pF Notes: (1) Cb is the total capacitance of one bus line in pF. (2) For maximum 0.8 V level during Acknowledge Pulse. 3. All timing values are referred to minimum VH and maximum VL levels. DATA tF tLOW tR tSU;DAT tF tHD;STA tSP tR tBUF CLK S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S Figure 4: Serial 2-Wire Data Input Timing PRELIMINARY DATA SHEET - Rev 1.5 04/2008 7 ACD2203 PERFORMANCE DATA 15.0 5.0 13.8 3.63 14.0 4.6 13.6 3.61 13.0 4.2 13.4 3.59 12.0 3.8 Conversion Gain 13.2 13.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3 Conversion Gain 11.0 3.57 Noise Figure Conversion Gain (dB) 3.65 Noise Figure (dB) Conversion Gain (dB) 14.0 10.0 3.55 35 45 55 75 85 3.0 -90 -84 -91 -86 Phase Noise (dBc/Hz) Figure 8: Typical Phase Noise at 10 kHz Offset vs. Ambient Temperature (VDD = +5 V, fLO2 = 1042 MHz) Phase Noise (dBc/Hz) Figure 7: Typical Phase Noise at 10 kHz Offset vs. Supply Voltage (TA = +25 C, fLO2 = 1042 MHz) -92 -93 -95 -88 -90 -92 -94 -94 4.7 4.8 4.9 5.0 5.1 5.2 5.3 25 35 45 Figure 9: Typical Local Oscillator Output Power vs. Supply Voltage (TA = +25 C, fLO2 = 1042 MHz) -5.0 -5.0 Output Power (dBm) -4.5 -6.0 75 85 -5.5 -6.0 -6.5 -6.5 -7.0 65 Figure 10: Typical Local Oscillator Output Power vs. Ambient Temperature (VDD = +5 V, fLO2 = 1042 MHz) -4.5 -5.5 55 Ambient Temperature (C) Supply Voltage (V) Output Power (dBm) 65 Ambient Temperature (C) Supply Voltage (V) -7.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3 25 35 Supply Voltage (V) 8 3.4 Noise Figure 25 Noise Figure (dB) Figure 6: Typical Conversion Gain and Noise Figure vs. Ambient Temperature (VDD = +5 V, fLO2 = 1042 MHz) Figure 5: Typical Conversion Gain and Noise Figure vs. Supply Voltage (TA = +25 C, fLO2 = 1042 MHz) PRELIMINARY DATA SHEET - Rev 1.5 04/2008 45 55 Ambient Temperature (C) 65 75 85 ACD2203 Figure 12: Typical Downconverter Prescaler Sensitivity vs. Local Oscillator Frequency (TA = +25 C, VDD = +5 V) -5 -12 -10 -14 Prescalar Sensitivity (dBm) Prescalar Sensitivity (dBm) Figure 11: Typical Upconverter Prescaler Sensitivity vs. Local Oscillator Frequency (TA = +25 C, VDD = +5 V) -15 -20 -25 -30 -35 500 700 900 1100 1300 1500 1700 1900 -16 -18 -20 -22 -24 400 2100 600 800 LO1 Frequency (MHz) Prescalar Sensitivity (dBm) Prescalar Sensitivity (dBm) -7.5 -8.0 -8.5 4.8 4.9 5.0 5.1 5.2 -16.5 -17.0 -17.5 -18.0 5.3 Supply Voltage (V) 4.8 4.9 5.0 5.1 5.2 5.3 Figure 16: Typical Downconverter Prescaler Sensitivity vs. Ambient Temperature (VDD = +5 V, fLO2 = 1000 MHz) -6.0 -15.0 -6.5 Prescalar Sensitivity (dBm) Prescalar Sensitivity (dBm) 4.7 Supply Voltage (V) Figure 15: Typical Upconverter Prescaler Sensitivity vs. Ambient Temperature (VDD = +5 V, fLO1 = 2100 MHz) -7.0 -7.5 -8.0 -8.5 1400 -16.0 -7.0 4.7 1200 Figure 14: Typical Downconverter Prescaler Sensitivity vs. Supply Voltage (TA = +25 C, fLO2 = 1000 MHz) Figure 13: Typical Upconverter Prescaler Sensitivity vs. Supply Voltage (TA = +25 C, fLO1 = 2100 MHz) -9.0 1000 LO2 Frequency (MHz) 25 35 45 55 65 75 85 -15.5 -16.0 -16.5 -17.0 -17.5 25 35 Ambient Temperature (C) PRELIMINARY DATA SHEET - Rev 1.5 04/2008 45 55 65 75 85 Ambient Temperature (C) 9 ACD2203 Figure 17: Typical Conversion Gain and Noise Figure vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V, fLO2 = 1042 MHz) 5.0 Conversion Gain 13 4.2 12 3.8 11 3.4 10 0 5 10 15 180 4.6 Noise Figure 20 25 Current (mA) 14 200 N o is e F ig u re (d B ) C o n v e rs io n G a in (d B ) 15 Figure 18: Typical Total Current Consumption vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V) 160 140 120 100 3.0 80 0 5 10 R1 Resistor Value () 19 Cross Modulation (dBc) IIP3 (dBm) 25 -50 17 15 13 11 0 5 10 15 R1 Resistor Value () 10 20 Figure 20: Typical Cross Modulation vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V) Figure 19: Typical Input IP3 vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V) 9 15 R1 Resistor Value () 20 25 -55 -60 -65 0 5 10 R1 Resistor Value () PRELIMINARY DATA SHEET - Rev 1.5 04/2008 15 20 ACD2203 LOGIC PROGRAMMING The ACD2203 includes an interface for a two-wire serial data control bus that ANADIGICS has developed for use with its dual PLL synthesizers. This interface saves one connection between the host and the dual synthesizer, compared to a standard CLOCKDATA-ENABLE three-wire interface. The interface is optimized for applications in which the dual synthesizer is a slave receiver device. Hosts that conform to the I2C-Bus Specification standard can be used to program a dual PLL that uses this interface. level of a DC voltage applied to this pin determines the two-bit logic state, AS2 and AS1 to address the synthesizer. The software must be programmed with the corresponding decimal equivalent of the 8b word selected, as shown in Table 7. Once the dual PLL has recognized the Start indicator and the correct address word, it sends an address acknowledgement to the host by pulling the DATA line low for one clock pulse. The host can then begin to send data to program the dual PLL. Physical Interface The two-wire interface consists of two digital signal lines, CLOCK and DATA. The speed of the interface is nominally 400 kbits/sec. For data transmission, the signal on the DATA line must be stable when the CLOCK signal is high, and the state of the data must change only while the CLOCK signal is low. A logic level transition on the DATA line during a high CLOCK signal indicates the beginning or end of a data transmission, as specified in the following sections and shown in Figure 21. Sending Data After receiving the address byte acknowledgement from the dual PLL, the host begins sending programming data in 8-bit words. The MSB is sent first, and the LSB last. Following the receipt of each 8-bit data word, the dual PLL acknowledges receipt by pulling the DATA line low for one clock pulse. The data acknowledgement tells the host it may send the next data word. For the dual PLL, each group of three data words (24 bits total) is a significant block of information used to program one of four registers, as described in "Programming the Dual PLL." Addressing The Dual PLL Start Indicator: Stop Indicator: CLOCK Completing Data Transmissions After sending the final data word, the host sends a Stop indicator to mark the end of data transmission. A Stop is indicated by a low-to-high transition of the DATA signal while the CLOCK signal is held high. After receiving the Stop indicator, the dual PLL ceases to send further acknowledgements and begins to monitor the CLOCK and DATA signals for the next Start indicator. DATA CLOCK DATA Figure 21: Transmission Indicators The dual PLL monitors the CLOCK and DATA signals for a Start indication from the host. A Start is indicated by a high-to-low transition of the DATA signal while the CLOCK signal is high. Immediately following the Start indicator, the host sends an 8-bit address word to the dual PLL. The 8-bit word required to address the dual PLL is programmable via a DC voltage level applied to the address select pin. For example, a voltage of 4V<AS<5V corresponds to a value of C6h, or 11000110b. (The MSB is sent first, LSB last.) The Address Select pin (10) decodes an analog voltage input into two digital logic output bits AS1 and AS2. The Note: The Stop indicator does not directly control when the programming data is latched or takes effect; the data takes effect immediately following the receipt of each three-word block of data, which represents a complete 24-bit divider register. Resending Data If, for some reason, the data transmission fails or is interrupted, and the dual PLL fails to send an address word or data word acknowledgement to the host, the host can resend the data. To resend data, a new Start indicator and address word must be sent prior to any data words. Programming The Dual PLL Each synthesizer in the dual PLL contains programmable Reference and Main dividers, which allow a wide range of output frequencies. The 24-bit registers that control the dividers and other functions PRELIMINARY DATA SHEET - Rev 1.5 04/2008 11 ACD2203 Table 7: Address Select Decoding (TA = +25 C (1), VDD = +5 VDC) C (BINARY 12) AS2 AS1 VOLTAGE ON PIN 10, AS B7 B6 B5 B4 B3 B2 B1 B0 HEX DECIMAL VSS < AS < 0.8V 1 1 0 0 0 0 1 0 C2 194 1.1V < AS < 1.7V 1 1 0 0 0 0 0 0 C0 192 2.1V < AS < 2.7V 1 1 0 0 0 1 0 0 C4 196 3.15V < AS < 3.65V 1 1 0 0 0 0 0 0 C0 192 4.2V < AS < VDD 1 1 0 0 0 1 1 0 C6 198 Notes: (1) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 24-26. are each segmented into three 8-bit data words, and are programmed via the two-wire interface. Register Select Bits The two least significant bits of each register are register select bits that determine which register is programmed during a particular data entry cycle. Table 8 indicates the register select bit settings used to program each of the available registers. Reference Divider Programming The reference divider register for each synthesizer Table 8: Register Select Bits SELECT BITS DESTINATION REGISTER FOR SERIAL DATA S 2 S 1 0 0 Reference Divider Register for PLL2 0 1 Main Divider Register for PLL2 1 0 Reference Divider Register for PLL1 1 1 Main Divider Register for PLL1 of seven A counter bits, eleven B counter bits, two program mode bits and the two register select bits, as shown in Table 11. The main divider divide ratio, N, is determined by the values in the A and B counters. The eleven B Counter bits and allowed values are shown in Table 12, and the seven A Counter bits and allowed values are shown in Table 13. Note that there are some limitations on the ranges of the values for each counter. Pulse Swallow Function The VCO output frequency for the local oscillator is computed using the following equation: fVCO = N x fOSC/R where: N = [(P x B) + A] fVCO is the desired output frequency B is the divide ratio of the B counter (3 to 2047) A is the divide ratio of the A counter (0<A<P, A<B) fOSC is the frequency of the reference oscillator R is the divide ratio of the R counter (3 to 32767) P is the preset modulus of the prescalar (P=64). consists of fifteen divider bits, five program mode bits and the two register select bits, as shown in Table 9. The fifteen divider bits allow a divide ratio from 3 to 32767, inclusive, as shown in Table 10. Main Divider Programming The main divider register for each synthesizer consists 12 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 ACD2203 Table 9: Reference Divider Registers FIRST DATA WORD 24 23 22 Dummy/ Spacer X 2 21 20 19 SECOND DATA WORD 18 17 16 15 14 Program Mode X 1 D 5 D 4 D 3 13 12 11 THIRD DATA WORD 10 9 8 7 6 5 4 3 Reference Divider Divide Ratio, R D 2 D 1 R 15 R 14 R 13 R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 2 1 Select R 4 R 3 R 2 R 1 S 2 S 1 Table 9: Reference Divider Registers DIVIDE RATIO R R 15 R 14 R 13 R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 - - - - - - - - - - - - - - - - 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 11: Main Divider Registers FIRST DATA WORD 24 23 22 21 Dummy/ Spacer Program Mode X 2 C 2 X 1 C 1 20 19 18 SECOND DATA WORD 17 16 15 14 13 12 11 THIRD DATA WORD 10 9 8 B Counter B 11 B 10 B 9 B 8 B 7 B 6 B 5 7 6 5 4 3 A Counter B 4 B 3 B 2 B 1 A 7 A 6 A 5 A 4 A 3 2 1 Select A 2 A 1 S 2 S 1 Table 12: Main Divider B Counter Bits VALUE OF B COUNTER B 11 B 10 B 9 B 8 B 7 B 6 B 5 B 4 B 3 B 2 B 1 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 - - - - - - - - - - - - 2047 1 1 1 1 1 1 1 1 1 1 1 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 13 ACD2203 Table 11: Main Divider A Counter Bits VALUE OF A COUNTER A 7 A 6 A 5 A 4 A 3 A 2 A 1 Bit C1 in each main divider register sets the prescalar mode. Table 16 indicates the appropriate settings. (Currently, there is only one prescalar mode available for use.) 0 0 0 0 0 0 0 0 Table 16: Prescalar Mode 1 0 0 0 0 0 0 1 - - - - - - - - 127 1 1 1 1 1 1 1 Table 11: Phase Detector Polarity Bit S 2 S 1 D 1 0 0 PLL2 Phase Detector Polarity 1 0 PLL1 Phase Detector Polarity C 1 PRESCALAR MODE 0 64/65 1 (reserved for future use) Bit C2 in the main divider registers, bits D2 through D5 in the reference divider registers, and bits X1 and X2 in all registers are reserved bits that should be set to logic low for proper operation of the synthesizer. Programmable Modes Each register contains bits set aside for programming different modes of operation in the synthesizers. Bit D1 in each reference divider register controls the phase detector polarity. Table 14 shows how this bit controls the polarity, and the correct setting is determined by using Table 15 and Figure 22. Table 15: Phase Detector Polarity Selection D 1 POLARITY VCO CHARACTERISTICS 0 Negative curve (2) 1 Positive curve (1) (1) VCO OUTPUT FREQUENCY (2) VCO INPUT VOLTAGE Figure 22: VCO Characteristics 14 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 ACD2203 Synthesizer Programming Example The following example for programming the two synthesizers in the dual PLL details the calculations used to determine the required value of each bit in all four registers: Requirements Desired CATV input channel: "HHH" - 499.25 MHz picture carrier (501 MHz digital channel center frequency) (Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency) First IF frequency: 1087.75 MHz (recommended) Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz Phase detector comparison frequency for up converter: 250 KHz Crystal reference oscillator frequency: 4 MHz Calculation of Reference Divider Values The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired phase detector comparison frequency: R = fOSC / fPD For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison frequency are used to yield RPLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter R counter are RPLL2 = 000000001000000. For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison frequency are used to yield RPLL1 = 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter are RPLL1 = 000000000010000. Calculation of Main Divider Values The values for the A and B counters are determined by the desired VCO output frequency for the local oscillator and the phase detector comparison frequency: N = fVCO / f PD B = trunc(N / P) A = N - (B x P) The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example. The main divider ratio for the down converter, then, is NPLL2 = 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the ACD2203, BPLL2 = trunc(16672 / 64) = 260, and APLL2 = 16672 - (260 x 64) = 32. These results give bit values of BPLL2 = 00100000100 and APLL2 = 0100000 for the B and A counters. The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example. Therefore, NPLL1 = 1587 MHz / 250 KHz = 6348, BPLL1 = trunc(6348 / 64) = 99, and APLL1 = 6348 - (99 x 64) = 12. These results give bit values of BPLL1 = 00001100011 and APLL1 = 0001100 for the B and A counters. Phase Detector Polarity If the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be negative, and D1PLL1 = 1. If the VCO for the down converter has a positive slope, the phase detector polarity for PLL2 should be positive, and D1PLL2 = 0. In summary, for this example, the four register programming words are shown in Tables 17 and 18 on the following page. PRELIMINARY DATA SHEET - Rev 1.5 04/2008 15 ACD2203 Table 17: PLL1 and PLL2 Reference Divider Register Bits for Synthesizer Programming Example MSB Data Word Register Bit FIRST DATA WORD 24 23 22 Dummy/ Spacer Function Data 20 19 18 17 16 15 14 Program Mode 13 12 11 10 THIRD DATA WORD 9 8 7 6 5 4 3 Reference Divider Divide Ratio, R 2 1 Select X 2 X 1 D 5 D 4 D 3 D 2 D 1 R 15 R 14 R 13 R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 S 2 S 1 PLL2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 PLL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 Table 18: PLL1 and PLL2 Main Divider Register Bits for Synthesizer Programming Example MSB FIRST DATA WORD Data Word Register Bit 24 23 22 21 20 19 SECOND DATA WORD 18 17 16 15 14 13 12 11 10 LSB THIRD DATA WORD 9 8 7 6 5 4 3 2 1 Dummy/ Spacer Program Mode Data X 2 X 1 C 2 C 1 B 11 B 10 B 9 B 8 B 7 B 6 B 5 B 4 B 3 B 2 B 1 A 7 A 6 A 5 A 4 A 3 A 2 A 1 S 2 S 1 PLL2 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 PLL1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 Function 16 21 SECOND DATA WORD LSB B Counter A Counter PRELIMINARY DATA SHEET - Rev 1.5 04/2008 Select ACD2203 APPLICATION INFORMATION VSYN VSYN 20 k pins 17,18 pins 16,19 AV~ -1000 VSS VSS VSYN pin 13 pin 1 200 pin 2 VSS VSYN 300 k 5 k pin 14 pin 4 5 k GND GND VSS VSUP pin 27 10 pin 24 pin 5 5 pF 15 5 GND pin 28 5 pF 5 GND 10 pF OSCGND Figure 23: Equivalent Circuits PRELIMINARY DATA SHEET - Rev 1.5 04/2008 17 ACD2203 Figure 24: PC Board Layout Top View Figure 25: PC Board Layout Mid View RF RF IF AFC Out ACD22 03 4M Hz Xtal 1 18 Balun LO In J1 Figure 26: PC Board Layout Bottom View Figure 27: Evaluation Fixture Table 19: J1 Header Pinout Table 20: Fixture Pinout PIN FUNCTION PIN FUNCTION 1 Clock RF Downconverter RF Input 2 Data RF Downconverter RF Input 3 Ground IF IF Output (Single Ended) 4 AS AFC Out To Upconverter Oscillator Tuning Circuit 5 +5 VDC LO In Synthesizer RFU LO Input 6 +30 VDC PRELIMINARY DATA SHEET - Rev 1.5 04/2008 +5V X NC 5 4 1 2 3 +30V 6 J1 C5 C6 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 C7 R6 R3 address select voltage (see Table 7) AS C8 X1 R7 R4 L1 D1 RF RF R1 C1 C3 C2 +5V 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ACD2203 C12 C11 C10 C9 VSYN 15 REFOUT L2 RFU 16 R8 CPU CLK 17 RFD 19 CPD 18 VSS 20 VSS 21 GND 22 GND 23 REFIN DATA AS VSS VSS OSCGND OSCGND OSC OUT 24 TCKT GND 26 GND VSUP 25 VIF + IFOUT- 27 RFINISET VIF + IFOUT+ 28 RFIN+ C24 L3 C13 R9 C20 C21 DT1 IF C14 R10 R12 C17 C22 R11 C16 C23 C15 Q1 LOIN AFCOUT +5V C18 R13 C19 +30V ACD2203 Figure 28: Evaluation Fixture Schematic 19 ACD2203 Table 21: Evaluation Fixture Parts List ITEM # VALUE SIZE DESCRIPTION PART # C1, C2, C20 100pF 0603 Chip-capacitor C3 9pF 0603 C7, C8 30pF 0603 C12 220uF QTY VENDOR GRM39COG101J50V 3 Murata Chip-capacitor GRM39COG090C50V 1 Murata Chip-capacitor GRM39COG300J50V 2 Murata PCE2040CT-ND 1 DIGI-KEY 10V VA Capacitor Series C9, C11, C14, C21, C22 .1uF 0603 Chip-capacitor GRM39Y5V104Z16V 5 Murata C10, C23 1000pF 0603 Chip-capacitor GRM39X7R102K50V 2 Murata C15, C17 4700pF 0603 Chip-capacitor GRM39X7R472K25V 2 Murata C16 1uF 0603 Radial-lead Chip-capacitor RPE113-X7R-105-K-050 1 Murata C18 .01uF 0603 Chip-capacitor GRM39X7R103K25V 1 Murata C19 10uF 35 V TANT TE Series Cap. PCS6106CT-ND 1 DIGI-KEY C24 15pF 0603 Chip-capacitor GRM39COG150J50V 1 Murata C13 5600pF 0603 Chip-capacitor GRM39X7R562K50V 1 Murata 33pF 0603 Chip-capacitor GRM39COG330J50V 2 Murata R8 51 0603 Chip Resistor ERJ-3GSYJ510 1 Panasonic R1 10 0603 Chip Resistor ERJ-3GSYJ100 1 Panasonic R3, R4 2K 0603 Chip Resistor ERJ-3GSYJ202 2 Panasonic R12 1K 0603 Chip Resistor ERJ-3GSYJ102 1 Panasonic R11 2.7K 0603 Chip Resistor ERJ-3GSYJ272 1 Panasonic R7 3K 0603 Chip Resistor ERJ-3GSYJ302 1 Panasonic R13 22K 0603 Chip Resistor ERJ-3GSYJ223 1 Panasonic R10 8.2K 0603 Chip Resistor ERJ-3GSYJ822 1 Panasonic 0 0603 Chip Resistor ZC0603 2 RCD 5.6nH 0805 Inductor 0805CS-050X-BC 1 Coilcraft C5, C6 R6, R9 L1 20 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 ACD2203 Table 21: Evaluation Fixture Parts List continued ITEM # VALUE SIZE DESCRIPTION PART # L2 68nH 0805 Inductor L3 270nH 0805 D1 1SV245 DT1 4:1 Q1 30V SMD X1 4MHZ SOT-23 QTY VENDOR 0805CS-680X-BC 1 Coilcraft Inductor 0805CS-271X-BC 1 Coilcraft Varactor diode 1SV245 1 Toshiba Transformer ETC4-1-2 1 M/A-COM, Inc. North America Transistor NPN Darl. FMMTA13CT-ND 1 DIGI-KEY Crystal SE2618CT-ND 1 DIGI-KEY PRELIMINARY DATA SHEET - Rev 1.5 04/2008 21 ACD2203 PACKAGE OUTLINE Figure 29: S8 Package Outline - 28 Pin SSOP 22 PRELIMINARY DATA SHEET - Rev 1.5 04/2008 ACD2203 NOTES PRELIMINARY DATA SHEET - Rev 1.5 04/2008 23 ACD2203 Ordering Information ORDER NUMBER TEMPERATURE RANGE PACKAGE DESCRIPTION COMPONENT PACKAGING ACD2203RS8P1 -40C to +85C RoHS Compliant 28 Pin SSOP Tape & Reel, 3500 pieces per reel ANADIGICS, Inc. 141 Mount Bethel Road Warren, New Jersey 07059, U.S.A Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product's formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. 24 Preliminary Data Sheet - Rev 1.5 04/2008