04/2008
ACD2203
CATV/TV/Video Downconverter
with Dual Synthesizer
PRELIMINARY DATA SHEET - Rev 1.5
Figure 1: Downconverter Block Diagram
FEATURES
• IntegratedDownconverter
• IntegratedDualSynthesizer
• 256QAMCompatibility
• Single+5VPowerSupplyOperation
• LowPowerConsumption:<0.6W
• LowNoiseFigure:8dB
• HighConversionGain:10dB
• LowDistortion:-53dBc
• Two-WireInterface
• RoHSCompliantPackage
APPLICATIONS
• SetTopBoxes
• CATVVideoTuners
• DigitalTVTuners
• CATVDataTuners
• CableModems
S8 Package
28 Pin SSOP
PRODUCT DESCRIPTION
TheACD2203 uses both GaAs and Si technology
to provide the downconverter and dual synthesizer
functions of a double conversion tuner. The
performanceoftheincludedlocaloscillator,balanced
mixer and synthesizers meet the requirements for
CATV/TV/VideoandCableModemapplications.The
ACD2203issuppliedinaRoHScompliant28lead
SSOP package and requires a single +5 V supply
voltage.TheICiswellsuitedforapplicationswhere
smallsize,lowcost,lowauxiliarypartscountanda
no-compromiseperformanceisimportant.Itprovides
for cost reduction by lowering the component and
packaged IC count and decreasing the amount of
labor-intensive production alignment steps, while
signicantlyimprovingperformanceandreliability.
Figure 2: Dual Synthesizer Block Diagram
VIF+IFOUT+
OSC OUTTCKT
RFIN+
Phase Splitter
Low Noise
AmplifierMixer
RFIN-
VIF+IFOUT-
RF2:64/65
Prescaler
18 Bit RF2
N Counter
RF2
Phase
Detector
RF2
Charge
Pump
RF1
Phase
Detector
RF1
Charge
Pump
15 Bit RF2
R Counter
15 Bit RF1
R Counter
18 Bit RF1
N Counter
RF1: 64/65
Prescaler
Oscillator
24 Bit
Data Register
CPU
CPDRFD
REFIN
REFOUT
RFU
Clock
Data
AS 2Bit
A/D
2PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
Figure 3: Pinout
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
3
ACD2203
Table 1: Pin Description
PIN NAME DESCRIPTION PIN NAME DESCRIPTION
1RF
IN+
Downconverter
DifferentialRFInput 28 V
IF
+IF
OUT+
Downconverter
DifferentialIFOutput
Inductivelycoupledto
+V
DD
2RF
IN-
Downconverter
DifferentialRFInput 27 V
IF
+IF
OUT
-
Downconverter
DifferentialIFOutput
Inductivelycoupledto
+V
DD
3GND DownconverterGround
(Mustbeconnected) 26 GND DownconverterGround
(Mustbeconnected)
4I
SET
DownconverterGilbert
Cell Current Source
Resistor
25 V
SUP
OscillatorandPhase
SplitterSupply(+V
DD
)
5T
CKT
OscillatorInputPort
(Tankcircuitconnection) 24 OSC
OUT
OscillatorOutput
(Connected to
SynthesizerRFInput)
6OSC
GND
OscillatorTankCircuit
Ground(Nottobe
connected to any other
circuitground)
23 GND DownconverterGround
(Mustbeconnected)
7OSC
GND
SameasPin6 22 GND DownconverterGround
(Mustbeconnected)
8V
SS
SynthesizerGround
(Required) 21 V
SS
SynthesizerGround
(Required)
9 V
SS
SynthesizerGround
(Required) 20 V
SS
SynthesizerGround
(Required)
10 AS Address Select 19 RF
D
Synthesizer
DownconverterRFInput
11 D ATA 2-WireInterfaceData 18 CP
D
Synthesizer
Downconverter
ChargePumpOutput
12 CLK 2-WireInterfaceClock 17 CP
U
SynthesizerUpconverter
ChargePumpOutput
13 REF
IN
CrystalReferenceInput 16 RF
U
SynthesizerUpconverter
RFInput
14 REF
OUT
CrystalReferenceOutput 15 V
S YN
SynthesizerSupply
(+V
DD
)
4PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
Stresses in excess of the absolute ratings may cause permanent damage.
Functional operation is not implied under these conditions. Exposure
to absolute ratings for extended periods of time may adversely affect
reliability.
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical
specications.
Table 3: Operating Ranges
Notes:
(1) Mixer operation is possible beyond these frequencies with slightly reduced
performance.
(2) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient
Temperature is +25 °C, using the PC Board Layout shown in Figures 24-26.
PARAMETER MIN MAX UNIT
Supplyvoltage
(pins25,27&28)
(pin15)
-
-
+9
+6.5
V
DC
Voltageonpins10through14,16
through19withV
SS
=0V -0.3 V
S YN
+0.3 V
DC
InputVoltages(pins1,2&5) - 0 V
DC
InputPower
(pins1&2)
(pin5)
(pins13,16&19)
-
-
-
+10
+17
+20
dBm
StorageTemperature -55 +150 C
SolderingTemperature -260 C
SolderingTime -4Sec
ThermalImpedance,JC -40 C/W
PARAMETER MIN TYP MAX UNIT
DownconverterFrequencies
(1)
RFInput(RF)
IFOutput(IF)
LocalOscillator(LO)
900
35
865
-
-
-
1200
150
1350
MHz
SynthesizerFrequencies
UpconverterSynthesizer(RFU)
DownconverterSynthesizer(RFD)
ReferenceOscillator(REFIN)
PhaseDetector
400
400
2
-
-
-
4
-
2100
1400
20
10
MHz
SupplyVoltage:V
DD
(pins15,25,27,28) +4.70 +5 +5.25 VDC
AmbientOperatingTemperature:TA
(2)
-40 -+85 °C
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
5
ACD2203
Table 4: Electrical Specications - Downconverter Section
(TA = +25 °C (7), VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz)
Notes:
(1) As measured in ANADIGICS test xture with single-ended RF input.
(2) As measured in ANADIGICS test xture with differential RF inputs.
(3) SSB noise gure will be approximately 3 dB higher with single-ended RF input.
(4) Two tones: 1085 and 1091 MHz, -20 dBm each, 1091 MHz tone AM-modulated 99% at
15 kHz.
(5) Two tones: 1085 and 1091 MHz, -15 dBm each.
(6) R1 = 10 Ohms.
(7) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient
Temperature is +25 °C, using the PC Board Layout shown in Figures 24-26.
PARAMETER MIN TYP MAX UNIT
ConversionGain
(1)
ConversionGain
(2)
8
11
10
13
14
17 dB
SSBNoiseFigure
(2),(3)
-47dB
CrossModulation
(2),(4),(6)
--56 -53 dBc
3
rd
OrderIntermodulationDistortion
(IMD3)
(2),(5),(6)
- - -53 dBc
2-Tone3
rd
OrderInputInterceptPoint
(IIP3 )
(2),(5),(6)
+12 - - dBm
LOPhaseNoise(@10KHzOffset)
(1),(2)
--90 -85.5 dBc/Hz
LOOutputPower(pin24)
(1),(2)
-10 -5 -dBm
Spurious@IFOutput
LOSignalsandHarmonics
BeatsWithinOutputChannel
OtherBeatsfrom2to200MHz
OtherSpurious
-
-
-
-
-10
-48
-50
-10
-
-
-
-
dBm
dBc
dBm
dBm
IFSupplyCurrent(pin27&28)
(1),(2),(6)
-50 65 mA
Osc/PhaseSplitterSupplyCurrent
(pin25) -30 45 mA
PowerConsumption -400 550 mW
6PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
Table 5: Electrical Specications - Synthesizer Section
(TA = +25 °C (4), VDD = +5 VDC)
Notes:
(1) Measured at 250 kHz comparison frequency.
(2) Measured at 62.5 kHz comparison frequency.
(3) CPU and CPD = VCC/2.
(4) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient Temperature is +25 °C, using the PC
Board Layout shown in Figures 24-26.
PARAMETER MIN TYP MAX UNIT COMMENTS
PrescalarInputSensitivity
Upconverter:RF
U
(pin16)
(1)
Downconverter:RF
D
(pin19)
(2)
Upconverter:RF
U
(pin16)
(1)
Downconverter:RF
D
(pin19)
(2)
-7
-13
-6
-11
-
-
-
-
+20
+20
-
-
dBm
(overoperatingfrequency)
T
A
=+85°C,V
DD
=+4.7V
T
A
=+85°C,V
DD
=+4.7V
ReferenceOscillatorSensitivity(pin13) -0.5 -V
p-p
ChargePumpOutputCurrent
(3)
SINK
SOURCE
-
-
1.25
-1.25
-
-mA
SupplyCurrent -35 50 mA
PowerConsumption -165 250 mW
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
7
ACD2203
Figure 4: Serial 2-Wire Data Input Timing
Table 6: Digital 2-Wire Interface Specications
(TA = +25 °C, VDD = +5 VDC, ref. Figure 4)
Notes:
(1) Cb is the total capacitance of one bus line in pF.
(2) For maximum 0.8 V level during Acknowledge Pulse.
3. All timing values are referred to minimum VH and maximum VL levels.
PARAMETER SYMBOL MIN MAX UNIT
CLKFrequency f
CLK
1400 kHz
LogicHighInput(pins11,12) V
H
2.0 -V
LogicLowInput(pins11,12) V
L
-0.8 V
LogicInputCurrentConsumption
(pins11,12) I
LOG
-10 µA
AddressSelectInputCurrent
Consumption(pin10) I
AS
-10 µA
DataSinkCurrent
(2)
I
AK
-4.0 mA
BusFreeTimebetweenaSTOPand
STARTCondition t
BUF
1.3 -µs
HoldTime(repeated)STARTCondition.
Afterthisperiod,thefirstclockpulseis
generated.
t
HD ; S TA
0.6 -µs
LOWperiodofCLK t
LOW
1.3 -µs
HIGHperiodofCLK t
HIGH
0.6 -µs
Set-upTimeforaRepeatedSTART
Condition t
SU;STA
0.6 -µs
DataHoldTime(for2-wirebusdevices) t
HD;DAT
0.0 0.9 µs
DataSet-upTime t
SU;DAT
100 -ns
RiseTimeofDATAandCLKSignals t
R
20+0.1C
b
(1)
300 ns
FallTimeofDataandCLKSignals t
F
20+0.1C
b
(1)
300 ns
Set-upTimeforSTOPCondition t
SU;STO
0.6 -µs
CapacitiveLoadforEachBusLine C
b
-400 pF
8PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
Figure 10: Typical Local Oscillator Output Power
vs. Ambient Temperature
(V =+5V,f = 1042 MHz)
DD LO2
-7.0
-6.5
-6.0
-5.5
-5.0
-4.5
25 35 45 55 65 75 85
AmbientTemperature (°C)
Output Power (dBm)
Figure 8: Typical Phase Noise at 10 kHz Offset
vs. Ambient Temperature
(V =+5V,f = 1042 MHz)
DD LO2
-94
-92
-90
-88
-86
-84
25 35 45 55 65 75 85
AmbientTemperature (°C)
Phase Noise (dBc/Hz)
Figure 6: Typical Conversion Gain and Noise
Figure vs. Ambient Temperature
(V =+5V,f = 1042 MHz)
DD LO2
10.0
11.0
12.0
13.0
14.0
15.0
25 35 45 55 65 75 85
AmbientTemperature (°C)
Conversion Gain (dB)
3.0
3.4
3.8
4.2
4.6
5.0
Noise Figure (dB)
Conversion Gain
NoiseFigure
PERFORMANCE DATA
13.0
13.2
13.4
13.6
13.8
14.0
4.74.8 4.95.0 5.15.2 5.3
SupplyVoltage (V)
Conversion Gain (dB)
3.55
3.57
3.59
3.61
3.63
3.65
Noise Figure (dB)
Conversion Gain
NoiseFigure
Figure 5: Typical Conversion Gain and Noise
Figure vs. Supply Voltage
(T = +25 °C, f=1042 MHz)
A LO2
Figure 7: Typical Phase Noise at 10 kHz Offset
vs. Supply Voltage
(T = +25 °C, f=1042 MHz)
A LO2
-95
-94
-93
-92
-91
-90
4.74.8 4.95.0 5.15.2 5.3
SupplyVoltage (V)
Phase Noise (dBc/Hz)
Figure 9: Typical Local Oscillator Output Power
vs. Supply Voltage
(T = +25 °C, f=1042 MHz)
A LO2
-7.0
-6.5
-6.0
-5.5
-5.0
-4.5
4.74.8 4.95.0 5.15.2 5.3
Supply Voltage(V)
Output Power (dBm)
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
9
ACD2203
Figure 11:Typical Upconverter Prescaler
Sensitivity vs. Local Oscillator Frequency
(T = +25 °C, V=+5 V)
ADD
-35
-30
-25
-20
-15
-10
-5
500 700 900 1100 1300 1500 1700 1900 2100
LO1Frequency (MHz)
Prescalar Sensitivity (dBm)
Figure 13: Typical Upconverter Prescaler
Sensitivity vs. Supply Voltage
(T = +25 °C, f=2100 MHz)
A LO1
-9.0
-8.5
-8.0
-7.5
-7.0
4.74.8 4.95.0 5.15.2 5.3
SupplyVoltage (V)
Prescalar Sensitivity (dBm)
Figure 15: Typical Upconverter Prescaler
Sensitivity vs. Ambient Temperature
(V =+5V,f = 2100 MHz)
DD LO1
-8.5
-8.0
-7.5
-7.0
-6.5
-6.0
25 35 45 55 65 75 85
AmbientTemperature (°C)
Prescalar Sensitivity (dBm)
Figure 12: Typical Downconverter Prescaler
Sensitivity vs. Local Oscillator Frequency
(T = +25 °C, V=+5 V)
ADD
-24
-22
-20
-18
-16
-14
-12
400 600800 1000 1200 1400
LO2Frequency (MHz)
Prescalar Sensitivity (dBm)
Figure 14: Typical Downconverter Prescaler
Sensitivity vs. Supply Voltage
(T = +25 °C, f=1000 MHz)
A LO2
-18.0
-17.5
-17.0
-16.5
-16.0
4.74.8 4.95.0 5.15.2 5.3
SupplyVoltage (V)
Prescalar Sensitivity (dBm)
Figure 16: Typical Downconverter Prescaler
Sensitivity vs. Ambient Temperature
(V =+5V,f = 1000 MHz)
DD LO2
-17.5
-17.0
-16.5
-16.0
-15.5
-15.0
25 35 45 55 65 75 85
AmbientTemperature (°C)
Prescalar Sensitivity (dBm)
10 PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
Figure 17: Typical Conversion Gain and Noise
Figure vs. LNA/Mixer Current Control Resistor R1
(T = +25 °C, V=+5 V, f=1042 MHz)
ADD LO2
10
11
12
13
14
15
0510 15 20 25
R1 Resistor Value()
C o n v e r s io n G a i n (d B )
3.0
3.4
3.8
4.2
4.6
5.0
N o i s e F ig u re ( d B )
Conversion Gain
NoiseFigure
Figure 18: Typical Total Current Consumption
vs. LNA/Mixer Current Control Resistor R1
(T = +25 °C, V=+5 V)
ADD
80
100
120
140
160
180
200
0510 15 20 25
R1 Resistor Value(
)
Current (mA)
Figure 19: Typical Input IP3
vs. LNA/Mixer Current Control Resistor R1
(T = +25 °C, V=+5 V)
ADD
9
11
13
15
17
19
0510 15 20 25
R1 Resistor Value(
)
IIP3 (dBm)
Figure 20: Typical Cross Modulation
vs. LNA/Mixer Current Control Resistor R1
(T = +25 °C, V=+5 V)
ADD
-65
-60
-55
-50
0510 15 20
R1 Resistor Value(
)
Cross Modulation (dBc)
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
11
ACD2203
LOGIC PROGRAMMING
TheACD2203 includes an interface for a two-wire
serialdatacontrolbusthatANADIGICShasdeveloped
forusewithitsdualPLLsynthesizers.Thisinterface
saves one connection between the host and the
dual synthesizer, compared to a standard CLOCK-
DATA-ENABLEthree-wireinterface.Theinterfaceis
optimizedforapplicationsinwhichthedualsynthesizer
isaslavereceiverdevice.Hoststhatconformtothe
I2C-BusSpecicationstandardcanbeusedtoprogram
adualPLLthatusesthisinterface.
Physical Interface
Thetwo-wire interface consists oftwodigital signal
lines,CLOCKandDATA.Thespeedoftheinterface
is nominally 400 kbits/sec. For data transmission,
the signal on the DATA line must be stable when
theCLOCKsignalishigh,andthestateofthedata
mustchangeonlywhiletheCLOCKsignalislow.A
logicleveltransitionontheDATAlineduringahigh
CLOCKsignalindicatesthebeginningorendofadata
transmission,asspeciedinthefollowingsectionsand
showninFigure21.
Addressing The Dual PLL
levelofaDCvoltageappliedtothispindetermines
thetwo-bitlogicstate,AS2andAS1toaddressthe
synthesizer. The software must be programmed
with the corresponding decimal equivalent of the
8b word selected, as shown in Table 7. Once the
dualPLLhasrecognizedtheStart indicator and the
correct address word, it sends an address
acknowledgement to the host by pulling the DATA
linelowforoneclockpulse.Thehostcanthenbegin
tosenddatatoprogramthedualPLL.
Sending Data
Afterreceivingtheaddressbyteacknowledgementfrom
thedualPLL,thehostbeginssendingprogramming
data in 8-bit words. The MSB is sent rst, and the
LSB last. Following the receipt of each 8-bit data
word,thedualPLLacknowledgesreceiptbypulling
the DATA line low for one clock pulse. The data
acknowledgementtellsthehostitmaysendthenext
dataword.ForthedualPLL,eachgroupofthreedata
words(24bitstotal)isasignicantblockofinformation
usedtoprogramoneoffourregisters,asdescribedin
“ProgrammingtheDualPLL.”
Completing Data Transmissions
Aftersending the nal dataword,the host sendsa
Stopindicatortomarktheendofdatatransmission.
A Stopisindicatedbyalow-to-hightransitionofthe
DATA signal while the CLOCK signal is held high.
AfterreceivingtheStopindicator,thedualPLLceases
to send further acknowledgements and begins to
monitor the CLOCK and DATA signals for the next
Startindicator.
Note: The Stop indicator does not directly control when
the programming data is latched or takes effect; the
data takes effect immediately following the receipt of
each three-word block of data, which represents a
complete 24-bit divider register.
Resending Data
If,forsomereason,thedatatransmissionfailsoris
interrupted,andthedualPLLfailstosendanaddress
wordordatawordacknowledgementtothehost,the
hostcanresendthedata.Toresenddata,anewStart
indicatorandaddresswordmustbesentpriortoany
datawords.
Programming The Dual PLL
Each synthesizer in the dual PLL contains
programmable Reference and Main dividers, which
allowawiderangeofoutputfrequencies.The24-bit
registersthatcontrolthedividersandotherfunctions
DATA
CLOCK
Stop
Indicator:
DATA
CLOCK
Start
Indicator:
Figure 21: Transmission Indicators
ThedualPLLmonitorstheCLOCKandDATAsignals
foraStartindicationfromthehost.AStart is indicated
bya high-to-low transitionofthe DATAsignalwhile
theCLOCKsignalishigh.Immediatelyfollowingthe
Startindicator,thehostsendsan8-bitaddressword
tothedualPLL.The8-bitwordrequiredtoaddress
thedualPLLisprogrammableviaaDCvoltagelevel
applied to the address select pin. For example, a
voltageof4V<AS<5VcorrespondstoavalueofC6h,
or11000110b.(TheMSBissentrst,LSBlast.)The
AddressSelectpin(10)decodesananalogvoltage
inputintotwodigitallogicoutputbitsAS1andAS2.The
12 PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
areeachsegmentedintothree8-bitdatawords,and
areprogrammedviathetwo-wireinterface.
Register Select Bits
The two least signicant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table8indicatestheregisterselectbitsettingsused
toprogrameachoftheavailableregisters.
Reference Divider Programming
The reference divider register for each synthesizer
Table 7: Address Select Decoding
(TA = +25 °C (1), VDD = +5 VDC)
of sevenA counter bits, eleven B counter bits, two
programmode bits and the two register select bits,
asshowninTable11.Themaindividerdivideratio,N,
isdeterminedbythevaluesintheAandBcounters.
The eleven B Counter bits and allowed values are
showninTable12,andthesevenACounterbitsand
allowedvaluesareshowninTable13.Notethatthere
aresomelimitationsontherangesofthevaluesfor
eachcounter.
Pulse Swallow Function
TheVCOoutputfrequencyfor thelocaloscillatoris
computedusingthefollowingequation:
fVCO=NxfOSC/R
where:
N=[(PxB)+A]
fVCOisthedesiredoutputfrequency
BisthedivideratiooftheBcounter(3to2047)
AisthedivideratiooftheAcounter(0<A<P,A<B)
fOSCisthefrequencyofthereferenceoscillator
RisthedivideratiooftheRcounter(3to32767)
Pisthepresetmodulusoftheprescalar(P=64).
consistsoffteendividerbits,veprogrammodebits
andthetworegisterselectbits,asshowninTable9.
Thefteendividerbitsallowadivideratiofrom3to
32767,inclusive,asshowninTable10.
Main Divider Programming
Themaindividerregisterforeachsynthesizerconsists
Notes:
(1) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient Temperature is +25
°C, using the PC Board Layout shown in Figures 24-26.
VOLTAGE ON PIN
10, AS
C (BINARY 12) AS2 AS1
HEX DECIMAL
B7 B6 B5 B4 B3 B2 B1 B0
V
SS
<AS<0.8V 1 1 0 0 0 0 1 0 C2 194
1.1V<AS<1.7V 1 1 0 0 0 0 0 0 C0 192
2.1V<AS<2.7V 1 1 0 0 0 1 0 0 C4 196
3.15V<AS<3.65V 1 1 0 0 0 0 0 0 C0 192
4.2V<AS<V
DD
1 1 0 0 0 1 1 0 C6 198
Table 8: Register Select Bits
SELECT
BITS DESTINATION REGISTER FOR
SERIAL DATA
S
2
S
1
0 0 ReferenceDividerRegisterforPLL2
0 1 MainDividerRegisterforPLL2
1 0 ReferenceDividerRegisterforPLL1
1 1 MainDividerRegisterforPLL1
PRELIMINARY DATA SHEET - Rev 1.5
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13
ACD2203
Table 9: Reference Divider Registers
FIRST DATA WORD SECOND DATA WORD THIRD DATA WORD
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Dummy/
Spacer
Program Mode Reference Divider Divide Ratio, R Select
X
2
X
1
D
5
D
4
D
3
D
2
D
1
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
S
2
S
1
Table 9: Reference Divider Registers
DIVIDE
RATIO R
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3 000000000000011
4000000000000100
- ---------------
32767 111111111111111
Table 11: Main Divider Registers
FIRST DATA WORD SECOND DATA WORD THIRD DATA WORD
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Dummy/
Spacer
Program
Mode
B Counter A Counter Select
X
2
X
1
C
2
C
1
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
A
2
A
1
S
2
S
1
Table 12: Main Divider B Counter Bits
VALUE OF B
COUNTER
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
3 00000000011
400000000100
- -----------
2047 11111111111
14 PRELIMINARY DATA SHEET - Rev 1.5
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ACD2203
Programmable Modes
Eachregistercontainsbitssetasideforprogramming
differentmodesofoperationinthesynthesizers.BitD1
ineachreferencedividerregistercontrolsthephase
detectorpolarity.Table14showshowthisbitcontrols
thepolarity,andthecorrectsettingisdeterminedby
usingTable15andFigure22.
Figure 22: VCO Characteristics
(1)
(2)
VCO INPUT VOLTAGE
VCO OUTPUT
FREQUENCY
BitC1ineachmaindividerregistersetstheprescalar
mode. Table 16 indicates the appropriate settings.
(Currently,thereisonlyoneprescalarmodeavailable
foruse.)
Table 16: Prescalar Mode
BitC2inthemaindividerregisters,bitsD2throughD5
inthereferencedividerregisters,andbitsX1andX2
inallregistersarereservedbitsthatshouldbesetto
logiclowforproperoperationofthesynthesizer.
Table 11: Main Divider A Counter Bits
VALUE OF A
COUNTER
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0 0000000
1 0 0 0 0 0 0 1
- -------
127 1111111
Table 11: Phase Detector Polarity Bit
S
2
S
1
D
1
0 0 PLL2PhaseDetectorPolarity
1 0 PLL1PhaseDetectorPolarity
Table 15: Phase Detector Polarity Selection
D
1POLARITY
VCO
CHARACTERISTICS
0Negative curve(2)
1Positive curve(1)
C
1PRESCALAR MODE
064/65
1(reservedforfutureuse)
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
15
ACD2203
Synthesizer Programming Example
ThefollowingexampleforprogrammingthetwosynthesizersinthedualPLLdetailsthecalculationsusedto
determinetherequiredvalueofeachbitinallfourregisters:
Requirements
DesiredCATVinputchannel:“HHH”-499.25MHzpicturecarrier(501MHzdigitalchannelcenterfrequency)
(Second)IFpicturecarrieroutputfrequency:45.75MHz(44MHzdigitalchannelcenterfrequency)
FirstIFfrequency:1087.75MHz(recommended)
Phasedetectorcomparisonfrequencyfordownconverter(alsotuningincrement):62.5KHz
Phasedetectorcomparisonfrequencyforupconverter:250KHz
Crystalreferenceoscillatorfrequency:4MHz
CalculationofReferenceDividerValues
Thevalueforeachreferencedivideriscalculatedbydividingthereferenceoscillatorfrequencybythedesired
phasedetectorcomparisonfrequency:
R=fOSC/fPD
Forthedownconverter,the4MHzcrystaloscillatorfrequencyandthe62.5KHzphasedetectorcomparison
frequencyareusedtoyieldRPLL2=4MHz/62.5KHz=64,andsothebitvaluesforthedown converter
RcounterareRPLL2=000000001000000.
Fortheupconverter, the 4 MHz crystal oscillator frequency andthe250KHzphasedetectorcomparison
frequencyareusedtoyieldRPLL1=4MHz/250KHz=16,andsothebitvaluesfortheupconverterRcounter
areRPLL1=000000000010000.
CalculationofMainDividerValues
ThevaluesfortheAandBcountersaredeterminedbythedesiredVCOoutputfrequencyforthelocaloscillator
andthephasedetectorcomparisonfrequency:
N=fVCO/fPD B=trunc(N/P) A=N-(BxP)
Thedownconverterlocaloscillatorfrequencywillbe1087.75MHz-45.75MHz=1042MHzinthisexample.
Themaindividerratioforthedownconverter,then,isNPLL2=1042MHz/62.5KHz=16672.SinceP=64in
theACD2203,BPLL2=trunc(16672/64)=260,andAPLL2=16672-(260x64)=32.Theseresultsgivebitvalues
ofBPLL2=00100000100andAPLL2=0100000fortheBandAcounters.
Theupconverterlocaloscillatorfrequencywillbe499.25MHz+1087.75MHz=1587MHzinthisexample.
Therefore,NPLL1=1587MHz/250KHz=6348,BPLL1=trunc(6348/64)=99,andAPLL1=6348-(99x64)=12.
TheseresultsgivebitvaluesofBPLL1=00001100011andAPLL1=0001100fortheBandAcounters.
PhaseDetectorPolarity
IftheVCOfortheupconverterhasanegativeslope,thephasedetectorpolarityforPLL1shouldbenegative,
andD1PLL1=1.IftheVCOforthedownconverterhasapositiveslope,thephasedetectorpolarityforPLL2
shouldbepositive,andD1PLL2=0.
Insummary,forthis example,thefourregisterprogrammingwordsareshowninTables17 and18onthe
followingpage.
16 PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
LSB
MSB
Data Word
Register Bit
Function
Data
PLL2
PLL1
Table 17: PLL1 and PLL2 Reference Divider Register Bits
for Synthesizer Programming Example
Table 18: PLL1 and PLL2 Main Divider Register Bits
for Synthesizer Programming Example
FIRST DATA WORD SECOND DATA WORD THIRD DATA WORD
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Dummy/
Spacer Program Mode Reference Divider Divide Ratio, R Select
X
2
X
1
D
5
D
4
D
3
D
2
D
1
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
S
2
S
1
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
000000000000000001000010
Data Word
Register Bit
Function
Data
PLL2
PLL1
LSBMSB
FIRST DATA WORD SECOND DATA WORD THIRD DATA WORD
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Dummy/
Spacer
Program
Mode
B Counter A Counter Select
X
2
X
1
C
2
C
1
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
A
2
A
1
S
2
S
1
0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
17
ACD2203
APPLICATION INFORMATION
pins
17,18
VSYN
VSS
20 k
AV~ -1000
VSYN
VSS
pins
16,19
300 k
VSYN
VSS
pin 13
VSYN
VSS
pin 14
200
GND
pin1
pin2
pin4 GND
5k5k
10
pin 24
pin5
OSCGND
VSUP
15
10 pF
GND
pin28
pin27
GND
55
5pF5pF
Figure 23: Equivalent Circuits
18 PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
Figure 24: PC Board Layout Top View
Figure 26: PC Board Layout Bottom View
Figure 25: PC Board Layout Mid View
Figure 27: Evaluation Fixture
Table 19: J1 Header Pinout
Balun
J1
RF IF
AFC
Out
LO
In
RF
1
4M H z Xtal
ACD22
0
3
Table 20: Fixture Pinout
PIN FUNCTION
1Clock
2Data
3Ground
4AS
5+5V
DC
6+30V
DC
PIN FUNCTION
RF DownconverterRFInput
RF DownconverterRFInput
IF IFOutput(SingleEnded)
AFCOut ToUpconverterOscillatorTuningCircuit
LOIn SynthesizerRF
U
LOInput
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
19
ACD2203
Figure 28: Evaluation Fixture Schematic
2 27
16
15
1
14
22
24
25
23
21
20
19
18
17
28
26
9
8
7
10
6
11
5
12
4
13
3
RF
IN+
OSC
GND
OSC
GND
T
CKT
I
SET
GND
RF
IN-
DATA
CLK
REF
IN
REF
OUT
V
SYN
V
SS
GND
V
SS
GND
RF
D
CP
D
V
SUP
OSC
OUT
CP
U
V
IF
+ IF
OUT-
RF
U
V
IF
+ IF
OUT+
V
SS
V
SS
AS
GND
C20
R7
D1
ACD2203
R1
C2
C3
L1
C8
C21 C23
C22
L3
C24
C12 C11 C10
R8 L2
R9
C13
R10
C14
C15
R11
C17
C16
R13
RF
C1
RF
C9
+5V
R6
X1
C7
LO
IN
DT1
IF
+5V
R12
AFC
OUT
Q1
C18 C19
+30V
R3
R4
C5 C6
1
6
5
4
3
2
J1
+30V
+5V
NC
X
AS
address select voltage
(see Table 7)
20 PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
Table 21: Evaluation Fixture Parts List
ITEM # VALUE SIZE DESCRIPTION PART # QTY VENDOR
C1,C2,
C20
100pF 0603 Chip-capacitor
GRM39COG101J50V
3
Murata
C3 9pF 0603 Chip-capacitor
GRM39COG0
9
0C50V
1
Murata
C7,C8 30pF 0603 Chip-capacitor
GRM39COG300J50V
2
Murata
C12 220uF 10VVA
Series
Capacitor
PCE2040CT-ND
1
DIGI-K E Y
C9,C11,
C14,C21,
C22
.1uF 0603 Chip-capacitor
GRM39Y5V104Z16V
5
Murata
C10,C23 1000pF 0603 Chip-capacitor
GRM39X7R102K50V
2
Murata
C15,C17 4700pF 0603 Chip-capacitor
GRM39X7R472K25V
2
Murata
C16 1uF 0603 Radial-lead
Chip-capacitor
RPE113-X7R-105-K-050
1
Murata
C18 .01uF 0603 Chip-capacitor
GRM39X7R103K25V
1
Murata
C19 10uF 35V
TA NT
TESeriesCap.
PCS6106CT-ND
1
DIGI-K E Y
C24 15pF 0603 Chip-capacitor
GRM39COG150J50V
1
Murata
C13 5600pF 0603 Chip-capacitor
GRM39X7R562K50V
1
Murata
C5,C6 33pF 0603 Chip-capacitor
GRM39COG330J50V
2
Murata
R8 51 0603 ChipResistor
ERJ-3GSYJ510
1
Panasonic
R1 10 0603 ChipResistor
ERJ-3GSYJ100
1
Panasonic
R3,R4 2K 0603 ChipResistor
ERJ-3GSYJ202
2
Panasonic
R12 1K 0603 ChipResistor
ERJ-3GSYJ102
1
Panasonic
R11 2.7K 0603 ChipResistor
ERJ-3GSYJ272
1
Panasonic
R7 3K 0603 ChipResistor
ERJ-3GSYJ302
1
Panasonic
R13 22K 0603 ChipResistor
ERJ-3GSYJ223
1
Panasonic
R10 8.2K 0603 ChipResistor
ERJ-3GSYJ822
1
Panasonic
R6,R9 00603 ChipResistor
ZC0603
2
RCD
L1 5.6nH 0805 Inductor
0805CS-0
5
0X-BC
1
Coilcraft
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
21
ACD2203
Table 21: Evaluation Fixture Parts List continued
ITEM # VALUE SIZE DESCRIPTION PART # QTY VENDOR
L2 68nH 0805 Inductor
0805CS-680X-BC 1
Coilcraft
L3 270nH 0805 Inductor
0805CS-271X-BC 1
Coilcraft
D1 1SV245 Varactor diode
1SV245 1
Toshiba
DT1 4:1 Transformer
ETC4-1-2 1
M/A-COM,Inc.
NorthAmerica
Q1 30V
SMD
S OT- 2 3 TransistorNPN
Darl.
FMMTA13CT-ND 1
DIGI-K EY
X1 4MHZ Crystal
SE2618CT-ND
1DIGI-K EY
22 PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
PACKAGE OUTLINE
Figure 29: S8 Package Outline - 28 Pin SSOP
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
23
ACD2203
NOTES
24
IMPORTANT NOTICE
ANADIGICS,Inc.reservestherighttomakechangestoitsproductsortodiscontinueanyproductatanytimewithoutnotice.
TheproductspecicationscontainedinAdvancedProductInformationsheetsandPreliminaryDataSheetsaresubjectto
changepriortoaproduct’sformalintroduction.InformationinDataSheetshavebeencarefullycheckedandareassumed
tobereliable;however,ANADIGICSassumesnoresponsibilitiesforinaccuracies.ANADIGICSstronglyurgescustomersto
verifythattheinformationtheyareusingiscurrentbeforeplacingorders.
WARNING
ANADIGICSproductsarenotintendedforuseinlifesupportappliances,devices,orsystems.UseofanANADIGICSproduct
inanysuchapplicationwithoutwrittenconsentisprohibited.
ANADIGICS, Inc.
141MountBethelRoad
Warren,NewJersey07059,U.S.A
Tel:+1(908)668-5000
Fax:+1(908)668-5132
URL:http://www.anadigics.com
E-mail:Mktg@anadigics.com
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
ACD2203
ORDERING INFORMATION
ORDER NUMBER TEMPERATURE
RANGE
PACKAGE
DESCRIPTION COMPONENT PACKAGING
ACD2203RS8P1 -40°Cto+85°C RoHSCompliant
28PinSSOP Tape&Reel,3500piecesperreel