Digital Audio Driver with Discrete Deadtime and Protection
Product Summary
VSUPPLY 200 V max.
IO+/- 1 A / 1.2 A typ.
Selectable Deadtime
15 ns, 25 ns, 35 ns, 45 ns typ.
Prop Delay Time 60 ns typ.
Bi-Directional Over-
Current Sensing
Package
Typical Application Diagram
IRS20124(S)PbF
Data Sheet No. PD60240
www.irf.com 1
14-Lead SOIC
Features
• 200 V high voltage ratings deliver up to 1000 W
output power in Class D audio amplifier
applications
• Integrated deadtime generation and bi-directional
over-current sensing simplify design
•Programmable compensated preset deadtime for
improved THD performances over temperature
•High noise immunity
•Shutdown function protects devices from overload
conditions
• Operates up to 1 MHz
• 3.3 V/5 V logic compatible input
<200 V
HO
NC
VS
OCSET 1
OC
VCC
SD
DT/SD
COM
OCSET 2
IN
VB
LO
IRS20124
NC
NC
<20V
<20V
IN
OC
• RoHS compliant
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IRS20124S(PbF)
Symbol Definition Min. Max. Units
VB
High-side floating supply voltage -0.3 220
Vs
High-side floating supply voltage VB-20 VB+0.3
VHO High-side floating output voltage Vs-0.3 VB+0.3
VCC
Low-side fixed supply voltage -0.3 20
VLO
Low-side output voltage -0.3 Vcc+0.3
VIN Input voltage -0.3 Vcc+0.3
VOC OC pin input voltage -0.3 Vcc+0.3
VOCSET1 OCSET1 pin input voltage -0.3 Vcc+0.3
VOCSET2 OCSET2 pin input voltage -0.3 Vcc+0.3
dVs/dt Allowable Vs voltage slew rate - 50 V/ns
PDMaximum power dissipation - 1.25 W
RthJA Thermal resistance, junction to ambient - 100 °C/W
TJJunction temperature - 150
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) - 300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. All currents are defined positive into any lead. The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.
Description
The IRS20124 is a high voltage, high speed power MOSFET driver with internal deadtime and shutdown
functions specially designed for Class D audio amplifier applications.
The internal dead time generation block provides accurate gate switch timing and enables tight deadtime
settings for better THD performances.
In order to maximize other audio performance characteristics, all switching times are designed for immunity
from external disturbances such as VCC perturbation and incoming switching noise on the DT pin. Logic
inputs are compatible with LSTTL output or standard CMOS down to 3.0 V without speed degradation. The
output drivers feature high current buffers capable of sourcing 1.0 A and sinking 1.2 A. Internal delays are
optimized to achieve minimal deadtime variations. Proprietary HVIC and latch immune CMOS technologies
guarantee operation down to Vs= –4 V, providing outstanding capabilities of latch and surge immunities with
rugged monolithic construction.
V
°C
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IRS20124S(PbF)
Note 1: Logic operational for VS equal to -8 V to 200 V. Logic state held for VS equal to -8 V to -VBS.
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. The Vs and COM
offset ratings are tested with all supplies biased at a 15 V differential.
Symbol Definition Min. Max. Units
VB
High-side floating supply absolute voltage Vs+10 Vs+18
VS
High-side floating supply offset voltage Note 1 200
VHO High-side floating output voltage Vs VB
VCC
Low-side fixed supply voltage 10 18
VLO Low-side output voltage 0 VCC
VIN
Logic input voltage 0 VCC
VOC
OC pin input voltage 0 VCC
VOCSET1
OCSET1 pin input voltage 0 VCC
VOCSET2
OCSET2 pin input voltage 0 VCC
T
AAmbient Temperature -40 125 °C
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, CL = 1n F and TA = 25 °C unless otherwise specified. Fig. 2 shows the timing definitions.
Symbol Definition Min. Typ. Max. Units Test Conditions
ton
High & low-side turn-on propagation delay — 60 80 VS=0 V
toff
High & low-side turn-off propagation delay — 60 80 VS=200 V
trTurn-on rise time — 25 40
tfTurn-off fall time — 15 35
tsd
Shutdown propagation delay — 140 200
toc
Propagation delay time from Vs>Vsoc+ to OC — 280 —
OCSET1=3.22 V
OCSET2=1.20 V
twoc min
OC pulse width — 100 —
toc filt
OC input filter time — 200 —
DT1 Deadtime: LO turn-off to HO turn-on (DTLO-HO)
& HO turn-off to LO turn-on (DTHO-LO)
01540 V
DT>VDT1
DT2 Deadtime: LO turn-off to HO turn-on (DTLO-HO)
& HO turn-off to LO turn-on (DTHO-LO) 5V
DT1>VDT> VDT2
DT3 Deadtime: LO turn-off to HO turn-on (DTLO-HO)
& HO turn-off to LO turn-on (DTHO-LO)
DT4 Deadtime: LO turn-off to HO turn-on (DTLO-HO)
& HO turn-off to LO turn-on (DTHO-LO)VDT= VDT4
ns
V
5 25 50
10 35 60
15 45 70 VDT3>VDT>VDT4
VDT2>VDT>VDT3
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IRS20124S(PbF)
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V and TA = 25 °C unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
VIH Logic high input voltage 2.5 — — Vcc=10 V -20 V
VIL Logic low input voltage — — 1.2
VOH High level output voltage, VBIAS – VO— — 1.2
VOL Low level output voltage, VO— — 0.1
UVCC+
Vcc supply UVLO positive threshold 8.3 9.0 9.7
UVCC-
Vcc supply UVLO negative threshold 7.5 8.2 8.9
UVBS+
High-side well UVLO positive threshold 8.3 9.0 9.7
UVBS-
High-side well UVLO negative threshold 7.5 8.2 8.9
IQBS High-side quiescent current — — 1
IQCC Low-side quiescent current — — 4 VDT=Vcc
ILK High-to-low-side leakage current — — 50 VB=VS =200 V
IIN+ Logic “1” input bias current — 3 10 VIN=3.3 V
IIN- Logic “0” input bias current — 0 1.0 VIN=0V
Io+
Output high short circuit current (source) — 1.0 — Vo=0 V, PW<10 µs
Io-
Output low short circuit current (sink) — 1.2 — Vo=15 V, PW<10 µs
VDT1 DT mode select threshold 1 0.8(Vcc) 0.89(Vcc) 0.97(Vcc)
VDT2 DT mode select threshold 2 0.51(Vcc) 0.57(Vcc) 0.63(Vcc)
VDT3 DT mode select threshold 3 0.32(Vcc) 0.36(Vcc) 0.40(Vcc)
VDT4 DT mode select threshold 4 0.21(Vcc) 0.23(Vcc) 0.25(Vcc)
VSOC+
OC threshold in Vs 0.75 1.0 1.25
OCSET1=3.22 V
OCSET2=1.20 V
VSOC-
OC threshold in Vs -1.25 -1.0 -0.75
OCSET1=3.22 V
OCSET2=1.20 V
µA
mA
V
V
A
Io=0 A
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IRS20124S(PbF)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN
OCSET1
DT/SD
OCSET2
OC
COM
LO VCC
NC
VS
HO
VB
NC
NC
IR20124S 14 Lead SOIC (narrow body)
Lead Definitions
Symbol Description
VCC Low-side logic supply voltage
VB High-side floating supply
HO High-side output
VS High-side floating supply return
IN Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO
DT/SD Input for programmable deadtime, referenced to COM. shutdown LO and HO when tied to COM
COM Low-side supply return
LO Low-side output
OC Over-current output (negative logic)
OCSET1 Input for setting negative over current threshold
OCSET2 Input for setting positive over current threshold
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IRS20124S(PbF)
Block Diagram
SD
LEVEL
SHIFTER
UV
DETECT
VB
HO
VS
IN DEAD
TIME
DT/SD
UV
Q
S
R
CURRENT
SENSING
UV
DETECT
DELAY
OC
OCSET1
OCSET2
Vcc
LO
COM
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IRS20124S(PbF)
DT/SD
HO
LO
VSD
TSD
90%
Figure 1. Switching Time Waveform Definitions
Figure 2. Shutdown Waveform Definitions
50% 50%
toff(L)
ton(L)
90%
10%
90%
10%
DT
HO-LO
toff(H)
IN
HO
LO
ton(H)
DTLO-HO
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IRS20124S(PbF)
Figure 4. OC Waveform Definitions
toc filt
HIGH
VS
OC
Vsoct
COM
COM
twoc
VS
OC
VSoc+
tdoc
COM
COM
LO
VSoc-
IN
OCSET1
DT/SD
OCSET2
OC
COM
LO VCC
NC
VS
HO
VB
NC
NC
__
15V
15V
Vsoc+
Vsoc-
10k
OC
Vsoc+
Vsoc-
COM
VS
OC
Figure 5. OC Waveform Definitions
Figure 3. OC Input FilterTime Definitions
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IRS20124S(PbF)
0
40
80
120
160
200
-50 -25 0 25 50 75 100 125
Temperature (oC)
Figure 6A. Turn-On Time
vs. Temperature
0
40
80
120
160
200
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 6B. Turn-On Time
vs. Supply Vo ltag e
Turn-On Delay Time (ns)
Turn-On Delay Time (ns)
Typ.
Max .
0
30
60
90
120
150
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 7B. Turn-Off Time
v s. Supply Voltage
Turn-Off Time (ns)
Typ.
Max .
0
0
0
0
0
0
-50 -25 0 25 50 75 100 125
Temperature (oC)
0
30
60
90
120
150
Turn-Off Time (ns)
Figure 7A. Turn-Off Time
vs. Temperature
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IRS20124S(PbF)
10
20
30
40
50
60
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn-On Rise Time (ns)
Fiure 8 A . Turn-On Rise Ti me
vs.Temperature
10
20
30
40
50
60
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Turn-On Rise Time (ns)
Figure 8 B. Turn -On Rise Time
vs. Supply Vo ltag e
0
10
20
30
40
50
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn-Off Fall Time (ns)
Figur e 9A. Turn-Off Fall Time
vs. Temperature
0
10
20
30
40
50
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Turn-Off Fall Time (ns)
Figure 9 B. Turn -Of f Fall Time
vs. Supply Vo ltag e
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IRS20124S(PbF)
Min .
1
2
3
4
5
10 12 14 16 18 20
VCC Supply Voltage (V)
Input Voltage (V)
Fi gure 10B. Logic "1" Input Voltage
vs. Supply Voltage
Max .
0
1
2
3
4
-50-250 255075100125
Temperatre (oC)
Input Voltage (V)
Figure 11A. Logic "0 " Input Voltage
vs. Tempera ture
Max.
0
1
2
3
4
10 12 14 16 18 20
VCC Supply V oltage (V)
Input Voltage (V)
Figure 11B. Logi c "0" I nput Volta ge
vs. S u
pp
l
y
Vol ta
g
e
Min.
1
2
3
4
5
-50-250 255075100125
Temperature (oC)
Input Voltage (V)
Figure 10A. Logic "1" I nput Vol tage
vs. Temperature
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IRS20124S(PbF)
Max .
-1
0
1
2
3
4
-50-250 255075100125
Temperature (oC)
High Level Output Voltage (V)
Fig ure 12A . High Lev el Ou tp ut
vs. Tempera ture
Max .
0.00
0.05
0.10
0.15
0.20
0.25
-50-250 255075100125
Temperature (oC)
Low Level Output Voltage (V)
Figure 13A. Low Lev el O utput
vs.Tempera ture
Max .
0.00
0.05
0.10
0.15
0.20
0.25
10 12 14 16 18 20
VCC Supply Voltage (V)
Low Level Output Voltage (V)
Figure 13 B. Low Level Output
vs. Supply Voltage
Ma x .
0
1
2
3
4
10 12 14 16 18 20
VCC Supply Voltage (V)
High Level Output Voltage (V
)
Figure 12B. High Level Out put
v s. Supply Vol tage
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IRS20124S(PbF)
Max .
0
50
100
150
200
250
300
-50 -25 0 25 50 75 100 125
Temperature (oC)
Offset Supply Leakage Current (µA)
Figure 14A. Offset Supply Leakage
Current vs. T e mperatu re VB= 200 V
Ma x .
Typ.
-10
10
30
50
70
90
110
50 80 110 140 170 200
VB Boost Voltage (V)
Offset Supply Leakage Current (µA)
F igure 14B. Offset Supply Leakage
Current vs. Supply Volta ge
0.0
0.5
1.0
1.5
2.0
2.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
VBS Supply Current (µA)
Figure 15A. VBS S upply C urren t
vs. Tem
p
erature
0
1
1
2
2
3
10 12 14 16 18 20
VBS Supply Voltage (V)
VBS Supply Current (µA)
Figure 15B. VBS Supply C urrent
vs. Supply Vo ltag e
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IRS20124S(PbF)
Max .
0
2
4
6
8
10
-50 -25 0 25 50 75 100 125
Temperature (oC)
Vcc Supply Current (µA)
Figure 16A. VCC Supply Current
vs. Tempera ture
Ma x .
0
2
4
6
8
10
10 12 14 16 18 20
VCC Supply Voltage (V)
Vcc Supply Current (µΑ)
Figure 16B. VCC Supply Current
vs. S upply Voltage
0
6
12
18
24
30
-50 -25 0 25 50 75 100 125
Temperature (oC)
Logic "1" Input Current (µA)
Fi gure 17A. Logic "1 " Input Current
vs. Temperature
0
6
12
18
24
30
10 12 14 16 18 20
VCC Supply V oltage (V )
Logic "1" Input Current (µA)
Figur e 17B. Logic "1" Input Curr ent
vs. Supp l y Vol t age
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IRS20124S(PbF)
Typ.
Max.
Min.
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
Vc c S u p p l y C u r r e n t (µΑ)
Figure 19. VCC Undervoltage Threshold (+)
vs. Temperature
Typ.
Max.
Min.
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
Vc c S u p p l y C u r r e n t (µΑ )
Figure 20. VCC Undervoltage Threshold (-)
vs. Temperature
Max
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "0" Input Bias Current (µA)
Max
0
1
2
3
4
5
6
10 12 14 16 18 20
Supply Voltage (V)
Logic "0" Input Bias Current (µA)
Figure 18A. Logic "0" Input Bias Current
vs. Temperature
Figure 18B. Logic "0" Input Bias Current
vs. Voltage
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IRS20124S(PbF)
Typ.
0.5
0.7
0.9
1.1
1.3
1.5
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Output Source Current (
Α)
Figure 23. O utput S ource Current
vs. S upp ly Vol ta ge
Ty p.
0.5
0.7
0.9
1.1
1.3
1.5
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Output Sink Current (
Α)
Figure 24. Output Si nk Current
vs. Supply Voltage
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
VBS Supply Current (µA)
Figur e 21. V BS Underv olta ge Threshold (+)
vs. Temperature
6
7
8
9
10
11
-50-25 0 25 50 75100125
Temperature (oC)
VBS Supply Current (µA)
Figur e 22. V BS Undervoltage Threshol d ( -)
vs. Temperature
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IRS20124S(PbF)
Typ.
-15
-13
-11
-9
-7
-5
10 12 14 16 18 20
VBS Floting Supply Voltage (V)
VS Offset Supply Voltage (V)
Figure 25. Maximum VS Negative Offset
vs. S upp ly Vol ta g e
Typ.
Max .
Min.
11
12
13
14
15
16
-50 -25 0 25 50 75 100 125
Temperature (oC)
VDT1 (V)
Figure 26. DT Mode Select Threshold (1)
vs. Tempera ture
Typ.
Max .
Min.
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
VDT2 (V)
Figure 27. DT Mode Select Threshold (2)
vs. Tempera ture
Ty p.
Max .
Min.
3
4
5
6
7
8
-50 -25 0 25 50 75 100 125
Temperature (oC)
VDT3 (V)
Figure 28. DT Mode Select Threshold (3)
vs. Tempera ture
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IRS20124S(PbF)
Typ.
20
28
36
44
52
60
-50 -25 0 25 50 75 100 125
Temperature (oC)
DT
LO-HO (ns)
Figure 30. DT LO Turn-Off to HO TurnOon (3)
vs. Temperature
2.0
2.5
3.0
3.5
4.0
4.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
VDT4 (V)
Figure 29. DT Mode Select Threshold (4)
vs. Temperature
Ty p.
Ma x .
Min .
-1.8
-1.5
-1.2
-0.9
-0.6
-0.3
-50-25 0 255075100125
Temperature (oC)
Negative OC TH (V
)
Figure 32. Negative OC Threshold(-) in VS
vs. Tem
p
erature
Typ.
Ma x .
Min.
0.0
0.4
0.8
1.2
1.6
2.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
Positive OC TH (V)
Figure 31. Positive OC Threshold(+) in VS
vs. Tem
p
erature
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IRS20124S(PbF)
14 0 V
70V
0V
15
25
35
45
55
65
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
Figure 32. IRS20124S vs. Frequency (IRFBC20)
Rgate=33 Ω, VCC=12 V
14 0 v
70v
0v
15
25
35
45
55
65
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
Figure 33. IRS20124S vs. Frequency (IRFBC30)
R
gate=22 Ω, VCC=12 V
14 0 V
70V
0V
15
25
35
45
55
65
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
Figure 34. IRS20124S vs. Frequency (IRFBC40)
Rgate=15 Ω, VCC=12 V
14 0 V
70V
0V
15
25
35
45
55
65
75
1 10 100 1000
Frequency (kHz)
Temperature (
oC)
Figure 35. IRS20124S vs. Frequency (IRFPE50)
Rgate=10 Ω, VCC=12 V
33.34.
35.36.
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IRS20124S(PbF)
Functional description
Programmable Dead-time
The IRS20124 has an internal deadtime generation
block to reduce the number of external components
in the output stage of a Class D audio amplifier.
Selectable deadtime through the DT/SD pin volt-
age is an easy and reliable function, which re-
quires only two external resistors. The deadtime
generation block is also designed to provide a
constant deadtime interval, independent of Vcc
fluctuations. Since the timings are critical to the
audio performance of a Class D audio amplifier,
the unique internal deadtime generation block is
designed to be immune to noise on the DT/SD
pin and the Vcc pin. Noise-free programmable
deadtime function is available by selecting
deadtime from four preset values, which are opti-
mized and compensated.
How to Determine Optimal Deadtime
Please note that the effective deadtime in an actual
application differs from the deadtime specified in
this datasheet due to finite fall time, tf. The
deadtime value in this datasheet is defined as the
time period from the starting point of turn-off on
one side of the switching stage to the starting
point of turn-on on the other side as shown in Fig.
5. The fall time of MOSFET gate voltage must be
subtracted from the deadtime value in the
datasheet to determine the effective dead time of
a Class D audio amplifier.
(Effective deadtime)
= (Deadtime in datasheet) – (fall time, tf)
HO (or LO)
LO (or HO)
tf
Dead-
Ef fect ive dea d- time
10%
10%
90%
Effective Deadtime
A longer deadtime period is required for a MOSFET
with a larger gate charge value because of the
longer tf. A shorter effective deadtime setting is
always beneficial to achieve better linearity in the
Class D switching stage. However, the likelihood
of shoot-through current increases with narrower
deadtime settings in mass production. Negative
values of effective deadtime may cause excessive
heat dissipation in the MOSFETs, potentially
leading to their serious damage. To calculate the
optimal deadtime in a given application, the fall
time (tf)for both output voltages, HO and LO, in
the actual circuit needs to be measured. In
addition, the effective deadtime can also vary with
temperature and device parameter variations.
Therefore, a minimum effective deadtime of 10 ns
is recommended to avoid shoot-through current
over the range of operating temperatures and
supply voltages.
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IRS20124S(PbF)
DT/SD pin
DT/SD pin provides two functions: 1) setting dead-
time and 2) shutdown. The IRS20124 determines
its operation mode based on the voltage applied
to the DT/SD pin. An internal comparator
translates which mode is being used by comparing
internal reference voltages. Threshold voltages for
each mode are set internally by a resistive voltage
divider off Vcc, negating the need of using a precise
absolute voltage to set the mode.
Vcc 0.89xVcc 0.57xVcc 0.36xVcc 0.23xVcc
Shutdown
45nS
35nS
25nS
15nS
Operational Mode
VDT
Dead-time
Deadtime Settings vs VDT Voltage
Design Example
Table 1 shows suggested values of resistance for
setting the deadtime. Resistors with up to 5%
tolerance can be
used if these
listed values are
followed.
Vcc
COM
DT/SD
>0.5mA
R1
R2
IRS20124
Table 1. Suggested Resistor Values for Deadtime
Settings
Shutdown
Since IRS20124 has internal deadtime generation,
independent inputs for HO and LO are no longer
provided. Shutdown mode is the only way to turn
off both MOSFETs simultaneously to protect them
from over current conditions. If the DT/SD pin de-
tects an input voltage below the threshold, VDT4,
the IRS20124 will output 0 V at both HO and LO
outputs, forcing the switching output node to go
into a high impedance state.
Over Current Sensing
In order to protect the power MOSFET, IRS20124
has a feature to detect over-current conditions,
which can occur when speaker wires are shorted
together. The over-current shutdown feature can
be configured by combining the current sensing
function with the shutdown mode via the DT/SD pin.
Load Current Direction in Class D Audio
Application
In a Class D audio amplifier, the direction of the
load current alternates according to the audio in-
put signal. An over current condition can therefore
happen during either a positive current cycle or a
negative current cycle. It should be noted that
External Resistor
Deadtime
mode
R1
(Ω) R2
(Ω)
DT/SD
(V)
DT1 <10k Open 1.00 (Vcc)
DT2 3.3k 8.2k 0.71 (Vcc)
DT3 5.6k 4.7k 0.46 (Vcc)
DT4 8.2k 3.3k 0.29 (Vcc)
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IRS20124S(PbF)
each MOSFET carries a part of the load current
in an audio cycle. Bi-directional current sensing
offers over current detection capabilities in both
cases by monitoring only the low side MOSFET.
Load Current
0
Bi-Directional Current Sensing
IRS20124 has an over-current detection function
utilizing RDS(ON) of the low side switch as a current
sensing shunt resistor. Due to the proprietary HVIC
process, the IRS20124 is able to sense negative
as well as positive current flow, enabling bi-direc-
tional load current sensing without the need for
any additional external passive components.
Direction in MOSFET Current and Load Current
vs
Vsoc+
Vsoc-
COM
~
~~
~~
~
~
~~
~~
~~
~~
~~
~~
~
~
~
(a ) Normal Operation
Condition
(b ) Over- Current in
Positive Load Current
(c ) Over- Current in
Negative Load Current
Vs Waveform in Over-Current Condition
IRS20124 measures the current during the period
when the low side MOSFET is turned on. Under
normal operating conditions, Vs voltage for the low
side switch is well within the trip threshold bound-
aries, VSOC- and VSOC+. In the case of Fig. 9(b) which
demonstrates the amplifier sourcing too much cur-
rent to the load, the Vs node is found below the trip
level, VSOC-. In Fig. 9(c) with opposite current direc-
tion, the amplifier sinks too much current from the
load, positioning Vs well above trip level, VSOC+.
Once the voltage in Vs exceeds the preset thresh-
old, the OC pin pulls down to COM to detect an
over-current condition.
Since the switching waveform usually contains
over/under shoot and associated oscillatory arti-
facts on their transient edges, a 200 ns blanking
interval is inserted in the Vs voltage sensing block
at the instant the low side switch is engaged.
Because of this blanking interval, the OC function
will be unable to detect over current conditions if
the low side ON duration less than 200 ns.
OCSE T1
OCSET2
Vs
LO
OC
+
+
-
-
OR
AND
Simplified Functional Block Diagram of
Bi-Directional Current Sensing
The bi-directional current sensing block has an
internal V level shifter feeding the signal to the
comparator. OCSET1 sets the threshold, and is
given a trip level at VSOC+, which is OCSET1 -V. In
the same way, for a given OCSET2, VSOC- is set at
OCSET2 -V.
www.irf.com 23
IRS20124S(PbF)
External Resistor Network to Set OC Threshold
Vcc
COM
OCSET1
>0.5mA
R3
R4
R5
OCSET2
How to set OC Threshold
The positive and negative trip thresholds for bi-
directional current sensing are set by the voltages
at OCSET1 and OCSET2.
The trip threshold voltages, VSOC+ and VSOC+, are
determined by the required trip current levels, ITRIP+
ITRIP-, and RDS(ON) in the low side MOSFET.
Since the sensed voltage of Vs is shifted up by
2.21 V internally and compared with the voltages
fed to the OCSET1 and OCSET2 pins, the required
value of OCSET1 with respect to COM is
VOCSET1 = VSOC+ + 2.21 V = I x RDS(ON) + 2.21 V
The same relation holds between OCSET2 and VSOC-,
VOCSET2 = VSOC- + 2.21 V = I x RDS(ON) + 2.21 V
In general, RDS(ON) has a positive temperature co-
efficient that needs to be considered when the
threshold level is being set. Please also note that,
in the negative load current direction, the sensing
voltage at the Vs node is limited by the body di-
ode of the low side MOSFET as explained later.
Design Example
This example demonstrates how to use the exter-
nal resistor network to set ITRIP+ and ITRIP- to be
±11 A, using a MOSFET that has RDS(ON) =60 µΩ.
VISET1 = VTH+ + 2.21 V = ITRIP+ x RDS(ON) + 2.21 V =
11 x 60 µΩ +2.21 V = 2.87 V
VISET2 = VTH- + 2.21 V = ITRIP- x RDS(ON) + 2.21 V =
(−11) V 60 µΩ +2.21 V = 1.55 V
The total resistance of resistor network is based
on the voltage at the Vcc and required bias cur-
rent in this resistor network.
Rtotal =R3 + R4 + R5 = Vcc / Ibias
= 12 V / 1 µΑ = 12 k Ω
The expected voltage across R3 is Vcc- VISET1
= 12 V - 2.87 V=9.13 V. Similarly, the voltages
across R4 is VSOC+ - VSOC- = 2.87 V - 1.55 V
=1.32 V, and the voltage across R5 is VISET2= 1.55
V respectively.
R3 =9.13 V/ Ibias = 9.13 kΩ
R4 =1.32 V/ Ibias = 1.32 kΩ
R5 =1.55 V/ Ibias = 1.55 kΩ
Choose R3= 9.09 kΩ R4=1.33 kΩ, R5=1.54 k Ω
from E-96 series.
Consequently, actual threshold levels are
VSOC+ =2.88 V gives ITRIP+ = 11.2 A
VSOC- =1.55 V gives ITRIP- = -11.0 A
Resisters with 1% tolerances are recommended.
www.irf.com 24
IRS20124S(PbF)
OC Output Signal
The OC pin is a 20 V open drain output. The OC
pin is pulled down to ground when an over current
condition is detected. A single external pull-up
resistor can be shared by multiple IRS20124 OC
pins to form the ORing logic. In order for a micro-
processor to read the OC signal, this information
is buffered with a mono stable multi vibrator to
ensure 100 ns minimum pulse width.
Because of unpredictable logic status of the OC
pin, the OC signal should be ignored during power
up/down.
Limitation from Body Diode in MOSFET
When a Class D stage outputs a positive current,
flowing from the Class D amp to the load, the body
diode of the MOSFET will turn on when the drain
to source voltage of the MOSFET become larger
than the diode forward drop voltage. In such a
case, the sensing voltage at the Vs pin of the
IRS20124 is clamped by the body diode. This
means that the effective RDS(ON) is now much lower
than expected from RDS(ON) of the MOSFET, and
the Vs node my not able to reach the threshold
to turn the OC output on before the MOSFET fails.
Therefore, the region where body diode clamping
takes a place should be avoided when setting VSOC-
.
For further application information for gate driver
IC please refer to AN-978 and DT98-2a. For fur-
ther application information for class D applica-
tion, please refer to AN-1070 and AN-1071.
Body Diode in MOSFET Clamps vs Voltage
VS - COM
ID
Body Diode Clamp OCSET2 should be
set in this region
}
0
www.irf.com 25
IRS20124S(PbF)
01-6019
01-3063 00 (MS-012AB)
14 Lead SOIC (narrow body)
Case Outline
www.irf.com 26
IRS20124S(PbF)
CARRIER TAPE DIMENSION FOR 14SOICN
Code Min Max Min Max
A 7.90 8.10 0.311 0.318
B 3.9 0 4.10 0.153 0.1 61
C 15.70 16.30 0.618 0.641
D 7.40 7.60 0.291 0.299
E 6.40 6.60 0.252 0.260
F 9.40 9.60 0.370 0.378
G 1 .50 n/a 0.05 9 n/a
H 1.50 1.60 0.059 0.062
M etr ic Im p erial
REEL DIMENSIONS FOR 14SOICN
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 22.40 n/a 0.881
G 18.50 21.10 0.728 0.830
H 16.40 18.40 0.645 0.724
M etr ic Im p erial
E
F
A
C
D
G
A
BH
N
OT E : CO NTROLLING
D
IMENSION IN MM
LOADED TAPE FEED DIR ECTION
A
H
F
E
G
D
B
C
Tape & Reel
14-Lead SOIC
www.irf.com27
IRS20124S(PbF)
SO-14 package is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at IR's Web Site http://www.irf.com
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel:(310) 252-7105
Data and specifications subject to change without notice. 12/4/2006
14-Lead SOIC IRS20124SPbF
14-Lead SOIC Tape & Reel IRS20124STRPbF
LEADFREE PART MARKING INFORMATION
Lead Free Released
Non-Lead Free
Released
Part number
Date code
IRSxxxxx
YWW?
?XXXX
Pin 1
Identifier
IR logo
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
P
?MARKING CODE
ORDER INFORMATION