FEBRUARY 1995 VOLUME V NUMBER 1
The LTC1410 Converts
Twelve Bits at 1.25MSPS
IN THIS ISSUE . . .
The LTC
1410 Converts Twelve
Bits at 1.25MSPS ................ 1
Dave Thomas
Editor’s Page ....................... 2
Richard Markell
LTC in the News .................. 2
DESIGN FEATURES
New LTC1266 Switching
Regulator Provides High
Efficiency at 10A Loads...... 3
Greg Dittmer
The LTC1267 Dual Switching-
Regulator Controller ........... 7
Randy G. Flatness
The LTC1265: a New, High-
efficiency Monolithic Buck
Converter .......................... 10
San-Hwa Chee
The LT
1175: Negative,
Low-Dropout Regulator ..... 13
Carl Nelson
The LTC1451 Family:12-Bit,
Rail-to-Rail, Micropower DACs
in SO-8 Packages .............. 15
Hassan Malik and Jim Brubaker
Power Factor Correction ... 17
Dale Eagar
Power for Pentium™ ......... 19
Craig Varga
PCMCIA Socket Voltage
Switching Matrix with
SafeSlot™ Protection ........ 22
Doug La Porte
DESIGN INFORMATION
LTC’s RS232 Transceivers
for DTE–DCE Switching .... 24
Gary Maulding
LTC Provides Two Crucial
Components for
HDSL Systems ................... 26
Kevin R. Hoskins
DESIGN IDEAS
.................................... 29–36
(complete list on page 29)
New Device Cameos ........... 39
by Dave Thomas
Introduction
Until now, designers of high-speed
data acquisition systems have had to
make some tough compromises when
picking 1MSPS 12-bit A/D con-
verters. The parts with the best
performance were hybrids in large
packages, which consumed 1W or
more and cost $100.00 or more. A few
manufactures offered monolithic so-
lutions, but they didn’t perform as
well as hybrids. Some of the mono-
lithic parts had poor AC performance
but good DC performance, whereas
others had good AC and inferior DC
performance. Now, LTC has a mono-
lithic, 1.25MSPS 12-bit ADC with the
performance of the best hybrids but
with the power, size, and cost of a
monolithic part. Some of the key fea-
tures of this new device include:
1.25 MSPS throughput
Low-power—150mW typical from
5V supplies
NAP and SLEEP power-shutdown
modes
Small package—28-pin SSOP
Not only does this device match or
beat the performance of expensive
hybrids, it also offers some new fea-
tures they never had, like true
differential inputs and two power
shutdown modes. These features can
help improve the performance of cur-
rent data-acquisition systems and
open up new applications that were
not previously possible because of
high power consumption.
High-Accuracy
Conversions: AC or DC
Figure 1 is a block diagram of the
LTC1410. A high-performance dif-
ferential sample-and-hold circuit
combined with an extremely fast,
successive-approximation ADC and
an on-chip reference deliver a previ-
ously unattainable combination of
AC and DC performance. A digital
interface allows easy connection to
microprocessors, FIFOs, or DSPs.
The DC specifications include a
0.8LSB maximum differential linear-
ity error and 0.5LSB maximum
integral linearity error guaranteed
over temperature. The gain of the
ADC is held nearly constant
over temperature with an on-chip
10ppm/°C curvature-corrected
bandgap reference.
The sample-and-hold circuit sets
the dynamic performance of the ADC.
The LTC1410 has a wide bandwidth
and very low distortion differential
sample-and-hold. Specifications in-
clude total harmonic distortion of
84dB for a 625kHz input and an
input bandwidth of 30MHz for the
sample-and-hold.
High-Impedance Inputs
Speed Data Acquisition
High speed ADCs are often used to
sample many different channels in
multiplexed systems. The LTC1410 is
well suited to these applications. The
high-impedance inputs are easy to
switch through a MUX without
continued on page 37
, LTC and LT are registered trademarks and SafeSlot is a trademark of Linear Technology Corporation.
Pentium is a trademark of Intel Corporation.
LINEAR TECHNOLOGY
LINEAR TECHNOLOGY
LINEAR TECHNOLOGY
2
Linear Technology Magazine • February 1995
Remembering the Six-Transistor Radio
by Richard Markell
EDITOR'S PAGE
have articles that detail several cir-
cuits for powering the Pentium™
microprocessor.
Also, we begin a series of articles
on power-factor correction. We
present Design Information on com-
ponents for HDSL and on RS232
transceivers for DTE-DCE switching.
Our Design Ideas section is, as usual,
overflowing.
How many years has it been since
the demise of the six-transistor ra-
dio? How many of us at LTC remember
our electronics class in junior high
school or even high school? I have
fond memories of walking around the
neighborhood with my crystal radio,
testing water pipes, fences, metal-
framed buildings, and the tree next to
my window, to see which would give
the best reception.
Nerd visions of the past? Perhaps,
but I think winding a tuning coil on a
used toilet paper roll teaches one
more than calling up the “coil” icon in
Crystal RadioBuilder for Windows™.
The six-transistor radio (Figure 1)
was not only a great tool for learning
electronics, but it taught many “teen-
ers” how to troubleshoot and, perhaps,
even how to think. I hope today’s kids
have their equivalent of the six-tran-
sistor radio. ★★★
Our lead article highlights the
LTC1410, a new 12-bit, 1.25MSPS
analog-to-digital converter specifi-
cally designed for both AC and DC
accuracy. This part consumes only
150 milliwatts from a ±5 volt supply.
We also introduce three new digital-
to-analog converters, the LTC1451,
LTC1452, and LTC1453. These parts
bring 12-bit performance, single-sup-
ply operation, and rail-to-rail voltage
output performance using a
three-wire serial interface to the ever-
growing LTC product line.
The LTC1472, a complete V
CC
and
VPP PCMCIA switch-matrix IC is the
subjects of a feature article. This is-
sue also introduces several new
switching regulators. The LTC1266 is
a synchronous, step-down switching
regulator that can drive two external,
N-channel MOSFETs. The LTC1266
can achieve high efficiency at loads to
10A or more. The LTC1265 is a step-
down converter in a 14-pin SOIC
package, capable of operating at fre-
quencies to 700kHz, that can supply
output currents up to 1.2 Amps. The
LTC1265 requires only 160 micro-
amps of quiescent current, which
decreases to only 5 microamps in
shutdown conditions.
The LTC1267 is a dual switching-
regulator controller with extremely
wide, 4V-to-40V input operating range
and reduced supply currents. This
dual controller provides efficiencies
better than 90% in a space-saving
28-pin SSOP package.
Additional new LTC products fea-
tured in this issue include the LT1175,
a negative low-dropout regulator. We
Figure 1. The classic six-transistor radio
Windows is a trademark of Microsoft Corporation.
LTC in the News
Linear Technology Reports
Record Quarterly Sales,
Increases Quarterly Dividend
Thanks to your support of Linear
Technology’s products, our sales
reached a record $62.1 million for
the second quarter of fiscal 1995,
ended January 1, 1995—an increase
of 29% over the same quarter last
year. Net income for the quarter was
$19.2 million, an increase of 47%
over last year. A quarterly cash divi-
dend of $0.07 was paid on February
15, 1995 to shareholders of record on
January 27, 1995.
In its November 7th, 1994 issue,
Forbes magazine again named Lin-
ear Technology one of its “Best 200
Small Public Companies in America.”
This marks the fifth year in a row that
the Company has been included.
This year Linear Technology ranked
97th, up from 102nd last year.
In a separate story in the same
issue, entitled “Small Footprints,
Big Impressions,” Forbes pointed
out that LTC is one of only two
companies on the list to have a
capitalized value greater than a bil-
lion dollars. Among 200 companies
in the listing, LTC is 40th in sales
growth, seventh in net income, and
fifth in market value. All in all, a
very impressive showing.
LTC received the Emerging Com-
pany Award for 1995 from the Silicon
Valley Chapter of Association for
Corporate Growth.
Linear Technology Magazine • February 1995
3
New LTC1266 Switching Regulator
Provides High Efficiency at 10A Loads
Introduction
The new LTC1266 is a synchro-
nous, stepdown switching-regulator
controller that can drive two exter-
nal, N-channel MOSFET switches.
The superior performance of N-chan-
nel MOSFETs enables the LTC1266
to achieve high efficiency at loads of
10A or more with few additional com-
ponents. Burst Mode™ operation
provides high efficiency at light
loads—efficiency is greater than 90%
for loads from 10mA to 10A. The
ability to provide 10A at high effi-
ciency is critical for supplying power
to Pentium™ applications.
The LTC1266 is based on the
LTC1148 architecture, and has most
of the features of this successful prod-
uct, including constant off-time,
current-mode architecture with au-
tomatic Burst Mode operation. As
with the LTC1148, current-mode con-
trol provides excellent line and load
transient response, inherent short-
circuit protection, and controlled
startup current with minimal voltage
overshoot. Pin-selectable shutdown
reduces the DC supply current to 40
by Greg Dittmer
microamps. The LTC1266 also has a
pin-selectable phase option, which
allows it to drive a P-channel top-side
switch, instead of an N-channel, as in
the case of the LTC1148.
Other new features of the LTC1266
not available in the LTC1148 include
an on-chip low-battery comparator,
pin-defeatable Burst Mode, a wider
voltage supply range (3.5V to 20V),
1% load regulation, and a higher
maximum frequency of 400kHz.
N-Channel versus P-Channel
The key to the LTC1266’s ability to
drive large loads at high efficiencies is
its ability to drive both top-side and
bottom-side N-channel MOSFETs.
The rest of the LTC1148 family con-
trollers require a P-channel MOSFET
for the top-side switch. For load cur-
rents above about 5 amps, there are
few P-channel MOSFETs available
that can do the job at reasonable
efficiencies.
The superiority of N-channel
MOSFETs over P-channels is due to
the lower R
DS(ON)
and lower gate ca-
pacitance achievable in the N-chan-
nel parts. The lower R
DS(ON)
results
from the higher mobility of electrons,
the majority carrier in N-channel de-
vices, compared to holes, the majority
carrier in P-channel devices. To com-
pensate for the higher R
DS(ON)
of the
P-channel, the channel width is usu-
ally made larger, resulting in higher
gate capacitance. Efficiency is in-
versely proportional to both R
DS(ON)
and gate capacitance. Higher R
DS(ON)
decreases efficiency due to higher I
2
R
losses and limits the maximum cur-
rent the MOSFET can handle without
exceeding thermal limitations; higher
gate capacitance increases losses due
to the increased charge required to
switch the MOSFETs on and off dur-
ing each switching cycle. Even with
these performance advantages, the
N-channel MOSFETs are generally
cheaper than P-channel.
Driving N-Channel MOSFETs
If N-channels are so superior to P-
channels, why are the rest of the
LTC1148 family of synchronous con-
trollers designed to drive P-channels?
The answer is that P-channels have a
distinct advantage—simplicity of the
gate drive. This is clear when com-
paring the waveforms in Figures 1a
and 1b. Because of the negative
threshold of the P-channel, the gate
potential must decrease below the
source (which is at V
IN
) by at least
V
GS(ON)
to turn it on. Hence, the top-
side MOSFET can be gated between
the available supply rail, V
IN
, and
ground.
On the other hand, driving an N-
channel top-side MOSFET isn’t so
straightforward. When the top-side
MOSFET is turned on, the source is
pulled up to V
IN
. Because the N-chan-
nel has a positive threshold voltage,
the gate must be above the source by
at least V
GS(ON)
. Thus, the top-side
drive must swing between ground
DESIGN FEATURES
Figure 1a. Drive requirements for all N-channel MOSFET buck converter
1266_1a.eps
V
OUT
SWITCH NODE
= M1 DRAIN
V
IN
0
V
IN
C
OUT
M2
N-CH
M1
P-CH
BOTTOM-SIDE
DRIVE
TOP-SIDE
DRIVE
+
TOP-SIDE
DRIVE
V
IN
V
GS
0
Figure 1b. Drive requirements for complementary MOSFET buck converter
1266_1b.eps
V
OUT
SWITCH NODE
= M1 SOURCE
V
IN
0
0
V
IN
C
OUT
M2
N-CH
M1
N-CH
BOTTOM-SIDE
DRIVE
TOP-SIDE
DRIVE
+
TOP-SIDE
DRIVE
V
IN
+ V
GS
V
GS
V
IN
Burst Mode is a trademark of Linear Technology Corporation.
4
Linear Technology Magazine • February 1995
Figure 2c. Waveforms for charge pump circuit
in Figure 2b
and V
IN
+ V
GS(ON)
. This requires a
second, higher supply rail equal to at
least V
IN
+ V
GS(ON)
.
There are two ways to obtain this
higher rail. The most straightforward
way is if a higher rail is already avail-
able, as is the case in most desktop
systems that have 12V supplies. This
configuration is shown in Figure 2a.
Note that the Power V
IN
input to the
LTC1266 is dedicated to powering the
internal drivers and is separate from
the main supply input. The Power V
IN
voltage cannot exceed 18V (20V max),
limiting the input voltage to
18 V
GS(ON)
. For a converter with
logic-level MOSFETs, this limits V
IN
to about 14V. The Power V
IN
voltage
must also meet its minimum require-
ment of V
IN
+ V
GS(ON)
(about 10V for a
5V to 3.3V converter) in order not to
burn up the high-side MOSFET due
to insufficient conductance at larger
output loads.
If this higher rail is not available, a
charge-pump circuit can be used to
pump V
IN
to the required level, as
shown in Figure 2b. During the off
cycle, when M2 is on, capacitor C1 is
charged to V
IN
through D1. Power V
IN
and the gate of the bottom-side MOS-
FET are therefore at V
IN
. When the
on-cycle commences, the internal
driver places the charge-pump ca-
pacitor voltage across the gate-source
of M1 and, as the source rises to V
IN
,
V
GS
remains constant at V
IN
. There
will be a small reduction of V
GS
as
some charge is transferred from the
charge-pump capacitor to the gate
capacitance of M1, although, for a
charge-pump capacitor of 0.1 micro-
farad or larger, this reduction is almost
negligible. During the on cycle, the
voltage at the LTC1266 Power V
IN
pin
rises to twice V
IN
. Since the absolute
maximum at this pin is 20V, this
limits V
IN
to 9V in this circuit con-
figuration. A higher V
IN
(about 13V) is
allowable if C1 is charged from a fixed
5V source. For voltages above 13V, a
P-channel top-side switch must be
used, since in this configuration, the
gate drive needs only to swing from
V
IN
to ground. Multiple P-channel
MOSFETs may need to be paralleled,
however, to meet the load
requirements.
Figures 3, 4, and 5 show the three
basic circuit configurations for the
LTC1266. The all-N-channel, exter-
nal Power V
IN
circuit shown in Figure
3 is a 3.3V/5A surface-mount con-
verter. The current-sense resistor
value is chosen to set the maximum
current to 5A, according to the for-
mula I
OUT
= 100mV/R
SENSE
. With V
IN
+
+
1266_3a.eps
LTC1266-3.3
D1
MBRS140T3
C
IN
100µF
20V
OSCON
× 2
V
IN
3.5V TO 14V
V
OUT
3.3V/5A
PINV
PWR V
IN
PWR V
IN
TDRIVE
BINHBINH
V
IN
C
T
I
TH
C
C
3300pF
0.1µF
C
T
130pF
R
C
470R
SENSE
0.02
L
5µH
1000pF
C
OUT
330µF
10V
× 2
SENSE
3
2
1
4
5
6
7
8
14
15
16
13
12
11
10
9
LB
OUT
PGND
BDRIVE
Si9410DY
Si9410DY
LB
IN
SGND
SHDN SHDN
NC
SENSE
+
Figure 3a. All N-channel 3.3V/5A regulator with external power V
IN
DESIGN FEATURES
1266_2c.eps
SWITCH NODE
= M1 SOURCE
POWER V
IN
0
V
IN
2V
IN
0
V
IN
0
V
IN
CAPACITOR
VOLTAGE
LOAD CURRENT (A)
90
85
80
95
100
EFFICIENCY (%)
5
1266_3b.eps
0.01 0.1 1
V
IN
= 5V
Figure 2a. Simplified schematic of all N-
channel converter with additional supply
voltage (Power V
IN
> V
IN
+ V
GS(ON)
)
V
IN
POWER V
IN
> V
IN
+ V
GS(ON)
M2
M1
BOTTOM
DRIVE
TOP
DRIVE
1266_2a.eps
VIN
POWER VIN C1
D1
M2
M1
BOTTOM
DRIVE
TOP
DRIVE
1266_2b.eps
Figure 2b. Simplified schematic of all
N-channel converter with charge pump
Figure 3b. Efficiency for Figure 3a’s circuit
Linear Technology Magazine • February 1995
5
Figure 4a. All N-channel single-supply 5V to 3.3 V/10 amp regulator
Figure 5a. Low-dropout 3.3V/3A complementary MOSFET regulator
+
+
1266_5a.eps
LTC1266-3.3
D1
MBRS140T3
C
IN
100µF
25V
V
IN
3.5V TO 18V
V
OUT
3.3V
3A
PINV
PWR V
IN
TDRIVE
BINHBINH
V
IN
C
T
I
TH
C
C
3300pF
0.1µF
C
T
250pF
R
C
1k R
SENSE
0.033
L
15µH
1000pF
C
OUT
220µF
10V
× 2
SENSE
3
2
1
4
5
6
7
8
14
15
16
13
12
11
10
9
LB
OUT
PGND
BDRIVE
Si9430DY
Si9410DY
LB
IN
SGND
SHDN SHDN
NC
SENSE
+
Figure 5b. Efficiency for Figure 5a’s circuit
= 5V, the 5µH inductor and 130pF
timing capacitor provide an operat-
ing frequency of 175kHz and a ripple
current of 1.25A. The V
GS(ON)
of the
Si9410 N-channel MOSFETs is 4.5V;
thus the minimum allowable voltage
at the external Power V
IN
is V
IN
MAX
+ 4.5V. At the other end, Power V
IN
should be kept under the maximum
safe level of 18V, limiting V
IN
to 18V
4.5V = 13.5V.
Figure 4 shows an LTC1266 in the
charge-pump configuration designed
to provide a 3.3V/10A output. The
Si4410s are new logic-level, surface-
mount, N-channel MOSFETs from
Siliconix that provide a mere 20
milliohms of on-resistance at V
GS
=
4.5V, and thus provide a 10A solution
with minimal components. The effi-
ciency plot shows that the converter
still is close to 90% efficient at 10A.
Because the charge-pump configura-
tion is used, the maximum allowable
V
IN
is 18V/2 = 9V. See the LTC1266
data sheet for a charge-pump circuit
that allows input voltages above 9V.
Due to the high AC currents in this
circuit, we recommend low ESR
OS-CON input/output capacitors to
maintain efficiency and stability.
Figure 5 shows the conventional P-
channel, topside switch circuit
configuration for implementing a
3.3V/3A regulator. The P-channel
configuration allows the widest pos-
sible supply range of the three basic
circuit configurations, 3.5V to 18V,
and provides extremely low dropout,
exceeding that of most linear regula-
tors. The low dropout results from the
LTC1266’s ability to achieve a 100%
duty cycle when in P-channel mode.
In N-channel mode, the duty cycle is
DESIGN FEATURES
+
+
1266_4a.eps
LTC1266-3.3
D1
MBRS340T3
C
IN
100µF
10V
OS-CON
× 3
V
IN
3.5V TO 9V
V
OUT
3.3V
10A
PINV
PWR V
IN
TDRIVE
BINHBINH
V
IN
C
T
I
TH
C
C
3300pF
0.1µF
1.0µF
C
T
220pF
R
C
470R
SENSE
0.01
L
5µH
1000pF
C
OUT
330µF
10V
× 3
SENSE
3
2
1
BAT85
BAT85
4
5
6
7
8
14
15
16
13
12
11
10
9
LB
OUT
PGND
BDRIVE
Si4410DY
Si4410DY
LB
IN
SGND
SHDN SHDN
NC
SENSE
+
Figure 4b. Efficiency for Figure 4a’s circuit
LOAD CURRENT (A)
90
85
80
95
100
EFFICIENCY (%)
10
1266_4b.eps
0.01 0.1 1
V
IN
= 5V
LOAD CURRENT (A)
90
85
80
95
100
EFFICIENCY (%)
3
1266_5b.eps
0.01 0.1 1
V
IN
= 5V
6
Linear Technology Magazine • February 1995
Figure 6. Efficiency comparison: Burst Mode
enabled/disabled
on continuous switching in the pri-
mary to transfer energy to the
secondary, disabling Burst Mode
guarantees this switching, indepen-
dent of the primary load.
Figure 7 shows the difference be-
tween LTC1266 operation at light
loads, with Burst Mode enabled and
disabled. When Burst Mode is en-
abled (Figure 7a), the lower limit of
the current-trip threshold (25mV/
R
SENSE
) prevents the current com-
parator from regulating a load below
this value. The output will slowly rise
until the hysteretic voltage compara-
tor trips, at which time sleep mode
commences. During sleep mode, both
MOSFETs are turned off and the out-
put capacitor supplies the load
current until it discharges to the lower
threshold of the voltage comparator.
When this lower threshold is reached,
the main loop turns on briefly again
to recharge the capacitor.
When Burst Mode is disabled, the
lower limit of the current trip thresh-
old is allowed to go below zero (instead
of 25mV/R
SENSE
). This allows the cur-
rent comparator to regulate the output
voltage down to zero load without
having to rely on the voltage com-
parator for regulation. At zero load,
the inductor-current waveform will
be symmetrical around zero, so that
the average current equals zero. Dur-
ing the negative current phase of the
cycle, current is reversing, that is,
flowing out of the output capacitor
back through the inductor to ground
or to the supply, in order to keep the
limited to less than 100% to ensure
proper startup, and thus the dropout
voltage for the all N-channel convert-
ers is slightly higher.
The three application circuits dem-
onstrate the fixed 3.3V version of the
LTC1266. The LTC1266 is also avail-
able in fixed 5.0V and adjustable
versions. All three versions are avail-
able in 16-pin narrow SOIC and DIP
packages.
Burst Mode Inhibit
The LTC1266 also provides a func-
tion to disable Burst Mode with a
CMOS logic high applied to pin 4.
When observing the performance of a
regulator at light loads with and with-
out Burst Mode (see Figure 6), the
performance enhancement that Burst
Mode offers is immediately obvious.
So why disable Burst Mode? There
are certain conditions when the dis-
advantages of Burst Mode outweigh
the advantages, and it is useful to
have an easy way to disable this fea-
ture. The most common reasons for
disabling Burst Mode are: 1) at light
loads, the long burst cycles cause
operating frequencies in the audio
range, causing audible noise;
2) Burst Mode puts certain restric-
tions on the maximum ESR of the
output capacitor, since excessive ESR
(relative to the sense resistor) may
falsely trigger Burst Mode. If Burst
Mode is disabled, this restriction can
be relaxed, at the expense of effi-
ciency; and 3) If the circuit uses
auxiliary winding(s), which depend
average current zero. The voltage com-
parator is not required when Burst
Mode is disabled; Therefore, to en-
sure that it doesn’t interfere with the
current comparator operation, the
upper threshold is raised up to take it
out of the picture; however, it is still
present to prevent the output voltage
from overshooting.
Low-Battery Comparator
The LTC1266 also includes a low-
battery comparator. This comparator
compares the voltage applied to pin
13 to an internal 1.25V reference and
provides an open-drain output at pin
14. This 1.25V reference is dedicated
to the low-battery comparator and is
active even when the rest of the chip
is shut down or nonfunctional due
to low supply voltage. This compara-
tor can operate down to a supply
voltage of 2.5V, whereas the rest of
the chip stops functioning at
about 3.5V.
Conclusion
The new LTC1266 synchronous
stepdown regulator controller is the
first LTC synchronous controller with
the ability to exploit the superior per-
formance of N-channel MOSFETs to
maximize efficiency and provide a
low-cost, compact solution for con-
verters. The extra features also
provided in this product—Burst Mode
inhibit and a low-battery compara-
tor—make it ideal in a wide variety of
applications.
DESIGN FEATURES
Figure 7b. Inductor current and output
voltage waveforms: Burst Mode disabled
Figure 7a. Inductor current and output
voltage waveforms: Burst Mode enabled
LOAD CURRENT (A)
80
70
60
90
100
EFFICIENCY (%)
5
1266_6.eps
0.01 0.1 1
BURST ENABLED
BURST INHIBITED
1266_7a.eps
25mV
R
SENSE
V
OUT
I
L
I
LOAD
VOLTAGE COMP-
HYSTERISIS
1266_7b.eps
V
OUT
I
L
I
LOAD
Linear Technology Magazine • February 1995
7
The LTC1267 Dual Switching-
Regulator Controller Operates
from High Input Voltages
Introduction
The LTC1267 dual switching regu-
lator controller is the latest addition
to Linear Technology’s family of bet-
ter than 90% efficient step-down DC/
DC converters. The LTC1267 features
an extremely wide, 4V-to-40V input
operating-voltage range and reduced
supply currents. The quiescent cur-
rent is a low 250 microamps, and
current in shutdown mode drops to
less than 20 microamps. The combi-
nation of low supply currents and
high input-voltage capability is ideal
for battery-powered applications that
require high-voltage AC wall
adapters.
LTC offers two versions of the
LTC1267, both in space-saving 28-
pin SSOP packages. The LTC1267
provides fixed output voltages of 3.3V
and 5V with individual shutdown
capability. The adjustable LTC1267-
ADJ provides two user-programmable
output voltages, set by external re-
sistive dividers.
High Efficiency with
Dual Output Voltages
To boost efficiency, a unique
EXT V
CC
pin on the LTC1267 (also
present on the single output LTC1159)
allows the MOSFET drivers and con-
trol circuitry to be powered from an
external source, such as the output
LTC1142 LTC1142HV LTC1142HV-ADJ LTC1143 LTC1267 LTC1267-ADJ
Minimum input voltage 4V 4V 4V 4V 5V 5V
Maximum input voltage (Abs Max) 16V 20V 20V 16V 40V 40V
Output voltage 3.3V & 5V 3.3V & 5V (2) ADJ 3.3V & 5V 3.3V & 5V (2) ADJ
Maximum switching frequency 250kHz 250kHz 250kHz 400kHz 400kHz 400kHz
MOSFET gate-drive voltage VIN VIN VIN VIN EXT VCC EXT VCC
Synchronous? YES YES YES NO YES YES
Package 28 SSOP 28 SSOP 28 SSOP 16 SOIC 28 SSOP 28 SSOP
Table 1. Dual-output switching-regulator controllers
DESIGN FEATURES
1267_1.eps
LTC1267
28-PIN SSOP
PNP SWITCH + LDO
DUAL LEVEL SHIFT
CONST
OFF-TIME
CONTROLLER
3.3V
V
IN
V
CC
SHDN3
3.3V OUT
SHDN5
5V OUT
MASTER SHDN
EXT V
CC
CONST
OFF-TIME
CONTROLLER
5V
4.5V
LDO
of the regulator itself. Obtaining con-
trol and driver power from V
OUT
improves efficiency at high input volt-
ages, since the resulting current
drawn from V
IN
is scaled by the duty
cycle of the regulator. During start-
up and short-circuit conditions,
operating power is supplied by an
internal 4.5V low-dropout regulator.
This regulator automatically turns
off when the EXT V
CC
pin rises above
4.5V. Figure 1 is a simplified block
diagram of the control circuitry.
This 28-pin controller shares the
same high performance, current-
mode architecture and Burst Mode™
Figure 1. Simplified block diagram, LTC1267
Figure 2. LTC1267 efficiency versus output
current of Figure 3 circuit
OUTPUT CURRENT
60
70
80
90
100
EFFICIENCY (%)
1A 2A
1267_2.eps
1mA 10mA 100mA
LTC1267
V
IN
= 12V
5V SECTION
LTC1267
V
IN
= 12V
3.3V SECTION
by Randy G. Flatness
8
Linear Technology Magazine • February 1995
DESIGN FEATURES
+
+
+
++ +
1000pF 1000pF
1N4148
1N4148
PDRIVE3
SENSE+3
SENSE–3
SGND3 C
T3
I
TH3
I
TH5
C
T5
SGND5
NGATE5
SENSE–5
SHDN3
SENSE+5
PGATE5
SHDN5
NGATE3
PGATE3
PDRIVE5
V
CC3
EXT V
CC
V
IN
V
CC
CAP3 CAP5
MASTER
SHDN V
CC5
PGND5PGND3
LTC1267
C
T5
270pF
711 9 10 15 16 20 22
R
C5
1k
C
C3
3300pF C
C5
3300pF
C
T3
270pF
R
C3
1k
0.15µF
0.1µF
123
827 26 28 21
25
24
17
18
19
23
4
5
14
13
12
6
V
OUT5 
5V/2A
C
OUT5
220µF
10V
× 2
R
SENSE5
50m
Q3
P-CH
Si9435DY
L2
33µH
D2
MBRS140T3
Q4
N-CH
Si9410DY
0.1µF
3.3µF
C
IN5
100µF
50V
33µF
Q1
P-CH
Si9435DY
Q2
N-CH
Si9410DY
0V = RUN
>2V = SHUTDOWN 0V = RUN
>2V = SHUTDOWN
D1
MBRS140T3
C
OUT3
220µF
10V
× 2
L1
20µH
R
SENSE3
50m
V
OUT3
3.3V/2A
5.5V < V
IN
< 28V
C
IN3
100µF
50V
0.15µF
1267_3.eps
R
SENSE
,:KRL SL-C1-1/2-R050J
L1:COILTRONICS CTX20-4
L2:COILTRONICS CTX33-4
KRL (603) 668-3210
COILTRONICS (407) 241-7876
Figure 3. LTC1267 dual output 3.3V and 5V high-efficiency regulator
+
+
+
++ +
1000pF 1000pF
1N4148
1N4148
PDRIVE1
SENSE+1
SENSE–1
SGND1 C
T1
I
TH1
I
TH2
C
T2
SGND2
PGND2
SENSE–2
SHDN1
SENSE+2
PGATE2
NGATE2
NGATE1
PGATE1
PDRIVE2
V
CC1
EXT V
CC
V
IN
V
CC
CAP1 CAP2
MASTER
SHDN V
CC2
V
FB2
V
FB1
LTC1267-ADJ
C
T2
270pF
14 10 8 9 15 16 20 19
R
C1
1k
C
C1
3300pF C
C2
3300pF
C
T1
270pF
R
C1
1k
0.15µF
0.1µF
123
727 26 28
100pF
21
25
24
17
18
23
22
4
5
13
12
11
6
V
OUT2 
5V/2A
C
OUT2
220µF
10V
× 2
R
SENSE2
50m
P-CH
Si9435DY
L2
33µH
D2
MBRS140T3
N-CH
Si9410DY
0.1µF
3.3µF
C
IN2
100µF
50V
33µF
P-CH
Si9435DY
N-CH
Si9410DY
0V = RUN
>2V = SHUTDOWN
D1
MBRS140T3
C
OUT1
220µF
10V
× 2
L1
20µH
R
SENSE1
40m
R2
100k
1%
R2 
150k
1%
R1
49.9k
1%
R1
52.3k
1%
V
OUT1
3.6V/2.5A
5.5V < V
IN
< 28V
C
IN1
100µF
50V
0.15µF
100pF
1267_4.eps
R
SENSE1
,: KRL SL-C1-1/2-R040J
R
SENSE2
,: KRL SL-C1-1/2-R050J
L1:COILTRONICS CTX20-4
L2:COILTRONICS CTX33-4
KRL (603) 668-3210
COILTRONICS (407) 241-7876
Figure 4. LTC1267 dual, adjustable, high-efficiency regulator circuit. Output voltages set at 3.6V and 5V
Linear Technology Magazine • February 1995
9
DESIGN FEATURES
Typical Applications
Fixed Output 3.3V
and 5V Converter
A fixed LTC1267 application cir-
cuit creating 3.3V/2A and 5V/2A is
shown in Figure 3. The operating
efficiency, shown in Figure 2, exceeds
90% for both the 3.3V and 5V sec-
tions. The 3.3V section of the circuit
in Figure 3 comprises the main switch
Q1, synchronous switch Q2, induc-
tor L1, and current shunt R
SENSE3
.
The 5V section is similar and com-
prises Q3, Q4, L2, and R
SENSE5
. Each
current-sense resistor (R
SENSE
) moni-
tors the inductor current and is used
to set the output current according to
the formula I
OUT
= 100mV/R
SENSE
.
Advantages of current control include
excellent line and load transient
rejection, inherent short-circuit pro-
tection, and controlled startup
currents. Peak inductor currents for
L1 and L2 are limited to 150mV/
R
SENSE
or 3.0A. The EXT V
CC
pin is
connected to the 5V output, increas-
ing efficiency at high input voltages.
The maximum input voltage is lim-
ited by the MOSFETs and should not
exceed 28V.
Adjustable Output
3.6V and 5V Converter
The adjustable output LTC1267-
ADJ shown in Figure 4 is configured
as a 3.6V/2.5A and 5V/2A converter.
The resistor divider composed of R1
and R2 sets the output voltage ac-
cording to the formula V
OUT
= 1.25V
(1 + R2/R1). The input voltage range
for this application is 5.5V to 28V.
Conclusion
The LTC1267 adds even more ver-
satility to Linear Technology’s family
of high-efficiency step-down regula-
tor controllers. Providing for up to
40V input voltage, the LTC1267
allows the use of higher voltage wall
adapters. The 28-pin SSOP package
and associated external components
make dual output voltage, high-effi-
ciency DC-to-DC conversion feasible
in the extremely small board space
available in today’s portable
electronics.
Description
Both regulator blocks in the
LTC1267 use a constant off-time cur-
rent-mode architecture. This results
in a power supply that has very high
efficiency over a wide load current
range, fast transient response, and
very low dropout. The LTC1267 is
ideal for applications that require 3.3V
and 5V to be implemented with the
highest conversion efficiencies over a
wide load current range in a small
board space. The LTC1267-ADJ has
two externally adjustable outputs,
which allow remote load sensing and
user-customized output voltages.
Each regulator section employs a
pair of external, complementary
MOSFETs and a user-programmable
current sense resistor for setting the
operating current level to optimize
performance for each application. A
master shutdown pin turns off both
main outputs and the 4.5V LDO. Both
outputs in the LTC1267 have indi-
vidual shutdown capability, whereas
the LTC1267-ADJ has a shutdown
LTC1142HV or LTC1142HV-ADJ can
be used.) At low input voltages, the
internal 4.5V low-dropout regulator
stays in regulation with only a 5V
input voltage, extracting the maxi-
mum possible energy from the battery
pack.
All members of the LTC1142/
LTC1267 family are capable of 100%
duty cycle, providing very low drop-
out operation (lower than that of most
linear low-dropout regulators), and
all have built-in current limiting. As
the input voltage on the LTC1267
drops, the loop extends the on-time
for the P-channel switch (off-time is
constant), thereby keeping the in-
ductor ripple current constant.
Eventually the on-time extends so far
that the P-channel MOSFET is on at
DC or 100% duty cycle. Load and line
regulation are excellent for a wide
variety of conditions, including
making the transition from Burst
Mode™ operation to continuous-
mode operation.
operation as the LTC1142HV (see the
comparison in Table 1). The LTC1267
automatically switches to Burst
Mode™ operation at low output cur-
rents to maintain greater than 90%
efficiency over two decades of load
current range. The wide operating
range is illustrated by the typical
efficiency curve of Figure 2. Battery
life is extended by providing high
efficiencies at load currents from a
few milliamps (when the device is in
standby or sleep modes) to Amps (un-
der full power conditions).
pin for only one of its two outputs.
The higher input-voltage capabil-
ity of the LTC1267 is required by
battery-powered systems that use
many cells in series to provide more
power and longer battery life for high-
performance portable systems. For
12-cell and larger applications, the
AC adapter voltage can be as high as
30V, well below the 40V maximum of
the LTC1267, allowing operation di-
rectly from the AC adapter. (If the
application uses an AC adapter volt-
age of 18V or less, the dual output
All members of the LTC1142/LTC1267
family are capable of 100% duty cycle,
providing very low dropout operation
lower than that of most linear low-dropout
regulators and all have built-in current limiting
10
Linear Technology Magazine • February 1995
The LTC1265: a New, High-Efficiency
Monolithic Buck Converter
Introduction
The LTC1265 is a 14-pin SOIC
stepdown converter (also available in
a DIP package), capable of operating
at frequencies up to 700kHz. High-
frequency operation permits the use
of a small inductor for size-sensitive
applications. The LTC1265 has an
internal 0.3 (at a supply voltage of
10V) P-channel power MOSFET
++
L1
*
33µH
V
IN
5.4V TO 12V
PWR V
IN
PWR V
IN
LTC1265-5
SW
PGND
SGND
NC
1000pF
SENSE
+
10
2
6
7
14
131
12 D1
MBRS130LT3
11
8
9
SHUTDOWN
V
IN
I
TH
SENSE
1265_1.eps
130pF
C
IN††
68µF
20V 0.1µF
R
SENSE**
0.1
C
OUT
220µF
10V
V
OUT
5V/1A
*COILTRONICS CTX33-4
**KRL SL-C1-OR100J
†
AVX TPSE227K010
††
AVX TPSE686k020
1k
5C
T
3900pF
COILTRONICS 407-241-7876
KRL/BANTRY 603-668-3210
Figure 1. High-efficiency step-down converter
DESIGN FEATURES
LOAD CURRENT (A)
0.01
70
EFFICIENCY (%)
75
80
85
90
100
0.10 1.00
1265_2.eps
95
VIN = 6V VOUT = 5V
VIN = 9V
L = 33µH
VOUT = 5V
RSENSE = 0.1
CT = 130pF
Figure 2. Efficiency versus load current
FREQUENCY (kHz)
0
0
SWITCHING CURRENT (mA)
1.0
2.0
3.0
4.0
200
1265_3.eps
400
5.0
5.5
4.5
3.5
2.5
1.5
0.5
600 800
V
IN
= 12V
V
IN
= 9V
V
IN
= 6V
Figure 3. Gate charge losses versus frequency
The LTC1265, like the LTC1147, is
a current-mode DC-to-DC converter
with Burst Mode™ operation. The
current-mode architecture gives the
LTC1265 excellent load and line regu-
lation. Burst Mode results in high
efficiency with both high and low load
currents. The LTC1265 comes in three
versions: the LTC1265-5 (5V output),
the LTC1265-3.3 (3.3V output), and
the LTC1265 (adjustable). All ver-
sions operate down to an input voltage
of 3.5V and up to an absolute maxi-
mum of 13.5V.
Efficiency
Figure 1 shows a typical LTC1265-5
application circuit. The efficiency
curves for two different input volt-
ages are shown in Figure 2. Note that
the efficiency for a 6V input exceeds
90% over a load range from less than
10mA to 850mA. This makes the
LTC1265 attractive for all battery
operated products and efficiency-
sensitive applications.
High-Frequency Operation
Although the LTC1265 is capable
of operating at frequencies up to
700kHz, the highest efficiency is
achieved at an operating frequency of
about 200kHz. As the frequency in-
creases, losses due to the gate charge
of the P-channel power MOSFET
increase (see Figure 3). In space-
sensitive applications, high fre-
quency operation allows the use of
smaller components at the cost of
four to five efficiency points.
The LTC1265 uses a
constant off-time, current-
mode architecture. This
results in a power supply
that has very high
efficiency over a wide
load-current range
switch, which is capable of supplying
up to 1.2A of output current. With no
load, the converter requires only
160µA of quiescent current; this de-
creases to a mere 5µA in shutdown
conditions. In dropout mode, the in-
ternal P-channel power MOSFET
switch is turned on continuously (at
DC), thereby maximizing the life of
the battery source. The part is pro-
tected from output shorts by its
built-in current limiting. In addition
to the features already mentioned,
the LTC1265 incorporates a low-
battery detector.
by San-Hwa Chee
Linear Technology Magazine • February 1995
11
DESIGN FEATURES
Figure 4. Short-circuit and start-up response
of the LTC1265
OUTPUT
SHORTED
VOUT
1V/DIV
SHORT
CIRCUIT
STIMULUS
Figure 5. Load transient response
850mA
50mA
0
TOP TRACE: LOAD CURRENT
BOTTOM TRACE: AC COUPLED
OUTPUT VOLTAGE (50mV/DIV)
Figure 6. High-efficiency 5V to 3.3V converter
+
L1*
47µH
1k
V
IN
5V
PWR V
IN
PWR V
IN
LTC1265-3.3
SW
PGND
SGND
SHUTDOWN SHDN
NC
SENSE
+
2
3
5
6
7
14
113
12
D1
MBRS130LT1
11
10
9
8
V
IN
4LB
IN
LB
OUT
C
T
I
THR
SENSE
1265_6.eps
3900pF
270pF
0.1µFC
IN
100µF
10V 0.1**
+
C
OUT††
220µF
10V
V
OUT
3.3V
1A
1000pF
*COILCRAFT D03316-473
**KRL SL-C1-OR100J
†
AVX TAJD100K010
††
AVX TAJD226K010
COILCRAFT 708-639-6400
KRL/BANTRY 603-668-3210
Figure 7. Efficiency versus load current
LOAD CURRENT (mA)
70
75
90
85
80
95
100
EFFICIENCY (%)
1000
1265_7.eps
1 10 100
L1 = 47µH
V
OUT
= 3.3V
R
SENSE
= 0.1
C
T
= 270pF
Figure 8. 2.5mm-high, 5V-to-3.3V converter (500mA output current)
+
L1*
18µH
1k
V
IN
5V
PWR V
IN
PWR V
IN
LTC1265-3.3
SW
PGND
SGND
SHUTDOWN SHDN
NC
SENSE
+
2
3
5
6
7
14
113
12
D1
MBRS0520LT1
11
10
9
8
V
IN
4LB
IN
LB
OUT
C
T
I
THR
SENSE
1265_8.eps
3300pF
51pF
0.1µFC
IN
15µF
10V × 2 0.20**
+
C
OUT††
22µF
6.3V 
× 2
V
OUT
3.3V
500mA
1000pF
*SUMIDA CLS62-180
**KRL SL-C1-OR200J
†
AVX TAJB155K010
††
AVX TAJB225K06
SUMIDA 708-956-0666
KRL/BANTRY 603-668-3210
Constant Off-Time
Architecture
The LTC1265 uses a constant off-
time, current-mode architecture. This
results in a power supply that has
very high efficiency over a wide
load-current range, fast transient re-
sponse, and very low dropout
characteristics. The off-time is set by
an external capacitor, and is con-
stant whenever the output is in
regulation. When the output is not in
regulation, the off-time is inversely
proportional to the output voltage.
By using a constant off-time scheme,
the inductor’s ripple current is pre-
dictable and well controlled under all
operating conditions, making the se-
lection of the inductor much easier.
The inductor’s peak-to-peak ripple
current is inversely proportional to
the inductance in continuous mode.
If a lower ripple current is desired, a
larger inductor can be used for a
given value of external capacitor.
12
Linear Technology Magazine • February 1995
DESIGN FEATURES
powered-on or recovering from a short
circuit. This is achieved by making
the off-time inversely proportional to
the output voltage when the output is
still in the process of reaching its
regulated value. When the output is
shorted to ground, the off-time is
extended long enough to prevent in-
ductor current run-away. When the
short is removed, the output capaci-
tor begins to charge and the off-time
gradually decreases. Note the absence
of overshoot when the output comes
out of a short-circuit, as shown in
Figure 4. The initial power-up wave-
form is similar.
In addition, the LTC1265 has ex-
cellent load-transient response. When
the load current drops suddenly, the
feedback loop responds quickly by
turning off the internal P-channel
switch. Sudden increases in output
current will be met initially by
the output capacitor, causing the
output voltage to drop slightly. Tight
control of the inductor’s current, as
mentioned above, means that out-
put-voltage overshoot is virtually
eliminated (see Figure 5).
Typical Applications
5V-to-3.3V Converter
Figure 6 shows the LTC1265 con-
figured for 3.3V output with 1A
output-current capability. This cir-
cuit operates at a frequency of 100kHz.
Figure 7 is the efficiency plot of the
Figure 10. Positive (+3.5 to 7.5V) to negative (5V) converter
LOAD CURRENT (mA)
70
75
90
85
80
95
EFFICIENCY (%)
500
1265_9.eps
1 10 100
L1 = 18µH
V
OUT
= 3.3V
R
SENSE
= 0.20
C
T
= 50pF
100% Duty Cycle
in Dropout Mode
When the input voltage decreases,
the switching frequency decreases.
With the off-time constant, the on-
time is increased to maintain the
same peak-to-peak ripple current in
the inductor. When the input-to-out-
put voltage differential drops below
1.5V, the off-time is reduced. This
prevents the operating frequency from
dropping below 20kHz as the regula-
tor approaches dropout. As the input
voltage drops further, the P-channel
switch is turned on for 100% of the
cycle. The dropout voltage is gov-
erned by the switch resistance, load
current, and current-sense resistor.
Good Start-Up
and Transient Behavior
The LTC1265 exhibits excellent
start-up behavior when it is initially
circuit. At a load current of 100mA,
the efficiency is at 92%; the efficiency
falls to 82% at a 1A output.
2.5mm Typical-Height
5V-to-3.3V Regulator
Figure 8 shows the schematic for a
very thin 5V-to-3.3V converter. For
the LTC1265 to be able to source
500mA output current and yet meet
the height requirement, a small-value
inductor must be used. The circuit
operates at a high frequency (500kHz
typically), increasing the gate charge
losses. Figure 9 is the efficiency curve
for this application.
Positive-to-Negative Converter
Besides converting from a positive
input to positive output, the LTC1265
can be configured to perform a posi-
tive-to-negative conversion. Figure
10 shows the schematic for this
application.
Conclusion
The LTC1265, with its low dropout
and high efficiency, is ideal for
battery-operated products and effi-
ciency-sensitive applications. In
addition, its ability to operate at high
frequencies allows the use of
small inductors for size-sensitive
applications.
+
+
L1*
47µH
1k
V
IN
3.5V TO 7.5V
PWR V
IN
PWR V
IN
LTC1265-5
SW
PGND
SGND
SHUTDOWN
NC
SENSE
+
2
3
5
6
7
14
113
12
D1
MBRS130LT3
TP0610L
SHUTDOWN
11
10
9
8
V
IN
4LB
IN
LB
OUT
C
T
I
THR
SENSE
1265_10.eps
2200pF
220pF
C
OUT††
100µF/10V
0.1µF
C
IN
22µF
25V 
× 2V
OUT
–5V
R
SENSE**
0.1
100k
1000pF
†
AVX TPSD226K025
††
AVX TPSD106K010
*L1 SELECTION
MANUFACTURER PART NO.
COILTRONICS CTX50-4
COILCRAFT D03316-473
DALE LPT4545-500LA
SUMIDA CD75-470
**KRL SL-C1-OR100J
V
IN
(V) I
OUT (MAX)
(mA)
3.5 360
4.0 430
5.0 540
6.0 630
7.0 720
7.5 740
Figure 9. Efficiency versus load current
Linear Technology Magazine • February 1995
13
Figure 1a. Typical LT1175 circuit
+
+
1175_1a.eps
SENSE
GND
LT1175-5
SHDN
OUT
SHUTDOWN
LOGIC
INPUT
C
OUT
0.1µF
5V/500mA
I
LIM2
I
LIM4
OPTIONAL INPUT CAPACITOR.
NEEDED ONLY IF LT1175 IS REMOTE
FROM INPUT SUPPLY CAPACITOR.
> 2V OR < –2V TO
TURN REGULATOR ON
The LT1175: Negative, Low-Dropout
Regulator Complements
LT1121/LT1129 Series
Introduction
The LT1175 is a micropower, nega-
tive, low-dropout regulator that can
supply up to 500mA load current. It
is intended for regulating negative
voltages between3.8V and20V, with
input voltages up to30V. Several
new design techniques make the
LT1175 easy to use and very tolerant
of variations in the quality and size of
the output capacitor. A low-dropout
configuration, using an NPN pass
transistor, gives the LT1175 the lin-
ear dropout characteristics of a large
area FET design but with much
smaller die area.
Figure 1a shows the basic configu-
ration of the LT1175. In addition to
the three terminals needed for a
simple regulator, it has an output
Sense pin, a Shutdown pin, and two
current-limit-set pins (I
LIM
). The total
pin count is seven, allowing two pins
on the 8-pin SO or DIP packages to be
connected internally to the die-at-
tach paddle. This gives much lower
thermal resistance, allowing higher
power dissipation in the regulator.
For even higher power dissipation,
the LT1175 is available in the 5-pin,
surface-mount TO-220 package. The
adjustable version of the part is shown
in Figure 1b. Both I
LIM
pins are inter-
nally connected to the input pin when
the 5-pin package is used.
In the adjustable version, the Sense
pin allows custom selection of output
voltage, with an external divider set
to generate 3.8V at the Sense pin. The
fixed 5V version uses the Sense pin to
give true Kelvin connections to the
load or to drive an external pass tran-
sistor for higher output currents. A
separate Sense pin also allows for a
new loop compensation technique
described in more detail later.
Shutdown
The Shutdown pin is especially
configured to be driven from either
positive-voltage logic or with nega-
tive-only logic. Forcing the Shutdown
pin two volts either above or below
the ground pin will turn the regulator
“on.” This makes it simple to connect
directly to positive logic signals for
active-low shutdown. If no positive
voltages are available, the Shutdown
pin can be driven below the ground
pin to turn the regulator “on.” When
left open, the Shutdown pin will de-
fault low to a regulator “on” condition.
For all voltages below the absolute
maximum ratings, the shutdown pin
draws only a few microamperes of
current.
In shutdown conditions, the
LT1175 draws only about 10 micro-
amps. Special circuitry is used to
minimize increases in shutdown cur-
rent at high temperatures, but a slight
increase is seen above 125°C. One
option not taken was to actively pull
down on the output during shut-
down. This is normally a good thing
when the regulator is used by itself,
but it prevents the user from shutting
down the regulator when a second
source of output power is connected
to the LT1175 output. If active output
pulldown is needed in shutdown
conditions, this can be added exter-
nally with a few simple components.
Better Anti-Saturation
The NPN bipolar pass transistor
used in the LT1175 gives small die
area with low saturation resistance,
but without precautions, this could
cause quiescent supply current to be
very high under certain conditions.
When the regulator input voltage is
too low to maintain a regulated out-
put, the pass transistor is driven hard
by the error amplifier as it tries to
maintain regulation. The current
drawn by the driver transistor (Q2 in
Figure 3) could be tens of milliam-
peres with little or no load on the
output. This was the case for older IC
designs that did not actively limit
driver current when the power tran-
sistor saturated. The LT1175 uses a
new anti-saturation technique that
prevents high driver current, yet al-
lows the power transistor to approach
its theoretical saturation limit. Using
parallel feedback to the base of the
driver and the error amplifier
controls operating points for the anti-
saturation circuitry much more
precisely and achieves good loop sta-
bility. Very little increase in quiescent
current is seen as the regulator en-
ters the dropout condition.
Figures 2a and 2b, respectively,
show the dropout and quiescent-
operating-current characteristics of
the LT1175. Note that the new anti-
saturation circuitry keeps the dropout
Figure 1b. Higher power LT1175 circuit:
Adjustable LT1175 is available in TO-220
package
DESIGN FEATURES
+
+
1175_1b.eps
SENSE
GND
LT1175-ADJ
SHDN
NC
OUT
INPUT
R1
383k
R2
221k
C
OUT
0.1µF
–6V
500mA
by Carl Nelson
14
Linear Technology Magazine • February 1995
INPUT VOLTAGE (V)
0
50
100
150
INPUT CURRENT (µA)
10
1175_2b.eps
0 4682
FIXED 5V PART
I
LOAD
= 0
DROPOUT REGION
(EXCESS CURRENT
IS MINIMAL)
OUTPUT
BEGINS
REGULATING
HERE
LOAD CURRENT (A)
0
0.2
0.4
0.6
MINIMUM INPUT TO OUTPUT VOLTAGE (V)
0.5
1175_2a.eps
0 0.2 0.3 0.40.1
Figure 2a. LT1175 dropout characteristics
+
1175_3.eps
OUTPUT
Q2
R
C††
0.3
–V
IN
R2
R1
C
OUT
ESR
Q1***Q3**
R
N
R
LIM
C
F
*
REF
A1
LT1175
LOAD
* AC FEEDFORWARD PATH
** NEGATIVE DC FEEDBACK AT LIGHT LOADS
*** POWER TRANSISTOR
† CURRENT LIMIT SENSE RESISTOR
†† PARASITIC COLLECTOR RESISTANCE
Figure 3. Block diagram of LT1175 illustrating
new design techniques for internal frequency
compensation and the error amplifier designs
characteristics close to the optimal
resistive shape, with very little excess
quiescent current in dropout condi-
tions.
Current Limit
The LT1175 uses two I
LIM
pins to
set the current limit at 200, 400, 600,
or 800mA. This allows users to select
current limits tailored to specific
applications. Fixed-current-limit de-
signs often result in short circuit
currents three to ten times higher
than full load current, and this can
create problems with input overload
or excessive power dissipation in a
faulted load. Current limit is 200mA
with both I
LIM
pins floating. I
LIM2
adds
200mA of available current and I
LIM4
adds 400mA. The LT1175 is guaran-
teed to be “blowout proof,” regardless
of the current-limit setting. Internal
power limiting (also known as
foldback current limiting) and ther-
mal shutdown protect the device from
destructive junction temperatures.
An Improved Feedback Loop
Several new regulator design tech-
niques make the LT1175 extremely
tolerant of output capacitor varia-
tions. Like most low-dropout designs,
which use a collector or drain of the
power transistor to drive the output
node, the LT1175 uses the output
capacitor as part of the overall loop
compensation. This generally requires
the output capacitor to have a mini-
mum value of 1–100µF, a maximum
ESR (effective series resistance) of
0.1–1, and a minimum ESR in the
range of 0.03–0.3. These restric-
tions usually could be met only with
good-quality solid-tantalum capaci-
tors. Aluminum capacitors have
problems with high ESR unless much
higher values of capacitance (physi-
cally large capacitors) are used.
Ceramic or film capacitors have too
low an ESR, which makes the capaci-
tance/ESR zero frequency too high to
maintain phase margin in the regu-
lator. Even with optimum capacitors,
loop-phase margin was very low in
previous designs when output cur-
rent was low. These problems led to a
new design technique for the LT1175
error amplifier and internal frequency
compensation, as shown in Figure 3.
A conventional regulator loop con-
sists of error amplifier A1, driver
transistor Q2, and power transistor
Q1. Added to this basic loop are sec-
ondary loops generated by Q3 and C
F
.
A DC negative feedback current fed
into the error amplifier through Q3
and R
N
results in very low overall loop
gain at light load currents. This is not
a problem because very little gain is
needed at light loads. The combina-
tion of low gain at light loads and the
DC feedback moves the parasitic pole
frequency at Q2’s base out in fre-
quency. The combination of these
two effects dramatically improves loop
phase margin at light loads, and
makes the loop tolerate large ESR in
the output capacitor. With heavy
loads, loop phase and gain are not
nearly as troublesome, and the
negative feedback could degrade regu-
lation. The logarithmic behavior of
the base-emitter voltage of Q1 re-
duces Q3’s negative feedback at heavy
loads to prevent poor regulation.
In a conventional design, even with
the nonlinear feedback, poor loop
phase margin would occur at me-
dium to heavy loads if the ESR of the
output capacitor fell below 0.3. This
condition can occur with ceramic or
film capacitors, which often have
ESRs under 0.1. The user is forced
to add a resistor in series with the
capacitor to guarantee loop stability.
The LT1175 uses a unique AC feed-
forward technique to eliminate this
problem. C
F
is a conventional feed-
forward capacitor, often used in
regulators to cancel the pole formed
by the output capacitor. It would nor-
mally be connected from the regulated
output node to feedback node at the
R1–R2 junction, or to an internal
node on the amplifier, as shown in
Figure 3. In this case, however, it is
connected to the internal structure of
the power transistor. RC is the
unavoidable parasitic collector resis-
tance of the power transistor. Access
to the node at the bottom of RC is
available only in monolithic struc-
tures, where Kelvin connections can
be made to the NPN buried-collector
layer. The loop now responds as if RC
were in series with the output capaci-
tor, and good loop stability is achieved
continued on page 38
DESIGN FEATURES
Figure 2b. LT1175 quiescent operating
current
Linear Technology Magazine • February 1995
15
The LTC1451, LTC1452, and LTC1453:
12-Bit, Rail-to-Rail, Micropower DACs
in SO-8 Packages
The LTC1451 has an onboard ref-
erence of 2.048V and a nominal output
swing of 4.095V. It operates from a
single 4.5V to 5.5V supply dissipat-
ing 2mW (I
CC
typical = 400µA).
The LTC1452 is a multiplying DAC
with no onboard reference and a full-
scale output of twice the reference
input. It operates from a single sup-
ply that can range from 2.7V to 5.5V.
It dissipates 1.125 mW (I
CC
typical =
225µA) at a 5V supply and a mere
0.5mW (I
CC
typical = 160µA) at a 3V
supply.
The LTC1453 has a 1.22V onboard
reference and a convenient full scale
of 2.5V. It can operate on a single
supply with a wide range of 2.7V to
5.5V. It dissipates 0.75mW (I
CC
typi-
cal = 250µA) with a 3V supply.
DESIGN FEATURES
+
1451_1.eps
CONTROL
LOGIC
POWER ON
RESET
REFERENCE
LTC1451: 2.048V
LTC1452: EXT REF
LTC1453: 1.22V
12-BIT
SHIFT
REGISTER
DAC
REGISTER
2
DIN
3
CS/LD
4
DOUT
1
CLK
7VOUT
6REF
5GND
8VCC
12-BIT
DAC
LTC1451
LTC1452
LTC1453
Figure 1. Block diagram, LTC1451 family
Flexible, Micropower
DACs Offer True
Rail-to-Rail Performance
The LTC1451, LTC1452, and
LTC1453 are complete 12-bit, single-
supply, rail-to-rail, voltage-output
digital-to-analog converters. They
include an output buffer amplifier
and a Serial-Peripheral Interface (SPI)
compatible, three-wire serial inter-
face; a data-output pin makes daisy
chaining possible. These DACs are
guaranteed to have a DNL error of
less than 0.5LSB. The typical DNL
error is about 0.2LSB. A built-in
power-on reset clears the output to
zero scale. The output amplifier can
swing to within 5 millivolts of V
CC
when unloaded and can source or
sink 5mA at a 4.5V supply. These
DACs come in 8-pin PDIP and SO-8
packages.
1451_2.eps
MICROPROCESSOR
D
IN
CLK
CS/LD
V
REF
V
CC
2.7V TO 5.5V
0.1µF
OUTPUT
0V TO 2.5V
V
OUT
LTC1453
1.22V
GND
D
OUT
TO NEXT DAC FOR
DAISY-CHAINING
Figure 2. The 3V LTC1453 is SPI compatible
and communicates with both 5V and 3V
processors
Circuit Topology
Easy-to-Use,
Space-Saving Serial I/O
Figure 1 shows a block and pin
diagram of the LTC1451. The three
digital inputs, CLK, DIN, and CS/LD
are TTL-level compatible. Data is
shifted into the input shift register,
MSB first, on the rising edge of CLK.
When CS/LD is high, the DAC regis-
ters are loaded from the shift register
and the CLK is disabled internally to
prevent noise. Data is latched in the
DAC registers on the falling edge of
CS/LD, and is shifted out MSB first
through the D
OUT
pin. Multiple DACs
can be daisy chained by connecting
the D
OUT
pin of one DAC to the DIN
pin of the next. The digital inputs can
swing to 5V, even when the DAC’s V
CC
is at 3V. This allows more flexibility
when interfacing to the DAC. Figure 2
shows how these DACs are typically
used with a 3V or 5V supply.
by Hassan Malik
and Jim Brubaker
16
Linear Technology Magazine • February 1995
Patented Architecture
Guarantees Excellent DNL
Figure 3 shows a block diagram of
the DAC core. The LTC1451 family
uses a proprietary architecture first
used in the LTC1257 and described
in more detail in Volume III, Number
3 of Linear Technology. In this archi-
tecture, the MSBs are decoded using
a resistor ladder and the LSBs are
decoded using a proprietary ampli-
fier input stage. It requires no laser
trimming and is inherently mono-
tonic, with a typical DNL error of
0.2LSB.
Rail-to-Rail Output
The output amplifier is connected
in a gain-of-two configuration, which
means that the output at full scale is
twice the reference voltage connected
to the resistor ladder. The references
on both the LTC1451 and LTC1453
can be overdriven to a higher voltage
to increase the full-scale output. The
opamp can swing to within 5mV of
V
CC
when unloaded, giving these
rail-to-rail DACs an exceptional out-
put-swing capability. The op amp can
source or sink 5mA, even at a 4.5V
supply, and has an output imped-
ance of 50 when swinging to the
DESIGN FEATURES
+
1451_4.eps
IN
1µF
CLK
VCC VREF
LTC1453 OUT 45k 5k
1k Q1
2N3440
RS
10IOUT
VLOOP = 3.3V ~ 30V
10k500
CLK
DIN
CS/LD
CLK
DIN
CS/LD
4N28
3 × OPTO-
ISOLATORS 3.3V
LT1077
3k
90k 5k
FROM
OPTO-
ISOLATED
INPUTS
DIN
CS/LD
OUT
LT1121-3.3
Figure 4. Opto-isolated 4–20 milliamp process controller
+
R
R
RESISTOR
STRING
VOUT
0V TO 4.095V–LTC1451
0V TO 2X V REF –LTC1452
0V TO 2.50V–LTC1453
2.048V–LTC1451
EXTERNAL–LTC1452
1.22V–LTC1453
1451_3.eps
REF
rails. It has a wide input common-
mode range that extends from ground
to V
CC
1.5V. The output glitch at
midscale is 20nV-s and the digital
feedthrough is a negligible 0.15nV-s.
A Wide Range of Applications
Some of the applications for this
family include digital calibration, in-
dustrial process control, automatic
test equipment, cellular telephones,
and portable, battery-powered appli-
cations, where low supply current is
essential.
Loop-Powered 4–20mA
Process Controller
Figure 4 shows how to use an
LTC1453 to make an opto-isolated
digitally controlled 4–20mA process
controller. The controller circuitry,
including the opto-isolation, is pow-
ered by the loop voltage, which can
have a wide range of 3.3V to 30V. The
1.22V reference output of the
LTC1453 is used for the 4mA offset
current and V
OUT
is used for the digi-
tally controlled 0–16mA current. R
S
is a sense resistor and the op amp
modulates the transistor Q1 to pro-
vide the 4–20mA current through this
resistor. The potentiometers allow for
offset and full-scale adjustment. The
control circuitry dissipates well un-
der the 4mA budget at zero scale.
Conclusions
The LTC1451, LTC1452, and
LTC1453 are the most flexible, mi-
cropower, stand-alone DACs that offer
true rail-to-rail performance. This
flexibility, along with the tiny SO-8
package, allows these parts to be used
in a wide range of applications where
size, power, DNL, and single-supply
operation are important.
Figure 3. Proprietary op amp input stage
ensures excellent DNL
Linear Technology Magazine • February 1995
17
TIME
CAPACITOR CURRENT
pfca_1c.eps
Power Factor Correction: Part I
Introduction
The term “power-factor correction”
(PFC) refers to the reduction of the
harmonic content, and/or the align-
ing of the phase angle of incoming
current so that it is in phase with the
line voltage required to operate an
electronic device. PFC is considered
very beneficial to the environment
because it makes more efficient use
of existing power plants. PFC is sub-
ject to legislation and policy making
throughout the industrialized world.
The European standard (IEC 555)
sets maximum permissible values for
the harmonics of the input line cur-
rent that may be produced by
equipment meeting these standards.
By 1996, TV sets and other consumer
equipment will be required to incor-
porate PFC. The benefit of PFC is
realized as energy savings seen
throughout the power distribution
system. With PFC implemented
throughout the industry, fewer new
power plants will need to be built to
meet projected energy demands. Con-
sumers will pay more for “poor power
factor” power at the power meter; it is
hoped that, as a result, they will
choose the beneficial “green” or PFC-
equipped devices to save energy
dollars.
Equipment that uses DC voltages
derived from the AC line generally
have a poor power factor because of
the capacitive input to the DC power
section. The waveforms in Figure 1
show the “evils” of capacitor input
power supplies. Figure 1a represents
the input line voltage; Figure 1b rep-
resents a “nice” waveform of current
as drawn by a resistive load; Figure
1c represents the harmonic-rich
current waveform drawn by a capaci-
tive-input power supply.
How PFC Performs Its Magic
The trick behind PFC is simple:
make the input look as much like a
resistor as possible. Resistors have
the perfect power factor (unity). From
the power utility company’s viewpoint,
unity power factor is the load of choice,
a load that allows their power distri-
bution system to operate at its
maximum efficiency.
Emulating a Resistor
A resistor is emulated at the input
port of a PFC by loading the incoming
power line with a programmable cur-
rent sink that is programmed with a
voltage proportional to the instanta-
neous line voltage (Figure 2a.) The
programmable current sink is the
input characteristic of a “lossless
energy converter” (detailed in Figure
2b). The energy converter intercepts
instantaneous power from the power
line, which is the product of the
instantaneous voltage and the in-
stantaneous current entering the
energy converter. All energy inter-
cepted by the energy converter is
delivered to the load device.
Although the devices detailed in
Figures 2a and 2b emulate resistors,
they provide no means of controlling
the overall level of power intercepted
from the power line. The circuit in
Figure 2c allows for variation in both
line voltage and load power. The “load
device” detailed in Figures 2b and 2c
is invariably a low AC impedance
device; such devices include, but are
not limited to, capacitors, batteries,
and voltage sources.
The overall goal of PFC is to trans-
fer power from a “wiggly” source such
as an AC power line to a relatively
benign DC voltage. This task must be
performed without stuffing a bunch
of harmonic junk back on the AC
power line.
pfca_2a.eps
POWER
LINE
Figure 2a. Programmable current sink
pfca_2b.eps
POWER
LINE ENERGY
CONVERTER LOAD
DEVICE
pfca_2c.eps
POWER
LINE ENERGY
CONVERTER LOAD
DEVICE
DESIGN FEATURES
TIME
VOLTS
pfca_1a.eps



TIME
RESISTOR CURRENT
pfca_1b.eps
by Dale Eagar
Figure 2b. Non-programmable energy
converter (aka PFC)
Figure 2c. Programmable energy converter
(aka PFC)
Figure 1a. Input line voltage
Figure 1c. Current drawn by a capacitive-
input power supply
Figure 1b. Current drawn by a pure
resistive load
18
Linear Technology Magazine • February 1995
pfca_3.eps
POWER
LINE E1 E2 E3I3
I1
~
~
+
LOAD
DEVICE
I2
BOX
3
BOX
1BOX
2
Figure 3. Detailed block diagram of energy converter






0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
AMPS
pfca_4e.eps
I2
I1
I3



0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
AMPS
pfca_4f.eps
I3
I1
I2
The Energy Converter Box
How it Works
The energy converter shown in Fig-
ure 2b obeys the laws of conservation
of energy (as we all must). As the
energy intercepted at the input is
transformed from one voltage to an-
other, the current is also transformed
from one value to another. The energy
stays the same.
The “guts” inside the energy con-
verter block of Figure 2b are further
detailed in Figure 3. Regardless of the
circuitry in boxes 1–3, we can be sure
that Kirkhoff will have his way: I1 + I2
+ I3 = 0. Further, we shall assume
that whatever occupies the three
boxes is lossless (a pretty good as-
PFC: (Power Factor Correction)
The process used to make
capacitors look like resistors. PFC
became popular in the early 1990’s
when the earthlings realized that
about 10% of the power they har-
nessed on their planet was being
converted to heat. This heat, which
was dissipated through their power
distribution network, become a
contributing factor in their global
warming trend. (see History of
the Sol System, Vol. 17, pp.
137,657–137,698.)
DESIGN FEATURES
sumption in a PFC with better than
95% efficiency). Since the energy in-
tercepted from the input power line
E1 cannot be dissipated in the lossless
contents of Boxes 1, 2, and 3, it will be
losslessly transferred to the output
E3.
Figure 4 illustrates the waveforms
of a 300W, 120V-to-382VDC power
conditioner (refer also to Figure 3).
Figure 4a shows E1, the input power
line voltage of 120V
RMS
. Figure 4b
details E2, the full-wave-rectified sine
wave.
The energy converter does magic
things in the three boxes to cause the
waveshape of the input current I1
(Figure 4c) to be a replica of the input
voltage E2, with only the magnitude
being different. The power intercepted
from the input is P1:
P1 = I1 × E2 (see Figure 4d).
Note that the input power is a
sinusoidal waveshape, is always posi-
tive, and is at twice the line voltage
frequency. This is exactly what the
waveshape and frequency of the power
delivered from a sine wave source to a
resistive load looks like.
All of the power intercepted by the
energy converter circuit is transferred
continued on page 21




0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
I1 (AMPS)
pfca_4c.eps




0
25
50
75
100
125
150
175
200
E2 (VOLTS)
pfca_4b.eps



–200
–150
–100
–50
0
50
100
150
200
E1 (VOLTS)
pfca_4a.eps



0
100
200
300
400
500
600
P1 (WATTS)
pfca_4d.eps
Figure 4a. E1, input voltage waveform:
300W idealized PFC Figure 4b. E2, full-wave-rectified
sinewave: 300W idealized PFC Figure 4c. I1, input current:
300W idealized PFC
Figure 4d. P1, power intercepted
from the input (P1 = I1 × E2): 300W
idealized PFC
Figure 4f. Input current, I1, and current through
Box 3, I3. I2 is obtained by subtraction. 300W
idealized PFC
Figure 4e. Input current, I1, and output
current, I2. I3 is obtained by subtraction.
300W idealized PFC
Linear Technology Magazine • February 1995
19
Power for Pentium
TM
LTC1266 Drives
N-Channel MOSFETs
The LTC1266 controller offers sev-
eral advantages over its predecessors.
First, it will drive all N-channel
MOSFETs instead of requiring P-FETs
for the high side switches. This low-
ers cost and improves efficiency. It
also has an improved, higher-gain
error amplifier, which results in bet-
ter load regulation, compared to that
of the LTC1148 family. There is also
an undedicated comparator, which
may be used for a “power-good” moni-
tor or an overvoltage detector in these
applications. There is a shutdown
pin and a new burst-inhibit function.
Figure 1. Pentium P54C 5/10 amp power supply circuit
DESIGN FEATURES
Introduction
Providing power for the Pentium
microprocessor family is not a trivial
task by any means. In an effort to
simplify this task we have developed
a new control circuit and spent con-
siderable time developing an
optimized decoupling network. Here
are several circuits using the new
LTC1266 synchronous buck-
regulator control chip to provide
power for the P54C, P54C-VR, and
P54C-VRE microprocessors. The
P54C has a supply requirement of
3.3V ±5%, the P54C-VR requires 3.3V
+5%/0%, and the P54C-VRE
requires 3.525V ±75mV.
Burst mode is inhibited on all the
designs shown here, but for the P54C
supplies, (non-VR/VRE parts) burst
may be enabled if desired, resulting
in improved light-load efficiency. This
is done by tying pin 4 low. The refer-
ence tolerance available on the
LTC1266 (or on any other PWM con-
troller, for that matter) is not accurate
enough for the -VR or -VRE specifica-
tions. The LT1431, however, has a
sufficiently accurate reference for
these applications, and permits very
effective remote sensing (see Figure
2). Do not enable Burst Mode on the
+
+
+
+
+ + +
P54pwr_1.eps
TDRV
PWRV
IN
12V
D2
MBR120T3
C2
1µF
5V
C1
0.22µF
D1
MBR120T3 SEE
NOTE 4
PINV
BINH
V
IN
C
T
I
TH
C7
2200pF
C3
1000pF
C8
1000pF
C14
120µF
C6
1µF
R5
10k
SENSE
1
2
3
4
5
6
7
8
16
15
14
5
Q1
678
1
4
SEE NOTE 5
23
5
Q2
Si9410
D3
MBRS320T3
678
1
4
23
L1
3µH
R2
100R3
100
R1
10k
1%
SEE NOTE 7
R6
13
12
11
10
9
BDRV
PGND
LBO
LTC1266
U1 LBIN
SGND
S/D
V
FB
SENSE+
R7
6.04k
1%
R4
100
C9
330µF
6.3V
C4
220µF
10V
C5
220µF
10V
SEE NOTE 6
C12
220µF
10V
C13
220µF
10V
SENSE
C10
330µF
6.3V
C11
330µF
6.3V
V
OUT
NOTES:
1.CIRCUIT SHOWN IS 5V TO 3.3V AT 5A OR 10A, ±5%.
2.ASSUMES APROX. 400 µF OF TANTALUM CAPACITOR IN µP SOCKET CAVITY
IN ADDITION TO OUTPUT CAPACITORS SHOWN ON POWER SUPPLY.
3.ALL POLARIZED CAPACITORS ARE AVX TYPE TPS OR EQUIVALENT.
4.IF 12V IS AVAILABLE, THESE PARTS MAY BE ELIMINATED.
5.FOR 5A OUTPUT USE Si9410. FOR 10A, USE Si4410.
6.PARTS MAY BE ELIMINATED IN 5A DESIGN.
7.VALUE FOR 5A IS 0.02 . FOR 10A USE 0.01.
by Craig Varga