Hitachi Single-Chip Microcomputer
H8/3437 Series
H8/3437
HD6473437, HD6433437
H8/3436
HD6433436
H8/3434
HD6473434, HD6433434
H8/3434 F-ZTATTM
HD64F3434
H8/3437 F-ZTATTM
HD64F3437
Hardware Manual
ADE-602-077C
Preface
The H8/3437 Series is a series of high-performance microcontrollers with a fast H8/300 CPU core
and a set of on-chip supporting functions optimized for embedded control. These include ROM,
RAM, four types of timers, a serial communication interface, optional I2C bus interface, host
interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system
configurations, so that compact, high-performance systems can be implemented easily. The series
includes the H8/3437 with 60-kbyte ROM and 2-kbyte RAM, the H8/3436 with 48-kbyte ROM and
2-kbyte RAM, and the H8/3434 with 32-kbyte ROM and 1-kbyte RAM.
The H8/3437, H8/3436, and H8/3434 are available in mask-ROM versions. The H8/3437 and
H8/3434 are also available in ZTAT™*1 (zero turn-around time) versions, providing a quick and
flexible response to conditions from ramp-up through full-scale volume production, even for
applications with frequently-changing specifications. In addition, the H8/3434 and H8/3437 have
F-ZTAT™*2 (flexible-ZTAT) versions with on-board programmability.
This manual describes the hardware of the H8/3437 Series. Refer to the H8/300 Series
Programming Manual for a detailed description of the instruction set.
Notes: 1. ZTAT™ is a trademark of Hitachi, Ltd.
2. F-ZTAT™ is a trademark of Hitachi, Ltd.
Main Amendments and Additions in this Edition
Page Title Amendment/Addition
All Addition of H8/3437F-ZTAT version
Addition of ROM descriptions
Section 18 Mask ROM Version/ZTAT Version
Section 19 32-Kbyte Flash Memory Version
Section 20 60-Kbyte Flash Memory Version
491 Table 22-2 DC Characteristics (5-V Version) Values changed for “Input capacitance”
item
495 Table 22-3 DC Characteristics (4-V Version) Values changed for “Input capacitance”
item
498 Table 22-4 DC Characteristics (3-V Version) Values changed for “Input capacitance”
item
505 Table 22-10 Timing Conditions of On-Chip Values changed for “HIF write cycle”
Supporting Modules item
Contents
Section 1 Overview..................................................................................................... 1
1.1 Overview ........................................................................................................................ 1
1.2 Block Diagram................................................................................................................5
1.3 Pin Assignments and Functions...................................................................................... 6
1.3.1 Pin Arrangement............................................................................................. 6
1.3.2 Pin Functions.................................................................................................. 7
Section 2 CPU............................................................................................................... 17
2.1 Overview ........................................................................................................................ 17
2.1.1 Features........................................................................................................... 17
2.1.2 Address Space................................................................................................. 18
2.1.3 Register Configuration.................................................................................... 18
2.2 Register Descriptions...................................................................................................... 19
2.2.1 General Registers............................................................................................ 19
2.2.2 Control Registers............................................................................................ 19
2.2.3 Initial Register Values .................................................................................... 20
2.3 Data Formats................................................................................................................... 21
2.3.1 Data Formats in General Registers................................................................. 22
2.3.2 Memory Data Formats.................................................................................... 23
2.4 Addressing Modes.......................................................................................................... 24
2.4.1 Addressing Mode............................................................................................ 24
2.4.2 Calculation of Effective Address.................................................................... 26
2.5 Instruction Set................................................................................................................. 30
2.5.1 Data Transfer Instructions .............................................................................. 31
2.5.2 Arithmetic Operations .................................................................................... 33
2.5.3 Logic Operations ............................................................................................ 34
2.5.4 Shift Operations.............................................................................................. 34
2.5.5 Bit Manipulations ........................................................................................... 36
2.5.6 Branching Instructions.................................................................................... 41
2.5.7 System Control Instructions ........................................................................... 43
2.5.8 Block Data Transfer Instruction ..................................................................... 44
2.6 CPU States...................................................................................................................... 46
2.6.1 Overview......................................................................................................... 46
2.6.2 Program Execution State ................................................................................ 47
2.6.3 Exception-Handling State............................................................................... 47
2.6.4 Power-Down State.......................................................................................... 47
2.7 Access Timing and Bus Cycle........................................................................................ 48
2.7.1 Access to On-Chip Memory (RAM and ROM) ............................................. 48
2.7.2 Access to On-Chip Register Field and External Devices............................... 50
Section 3 MCU Operating Modes and Address Space..................................... 53
3.1 Overview ........................................................................................................................ 53
3.1.1 Mode Selection............................................................................................... 53
3.1.2 Mode and System Control Registers ............................................................. 54
3.2 System Control Register (SYSCR)................................................................................. 54
3.3 Mode Control Register (MDCR).................................................................................... 57
3.4 Address Space Map in Each Operating Mode................................................................ 58
Section 4 Exception Handling.................................................................................. 61
4.1 Overview ........................................................................................................................ 61
4.2 Reset ........................................................................................................................61
4.2.1 Overview......................................................................................................... 61
4.2.2 Reset Sequence............................................................................................... 61
4.2.3 Disabling of Interrupts after Reset.................................................................. 64
4.3 Interrupts ........................................................................................................................ 64
4.3.1 Overview......................................................................................................... 64
4.3.2 Interrupt-Related Registers............................................................................. 66
4.3.3 External Interrupts.......................................................................................... 70
4.3.4 Internal Interrupts ........................................................................................... 70
4.3.5 Interrupt Handling .......................................................................................... 71
4.3.6 Interrupt Response Time................................................................................. 76
4.3.7 Precaution....................................................................................................... 77
4.4 Note on Stack Handling.................................................................................................. 78
Section 5 Wait-State Controller............................................................................... 79
5.1 Overview ........................................................................................................................ 79
5.1.1 Features........................................................................................................... 79
5.1.2 Block Diagram................................................................................................ 79
5.1.3 Input/Output Pins............................................................................................ 80
5.1.4 Register Configuration.................................................................................... 80
5.2 Register Description ....................................................................................................... 80
5.2.1 Wait-State Control Register (WSCR)............................................................. 80
5.3 Wait Modes..................................................................................................................... 82
Section 6 Clock Pulse Generator............................................................................. 85
6.1 Overview ........................................................................................................................ 85
6.1.1 Block Diagram................................................................................................ 85
6.1.2 Wait-State Control Register (WSCR)............................................................. 86
6.2 Oscillator Circuit ............................................................................................................ 87
6.3 Duty Adjustment Circuit................................................................................................. 92
6.4 Prescaler ........................................................................................................................ 92
Section 7 I/O Ports....................................................................................................... 93
7.1 Overview ........................................................................................................................ 93
7.2 Port 1 ........................................................................................................................ 96
7.2.1 Overview......................................................................................................... 96
7.2.2 Register Configuration and Descriptions........................................................ 97
7.2.3 Pin Functions in Each Mode........................................................................... 99
7.2.4 Input Pull-Up Transistors ............................................................................... 101
7.3 Port 2 ........................................................................................................................ 102
7.3.1 Overview......................................................................................................... 102
7.3.2 Register Configuration and Descriptions........................................................ 103
7.3.3 Pin Functions in Each Mode........................................................................... 105
7.3.4 Input Pull-Up Transistors ............................................................................... 107
7.4 Port 3 ........................................................................................................................ 108
7.4.1 Overview......................................................................................................... 108
7.4.2 Register Configuration and Descriptions........................................................ 109
7.4.3 Pin Functions in Each Mode........................................................................... 111
7.4.4 Input Pull-Up Transistors ............................................................................... 112
7.5 Port 4 ........................................................................................................................ 113
7.5.1 Overview......................................................................................................... 113
7.5.2 Register Configuration and Descriptions........................................................ 114
7.5.3 Pin Functions.................................................................................................. 116
7.6 Port 5 ........................................................................................................................ 118
7.6.1 Overview......................................................................................................... 118
7.6.2 Register Configuration and Descriptions........................................................ 118
7.6.3 Pin Functions.................................................................................................. 120
7.7 Port 6 ........................................................................................................................ 121
7.7.1 Overview......................................................................................................... 121
7.7.2 Register Configuration and Descriptions........................................................ 122
7.7.3 Pin Functions.................................................................................................. 124
7.7.4 Input Pull-Up Transistors ............................................................................... 126
7.8 Port 7 ........................................................................................................................ 127
7.8.1 Overview......................................................................................................... 127
7.8.2 Register Configuration and Descriptions........................................................ 128
7.9 Port 8 ........................................................................................................................ 129
7.9.1 Overview......................................................................................................... 129
7.9.2 Register Configuration and Descriptions........................................................ 130
7.9.3 Pin Functions.................................................................................................. 132
7.10 Port 9 ........................................................................................................................ 134
7.10.1 Overview......................................................................................................... 134
7.10.2 Register Configuration and Descriptions........................................................ 135
7.10.3 Pin Functions.................................................................................................. 137
7.11 Port A ........................................................................................................................ 139
7.11.1 Overview......................................................................................................... 139
7.11.2 Register Configuration and Descriptions........................................................ 139
7.11.3 Pin Functions in Each Mode........................................................................... 141
7.11.4 Input Pull-Up Transistors ............................................................................... 142
7.12 Port B ........................................................................................................................ 143
7.12.1 Overview......................................................................................................... 143
7.12.2 Register Configuration and Descriptions........................................................ 144
7.12.3 Pin Functions in Each Mode........................................................................... 146
7.12.4 Input Pull-Up Transistors ............................................................................... 147
Section 8 16-Bit Free-Running Timer ................................................................... 149
8.1 Overview ........................................................................................................................ 149
8.1.1 Features........................................................................................................... 149
8.1.2 Block Diagram................................................................................................ 150
8.1.3 Input and Output Pins..................................................................................... 151
8.1.4 Register Configuration.................................................................................... 151
8.2 Register Descriptions...................................................................................................... 152
8.2.1 Free-Running Counter (FRC)......................................................................... 152
8.2.2 Output Compare Registers A and B (OCRA and OCRB).............................. 153
8.2.3 Input Capture Registers A to D (ICRA to ICRD)........................................... 153
8.2.4 Timer Interrupt Enable Register (TIER)......................................................... 155
8.2.5 Timer Control/Status Register (TCSR) .......................................................... 157
8.2.6 Timer Control Register (TCR)........................................................................ 159
8.2.7 Timer Output Compare Control Register (TOCR)......................................... 161
8.3 CPU Interface ................................................................................................................. 163
8.4 Operation ........................................................................................................................ 166
8.4.1 FRC Increment Timing................................................................................... 166
8.4.2 Output Compare Timing................................................................................. 168
8.4.3 FRC Clear Timing .......................................................................................... 169
8.4.4 Input Capture Timing ..................................................................................... 170
8.4.5 Timing of Input Capture Flag (ICF) Setting................................................... 173
8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB) .................... 174
8.4.7 Setting of FRC Overflow Flag (OVF)............................................................ 175
8.5 Interrupts ........................................................................................................................ 175
8.6 Sample Application ........................................................................................................ 176
8.7 Application Notes........................................................................................................... 177
Section 9 8-Bit Timers................................................................................................ 183
9.1 Overview ........................................................................................................................ 183
9.1.1 Features........................................................................................................... 183
9.1.2 Block Diagram................................................................................................ 184
9.1.3 Input and Output Pins..................................................................................... 185
9.1.4 Register Configuration.................................................................................... 185
9.2 Register Descriptions...................................................................................................... 186
9.2.1 Timer Counter (TCNT)................................................................................... 186
9.2.2 Time Constant Registers A and B (TCORA and TCORB)............................ 186
9.2.3 Timer Control Register (TCR)........................................................................ 187
9.2.4 Timer Control/Status Register (TCSR) .......................................................... 190
9.2.5 Serial/Timer Control Register (STCR)........................................................... 192
9.3 Operation ........................................................................................................................ 193
9.3.1 TCNT Increment Timing................................................................................ 193
9.3.2 Compare-Match Timing ................................................................................. 195
9.3.3 External Reset of TCNT................................................................................. 197
9.3.4 Setting of TCSR Overflow Flag (OVF).......................................................... 197
9.4 Interrupts ........................................................................................................................ 198
9.5 Sample Application ........................................................................................................ 198
9.6 Application Notes........................................................................................................... 199
9.6.1 Contention between TCNT Write and Clear ................................................. 199
9.6.2 Contention between TCNT Write and Increment .......................................... 200
9.6.3 Contention between TCOR Write and Compare-Match ............................... 201
9.6.4 Contention between Compare-Match A and Compare-Match B ................... 202
9.6.5 Increment Caused by Changing of Internal Clock Source ............................. 202
Section 10 PWM Timers.............................................................................................. 205
10.1 Overview ........................................................................................................................ 205
10.1.1 Features........................................................................................................... 205
10.1.2 Block Diagram................................................................................................ 206
10.1.3 Input and Output Pins..................................................................................... 207
10.1.4 Register Configuration.................................................................................... 207
10.2 Register Descriptions...................................................................................................... 208
10.2.1 Timer Counter (TCNT)................................................................................... 208
10.2.2 Duty Register (DTR) ...................................................................................... 208
10.2.3 Timer Control Register (TCR)........................................................................ 209
10.3 Operation ........................................................................................................................ 211
10.3.1 Timer Increment ............................................................................................. 211
10.3.2 PWM Operation.............................................................................................. 212
10.4 Application Notes........................................................................................................... 213
Section 11 Watchdog Timer........................................................................................ 215
11.1 Overview ........................................................................................................................ 215
11.1.1 Features........................................................................................................... 215
11.1.2 Block Diagram................................................................................................ 216
11.1.3 Register Configuration.................................................................................... 216
11.2 Register Descriptions...................................................................................................... 217
11.2.1 Timer Counter (TCNT)................................................................................... 217
11.2.2 Timer Control/Status Register (TCSR) .......................................................... 217
11.2.3 Register Access............................................................................................... 219
11.3 Operation ........................................................................................................................ 220
11.3.1 Watchdog Timer Mode................................................................................... 220
11.3.2 Interval Timer Mode....................................................................................... 221
11.3.3 Setting the Overflow Flag............................................................................... 221
11.4 Application Notes........................................................................................................... 222
11.4.1 Contention between TCNT Write and Increment........................................... 222
11.4.2 Changing the Clock Select Bits (CKS2 to CKS0).......................................... 222
11.4.3 Recovery from Software Standby Mode ........................................................ 222
Section 12 Serial Communication Interface........................................................... 223
12.1 Overview ........................................................................................................................ 223
12.1.1 Features........................................................................................................... 223
12.1.2 Block Diagram................................................................................................ 225
12.1.3 Input and Output Pins..................................................................................... 226
12.1.4 Register Configuration.................................................................................... 227
12.2 Register Descriptions...................................................................................................... 228
12.2.1 Receive Shift Register (RSR)......................................................................... 228
12.2.2 Receive Data Register (RDR)......................................................................... 228
12.2.3 Transmit Shift Register (TSR)........................................................................ 228
12.2.4 Transmit Data Register (TDR) ....................................................................... 229
12.2.5 Serial Mode Register (SMR).......................................................................... 229
12.2.6 Serial Control Register (SCR)........................................................................ 232
12.2.7 Serial Status Register (SSR)........................................................................... 235
12.2.8 Bit Rate Register (BRR)................................................................................. 238
12.2.9 Serial/Timer Control Register (STCR)........................................................... 243
12.3 Operation ........................................................................................................................ 244
12.3.1 Overview......................................................................................................... 244
12.3.2 Asynchronous Mode....................................................................................... 246
12.3.3 Synchronous Mode......................................................................................... 260
12.4 Interrupts ........................................................................................................................ 269
12.5 Application Notes........................................................................................................... 269
Section 13 I2C Bus Interface [Option]..................................................................... 273
13.1 Overview ........................................................................................................................ 273
13.1.1 Features........................................................................................................... 273
13.1.2 Block Diagram................................................................................................ 275
13.1.3 Input/Output Pins............................................................................................ 276
13.1.4 Register Configuration.................................................................................... 276
13.2 Register Descriptions...................................................................................................... 277
13.2.1 I2C Bus Data Register (ICDR) ....................................................................... 277
13.2.2 Slave Address Register (SAR)........................................................................ 277
13.2.3 I2C Bus Mode Register (ICMR)..................................................................... 278
13.2.4 I2C Bus Control Register (ICCR)................................................................... 280
13.2.5 I2C Bus Status Register (ICSR)...................................................................... 283
13.2.6 Serial/Timer Control Register (STCR)........................................................... 287
13.3 Operation ........................................................................................................................ 288
13.3.1 I2C Bus Data Format ...................................................................................... 288
13.3.2 Master Transmit Operation............................................................................. 290
13.3.3 Master Receive Operation .............................................................................. 292
13.3.4 Slave Transmit Operation............................................................................... 294
13.3.5 Slave Receive Operation................................................................................. 296
13.3.6 IRIC Set Timing and SCL Control................................................................. 297
13.3.7 Noise Canceler................................................................................................ 298
13.3.8 Sample Flowcharts.......................................................................................... 299
13.4 Application Notes........................................................................................................... 303
Section 14 Host Interface............................................................................................. 305
14.1 Overview ........................................................................................................................ 305
14.1.1 Block Diagram................................................................................................ 306
14.1.2 Input and Output Pins..................................................................................... 307
14.1.3 Register Configuration.................................................................................... 308
14.2 Register Descriptions...................................................................................................... 309
14.2.1 System Control Register (SYSCR)................................................................. 309
14.2.2 Host Interface Control Register (HICR)......................................................... 309
14.2.3 Input Data Register (IDR1) ............................................................................ 310
14.2.4 Output Data Register (ODR1)........................................................................ 311
14.2.5 Status Register (STR1)................................................................................... 311
14.2.6 Input Data Register (IDR2) ............................................................................ 312
14.2.7 Output Data Register (ODR2)........................................................................ 313
14.2.8 Status Register (STR2)................................................................................... 313
14.2.9 Serial/Timer Control Register (STCR)........................................................... 315
14.3 Operation ........................................................................................................................ 316
14.3.1 Host Interface Operation................................................................................. 316
14.3.2 Control States.................................................................................................. 316
14.3.3 A20 Gate.......................................................................................................... 317
14.4 Interrupts ........................................................................................................................ 320
14.4.1 IBF1, IBF2...................................................................................................... 320
14.4.2 HIRQ11, HIRQ1, and HIRQ12 ........................................................................ 320
14.5 Application Note............................................................................................................. 321
Section 15 A/D Converter............................................................................................ 323
15.1 Overview ........................................................................................................................ 323
15.1.1 Features........................................................................................................... 323
15.1.2 Block Diagram................................................................................................ 324
15.1.3 Input Pins........................................................................................................ 325
15.1.4 Register Configuration.................................................................................... 326
15.2 Register Descriptions...................................................................................................... 327
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)........................................ 327
15.2.2 A/D Control/Status Register (ADCSR).......................................................... 328
15.2.3 A/D Control Register (ADCR)....................................................................... 330
15.3 CPU Interface ................................................................................................................. 331
15.4 Operation ........................................................................................................................ 332
15.4.1 Single Mode (SCAN = 0)............................................................................... 332
15.4.2 Scan Mode (SCAN = 1).................................................................................. 334
15.4.3 Input Sampling and A/D Conversion Time.................................................... 336
15.4.4 External Trigger Input Timing........................................................................ 337
15.5 Interrupts ........................................................................................................................ 338
15.6 Application Notes........................................................................................................... 338
Section 16 D/A Converter............................................................................................ 339
16.1 Overview ........................................................................................................................ 339
16.1.1 Features........................................................................................................... 339
16.1.2 Block Diagram................................................................................................ 340
16.1.3 Input and Output Pins..................................................................................... 341
16.1.4 Register Configuration.................................................................................... 341
16.2 Register Descriptions...................................................................................................... 342
16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ........................................... 342
16.2.2 D/A Control Register (DACR)....................................................................... 342
16.3 Operation ........................................................................................................................ 344
Section 17 RAM............................................................................................................. 345
17.1 Overview ........................................................................................................................ 345
17.1.1 Block Diagram................................................................................................ 345
17.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR)................. 346
17.2 Operation ........................................................................................................................ 346
17.2.1 Expanded Modes (Modes 1 and 2)................................................................. 346
17.2.2 Single-Chip Mode (Mode 3)........................................................................... 346
Section 18 ROM (Mask ROM version/ZTAT version)....................................... 347
18.1 Overview ........................................................................................................................ 347
18.1.1 Block Diagram................................................................................................ 348
18.2 PROM Mode (H8/3437, H8/3434)................................................................................. 349
18.2.1 PROM Mode Setup......................................................................................... 349
18.2.2 Socket Adapter Pin Assignments and Memory Map...................................... 349
18.3 PROM Programming...................................................................................................... 352
18.3.1 Programming and Verification....................................................................... 353
18.3.2 Notes on Programming................................................................................... 356
18.3.3 Reliability of Programmed Data..................................................................... 357
Section 19 ROM (Flash memory 32 kbytes version).......................................... 359
19.1 Flash Memory Overview................................................................................................ 359
19.1.1 Flash Memory Operating Principle ................................................................ 359
19.1.2 Mode Programming and Flash Memory Address Space................................ 359
19.1.3 Features........................................................................................................... 360
19.1.4 Block Diagram................................................................................................ 361
19.1.5 Input/Output Pins............................................................................................ 362
19.1.6 Register Configuration.................................................................................... 362
19.2 Flash Memory Register Descriptions ............................................................................. 363
19.2.1 Flash Memory Control Register (FLMCR).................................................... 363
19.2.2 Erase Block Register 1 (EBR1)...................................................................... 364
19.2.3 Erase Block Register 2 (EBR2)...................................................................... 365
19.2.4 Wait-State Control Register (WSCR)............................................................. 366
19.3 On-Board Programming Modes ..................................................................................... 369
19.3.1 Boot Mode...................................................................................................... 370
19.3.2 User Program Mode........................................................................................ 376
19.4 Programming and Erasing Flash Memory...................................................................... 378
19.4.1 Program Mode................................................................................................ 378
19.4.2 Program-Verify Mode .................................................................................... 378
19.4.3 Programming Flowchart and Sample Program............................................... 379
19.4.4 Erase Mode..................................................................................................... 381
19.4.5 Erase-Verify Mode ......................................................................................... 381
19.4.6 Erasing Flowchart and Sample Program ........................................................ 382
19.4.7 Prewrite Verify Mode..................................................................................... 395
19.4.8 Protect Modes................................................................................................. 395
19.4.9 Interrupt Handling during Flash Memory Programming and Erasing............ 396
19.5 Flash Memory Emulation by RAM................................................................................ 398
19.6 Flash Memory PROM Mode (H8/3434F) ...................................................................... 401
19.6.1 PROM Mode Setting ...................................................................................... 401
19.6.2 Socket Adapter and Memory Map.................................................................. 401
19.6.3 Operation in PROM Mode.............................................................................. 403
19.7 Flash Memory Programming and Erasing Precautions.................................................. 411
Section 20 ROM (Flash memory 60 kbytes version).......................................... 419
20.1 Flash Memory Overview................................................................................................ 419
20.1.1 Flash Memory Operating Principle ................................................................ 419
20.1.2 Mode Programming and Flash Memory Address Space................................ 419
20.1.3 Features........................................................................................................... 420
20.1.4 Block Diagram................................................................................................ 421
20.1.5 Input/Output Pins............................................................................................ 422
20.1.6 Register Configuration.................................................................................... 422
20.2 Flash Memory Register Descriptions ............................................................................. 423
20.2.1 Flash Memory Control Register (FLMCR).................................................... 423
20.2.2 Erase Block Register 1 (EBR1)...................................................................... 424
20.2.3 Erase Block Register 2 (EBR2)...................................................................... 425
20.2.4 Wait-State Control Register (WSCR)............................................................. 426
20.3 On-Board Programming Modes ..................................................................................... 429
20.3.1 Boot Mode...................................................................................................... 430
20.3.2 User Program Mode........................................................................................ 436
20.4 Programming and Erasing Flash Memory...................................................................... 438
20.4.1 Program Mode................................................................................................ 438
20.4.2 Program-Verify Mode .................................................................................... 438
20.4.3 Programming Flowchart and Sample Program............................................... 439
20.4.4 Erase Mode..................................................................................................... 441
20.4.5 Erase-Verify Mode ......................................................................................... 441
20.4.6 Erasing Flowchart and Sample Program ........................................................ 442
20.4.7 Prewrite Verify Mode..................................................................................... 455
20.4.8 Protect Modes................................................................................................. 455
20.4.9 Interrupt Handling during Flash Memory Programming and Erasing............ 456
20.5 Flash Memory Emulation by RAM................................................................................ 458
20.6 Flash Memory PROM Mode (H8/3437F) ...................................................................... 461
20.6.1 PROM Mode Setting ...................................................................................... 461
20.6.2 Socket Adapter and Memory Map.................................................................. 461
20.6.3 Operation in PROM Mode.............................................................................. 463
20.7 Flash Memory Programming and Erasing Precautions.................................................. 471
Section 21 Power-Down State.................................................................................... 479
21.1 Overview ........................................................................................................................ 479
21.1.1 System Control Register (SYSCR)................................................................. 480
21.2 Sleep Mode..................................................................................................................... 482
21.2.1 Transition to Sleep Mode................................................................................ 482
21.2.2 Exit from Sleep Mode..................................................................................... 482
21.3 Software Standby Mode ................................................................................................. 483
21.3.1 Transition to Software Standby Mode............................................................ 483
21.3.2 Exit from Software Standby Mode................................................................. 483
21.3.3 Clock Settling Time for Exit from Software Standby Mode.......................... 484
21.3.4 Sample Application of Software Standby Mode............................................ 485
21.3.5 Application Note............................................................................................. 485
21.4 Hardware Standby Mode................................................................................................ 487
21.4.1 Transition to Hardware Standby Mode........................................................... 487
21.4.2 Recovery from Hardware Standby Mode....................................................... 487
21.4.3 Timing Relationships...................................................................................... 488
Section 22 Electrical Specifications.......................................................................... 489
22.1 Absolute Maximum Ratings........................................................................................... 489
22.2 Electrical Characteristics................................................................................................ 490
22.2.1 DC Characteristics.......................................................................................... 490
22.2.2 AC Characteristics.......................................................................................... 502
22.2.3 A/D Converter Characteristics........................................................................ 507
22.2.4 D/A Converter Characteristics........................................................................ 508
22.3 MCU Operational Timing............................................................................................... 509
22.3.1 Bus Timing ..................................................................................................... 509
22.3.2 Control Signal Timing.................................................................................... 511
22.3.3 16-Bit Free-Running Timer Timing ............................................................... 513
22.3.4 8-Bit Timer Timing......................................................................................... 514
22.3.5 Pulse Width Modulation Timer Timing ......................................................... 515
22.3.6 Serial Communication Interface Timing........................................................ 516
22.3.7 I/O Port Timing............................................................................................... 517
22.3.8 Host Interface Timing..................................................................................... 518
22.3.9 I2C Bus Timing (Option)................................................................................ 519
22.3.10 Reset Output Timing....................................................................................... 519
22.3.11 External Clock Output Timing ....................................................................... 520
Appendix A CPU Instruction Set.................................................................................. 521
A.1 Instruction Set List.......................................................................................................... 521
A.2 Operation Code Map....................................................................................................... 529
A.3 Number of States Required for Execution...................................................................... 531
Appendix B Internal I/O Register................................................................................. 537
B.1 Addresses........................................................................................................................ 537
B.2 Function.......................................................................................................................... 542
Appendix C I/O Port Block Diagrams........................................................................ 597
C.1 Port 1 Block Diagram..................................................................................................... 597
C.2 Port 2 Block Diagram..................................................................................................... 598
C.3 Port 3 Block Diagram..................................................................................................... 599
C.4 Port 4 Block Diagrams.................................................................................................... 600
C.5 Port 5 Block Diagrams.................................................................................................... 604
C.6 Port 6 Block Diagrams.................................................................................................... 607
C.7 Port 7 Block Diagrams.................................................................................................... 611
C.8 Port 8 Block Diagrams.................................................................................................... 612
C.9 Port 9 Block Diagrams.................................................................................................... 618
C.10 Port A Block Diagram.................................................................................................... 624
C.11 Port B Block Diagram .................................................................................................... 625
Appendix D Pin States..................................................................................................... 626
D.1 Port States in Each Mode................................................................................................ 626
Appendix E Timing of Transition to and Recovery
from Hardware Standby Mode.............................................................. 629
Appendix F Option Lists ................................................................................................ 630
Appendix G Product Code Lineup............................................................................... 632
Appendix H Package Dimensions................................................................................ 633
Section 1 Overview
1.1 Overview
The H8/3437 Series of single-chip microcomputers features an H8/300 CPU core and a complement
of on-chip supporting modules implementing a variety of system functions.
The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-manipulation
instructions, ideally suited for realtime control applications. The on-chip supporting modules
implement peripheral functions needed in system configurations. These include ROM, RAM, four
types of timers (a 16-bit free-running timer, 8-bit timers, PWM timers, and a watchdog timer), a
serial communication interface (SCI), an I2C bus interface [option], a host interface (HIF), an A/D
converter, a D/A converter, and I/O ports.
The H8/3437 Series can operate in single-chip mode or in two expanded modes, depending on the
requirements of the application.
Besides the mask-ROM versions of the H8/3437 Series, there are ZTAT™*1 versions with on-chip
PROM, and an F-ZTAT™*2 version with on-chip flash memory. The F-ZTAT™ version can be
programmed or reprogrammed on-board in application systems.
Notes: 1. ZTAT™ (zero turn-around time) is a trademark of Hitachi, Ltd.
2. F-ZTAT™ (flexible-ZTAT) is a trademark of Hitachi, Ltd.
Table 1-1 lists the features of the H8/3437 Series.
1
Table 1-1 Features
Item Specification
CPU Two-way general register configuration
• Eight 16-bit registers, or
• Sixteen 8-bit registers
High-speed operation
• Maximum clock rate (øclock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz at 3 V
• 8- or 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns (12 MHz),
200 ns (10 MHz)
•8
×8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)
• 16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)
Streamlined, concise instruction set
• Instruction length: 2 or 4 bytes
• Register-register arithmetic and logic operations
• MOV instruction for data transfer between registers and memory
Instruction set features
• Multiply instruction (8 bits ×8 bits)
• Divide instruction (16 bits ÷ 8 bits)
• Bit-accumulator instructions
• Register-indirect specification of bit positions
Memory • H8/3437: 60-kbyte ROM; 2-kbyte RAM
• H8/3436: 48-kbyte ROM; 2-kbyte RAM
• H8/3434: 32-kbyte ROM; 1-kbyte RAM
16-bit free- • One 16-bit free-running counter (can also count external events)
running timer • Two output-compare lines
(1 channel) • Four input capture lines (can be buffered)
8-bit timer Each channel has
(2 channels) • One 8-bit up-counter (can also count external events)
• Two time constant registers
PWM timer • Duty cycle can be set from 0 to 100%
(2 channels) • Resolution: 1/250
Watchdog timer • Overflow can generate a reset or NMI interrupt
(WDT) • Also usable as interval timer
(1 channel)
Serial • Asynchronous or synchronous mode (selectable)
communication • Full duplex: can transmit and receive simultaneously
interface (SCI) • On-chip baud rate generator
(2 channels)
2
Table 1-1 Features (cont)
Item Specification
I2C bus interface • Conforms to Philips I2C bus interface
(1 channel) [option] • Includes single master mode and slave mode
Host interface • 8-bit host interface port
(HIF) • Three host interrupt requests (HIRQ1, HIRQ11, HIRQ12)
• Regular and fast A20 gate output
• Two register sets, each with two data registers and a status register
Keyboard • Controls a matrix-scan keyboard by providing a keyboard scan function with
controller wake-up interrupts and sense ports
A/D converter • 10-bit resolution
• Eight channels: single or scan mode (selectable)
• Start of A/D conversion can be externally triggered
• Sample-and-hold function
D/A converter • 8-bit resolution
• Two channels
I/O ports • 74 input/output lines (16 of which can drive LEDs)
• 8 input-only lines
Interrupts • Nine external interrupt lines: NMI, IRQ0to IRQ7
• 26 on-chip interrupt sources
Wait control • Three selectable wait modes
Operating • Expanded mode with on-chip ROM disabled (mode 1)
modes • Expanded mode with on-chip ROM enabled (mode 2)
• Single-chip mode (mode 3)
Power-down • Sleep mode
modes • Software standby mode
• Hardware standby mode
Other features • On-chip oscillator
3
Table 1-1 Features (cont)
Item Specification
Series lineup Part Number
5-V Version
(16 MHz)
4-V Version 3-V Version
Product Name (12 MHz) (10 MHz) Package ROM
H8/3437 F-ZTAT HD64F3437F16 HD64F3437F16 100-pin QFP Flash
(FP-100B) memory
HD64F3437TF16 HD64F3437TF16 100-pin TQFP
(TFP-100B)
H8/3437 ZTAT HD6473437F16 HD6473437F16 100-pin QFP PROM
(FP-100B)
HD6473437TF16 HD6473437TF16 100-pin TQFP
(TFP-100B)
H8/3437 HD6433437F16 HD6433437VF10 100-pin QFP Mask ROM
HD6433437F12 (FP-100B)
HD6433437TF16 HD6433437VTF10 100-pin TQFP
HD6433437TF12 (TFP-100B)
H8/3436 HD6433436F16 HD6433436VF10 100-pin QFP Mask ROM
HD6433436F12 (FP-100B)
HD6433436TF16 HD6433436VTF10 100-pin TQFP
HD6433436TF12 (TFP-100B)
H8/3434 F-ZTAT HD64F3434F16 HD64F3434F16 100-pin QFP Flash
(FP-100B) memory
HD64F3434TF16 HD64F3434TF16 100-pin TQFP
(TFP-100B)
H8/3434 ZTAT HD6473434F16 HD6473434F16 100-pin QFP PROM
(FP-100B)
HD6473434TF16 HD6473434TF16 100-pin TQFP
(TFP-100B)
H8/3434 HD6433434F16 HD6433434VF10 100-pin QFP Mask ROM
HD6433434F12 (FP-100B)
HD6433434TF16 HD6433434VTF10 100-pin TQFP
HD6433434TF12 (TFP-100B)
The I2C bus interface is an available option. Please note the following points
regarding this option.
1. Contact your local Hitachi representative to order the I2C bus interface.
2. In mask ROM versions, chips featuring the I2C bus interface include a W in
the part number.
Example: HD6433437WTF, HD6433434WF, etc.
3. Although ZTAT and F-ZTAT chips have identical part numbers, inform your
local Hitachi representative when ordering the I2C bus interface.
4
1.2 Block Diagram
Figure 1-1 shows a block diagram of the H8/3437 Series.
Figure 1-1 Block Diagram
PB0/XDB0
PB1/XDB1
PB2/XDB2
PB3/XDB3
PB4/XDB4
PB5/XDB5
PB6/XDB6
PB7/XDB7
P90/ADTRG/ECS2/IRQ2
P91/IRQ1/EIOW
P92/IRQ0
P93/RD
P94/WR
P95/AS
P96/ø
P97/WAIT/SDA
P30/D0/HDB0
P31/D1/HDB1
P32/D2/HDB2
P33/D3/HDB3
P34/D4/HDB4
P35/D5/HDB5
P36/D6/HDB6
P37/D7/HDB7
P80/HA0
P81/GA20
P82/CS1
P83/IOR
P84/TxD1/IRQ3/IOW
P85/RxD1/IRQ4/CS2
P86/SCK1/IRQ5/SCL
PA0/KEYIN8
PA1/KEYIN9
PA2/KEYIN10
PA3/KEYIN11
PA4/KEYIN12
PA5/KEYIN13
PA6/KEYIN14
PA7/KEYIN15
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
KEYIN0/P60/FTCI
KEYIN1/P61/FTOA
KEYIN2/P62/FTIA
KEYIN3/P63/FTIB
KEYIN4/P64/FTIC
KEYIN5/P65/FTID
KEYIN6/P66/FTOB/IRQ6
KEYIN7/P67/IRQ7
P40/TMCI0
P41/TMO0
P42/TMRI0
HIRQ11/P43/TMCI1
HIRQ1/P44/TMO1
HIRQ12/P45/TMRI1
P46/PW0
P47/PW1
P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P50/TxD0
P51/RxD0
P52/SCK0
AVref
AVCC
AVSS
RESO
RES
STBY
NMI
MD0
MD1
VCCB
VCC
VCC
VSS
VSS
VSS
VSS
XTAL
EXTAL
Port 6 Port 2 Port 1 Port A
Data bus (low)
RAM
H8/3437: 2 kbytes
H8/3436: 2 kbytes
H8/3434: 1 kbyte
10-bit
A/D converter
(8 channels)
8-bit
D/A converter
(2 channels)
16-bit
free-running
timer
8-bit timer
(2 channels)
PWM timer
(2 channels)
Clock pulse
generator
H8/3437
60 kbytes
2 kbytes
H8/3436
48 kbytes
2 kbytes
H8/3434
32 kbytes
1 kbyte
Memory Sizes
ROM
RAM
ROM
(flash memory,
PROM, or
mask ROM)
H8/3437: 60 kbytes
H8/3436: 48 kbytes
H8/3434: 32 kbytes
Watchdog
timer Host
interface
Serial
communication
interface (2 channels)
I2C bus interface
(1 channel) [option]
Port 4 Port 7 Port 5
Port 8 Port 3 Port 9 Port B
CPU
H8/300
Data bus (high)
Address bus
5
1.3 Pin Assignments and Functions
1.3.1 Pin Arrangement
Figure 1-2 shows the pin arrangement of the FP-100B and TFP-100B packages.
Figure 1-2 Pin Arrangement (FP-100B, TFP-100B, Top View)
P14/A4
P15/A5
P16/A6
P17/A7
VSS
VSS
PB4/XDB4
PB5/XDB5
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
VCC
PB6/XDB6
PB7/XDB7
P47/PW1
P46/PW0
P45/TMRI1/HIRQ12
P44/TMO1/HIRQ1
P43/TMCI1/HIRQ11
P42/TMRI0
RES
XTAL
EXTAL
VCCB
MD1
MD0
NMI
FVPP/STBY
VCC
KEYIN15/PA7
KEYIN14/PA6
SCK0/P52
RxD0/P51
TxD0/P50
VSS
SDA/WAIT/P97
ø/P96
AS/P95
WR/P94
KEYIN13/PA5
KEYIN12/PA4
RD/P93
IRQ0/P92
EIOW/IRQ1/P91
ADTRG/ECS2/IRQ2/P90
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RESO
P86/IRQ5/SCK1/SCL
P85/IRQ4/RxD1/CS2
P84/IRQ2/TxD1/IOW
P83/IOR
P82/CS1
P81/GA20
P80/HA0
VSS
PB0/XDB0
PB1/XDB1
P37/HDB7/D7
P36/HDB6/D6
P35/HDB5/D5
P34/HDB4/D4
P33/HDB3/D3
P32/HDB2/D2
P31/HDB1/D1
P30/HDB0/D0
PB2/XDB2
PB3/XDB3
P10/A0
P11/A1
P12/A2
P13/A3
FTCI/KEYIN0/P60
FTOA/KEYIN1/P61
FTIA/KEYIN2/P62
FTIB/KEYIN3/P63
KEYIN11/PA3
KEYIN10/PA2
FTIC/KEYIN4/P64
FTID/KEYIN5/P65
FTOB/IRQ6/KEYIN6/P66
IRQ7/KEYIN7/P67
AVref
AVCC
AN0/P70
AN1/P71
AN2/P72
AN3/P73
AN4/P74
AN5/P75
DA0/AN6/P76
DA1/AN7/P77
AVSS
KEYIN9/PA1
KEYIN8/PA0
TMCI0/P40
TMO0/P41
FP-100B, TFP-100B
(top view)
6
1.3.2 Pin Functions
(1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the
FP-100B and TFP-100B packages in each operating mode.
Table 1-2 Pin Assignments in Each Operating Mode
Pin No. Expanded Modes Single-Chip Mode Flash
Mode 3 EPROM Memory
FP-100B, PROM PROM
TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode
1RES RES RES RES VPP RES
2 XTAL XTAL XTAL XTAL NC XTAL
3 EXTAL EXTAL EXTAL EXTAL NC EXTAL
4V
CCBV
CCBV
CCBV
CCBV
CC VCC
5MD
1MD1MD1MD1VSS VSS
6MD
0MD0MD0MD0VSS VSS
7NMI NMI NMI NMI EA9FA9
8STBY STBY/FVPP STBY/FVPP STBY/FVPP VSS FVPP
9V
CC VCC VCC VCC VCC VCC
10 PA7/KEYIN15 PA7/KEYIN15 PA7/KEYIN15 PA7/KEYIN15 NC NC
11 PA6/KEYIN14 PA6/KEYIN14 PA6/KEYIN14 PA6/KEYIN14 NC NC
12 P52/SCK0P52/SCK0P52/SCK0P52/SCK0NC NC
13 P51/RxD0P51/RxD0P51/RxD0P51/RxD0NC NC
14 P50/TxD0P50/TxD0P50/TxD0P50/TxD0NC NC
15 VSS VSS VSS VSS VSS VSS
16 P97/WAIT/SDA P97/WAIT/SDA P97/SDA P97/SDA NC VCC
17øøP9
6
/ø P96/ø NC NC
18 AS AS P95P95NC FA16
19 WR WR P94P94NC FA15
20 PA5/KEYIN13 PA5/KEYIN13 PA5/KEYIN13 PA5/KEYIN13 NC NC
21 PA4/KEYIN12 PA4/KEYIN12 PA4/KEYIN12 PA4/KEYIN12 NC NC
22 RD RD P93P93NC WE
23 P92/IRQ0P92/IRQ0P92/IRQ0P92/IRQ0PGM VSS
Note: Pins marked NC should be left unconnected.
For details on PROM mode, refer to 18.2, PROM Mode, 19.6, Flash Memory PROM Mode
(H8/3434F) and 20.6, Flash Memory PROM Mode (H8/3437F).
In this chip, the same pin is used for STBY and FVpp. When this pin is driven low, a transition
is made to hardware standby mode. This occurs not only in the normal operating modes
(modes 1, 2, and 3), but also when programming flash memory with a PROM writer.
Therefore, a PROM writer should be used whose specifications provide for this pin to be held
at the Vcc level except when programming (FVpp = 12 V).
7
Table 1-2 Pin Assignments in Each Operating Mode (cont)
Pin No. Expanded Modes Single-Chip Mode Flash
Mode 3 EPROM Memory
FP-100B, PROM PROM
TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode
24 P91/IRQ1when HIF is disabled or STAC bit is 0 in STCR; EA15 VCC
EIOW/IRQ1when HIF is enabled and STAC bit is 1 in STCR
25 P90/IRQ2/ADTRG when HIF is disabled or STAC bit is 0 in STCR; EA16 VCC
ECS2/IRQ2when HIF is enabled and STAC bit is 1 in STCR
26 P60/FTCI/ P60/FTCI/ P60/FTCI/ P60/FTCI/ NC NC
KEYIN0KEYIN0KEYIN0KEYIN0
27 P61/FTOA/ P61/FTOA P61/FTOA P61/FTOA NC NC
KEYIN1KEYIN1KEYIN1KEYIN1
28 P62/FTIA/ P62/FTIA/ P62/FTIA/ P62/FTIA/ NC NC
KEYIN2KEYIN2KEYIN2KEYIN2
29 P63/FTIB/ P63/FTIB/ P63/FTIB/ P63/FTIB/ VCC VCC
KEYIN3KEYIN3KEYIN3KEYIN3
30 PA3/KEYIN11 PA3/KEYIN11 PA3/KEYIN11 PA3/KEYIN11 NC NC
31 PA2/KEYIN10 PA2/KEYIN10 PA2/KEYIN10 PA2/KEYIN10 NC NC
32 P64/FTIC/ P64/FTIC/ P64/FTIC/ P64/FTIC/ VCC VCC
KEYIN4KEYIN4KEYIN4KEYIN4
33 P65/FTID/ P65/FTID/ P65/FTID/ P65/FTID/ NC NC
KEYIN5KEYIN5KEYIN5KEYIN5
34 P66/FTOB/ P66/FTOB/ P66/FTOB/ P66/FTOB/ NC NC
IRQ6/KEYIN6IRQ6/KEYIN6IRQ6/KEYIN6IRQ6/KEYIN6
35 P67/IRQ7/P6
7
/IRQ7/P6
7
/IRQ7/P6
7
/IRQ7/NC V
SS
KEYIN7KEYIN7KEYIN7KEYIN7
36 AVref AVref AVref AVref VCC VSS
37 AVCC AVCC AVCC AVCC VCC VCC
38 P70/AN0P70/AN0P70/AN0P70/AN0NC NC
39 P71/AN1P71/AN1P71/AN1P71/AN1NC NC
40 P72/AN2P72/AN2P72/AN2P72/AN2NC NC
41 P73/AN3P73/AN3P73/AN3P73/AN3NC NC
42 P74/AN4P74/AN4P74/AN4P74/AN4NC NC
43 P75/AN5P75/AN5P75/AN5P75/AN5NC NC
44 P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0NC NC
Note: Pins marked NC should be left unconnected.
For details on PROM mode, refer to 18.2, PROM Mode, 19.6, Flash Memory PROM Mode
(H8/3434F) and 20.6, Flash Memory PROM Mode (H8/3437F).
8
Table 1-2 Pin Assignments in Each Operating Mode (cont)
Pin No. Expanded Modes Single-Chip Mode Flash
Mode 3 EPROM Memory
FP-100B, PROM PROM
TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode
45 P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1NC NC
46 AVSS AVSS AVSS AVSS VSS VSS
47 PA1/KEYIN9PA1/KEYIN9PA1/KEYIN9PA1/KEYIN9NC NC
48 PA0/KEYIN8PA0/KEYIN8PA0/KEYIN8PA0/KEYIN8NC NC
49 P40/TMCI0P40/TMCI0P40/TMCI0P40/TMCI0NC NC
50 P41/TMO0P41/TMO0P41/TMO0P41/TMO0NC NC
51 P42/TMRI0P42/TMRI0P42/TMRI0P42/TMRI0NC NC
52 P43/TMCI1/P4
3
/TMCI1/P4
3
/TMCI1HIRQ11/TMCI1NC NC
HIRQ11*HIRQ11*
53 P44/TMO1/P4
4
/TMO1/P4
4
/TMO1HIRQ1/TMO1NC NC
HIRQ1*HIRQ1*
54 P45/TMRI1/P4
5
/TMRI1/P4
5
/TMRI1HIRQ12/TMRI1NC NC
HIRQ12*HIRQ12*
55 P46/PW0P46/PW0P46/PW0P46/PW0NC NC
56 P47/PW1P47/PW1P47/PW1P47/PW1NC NC
57 PB7/XDB7** PB7/XDB7** PB7PB7NC NC
58 PB6/XDB6** PB6/XDB6** PB6PB6NC NC
59 VCC VCC VCC VCC VCC VCC
60 A15 P27/A15 P27P27CE CE
61 A14 P26/A14 P26P26EA14 FA14
62 A13 P25/A13 P25P25EA13 FA13
63 A12 P24/A12 P24P24EA12 FA12
64 A11 P23/A11 P23P23EA11 FA11
65 A10 P22/A10 P22P22EA10 FA10
66 A9P21/A9P21P21OE OE
67 A8P20/A8P20P20EA8FA8
68 PB5/XDB5** PB5/XDB5** PB5PB5NC NC
69 PB4/XDB4** PB4/XDB4** PB4PB4NC NC
70 VSS VSS VSS VSS VSS VSS
Note: Pins marked NC should be left unconnected.
For details on PROM mode, refer to 18.2, PROM Mode, 19.6, Flash Memory PROM Mode
(H8/3434F), and 20.6, Flash Memory PROM Mode (H8/3437F).
*Differs as in mode 3, depending on whether the host interface is enabled or disabled.
** XDB7to XDB6can only be used when the host interface is enabled.
9
Table 1-2 Pin Assignments in Each Operating Mode (cont)
Pin No. Expanded Modes Single-Chip Mode Flash
Mode 3 EPROM Memory
FP-100B, PROM PROM
TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode
71 VSS VSS VSS VSS VSS VSS
72 A7P17/A7P17P17EA7FA7
73 A6P16/A6P16P16EA6FA6
74 A5P15/A5P15P15EA5FA5
75 A4P14/A4P14P14EA4FA4
76 A3P13/A3P13P13EA3FA3
77 A2P12/A2P12P12EA2FA2
78 A1P11/A1P11P11EA1FA1
79 A0P10/A0P10P10EA0FA0
80 PB3/XDB3** PB3/XDB3** PB3PB3NC NC
81 PB2/XDB2** PB2/XDB2** PB2PB2NC NC
82 D0D0P30HDB0EO0FO0
83 D1D1P31HDB1EO1FO1
84 D2D2P32HDB2EO2FO2
85 D3D3P33HDB3EO3FO3
86 D4D4P34HDB4EO4FO4
87 D5D5P35HDB5EO5FO5
88 D6D6P36HDB6EO6FO6
89 D7D7P37HDB7EO7FO7
90 PB1/XDB1** PB1/XDB1** PB1PB1NC NC
91 PB0/XDB0** PB0/XDB0** PB0PB0NC NC
92 VSS VSS VSS VSS VSS VSS
93 P80/HA0*P80/HA0*P80HA0NC NC
94 P81/GA20*P81/GA20*P81P81/GA20 NC NC
95 P82/CS1*P82/CS1*P82CS1NC NC
96 P83/IOR*P83/IOR*P83IOR NC NC
Note: Pins marked NC should be left unconnected.
For details on PROM mode, refer to 18.2, PROM Mode, 19.6, Flash Memory PROM Mode
(H8/3434F) and 20.6, Flash Memory PROM Mode (H8/3437F).
*Differs as in mode 3, depending on whether the host interface is enabled or disabled.
** XDB7to XDB6can only be used when the host interface is enabled.
10
Table 1-2 Pin Assignments in Each Operating Mode (cont)
Pin No. Expanded Modes Single-Chip Mode Flash
Mode 3 EPROM Memory
FP-100B, PROM PROM
TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Mode Mode
97 P84/IRQ3/TxD1when HIF is disabled or STAC bit is 1 in STCR; NC NC
IOW/IRQ3when HIF is enabled and STAC bit is 0 in STCR
98 P85/IRQ4/RxD1when HIF is disabled or STAC bit is 1 in STCR; NC NC
CS2/IRQ4when HIF is enabled and STAC bit is 0 in STCR
99 P86/SCK1/P8
6
/SCK1/P8
6
/SCK1/P8
6
/SCK1/NC NC
IRQ5/SCL IRQ5/SCL IRQ5/SCL IRQ5/SCL
100 RESO RESO RESO RESO NC NC
Note: Pins marked NC should be left unconnected.
For details on PROM mode, refer to 18.2, PROM Mode, 19.6, Flash Memory PROM Mode
(H8/3434F) and 20.6, Flash Memory PROM Mode (H8/3437F).
11
(2) Pin Functions: Table 1-3 gives a concise description of the function of each pin.
Table 1-3 Pin Functions
Pin No.
FP-100B,
Type Symbol TFP-100B I/O Name and Function
Power VCC 9, 59 I Power: Connected to the power supply. Connect
both VCC pins to the system power supply.
VCCB4 II/O buffer power supply: Power supply for
input/output buffers at pins P86, P97, and PA4to
PA7.
VSS 15, 70, 71 I Ground: Connected to ground (0 V). Connect all
92 VSS pins to system ground (0 V).
Clock XTAL 2 I Crystal: Connected to a crystal oscillator. The crystal
frequency should be the same as the desired system
clock frequency. If an external clock is input at the
EXTAL pin, a reverse-phase clock should be input at
the XTAL pin.
EXTAL 3 I External crystal: Connected to a crystal oscillator or
external clock. The frequency of the external clock
should be the same as the desired system clock
frequency. See section 6.2, Oscillator Circuit, for
examples of connections to a crystal and external
clock.
ø17OSystem clock: Supplies the system clock to
peripheral devices.
System RES 1IReset: A low input causes the chip to reset.
control RESO 100 O Reset output: Outputs a reset signal to external
devices.
STBY 8IStandby: A transition to the hardware standby mode
(a power-down state) occurs when a low input is
received at the STBY pin.
Address bus A15 to A060 to 67, O Address bus: Address output pins.
72 to 79
Data bus D7to D089 to 82 I/O Data bus: 8-bit bidirectional data bus.
12
Table 1-3 Pin Functions (cont)
Pin No.
FP-100B,
Type Symbol TFP-100B I/O Name and Function
Bus control WAIT 16 I Wait: Requests the CPU to insert wait states into the
bus cycle when an external address is accessed.
RD 22 O Read: Goes low to indicate that the CPU is reading
an external address.
WR 19 O Write: Goes low to indicate that the CPU is writing to
an external address.
AS 18 O Address strobe: Goes low to indicate that there is a
valid address on the address bus.
Interrupt NMI 7INonmaskable interrupt: Highest-priority interrupt
signals request. The NMIEG bit in the system control register
(SYSCR) determines whether the interrupt is
recognized at the rising or falling edge of the NMI
input.
IRQ0to 23 to 25, I Interrupt request 0 to 7: Maskable interrupt
IRQ797 to 99, request pins.
34, 35
MD15IMode: Input pins for setting the MCU mode
MD06 operating mode according to the table below.
MD1MD0Mode Description
0 1 Mode 1 Expanded mode with
on-chip ROM disabled
1 0 Mode 2 Expanded mode with
on-chip ROM enabled
1 1 Mode 3 Single-chip mode
16-bit free- FTOA 27 O FRT output compare A and B: Output pins
running FTOB 34 controlled by comparators A and B of the free-
timer running timer.
(FRT) FTCI 26 I FRT counter clock input: Input pin for an external
clock signal for the free-running timer.
FTIA to 28, 29, 32, I FRT input capture A to D: Input capture pins for the
FTID 33 free-running timer.
13
Operating
mode
control
Table 1-3 Pin Functions (cont)
Pin No.
FP-100B,
Type Symbol TFP-100B I/O Name and Function
8-bit timer TMO050 O 8-bit timer output (channels 0 and 1):
TMO153 Compare-match output pins for the 8-bit timers.
TMCI049 I 8-bit timer counter clock input (channels 0
TMCI152 and 1): External clock input pins for the 8-bit timer
counters.
TMRI051 I 8-bit timer counter reset input (channels 0
TMRI154 and 1): A high input at these pins resets the 8-bit
timer counters.
PWM timer PW055 O PWM timer output (channels 0 and 1): Pulse-
PW156 width modulation timer output pins.
Serial TxD014 O Transmit data (channels 0 and 1): Data output
communi- TxD197 pins for the serial communication interface.
cation RxD013 I Receive data (channels 0 and 1): Data input
interface RxD198 pins for the serial communication interface.
(SCI) SCK012 I/O Serial clock (channels 0 and 1): Input/output
SCK199 pins for the serial clock.
Host interface HDB0to 82 to 89 I/O Host interface data bus: 8-bit bidirectional bus by
(HIF) HDB7which a host processor accesses the host interface.
CS1, CS295, 98 I Chip select 1 and 2: Input pins for selecting host
interface channels 1 and 2.
IOR 96 I I/O read: Read strobe input pin for the host interface.
IOW 97 I I/O write: Write strobe input pin for the host
interface.
HA093 I Command/data: Input pin indicating data access or
command access.
GA20 94 O Gate A20: A20 gate control signal output pin.
HIRQ153 O Host interrupts 1, 11, and 12: Output pins for
HIRQ11 52 interrupt request signals to the host processor.
HIRQ12 54
Keyboard KEYIN0to 26 to 29, I Keyboard input: Input pins from a matrix keyboard.
control KEYIN15 32 to 35, (Keyboard scan signals are normally output from
48, 47, P10to P17and P20to P27, allowing a maximum
31, 30, 16 ×16 key matrix. The number of keys can be
21, 20, further increased by use of other output ports.)
11, 10
14
Table 1-3 Pin Functions (cont)
Pin No.
FP-100B,
Type Symbol TFP-100B I/O Name and Function
Host interface XDB0to 91, 90, 81, I/O Host interface data bus: 8-bit bidirectional bus by
(expanded XDB780, 69, 68, which a host processor accesses the host interface.
modes) 58, 57
Host interface ECS225 I Host chip select 2: Input pin for selecting host
(if enabled interface channel 2.
when STAC EIOW 24 I I/O write: Write strobe input pin for the host
bit is 1 in interface.
STCR)
A/D AN7to 38 to 45 I Analog input: Analog signal input pins for the A/D
converter AN0converter.
ADTRG 25 I A/D trigger: External trigger input for starting the A/D
converter.
D/A DA044 O Analog output: Analog signal output pins for the D/A
converter DA145 converter.
A/D and D/A AVCC 37 I Analog reference voltage: Reference voltage pin
converters for the A/D and D/A converters. If the A/D and D/A
converters are not used, connect AVCC to the system
power supply.
AVSS 46 I Analog ground: Ground pin for the A/D and D/A
converters. Connect to system ground (0 V).
AVref 36 I Analog reference voltage: Analog reference
voltage input pins for A/D and D/A converters.
Flash FVPP 8IProgramming power supply for on-board
memory programming: Connect to a flash memory
[H8/3434, programming power supply (+12 V)
H8/3437
F-ZTAT]
I2C bus SCL 99 I/O I2C clock I/O: Input/output pin for I2C clock. Power is
interface supplied by I/O buffer power supply VCCB. Features
[option] a bus drive function.
SDA 16 I/O I2C data I/O: Input/output pin for I2C data. Power is
supplied by I/O buffer power supply VCCB. Features
a bus drive function.
15
Table 1-3 Pin Functions (cont)
Pin No.
FP-100B,
Type Symbol TFP-100B I/O Name and Function
I/O ports P17to P1072 to 79 I/O Port 1: An 8-bit input/output port with programmable
MOS input pull-ups and LED driving capability. The
direction of each bit can be selected in the port 1
data direction register (P1DDR).
P27to P2060 to 67 I/O Port 2: An 8-bit input/output port with programmable
MOS input pull-ups and LED driving capability. The
direction of each bit can be selected in the port 2
data direction register (P2DDR).
P37to P3089 to 82 I/O Port 3: An 8-bit input/output port with programmable
MOS input pull-ups. The direction of each bit can be
selected in the port 3 data direction register
(P3DDR).
P47to P4056 to 49 I/O Port 4: An 8-bit input/output port. The direction of
each bit can be selected in the port 4 data direction
register (P4DDR).
P52to P5012 to 14 I/O Port 5: A 3-bit input/output port. The direction of
each bit can be selected in the port 5 data direction
register (P5DDR).
P67to P6035 to 32, I/O Port 6: An 8-bit input/output port with programming
29 to 26 MOS input pull-ups. The direction of each bit can be
selected in the port 6 data direction register
(P6DDR).
P77to P7045 to 38 I Port 7: An 8-bit input port.
P86to P8099 to 93 I/O Port 8: A 7-bit input/output port. The direction of
each bit can be selected in the port 8 data direction
register (P8DDR). P86is powered by I/O buffer
power supply VCCB.
P97to P9016 to 19, I/O Port 9: An 8-bit input/output port. The direction of
22 to 25 each bit (except for P96) can be selected in the port 9
data direction register (P9DDR). P97is powered by
I/O buffer power supply VCCB.
PA7to PA010, 11, 20, I/O Port A: An 8-bit input/output port with programming
21, 30, 31, MOS input pull-ups. The direction of each bit
47, 48 can be selected in the port A data direction register
(PADDR). PA7to PA4are powered by I/O buffer
power supply VCCB. Features a bus drive function.
PB7to PB057, 58, 68, I/O Port B: An 8-bit input/output port with programming
69, 80, 81, MOS input pull-ups. The direction of each bit can be
90, 91 selected in the port B data direction register
(PBDDR).
Note: In this chip, the same pin is used for STBY and FVpp. When this pin is driven low, a transition
is made to hardware standby mode. This occurs not only in the normal operating modes
(modes 1, 2, and 3), but also when programming flash memory with a PROM writer.
Therefore, a PROM writer should be used whose specifications provide for this pin to be held
at the Vcc level except when programming (FVpp = 12 V).
16
Section 2 CPU
2.1 Overview
The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also
configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed
operation.
2.1.1 Features
The main features of the H8/300 CPU are listed below.
• Two-way register configuration
— Sixteen 8-bit general registers, or
— Eight 16-bit general registers
• Instruction set with 57 basic instructions, including:
— Multiply and divide instructions
— Powerful bit-manipulation instructions
• Eight addressing modes
— Register direct (Rn)
— Register indirect (@Rn)
— Register indirect with displacement (@(d:16, Rn))
— Register indirect with post-increment or pre-decrement (@Rn+ or @–Rn)
— Absolute address (@aa:8 or @aa:16)
— Immediate (#xx:8 or #xx:16)
— PC-relative (@(d:8, PC))
— Memory indirect (@@aa:8)
• Maximum 64-kbyte address space
• High-speed operation
— All frequently-used instructions are executed in two to four states
• Maximum clock rate (ø clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz at 3 V
— 8- or 16-bit register-register add or subtract: 125 ns (16 MHz), 167 ns (12 MHz),
200 ns (10 MHz)
—8 ×8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)
— 16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)
• Power-down mode
— SLEEP instruction
17
2.1.2 Address Space
The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code
and data combined. The memory map differs depending on the mode (mode 1, 2, or 3). For details,
see section 3.4, Address Space Map in Each Operating Mode.
2.1.3 Register Configuration
Figure 2-1 shows the internal register structure of the H8/300 CPU. There are two groups of
registers: the general registers and control registers.
Figure 2-1 CPU Registers
7070
15 0
PC
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
(SP) SP: Stack pointer
PC: Program counter
CCR: Condition code register
Carry flag
Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit
CCR I U H U N Z V C
General registers (Rn)
Control registers
75321064
18
2.2 Register Descriptions
2.2.1 General Registers
All the general registers can be used as both data registers and address registers. When used as
address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as
data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed
separately as 8-bit registers (R0H to R7H and R0L to R7L).
R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and
subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As
indicated in figure 2-2, R7 (SP) points to the top of the stack.
Figure 2-2 Stack Pointer
2.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the
PC is ignored (always regarded as 0).
(2) Condition Code Register (CCR): This 8-bit register contains internal status information,
including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt
mask bit (I).
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked.
This bit is set to 1 automatically by a reset and at the start of interrupt handling.
Unused area
Stack area
SP (R7)
19
Bit 6—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC,
ORC, and XORC instructions).
Bit 5—Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B,
NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise.
Similarly, it is set to 1 when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow
out of bit 11, and cleared to 0 otherwise. It is used implicitly in the DAA and DAS instructions.
Bit 4—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC,
ORC, and XORC instructions).
Bit 3—Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): This flag is set to 1 to indicate a zero result and cleared to 0 to indicate a
nonzero result.
Bit 1—Overflow Flag (V): This flag is set to 1 when an arithmetic overflow occurs, and cleared to
0 at other times.
Bit 0—Carry Flag (C): This flag is used by:
• Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the
result
• Shift and rotate instructions, to store the value shifted out of the most significant or least
significant bit
• Bit manipulation and bit load instructions, as a bit accumulator
The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR,
and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in conditional
branching instructions (BCC).
For the action of each instruction on the flag bits, see the H8/300 Series Programming Manual.
2.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt
mask bit (I) in the CCR is set to 1. The other CCR bits and the general registers are not initialized.
In particular, the stack pointer (R7) is not initialized. The stack pointer and CCR should be
initialized by software, by the first instruction executed after a reset.
20
2.3 Data Formats
The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data.
• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte
operand.
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed
BCD form. Each nibble of the byte is treated as a decimal digit.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits ×8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
21
2.3.1 Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2-3.
Figure 2-3 Register Data Formats
76543210 Don’t care
Data Type Register No. Data Format
70
1-bit data RnH
76543210
Don’t care 70
1-bit data RnL
MSB LSB Don’t care
70
Byte data RnH
Byte data RnL
Word data Rn
4-bit BCD data RnH
4-bit BCD data RnL
Legend
RnH:
RnL:
MSB:
LSB:
Upper digit of general register
Lower digit of general register
Most significant bit
Least significant bit
MSB LSB
Don’t care 70
MSB LSB
15 0
Upper digit Lower digit Don’t care
7034
Don’t care Upper digit Lower digit
70
34
22
2.3.2 Memory Data Formats
Figure 2-4 indicates the data formats in memory.
Word data stored in memory must always begin at an even address. In word access the least
significant bit of the address is regarded as 0. If an odd address is specified, no address error occurs
but the access is performed at the preceding even address. This rule affects MOV.W instructions
and branching instructions, and implies that only even addresses should be stored in the vector table.
Figure 2-4 Memory Data Formats
When the stack is addressed by register R7, it must always be accessed a word at a time. When the
CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word.
When they are restored, the lower byte is ignored.
Data Format
76543210
AddressData Type
70
Address n
MSB LSB
MSB
LSB
Upper 8 bits
Lower 8 bits
MSB LSBCCR
CCR*
MSB
LSB
MSB LSB
Address n
Even address
Odd address
Even address
Odd address
Even address
Odd address
1-bit data
Byte data
Word data
Byte data (CCR) on stack
Word data on stack
Note: * Ignored on return
Legend
CCR: Condition code register
23
2.4 Addressing Modes
2.4.1 Addressing Mode
The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these
addressing modes.
Table 2-1 Addressing Modes
No. Addressing Mode Symbol
(1) Register direct Rn
(2) Register indirect @Rn
(3) Register indirect with displacement @(d:16, Rn)
(4) Register indirect with post-increment @Rn+
Register indirect with pre-decrement @–Rn
(5) Absolute address @aa:8 or @aa:16
(6) Immediate #xx:8 or #xx:16
(7) Program-counter-relative @(d:8, PC)
(8) Memory indirect @@aa:8
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand. In most cases the general register is accessed as an 8-bit register.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits ×8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register
containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in MOV
instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4)
which is added to the contents of the specified general register to obtain the operand address. For
the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
• Register indirect with Post-Increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is incremented after the operand is accessed. The size of the increment is
1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the
original contents of the 16-bit general register must be even.
24
• Register Indirect with Pre-Decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is decremented before the operand is accessed. The size of the decrement
is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the
original contents of the 16-bit general register must be even.
(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx. The
upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to
65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.
(6) Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or a
16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate
values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit
manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the
instruction, specifying a bit number.
(7) Program-Counter-Relative—@(d:8, PC): This mode is used to generate branch addresses in
the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-
extended value to the program counter contents. The result must be an even number. The possible
branching range is –126 to +128 bytes (–63 to +64 words) from the current address.
(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0 to
255). The word located at this address contains the branch address. The upper 8 bits of the absolute
address are 0 (H'00), thus the branch address is limited to values from 0 to 255 (H'0000 to H'00FF).
Note that some of the addresses in this range are also used in the vector table. Refer to section 3.4,
Address Space Map in Each Operating Mode.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See section 2.3.2, Memory Data Formats, for further
information.
25
2.4.2 Calculation of Effective Address
Table 2-2 shows how the H8/300 calculates effective addresses in each addressing mode.
Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX.B,
SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also use immediate addressing (6).
The MOV instruction uses all the addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute (5)
addressing to identify a byte operand, and 3-bit immediate addressing to identify a bit within the
byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1)
to identify the bit.
26
Table 2-2 Effective Address Calculation
Addressing Mode and
Instruction Format
op reg
76 34015
No. Effective Address Calculation Effective Address
1 Register direct, Rn
Operands are contained in registers regm
and regn
Register indirect, @Rn 16-bit register contents 015
Register indirect with displacement,
@(d:16, Rn)
op regm regn
87 34015
op reg
76 34015
disp
op reg
76 34015
Register indirect with
post-increment, @Rn+
op reg
76 34015
Register indirect with pre-decrement,
@–Rn
2
3
4
1 for a byte operand, 2 for a word operand
015
disp
015
015
015
1 or 2
015
015
1 or 2
015
regm
30regn
30
16-bit register contents
16-bit register contents
16-bit register contents
*
*
*Note:
27
Table 2-2 Effective Address Calculation (cont)
Addressing Mode and
Instruction Format No. Effective Address Calculation Effective address
5 Absolute address
@aa:8
Operand is 1- or 2-byte immediate data
@aa:16
op 87 015
op 015
IMM
op disp
7015
PC-relative
@(d:8, PC)
6
7
015
PC contents 015
015
abs
H'FF 87 015
015
abs
op
#xx:16
op 87 015 IMM
Immediate
#xx:8
8Sign extension disp
28
Table 2-2 Effective Address Calculation (cont)
Addressing Mode and
Instruction Format No. Effective Address Calculation Effective Address
8 Memory indirect, @@aa:8
op 87 015
Memory contents (16 bits) 015
abs
H'00
87 015
Legend
reg:
op:
disp:
IMM:
abs:
General register
Operation code
Displacement
Immediate data
Absolute address
29
2.5 Instruction Set
The H8/300 CPU has 57 types of instructions, which are classified by function in table 2-3.
Table 2-3 Instruction Classification
Function Instructions Types
Data transfer MOV, MOVTPE*3, MOVFPE*3, PUSH*1, POP*13
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, 14
DAA, DAS, MULXU, DIVXU, CMP, NEG
Logic operations AND, OR, XOR, NOT 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, 8
ROTXR
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, 14
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
Branch Bcc*2, JMP, BSR, JSR, RTS 5
System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8
Block data transfer EEPMOV 1
Total 57
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn.
2. Bcc is a conditional branch instruction in which cc represents a condition code.
3. Not supported by the H8/3437 Series.
The following sections give a concise summary of the instructions in each category, and indicate the
bit patterns of their object code. The notation used is defined next.
Operation Notation
30
Rd General register (destination)
Rs General register (source)
Rn General register
(EAd) Destination operand
(EAs) Source operand
SP Stack pointer
PC Program counter
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
#imm Immediate data
#xx:3 3-Bit immediate data
#xx:8 8-Bit immediate data
#xx:16 16-Bit immediate data
disp Displacement
+ Addition
– Subtraction
×Multiplication
÷ Division
∧AND logical
∨OR logical
⊕Exclusive OR logical
→Move
¬ Not
2.5.1 Data Transfer Instructions
Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats.
Table 2-4 Data Transfer Instructions
Instruction Size*Function
MOV B/W (EAs) →Rd, Rs →(EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and
@Rn+ addressing modes are available for byte or word data. The
@aa:8 addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not specify
byte size for these two modes.
MOVTPE B Not supported by the H8/3437 Series.
MOVFPE B Not supported by the H8/3437 Series.
PUSH W Rn →@–SP
Pushes a 16-bit general register onto the stack. Equivalent to MOV.W
Rn, @–SP.
POP W @SP+ →Rn
Pops a 16-bit general register from the stack. Equivalent to MOV.W
@SP+, Rn.
Note: *Size: Operand size
B: Byte
W: Word
31
Figure 2-5 Data Transfer Instruction Codes
15 087
op rm rn MOV
Rm→Rn
15 087
op rm rn @Rm←→Rn
15 087
op rm rn @(d:16, Rm)←→Rn
disp
15 087
op rm rn @Rm+→Rn, or
Rn→@–Rm
15 087
op rn abs @aa:8←→Rn
15 087
op rn @aa:16←→Rn
abs
15 087
op rn IMM #xx:8→Rn
15 087
op rn #xx:16→Rn
IMM
15 087
op rn POP, PUSH
Legend
op:
rm, rn:
disp:
abs:
IMM:
Operation field
Register field
Displacement
Absolute address
Immediate data
15 087
op rn MOVFPE, MOVTPE
abs
32
2.5.2 Arithmetic Operations
Table 2-5 describes the arithmetic instructions. See figure 2-6 in section 2.5.4, Shift Operations, for
their object codes.
Table 2-5 Arithmetic Instructions
Instruction Size*Function
ADD B/W Rd ± Rs →Rd, Rd + #imm →Rd
SUB Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data
can be added or subtracted only when both words are in general
registers.
ADDX B Rd ± Rs ± C →Rd, Rd ± #imm ± C →Rd
SUBX Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data
and data in a general register.
INC B Rd ± #1 →Rd
DEC Increments or decrements a general register.
ADDS W Rd ± #imm →Rd
SUBS Adds or subtracts immediate data to or from data in a general
register. The immediate data must be 1 or 2.
DAA B Rd decimal adjust →Rd
DAS Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR.
MULXU B Rd ×Rs →Rd
Performs 8-bit ×8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
DIVXU B Rd ÷ Rs →Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
CMP B/W Rd – Rs, Rd – #imm
Compares data in a general register with data in another general
register or with immediate data. Word data can be compared only
between two general registers.
NEG B 0 – Rd →Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register.
Note: *Size: Operand size
B: Byte
W: Word
33
2.5.3 Logic Operations
Table 2-6 describes the four instructions that perform logic operations. See figure 2-6 in
section 2.5.4, Shift Operations, for their object codes.
Table 2-6 Logic Operation Instructions
Instruction Size*Function
AND B Rd ∧Rs →Rd, Rd ∧#imm →Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B Rd ∨Rs →Rd, Rd ∨#imm →Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B Rd ⊕Rs →Rd, Rd ⊕#imm →Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B ¬ (Rd) →(Rd)
Obtains the one’s complement (logical complement) of general register
contents.
Note: *Size: Operand size
B: Byte
2.5.4 Shift Operations
Table 2-7 describes the eight shift instructions. Figure 2-6 shows the object code formats of the
arithmetic, logic, and shift instructions.
Table 2-7 Shift Instructions
Instruction Size*Function
SHAL B Rd shift →Rd
SHAR Performs an arithmetic shift operation on general register contents.
SHLL B Rd shift →Rd
SHLR Performs a logical shift operation on general register contents.
ROTL B Rd rotate →Rd
ROTR Rotates general register contents.
ROTXL B Rd rotate through carry →Rd
ROTXR Rotates general register contents through the C (carry) bit.
Note: *Size: Operand size
B: Byte
34
Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes
15 087
op rm rn ADD, SUB, CMP,
ADDX, SUBX (Rm)
Legend
op:
rm, rn:
IMM:
Operation field
Register field
Immediate data
15 087
op rn ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
15 087
op rn MULXU, DIVXU
rm
15 087
rn IMM ADD, ADDX, SUBX,
CMP (#xx:8)
op
15 087
op rn AND, OR, XOR (Rm)
rm
15 087
rn IMM AND, OR, XOR (#xx:8)
op
15 087 rn SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
op
35
2.5.5 Bit Manipulations
Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats.
Table 2-8 Bit-Manipulation Instructions
Instruction Size*Function
BSET B 1 →(<bit no.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit is
specified by a bit number, given in 3-bit immediate data or the lower three
bits of a general register.
BCLR B 0 →(<bit no.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit is
specified by a bit number, given in 3-bit immediate data or the lower three
bits of a general register.
BNOT B ¬ (<bit no.> of <EAd>) →(<bit no.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit is specified
by a bit number, given in 3-bit immediate data or the lower three bits of a
general register
BTST B ¬ (<bit no.> of <EAd>) →Z
Tests a specified bit in a general register or memory and sets or clears
the Z flag accordingly. The bit is specified by a bit number, given in
3-bit immediate data or the lower three bits of a general register.
BAND B C ∧(<bit no.> of <EAd>) →C
ANDs the C flag with a specified bit in a general register or memory.
BIAND C ∧[¬ (<bit no.> of <EAd>)] →C
ANDs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
BOR B C ∨(<bit no.> of <EAd>) →C
ORs the C flag with a specified bit in a general register or memory.
BIOR C ∨[¬ (<bit no.> of <EAd>)] →C
ORs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
BXOR B C ⊕(<bit no.> of <EAd>) →C
XORs the C flag with a specified bit in a general register or memory.
Note: *Size: Operand size
B: Byte
36
Table 2-8 Bit-Manipulation Instructions (cont)
Instruction Size*Function
BIXOR B C ⊕¬ [(<bit no.> of <EAd>)] →C
XORs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
BLD B (<bit no.> of <EAd>) →C
Copies a specified bit in a general register or memory to the C flag.
BILD ¬ (<bit no.> of <EAd>) →C
Copies the inverse of a specified bit in a general register or memory to
the C flag.
The bit number is specified by 3-bit immediate data.
BST B C →(<bit no.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
BIST ¬ C →(<bit no.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
Note: *Size: Operand size
B: Byte
Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-modify-
write instructions. They read a byte of data, modify one bit in the byte, then write the byte back.
Care is required when these instructions are applied to registers with write-only bits and to the I/O
port registers.
Step Description
1 Read Read one data byte at the specified address
2 Modify Modify one bit in the data byte
3 Write Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under the
following conditions.
P47: Input pin, low
P46: Input pin, high
P45– P40: Output pins, low
The intended purpose of this BCLR instruction is to switch P40from output to input.
37
Before Execution of BCLR Instruction
P47P46P45P44P43P42P41P40
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
DDR 00111111
DR 10000000
Execution of BCLR Instruction
BCLR #0, @P4DDR ;clear bit 0 in data direction register
After Execution of BCLR Instruction
P47P46P45P44P43P42P41P40
Input/output Output Output Output Output Output Output Output Input
Pin state Low High Low Low Low Low Low High
DDR 11111110
DR 10000000
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR
is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to 0, making P40an input pin. In addition, P47DDR and P46DDR
are set to 1, making P47and P46output pins.
38
Figure 2-7 Bit Manipulation Instruction Codes (1)
15 087
op IMM rn Operand:
Bit no.:
Legend
op:
rm, rn:
abs:
IMM:
Operation field
Register field
Absolute address
Immediate data
15 087
op rn
BSET, BCLR, BNOT, BTST
register direct (Rn)
immediate (#xx:3)
Operand:
Bit no.: register direct (Rn)
register direct (Rm)
rm
15 087
op 0 Operand:
Bit no.:
register indirect (@Rn)
immediate (#xx:3)
rn
0
0
0
0
0
0
0IMM
15 087
op 0 Operand:
Bit no.:
register indirect (@Rn)
register direct (Rm)
rn
0
0
0
0
0
0
0rmop
15 087
op Operand:
Bit no.:
absolute (@aa:8)
immediate (#xx:3)
abs
0000IMM
op
op
15 087
op Operand:
Bit no.:
absolute (@aa:8)
register direct (Rm)
abs
0000rmop
15 087
op IMM rn Operand:
Bit no.: register direct (Rn)
immediate (#xx:3)
BAND, BOR, BXOR, BLD, BST
15 087
op 0 Operand:
Bit no.:
register indirect (@Rn)
immediate (#xx:3)
rn
0
0
0
0
0
0
0IMMop
15 087
op Operand:
Bit no.:
absolute (@aa:8)
immediate (#xx:3)
abs
0000IMMop
39
Figure 2-7 Bit Manipulation Instruction Codes (2)
Legend
op:
rm, rn:
abs:
IMM:
Operation field
Register field
Absolute address
Immediate data
15 087
op IMM rn Operand:
Bit no.: register direct (Rn)
immediate (#xx:3)
BIAND, BIOR, BIXOR, BILD, BIST
15 087
op 0 Operand:
Bit no.:
register indirect (@Rn)
immediate (#xx:3)
rn
0
0
0
0
0
0
0IMMop
15 087
op Operand:
Bit no.:
absolute (@aa:8)
immediate (#xx:3)
abs
0000IMMop
40
41
2.5.6 Branching Instructions
Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats.
Table 2-9 Branching Instructions
Instruction Size Function
Bcc — Branches if condition cc is true.
Mnemonic cc field Description Condition
BRA (BT) 0 0 0 0 Always (true) Always
BRN (BF) 0 0 0 1 Never (false) Never
BHI 0 0 1 0 High C ∨Z = 0
BLS 0 0 1 1 Low or same C ∨Z = 1
BCC (BHS) 0 1 0 0 Carry clear C = 0
(High or same)
BCS (BLO) 0 1 0 1 Carry set (low) C = 1
BNE 0 1 1 0 Not equal Z = 0
BEQ 0 1 1 1 Equal Z = 1
BVC 1 0 0 0 Overflow clear V = 0
BVS 1 0 0 1 Overflow set V = 1
BPL 1 0 1 0 Plus N = 0
BMI 1 0 1 1 Minus N = 1
BGE 1 1 0 0 Greater or equal N ⊕V = 0
BLT 1 1 0 1 Less than N ⊕V = 1
BGT 1 1 1 0 Greater than Z ∨(N ⊕V) = 0
BLE 1 1 1 1 Less or equal Z ∨(N ⊕V) = 1
JMP — Branches unconditionally to a specified address.
JSR — Branches to a subroutine at a specified address.
BSR — Branches to a subroutine at a specified displacement from the current
address.
RTS — Returns from a subroutine.
Figure 2-8 Branching Instruction Codes
Legend
op:
cc:
rm:
disp:
abs:
Operation field
Condition field
Register field
Displacement
Absolute address
15 087
op cc disp Bcc
15 087
op rm 0 JMP (@Rm)
000
15 087
op JMP (@aa:16)
abs
15 087
op abs JMP (@@aa:8)
15 087
op disp BSR
15 087
op rm 0 JSR (@Rm)
000
15 087
op JSR (@aa:16)
abs
15 087
op abs JSR (@@aa:8)
15 087
op RTS
42
2.5.7 System Control Instructions
Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats.
Table 2-10 System Control Instructions
Instruction Size Function
RTE — Returns from an exception-handling routine.
SLEEP — Causes a transition to the power-down state.
LDC B Rs →CCR, #imm →CCR
Moves immediate data or general register contents to the condition code
register.
STC B CCR →Rd
Copies the condition code register to a specified general register.
ANDC B CCR ∧#imm →CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨#imm →CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕#imm →CCR
Logically exclusive-ORs the condition code register with immediate data.
NOP — PC + 2 →PC
Only increments the program counter.
Note: *Size: Operand size
B: Byte
Figure 2-9 System Control Instruction Codes
Legend
op:
rn:
IMM:
Operation field
Register field
Immediate data
15 087
op RTE, SLEEP, NOP
15 087
op rn LDC, STC (Rn)
15 087
op IMM ANDC, ORC,
XORC, LDC (#xx:8)
43
2.5.8 Block Data Transfer Instruction
Table 2-11 describes the EEPMOV instruction. Figure 2-10 shows its object code format.
Table 2-11 Block Data Transfer Instruction/EEPROM Write Operation
Instruction Size Function
EEPMOV — if R4L ≠0 then
repeat @R5+ →@R6+
R4L – 1 →R4L
until R4L = 0
else next;
Moves a data block according to parameters set in general registers R4L,
R5, and R6.
R4L: size of block (bytes)
R5: starting source address
R6: starting destination address
Execution of the next instruction starts as soon as the block transfer is
completed.
Figure 2-10 Block Data Transfer Instruction/EEPROM Write Operation Code
Legend
op: Operation field
15 087
op
op
44
Notes on EEPMOV Instruction
1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
H'FFFF
Not allowed
←R6
←R6 + R4L
R5 →
R5 + R4L →
←R6
←R6 + R4L
R5 →
R5 + R4L →
45
2.6 CPU States
2.6.1 Overview
The CPU has three states: the program execution state, exception-handling state, and power-down
state. The power-down state is further divided into three modes: sleep mode, software standby
mode, and hardware standby mode. Figure 2-11 summarizes these states, and figure 2-12 shows a
map of the state transitions.
Figure 2-11 Operating States
State Program execution state
The CPU executes successive program instructions.
Exception-handling state
A transient state triggered by a reset or interrupt. The CPU executes
a hardware sequence that includes loading the program counter from
the vector table.
Power-down state
A state in which some or
all of the chip functions are
stopped to conserve power.
Sleep mode
Software standby mode
Hardware standby mode
46
Figure 2-12 State Transitions
2.6.2 Program Execution State
In this state the CPU executes program instructions.
2.6.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or interrupted and
changes its normal processing flow. In interrupt exception handling, the CPU references the stack
pointer (R7) and saves the program counter and condition code register on the stack. For further
details see section 4, Exception Handling.
2.6.4 Power-Down State
The power-down state includes three modes: sleep mode, software standby mode, and hardware
standby mode.
(1) Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU
register contents remain unchanged and the on-chip supporting modules continue to function.
Reset state Hardware
standby mode
Interrupt request
RES = 1
Power-down state
Sleep mode
Exception-
handling state
Program
execution state
Exception
handling
request Exception
handing
SLEEP instruction
with SSBY bit set
STBY = 1, RES = 0
SLEEP
instruction
Software
standby mode
NMI, IRQ0
to IRQ2 or IRQ6
Notes: 1.
2.
A transition to the reset state occurs when RES goes low, except when the chip
is in the hardware standby mode.
A transition from any state to the hardware standby mode occurs when STBY
goes low.
47
(2) Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY
(Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-chip
supporting modules halt. The on-chip supporting modules are initialized, but the contents of the on-
chip RAM and CPU registers remain unchanged as long as a specified voltage is supplied. I/O port
outputs also remain unchanged.
(3) Hardware Standby Mode: Is entered when the input at the STBY pin goes low. All chip
functions halt, including I/O port output. The on-chip supporting modules are initialized, but on-
chip RAM contents are held.
See section 21, Power-Down State, for further information.
2.7 Access Timing and Bus Cycle
The CPU is driven by the system clock (ø). The period from one rising edge of the system clock to
the next is referred to as a “state.” Memory access is performed in a two- or three-state bus cycle.
On-chip memory, on-chip supporting modules, and external devices are accessed in different bus
cycles as described below.
2.7.1 Access to On-Chip Memory (RAM and ROM)
On-chip ROM and RAM are accessed in a cycle of two states designated T1and T2. Either byte or
word data can be accessed, via a 16-bit data bus. Figure 2-13 shows the on-chip memory access
cycle. Figure 2-14 shows the associated pin states.
48
Figure 2-13 On-Chip Memory Access Cycle
Figure 2-14 Pin States during On-Chip Memory Access Cycle
Bus cycle
T1 state T2 state
Address
ø
Address bus
AS: High
RD: High
WR: High
Data bus:
high impedance state
Bus cycle
Internal data bus (read)
Internal address bus
Internal read signal
Internal write signal
Internal data bus (write)
Address
T1 state T2 state
ø
Write data
Read data
49
2.7.2 Access to On-Chip Register Field and External Devices
The on-chip supporting module registers and external devices are accessed in a cycle consisting of
three states: T1, T2, and T3. Only one byte of data can be accessed per cycle, via an 8-bit data bus.
Access to word data or instruction codes requires two consecutive cycles (six states).
Figure 2-15 shows the access cycle for the on-chip register field. Figure 2-16 shows the associated
pin states. Figures 2-17 (a) and (b) show the read and write access timing for external devices.
Figure 2-15 On-Chip Register Field Access Cycle
Bus cycle
Internal data bus
(read)
Internal address
bus
Internal read
signal
Internal write
signal
Internal data bus
(write)
ø
Address
Write data
T1 state T2 state T3 state
Read data
50
Figure 2-16 Pin States during On-Chip Register Field Access Cycle
Figure 2-17 (a) External Device Access Timing (Read)
Read cycle
Address
Read data
T1 state T2 state T3 state
ø
Address bus
AS
WR: High
Data bus
RD
Address
Bus cycle
T3 stateT2 state
T1 state
ø
Address bus
AS: High
RD: High
WR: High
Data bus:
high impedance state
51
Figure 2-17 (b) External Device Access Timing (Write)
Write cycle
Address
Write data
T1 state T2 state T3 state
ø
Address bus
AS
WR
Data bus
RD: High
52
Section 3 MCU Operating Modes and Address Space
3.1 Overview
3.1.1 Mode Selection
The H8/3437 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the
inputs at the mode pins (MD1and MD0). See table 3-1.
Table 3-1 Operating Modes
Mode MD1MD0Address space On-chip ROM On-chip RAM
Mode 0 Low Low — — —
Mode 1 Low High Expanded Disabled Enabled*
Mode 2 High Low Expanded Enabled Enabled*
Mode 3 High High Single-chip Enabled Enabled
Note: *If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory
can be accessed instead.
Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices.
The maximum address space supported by these externally expanded modes is 64 kbytes.
In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are used.
All ports are available for general-purpose input and output.
Mode 0 is inoperative in the H8/3437 Series. Avoid setting the mode pins to mode 0.
53
3.1.2 Mode and System Control Registers
Table 3-2 lists the registers related to the chip’s operating mode: the system control register
(SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the
mode pins MD1and MD0.
Table 3-2 Mode and System Control Registers
Name Abbreviation Read/Write Address
System control register SYSCR R/W H'FFC4
Mode control register MDCR R H'FFC5
3.2 System Control Register (SYSCR)
The system control register (SYSCR) is an 8-bit register that controls the operation of the chip.
Bit 7—Software Standby (SSBY): Enables transition to the software standby mode. For details,
see section 21, Power-Down State.
On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1. It
can be cleared by writing 0.
Bit 7
SSBY Description
0 The SLEEP instruction causes a transition to sleep mode. (Initial value)
1 The SLEEP instruction causes a transition to software standby mode.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
54
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time
when the chip recovers from the software standby mode by an external interrupt. During the
selected time the CPU and on-chip supporting modules continue to stand by. These bits should be
set according to the clock frequency so that the settling time is at least 8 ms. For specific settings,
see section 21.3.3, Clock Settling Time for Exit from Software Standby Mode.
ZTAT and Mask ROM Versions
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Settling time = 8,192 states (Initial value)
0 0 1 Settling time = 16,384 states
0 1 0 Settling time = 32,768 states
0 1 1 Settling time = 65,536 states
1 0 — Settling time = 131,072 states
1 1 — Unused
F-ZTAT Version
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Settling time = 8,192 states (Initial value)
0 0 1 Settling time = 16,384 states
0 1 0 Settling time = 32,768 states
0 1 1 Settling time = 65,536 states
1 0 0 Settling time = 131,072 states
1 0 1 Settling time = 1,024 states
1 1 — Unused
Note: When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted.
If a period exceeding øp/1,024 (e.g. øp/2,048) is specified when selecting the 8-bit timer,
PWM timer, or watchdog timer clock, the counter in the timer will not count up normally when
1,024 states is specified for the settling time. To avoid this problem, set the STS value just
before the transition to software standby mode (before executing the SLEEP instruction), and
re-set the value of STS2 to STS0 to a value from 000 to 100 directly after software standby
mode is cleared by an interrupt.
55
Bit 3—External Reset (XRST): Indicates the source of a reset. A reset can be generated by input
of an external reset signal, or by a watchdog timer overflow when the watchdog timer is used.
XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer
overflow.
Bit 3
XRST Description
0 Reset was caused by watchdog timer overflow.
1 Reset was caused by external input. (Initial value)
Bit 2—NMI Edge (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG Description
0 An interrupt is requested on the falling edge of the NMI input. (Initial value)
1 An interrupt is requested on the rising edge of the NMI input.
Bit 1—Host Interface Enable (HIE): Enables or disables the host interface function. When
enabled, the host interface processes host-slave data transfers, operating in slave mode.
Bit 1
HIE Description
0 The host interface is disabled. (Initial value)
1 The host interface is enabled (slave mode).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized
by a reset, but is not initialized in the software standby mode.
Bit 0
RAME Description
0 The on-chip RAM is disabled.
1 The on-chip RAM is enabled. (Initial value)
56
3.3 Mode Control Register (MDCR)
The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the chip.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bit 2—Reserved: This bit cannot be modified and is always read as 1.
Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the
mode pins (MD1and MD0), thereby indicating the current operating mode of the chip. MDS1
corresponds to MD1and MDS0 to MD0. These bits can be read but not written. When the mode
control register is read, the levels at the mode pins (MD1and MD0) are latched in these bits.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
0
—
3
—
0
—
0
MDS0
R
2
—
1
—
1
MDS1
R
*
Note: Initialized according to MD1 and MD0 inputs.
*
*
57
3.4 Address Space Map in Each Operating Mode
Figures 3-1 and 3-2 show memory maps of the H8/3437, H8/3436, and H8/3434 in modes 1, 2,
and 3.
Figure 3-1 H8/3437 Address Space Map
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'F780
H'F77F
H'004C
H'004B
H'0000
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'F780
H'F77F
H'FFFF
H'FF88
H'FF7F
H'FF80
H'EF80
H'EF7F
H'004C
H'004B
H'0000
H'004C
H'004B
H'0000
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
Vector table
On-chip ROM
61,312 bytes
Vector tableVector table
External address space
On-chip RAM*,
2,048 bytes On-chip RAM,
2,048 bytes
External address space
External address space
External address space
On-chip RAM*,
2,048 bytes
On-chip register field On-chip register field On-chip register field
External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Note: *
On-chip ROM
63,360 bytes
H'FF7F
58
Figure 3-2 H8/3436 Address Space Map
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'F780
H'F77F
H'004C
H'004B
H'0000
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'F780
H'F77F
H'FFFF
H'FF88
H'FF7F
H'EF80
H'EF7F
H'BFFF
H'C000
H'004C
H'004B
H'0000
H'004C
H'004B
H'0000
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
Vector table
On-chip ROM
49,152 bytes
Vector tableVector table
Reserved*1
External address space
On-chip RAM*2,
2,048 bytes On-chip RAM
2,048 bytes
External address space
External address space
External address space
On-chip RAM*2,
2,048 bytes
On-chip register field On-chip register field On-chip register field
Do not access reserved areas.
External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Notes: *1
*2
H'BFFF
H'C000
On-chip ROM
49,152 bytes
Reserved*1
H'F780
H'F77F
59
Figure 3-3 H8/3434 Address Space Map
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FB80
H'FB7F
H'F780
H'F77F
H'004C
H'004B
H'0000
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FB80
H'FB7F
H'F780
H'F77F
H'FFFF
H'FF88
H'FF7F
H'FB80
H'EF80
H'EF7F
H'8000 H'8000
H'7FFF
H'004C
H'004B
H'0000
H'004C
H'004B
H'0000
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
Vector table
On-chip ROM
32,768 bytes
Vector tableVector table
Reserved*1
Reserved*1, *2Reserved*1, *2
External address space
On-chip RAM*2,
1,024 bytes On-chip RAM
1,024 bytes
External address space
External address space
External address space
On-chip RAM*2,
1,024 bytes
On-chip register field On-chip register field On-chip register field
Do not access reserved areas.
External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Notes: *1
*2
H'7FFF
On-chip ROM
32,768 bytes
Reserved*1
Reserved*1
H'F780
H'F77F
60
Section 4 Exception Handling
4.1 Overview
The H8/3437 Series recognizes two kinds of exceptions: interrupts and the reset. Table 4-1 indicates
their priority and the timing of their hardware exception-handling sequence.
Table 4-1 Hardware Exception-Handling Sequences and Priority
Type of Detection
Priority Exception Timing Timing of Exception-Handling Sequence
High Reset Synchronized The hardware exception-handling sequence begins as
with clock soon as RES changes from low to high.
Interrupt End of instruction When an interrupt is requested, the hardware
execution*exception-handling sequence begins at the end of
the current instruction, or at the end of the current
Low hardware exception-handling sequence.
Note: *Not detected after ANDC, ORC, XORC, and LDC instructions.
4.2 Reset
4.2.1 Overview
A reset has the highest exception-handling priority. When the RES pin goes low or when there is a
watchdog timer reset (when the reset option is selected for watchdog timer overflow), all current
processing stops and the chip enters the reset state. The internal state of the CPU and the registers of
the on-chip supporting modules are initialized. The reset exception-handling sequence starts when
RES returns from low to high, or at the end of a watchdog reset pulse.
4.2.2 Reset Sequence
The reset state begins when RES goes low or a watchdog reset is generated. To ensure correct
resetting, at power-on the RES pin should be held low for at least 20 ms. In a reset during operation,
the RES pin should be held low for at least 10 system clock cycles. The watchdog reset pulse width
is always 518 system clocks. For the pin states during a reset, see appendix D, Pin States.
The following sequence is carried out when reset exception handling begins.
(1) The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit in the condition code register (CCR) is set to 1.
(2) The CPU loads the program counter with the first word in the vector table (stored at addresses
H'0000 and H'0001) and starts program execution.
The RES pin should be held low when power is switched off, as well as when power is switched on.
61
Figure 4-1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4-2 indicates the
timing in mode 1.
Figure 4-1 Reset Sequence (Mode 2 or 3, Program Stored in On-Chip ROM)
(1)
ø
RES/watchdog timer
reset (internal)
(2)
Internal address
bus
Internal read
signal
Internal write
signal
Internal data bus
(16 bits)
(1) Reset vector address (H'0000)
(2) Starting address of program
(3) First instruction of program
Vector
fetch Internal
processing Instruction
prefetch
(2) (3)
62
Figure 4-2 Reset Sequence (Mode 1)
(1) (3) (5) (7)
(1), (3) Reset vector address: (1) = H'0000, (3) = H'0001
(2), (4) Starting address of program (contents of reset vector): (2) = upper byte, (4) = lower byte
(5), (7) Starting address of program: (5) = (2) (4), (7) = (2) (4) + 1
(6), (8) First instruction of program: (6) = first byte, (8) = second byte
Vector fetch
Internal
process-
ing Instruction prefetch
RES/watchdog timer
reset (internal)
D7 to D0
(8 bits)
A15 to A0
ø
RD
WR
(2) (4) (6) (8)
63
4.2.3 Disabling of Interrupts after Reset
After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7),
the program counter and condition code register might not be saved correctly, leading to a program
crash. To prevent this, all interrupts, including NMI, are disabled immediately after a reset. The first
program instruction is therefore always executed. This instruction should initialize the stack pointer
(example: MOV.W #xx:16, SP).
After reset exception handling, in order to initialize the contents of CCR, a CCR manipulation
instruction can be executed before an instruction to initialize the stack pointer. Immediately after
execution of a CCR manipulation instruction, all interrupts including NMI are disabled. Use the
next instruction to initialize the stack pointer.
4.3 Interrupts
4.3.1 Overview
The interrupt sources include nine external sources from 23 input pins (NMI, IRQ0to IRQ7, and
KEYIN0to KEYIN15), and 26 internal sources in the on-chip supporting modules. Table 4-2 lists
the interrupt sources in priority order and gives their vector addresses. When two or more interrupts
are requested, the interrupt with highest priority is served first.
The features of these interrupts are:
• NMI has the highest priority and is always accepted. All internal and external interrupts except
NMI can be masked by the I bit in the CCR. When the I bit is set to 1, interrupts other than
NMI are not accepted.
• IRQ0to IRQ7can be sensed on the falling edge of the input signal, or level-sensed. The type of
sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the
rising or falling edge can be selected.
• All interrupts are individually vectored. The software interrupt-handling routine does not have
to determine what type of interrupt has occurred.
• IRQ6is multiplexed with 16 external sources (KEYIN0to KEYIN15). KEYIN0to KEYIN15
can be masked individually by user software.
• The watchdog timer can generate either an NMI or overflow interrupt, depending on the needs
of the application. For details, see section 11, Watchdog Timer.
64
Table 4-2 Interrupts
Interrupt source No. Vector Table Address Priority
NMI 3 H'0006 to H'0007 High
IRQ0 4 H'0008 to H'0009
IRQ1 5 H'000A to H'000B
IRQ2 6 H'000C to H'000D
IRQ3 7 H'000E to H'000F
IRQ4 8 H'0010 to H'0011
IRQ5 9 H'0012 to H'0013
IRQ6 10 H'0014 to H'0015
IRQ7 11 H'0016 to H'0017
16-bit free- ICIA (Input capture A) 12 H'0018 to H'0019
running timer ICIB (Input capture B) 13 H'001A to H'001B
ICIC (Input capture C) 14 H'001C to H'001D
ICID (Input capture D) 15 H'001E to H'001F
OCIA (Output compare A) 16 H'0020 to H'0021
OCIB (Output compare B) 17 H'0022 to H'0023
FOVI (Overflow) 18 H'0024 to H'0025
8-bit timer 0 CMI0A (Compare-match A) 19 H'0026 to H'0027
CMI0B (Compare-match B) 20 H'0028 to H'0029
OVI0 (Overflow) 21 H'002A to H'002B
8-bit timer 1 CMI1A (Compare-match A) 22 H'002C to H'002D
CMI1B (Compare-match B) 23 H'002E to H'002F
OVI1 (Overflow) 24 H'0030 to H'0031
Host interface IBF1 (IDR1 receive end) 25 H'0032 to H'0033
IBF2 (IDR2 receive end) 26 H'0034 to H'0035
Serial ERI0 (Receive error) 27 H'0036 to H'0037
communication RXI0 (Receive end) 28 H'0038 to H'0039
interface 0 TXI0 (TDR empty) 29 H'003A to H'003B
TEI0 (TSR empty) 30 H'003C to H'003D
Serial ERI1 (Receive error) 31 H'003E to H'003F
communication RXI1 (Receive end) 32 H'0040 to H'0041
interface 1 TXI1 (TDR empty) 33 H'0042 to H'0043
TEI1 (TSR empty) 34 H'0044 to H'0045
A/D converter ADI (Conversion end) 35 H'0046 to H'0047
Watchdog timer WOVF (WDT overflow) 36 H'0048 to H'0049
I2C bus interface IICI (Transfer end) 37 H'004A to H'004B Low
Notes: 1. H'0000 and H'0001 contain the reset vector.
2. H'0002 to H'0005 are reserved in the H8/3437 Series and are not available to the user.
65
4.3.2 Interrupt-Related Registers
The interrupt-related registers are the system control register (SYSCR), IRQ sense control register
(ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask registers (KMIMR and
KMIMRA).
Table 4-3 Registers Read by Interrupt Controller
Name Abbreviation Read/write Address
System control register SYSCR R/W H'FFC4
IRQ sense control register ISCR R/W H'FFC6
IRQ enable register IER R/W H'FFC7
Keyboard matrix interrupt mask register KMIMR R/W H'FFF1
Keyboard matrix interrupt mask register A KMIMRA R/W H'FFF3
System Control Register (SYSCR)
The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register.
Bit 2—NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the
falling or rising edge of the NMI input signal.
Bit 2
NMIEG Description
0 An interrupt is generated on the falling edge of NMI. (Initial state)
1 An interrupt is generated on the rising edge of NMI.
See section 3.2, System Control Register, for information on the other SYSCR bits.
IRQ Sense Control Register (ISCR)
Bit
Initial value
Read/Write
7
IRQ7SC
0
R/W
6
IRQ6SC
0
R/W
5
IRQ5SC
0
R/W
4
IRQ4SC
0
R/W
3
IRQ3SC
0
R/W
0
IRQ0SC
0
R/W
2
IRQ2SC
0
R/W
1
IRQ1SC
0
R/W
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
66
Bits 7 to 0—IRQ7to IRQ0Sense Control (IRQ7SC to IRQ0SC): These bits determine whether
IRQ7to IRQ0are level-sensed or sensed on the falling edge.
Bits 7 to 0
IRQ7SC to IRQ0SC Description
0 An interrupt is generated when IRQ7to IRQ0(Initial state)
inputs are low.
1 An interrupt is generated by the falling edge of the IRQ7to IRQ0inputs.
IRQ Enable Register (IER)
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable the IRQ7to
IRQ0interrupts individually.
Bits 7 to 0
IRQ7E to IRQ0E Description
0 IRQ7to IRQ0interrupt requests are disabled. (Initial state)
1 IRQ7to IRQ0interrupt requests are enabled.
When edge sensing is selected (by setting bits IRQ7SC to IRQ0SC to 1), it is possible for an
interrupt-handling routine to be executed even though the corresponding enable bit (IRQ7E to
IRQ0E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit
(IRQ7E to IRQ0E) is set to 1, the request will be held pending until served. If the enable bit is
cleared to 0 while the request is still pending, the request will remain pending, although new
requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the interrupt-
handling routine can be executed even though the enable bit is now 0.
If execution of interrupt-handling routines under these conditions is not desired, it can be avoided
by using the following procedure to disable and clear interrupt requests.
1. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically
when execution jumps to an interrupt vector.
2. Clear the desired bits from IRQ7E to IRQ0E to 0 to disable new interrupt requests.
3. Clear the corresponding IRQ7SC to IRQ0SC bits to 0, then set them to 1 again. Pending IRQn
interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0.
Bit
Initial value
Read/Write
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
67
Keyboard Matrix Interrupt Mask Register (KMIMR)
To control interrupts from a 16 ×16 matrix keyboard at key-sense input pins KEYIN0to KEYIN15,
there are two keyboard matrix interrupt mask registers, KMIMR and KMIMRA. Bits KMIMR7 to
KMIMR0 in KMIMR correspond to key-sense inputs KEYIN7to KEYIN0. Bits KMIMR15 to
KMIMR8 in KMIMRA correspond to key-sense inputs KEYIN15 to KEYIN8. Initially, the
KMIMR6 bit that corresponds to the IRQ6/KEYIN6pin is in the interrupt-enabled state, and the
other interrupt mask bits are in the interrupt-disabled state.
KMIMR is an 8-bit readable/writable register used in keyboard matrix scanning and sensing. This
register initializes to a state in which only the input at the IRQ6pin is enabled. To enable key-sense
input interrupts from two or more pins during keyboard scanning and sensing, clear the
corresponding mask bits to 0.
Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR7 to KMIMR0): These bits control
key-sense input interrupt requests KEYIN7to KEYIN0.
Bits 7 to 0
KMIMR7 to KMIMR0 Description
0 Key-sense input interrupt request is enabled.
1 Key-sense input interrupt request is disabled. (Initial value)*
Note: *Except KMIMR6, which is initially 0.
Bit
Initial value
Read/Write
7
KMIMR15
1
R/W
6
KMIMR14
1
R/W
5
KMIMR13
1
R/W
4
KMIMR12
1
R/W
3
KMIMR11
1
R/W
0
KMIMR8
1
R/W
2
KMIMR10
1
R/W
1
KMIMR9
1
R/W
Bit
Initial value
Read/Write
7
KMIMR7
1
R/W
6
KMIMR6
0
R/W
5
KMIMR5
1
R/W
4
KMIMR4
1
R/W
3
KMIMR3
1
R/W
0
KMIMR0
1
R/W
2
KMIMR2
1
R/W
1
KMIMR1
1
R/W
68
Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR15 to KMIMR8): These bits control
key-sense input interrupt requests KEYIN15 to KEYIN8.
Bits 7 to 0
KMIMR15 to KMIMR8 Description
0 Key-sense input interrupt request is enabled.
1 Key-sense input interrupt request is disabled. (Initial value)
Figure 4-3 shows the relationship between the IRQ6interrupt, KMIMR, and KMIMRA.
Figure 4-3 KMIMR, KMIMRA, and IRQ6Interrupt
IRQ6E
IRQ6SC
KMIMR0 (1)
P60/KEYIN0
KMIMR6 (0)
P66/KEYIN6/IRQ6
KMIMR7 (1)
P67/KEYIN7
KMIMR15 (1)
PA7/KEYIN15
KMIMR8 (1)
PA0/KEYIN8
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
IRQ6 internal signal
Edge/level select
and enable/
disable control
IRQ6
interrupt
Initial values are given in parentheses
69
4.3.3 External Interrupts
The nine external interrupts are NMI and IRQ0to IRQ7. NMI, IRQ0, IRQ1, IRQ2, and IRQ6can be
used to recover from software standby mode.
(1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal
regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected by the
NMIEG bit in the system control register. The NMI vector number is 3. In the NMI hardware
exception-handling sequence the I bit in the CCR is set to 1.
(2) IRQ0to IRQ7: These interrupt signals are level-sensed or sensed on the falling edge of the
input, as selected by ISCR bits IRQ0SC to IRQ7SC. These interrupts can be masked collectively by
the I bit in the CCR, and can be enabled and disabled individually by setting and clearing bits
IRQ0E to IRQ7E in the IRQ enable register.
The IRQ6input signal can be logically ORed internally with the key sense input signals. When
KEYIN0to KEYIN15 pins (P60to P67and PA0to PA7) are used for key sense input, the
corresponding KMIMR bits should be cleared to 0 to enable the corresponding key sense input
interrupts. KMIMR bits corresponding to unused key sense inputs should be set to 1 to disable the
interrupts. All 16 key sense interrupts are combined into a single IRQ6interrupt.
When one of these interrupts is accepted, the I bit is set to 1. IRQ0to IRQ7have interrupt vector
numbers 4 to 11. They are prioritized in order from IRQ7(low) to IRQ0(high). For details, see table
4-2.
Interrupts IRQ0to IRQ7do not depend on whether pins IRQ0to IRQ7are input or output pins.
When using external interrupts IRQ0to IRQ7, clear the corresponding DDR bits to 0 to set these
pins to the input state, and do not use these pins as input or output pins for the timers, serial
communication interface, I2C bus interface, host interface, or A/D converter.
4.3.4 Internal Interrupts
Twenty-six internal interrupts can be requested by the on-chip supporting modules. Each interrupt
source has its own vector number, so the interrupt-handling routine does not have to determine
which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to 1.
When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except
NMI). The vector numbers are 12 to 37. For the priority order, see table 4-2.
70
4.3.5 Interrupt Handling
Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt
requests, commands the CPU to start the hardware interrupt exception-handling sequence, and
furnishes the necessary vector number. Figure 4-4 shows a block diagram of the interrupt controller.
Figure 4-4 Block Diagram of Interrupt Controller
The IRQ interrupts and interrupts from the on-chip supporting modules (except for reset selected for
a watchdog timer overflow) all have corresponding enable bits. When the enable bit is cleared to 0,
the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These interrupts
can also all be masked by setting the CPU’s interrupt mask bit (I) to 1. Accordingly, these interrupts
are accepted only when their enable bit is set to 1 and the I bit is cleared to 0.
The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware standby
mode.
IRQ0 flag
IRQ0E
IRIC
IEIC
CPU
I (CCR)
NMI interrupt Interrupt
controller
Priority
decision
IRQ0
interrupt Interrupt request
Vector number
IICI
interrupt
Note: *
*
For edge-sensed interrupts, these AND gates change to the circuit shown below.
IRQ0 edge
IRQ0E SQ
IRQ0 flag
IRQ0 interrupt
71
When an NMI or another enabled interrupt is requested, the interrupt controller transfers the
interrupt request to the CPU and indicates the corresponding vector number. (When two or more
interrupts are requested, the interrupt controller selects the vector number of the interrupt with the
highest priority.) When notified of an interrupt request, at the end of the current instruction or
current hardware exception-handling sequence, the CPU starts the hardware exception-handling
sequence for the interrupt and latches the vector number.
Figure 4-5 is a flowchart of the interrupt (and reset) operations. Figure 4-7 shows the interrupt
timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM
and the stack is in on-chip RAM.
(1) An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when
an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the
enable bit of that interrupt is set to 1.
(2) The interrupt controller checks the I bit in CCR and accepts the interrupt request if the I bit is
cleared to 0. If the I bit is set to 1 only NMI requests are accepted; other interrupt requests
remain pending.
(3) Among all accepted interrupt requests, the interrupt controller selects the request with the
highest priority and passes it to the CPU. Other interrupt requests remain pending.
(4) When it receives the interrupt request, the CPU waits until completion of the current instruction
or hardware exception-handling sequence, then starts the hardware exception-handling
sequence for the interrupt and latches the interrupt vector number.
(5) In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the
stack. See figure 4-6. The stacked PC indicates the address of the first instruction that will be
executed on return from the software interrupt-handling routine.
(6) Next the I bit in CCR is set to 1, masking all further interrupts except NMI.
(7) The vector address corresponding to the vector number is generated, the vector table entry at
this vector address is loaded into the program counter, and execution branches to the software
interrupt-handling routine at the address indicated by that entry.
72
Figure 4-5 Hardware Interrupt-Handling Sequence
Program execution
No
No
No
Yes
No
Yes
Yes
Yes
No
Yes
NMI?
I = 0?
IRQ0?
IRQ1?
IICI?
Reset
I← 1
Interrupt
requested?
Pending
Latch vector no.
Save PC
Save CCR
Read vector address
Branch to software
interrupt-handling
routine
Yes
73
Figure 4-6 Usage of Stack in Interrupt Handling
The CCR is comprised of one byte, but when it is saved to the stack, it is treated as one word of
data. During interrupt processing, two identical bytes of CCR data are saved to the stack to create
one word of data. When the RTE instruction is executed to restore the value from the stack, the byte
located at the even address is loaded into CCR, and the byte located at the odd address is ignored.
SP(R7)SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4 Even address
CCR
CCR*
PC (upper byte)
Before interrupt
is accepted After interrupt
is accepted
Pushed onto stack
Program counter
Condition code register
Stack pointer
PC:
CCR:
SP:
The PC contains the address of the first instruction
executed after return.
Registers must be saved and restored by word
access at an even address.
Notes: 1.
2.
* Ignored on return.
Stack area
PC (lower byte)
74
Figure 4-7 Timing of Interrupt Sequence
(3) (5) (6) (8) (9)(1)
Interrupt priority
decision. Wait for
end of instruction.
Interrupt
accepted
Internal
process-
ing Stack Vector
fetch Internal
process-
ing
Instruction prefetch
(first instruction of
interrupt-handling
routine)
Interrupt request
signal
Internal address
bus
Internal write
signal
Internal read
signal
Internal 16-bit
data bus
ø
(1)(2) (4) (7) (9) (10)
Instruction
prefetch
(1)
(2) (4)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from interrupt-handling
routine.)
Instruction code (Not executed)
Instruction prefetch address (Not executed)
SP–2
SP–4
CCR
Address of vector table entry
Vector table entry (address of first instruction of interrupt-handling routine)
First instruction of interrupt-handling routine
75
4.3.6 Interrupt Response Time
Table 4-4 indicates the number of states that elapse from an interrupt request signal until the first
instruction of the software interrupt-handling routine is executed. Since on-chip memory is accessed
16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in
on-chip ROM and the stack in on-chip RAM.
Table 4-4 Number of States before Interrupt Service
Number of States
No. Reason for Wait On-Chip Memory External Memory
1 Interrupt priority decision 2*32*3
2 Wait for completion of 1 to 13 5 to 17*2
current instruction*1
3 Save PC and CCR 4 12*2
4 Fetch vector 2 6*2
5 Fetch instruction 4 12*2
6 Internal processing 4 4
Total 17 to 29 41 to 53 *2
Notes: 1. These values do not apply if the current instruction is EEPMOV.
2. If wait states are inserted in external memory access, add the number of wait states.
3. 1 for internal interrupts.
76
4.3.7 Precaution
Note that the following type of contention can occur in interrupt handling.
When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt
becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a BCLR
or MOV instruction, for example, and the interrupt is requested during execution of that instruction,
at the instant when the instruction ends the interrupt is still enabled, so after execution of the
instruction, the hardware exception-handling sequence is executed for the interrupt. If a higher-
priority interrupt is requested at the same time, however, the hardware exception-handling sequence
is executed for the higher-priority interrupt and the interrupt that was disabled is ignored.
Similar considerations apply when an interrupt request flag is cleared to 0.
Figure 4-8 shows an example in which the OCIAE bit is cleared to 0.
Figure 4-8 Contention between Interrupt and Disabling Instruction
The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt mask
bit (I) is set to 1.
ø
Internal address bus
OCIAE
OCIA interrupt handling
OCIA interrupt signal
OCFA
CPU write
cycle to TIER
Internal write signal
TIER address
77
4.4 Note on Stack Handling
In word access, the least significant bit of the address is always assumed to be 0. The stack is always
accessed by word access. Care should be taken to keep an even value in the stack pointer (general
register R7). Use the PUSH and POP (or MOV.W Rn, @–SP and MOV.W @SP+, Rn) instructions
to push and pop registers on the stack.
Setting the stack pointer to an odd value can cause programs to crash. Figure 4-9 shows an example
of damage caused when the stack pointer contains an odd address.
Figure 4-9 Example of Damage Caused by Setting an Odd Address in R7
PCH
SP PCLH'FECD
H'FECF
H'FECC
BSR instruction MOV.B R1L, @–R7
PC is improperly stored
beyond top of stack
H'FECF set in SP PCH is lost
PCH:
PCL:
R1L:
SP:
Upper byte of program counter
Lower byte of program counter
General register
Stack pointer
SP
R1L
SP
PCL
78
Section 5 Wait-State Controller
5.1 Overview
The H8/3437 Series has an on-chip wait-state controller that enables insertion of wait states into bus
cycles for interfacing to low-speed external devices.
5.1.1 Features
Features of the wait-state controller are listed below.
• Three selectable wait modes: programmable wait mode, pin auto-wait mode, and pin wait mode
• Automatic insertion of zero to three wait states
5.1.2 Block Diagram
Figure 5-1 shows a block diagram of the wait-state controller.
Figure 5-1 Block Diagram of Wait-State Controller
WAIT Wait-state controller
(WSC)
WSCR
Internal data bus
Wait request
signal
Legend
WSCR: Wait-state control register
79
5.1.3 Input/Output Pins
Table 5-1 summarizes the wait-state controller’s input pin.
Table 5-1 Wait-State Controller Pins
Name Abbreviation I/O Function
Wait WAIT Input Wait request signal for access to external addresses
5.1.4 Register Configuration
Table 5-2 summarizes the wait-state controller’s register.
Table 5-2 Register Configuration
Address Name Abbreviation R/W Initial Value
H'FFC2 Wait-state control register WSCR R/W H'08
5.2 Register Description
5.2.1 Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller
(WSC) and specifies the number of wait states. It also controls emulation of flash memory by RAM,
and frequency division of the clock signals supplied to the supporting modules.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
Initial value
Read/Write
7
RAMS
0
R/W
6
RAM0
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
80
Bit 7—RAM Select (RAMS)
Bit 6—RAM Area Select (RAM0)
Bits 7 and 6 select a RAM area for emulation of flash memory updates. For details, see the flash
memory description in section 19, 20, ROM.
Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to
supporting modules. For details, see section 6, Clock Pulse Generator.
Bit 4—Reserved: This bit is reserved, but it can be written and read. Its initial value is 0.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode.
Bit 3 Bit 2
WMS1 WMS0 Description
0 0 Programmable wait mode
1 No wait states inserted by wait-state controller
1 0 Pin wait mode (Initial value)
1 Pin auto-wait mode
Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted
in access to external address areas.
Bit 1 Bit 0
WC1 WC0 Description
0 0 No wait states inserted by wait-state controller (Initial value)
1 1 state inserted
1 0 2 states inserted
1 3 states inserted
81
5.3 Wait Modes
Programmable Wait Mode: The number of wait states (TW) selected by bits WC1 and WC0 are
inserted in all accesses to external addresses. Figure 5-2 shows the timing when the wait count is 1
(WC1 = 0, WC0 = 1).
Figure 5-2 Programmable Wait Mode
T
1 T
2 T
W T
3
ø
Address bus
AS
RD
WR
Data bus
Data bus
External address
Read data
Write data
Read
access
Write
access
82
Pin Wait Mode: In all accesses to external addresses, the number of wait states (TW) selected by
bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (ø) in the last
of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait states
continue to be inserted until the WAIT signal goes high.
Pin wait mode is useful for inserting four or more wait states, or for inserting different numbers of
wait states for different external devices.
Figure 5-3 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait
state is inserted by WAIT input.
Figure 5-3 Pin Wait Mode
Address bus
Data bus
AS
RD
WR
T
1 T
2 T
W T
W T
3
Write data
*
Read data
*
Read
access
Write
access
Note: Arrows indicate time of sampling of the pin.*WAIT
ø
pin
WAIT
Data bus
External address
Write data
Inserted by
wait count Inserted by
signalWAIT
83
Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits
WC1 and WC0 are inserted.
In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the T2state, the
number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait states
are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy
interface to low-speed memory, simply by routing the chip select signal to the WAIT pin.
Figure 5-4 shows the timing when the wait count is 1.
Figure 5-4 Pin Auto-Wait Mode
ø
Address bus
Data bus
AS
RD
WR
Data bus
T
1 T
2 T
3 T
1 T
2 T
W T
3
**
Read data Read data
Write data Write data
Read
access
Write
access
Note: Arrows indicate time of sampling of the pin.*WAIT
External address External address
WAIT
84
Section 6 Clock Pulse Generator
6.1 Overview
The H8/3437 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a
duty adjustment circuit, and a divider and a prescaler that generates clock signals for the on-chip
supporting modules.
6.1.1 Block Diagram
Figure 6-1 shows a block diagram of the clock pulse generator.
Figure 6-1 Block Diagram of Clock Pulse Generator
Input an external clock signal to the EXTAL pin, or connect a crystal resonator to the XTAL and
EXTAL pins. The system clock frequency (ø) will be the same as the input frequency. This same
system clock frequency (øP) can be supplied to timers and other supporting modules, or it can be
divided by two. The selection is made by software, by controlling the CKDBL bit.
XTAL
EXTAL Oscillator
circuit
Duty
adjustment
circuit
Frequency
divider (1/2) CKDBL
ø
(system
clock)
øP
(for sup-
porting
modules) Prescaler
øP/2 to øP/4096
85
6.1.2 Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals
supplied to the supporting modules. It also controls wait-state insertion and emulation of flash
memory by RAM.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—RAM Select (RAMS)
Bit 6—RAM Area Select (RAM0)
Bits 7 and 6 select a RAM area that can be used to emulate flash memory updates. For details, see
the flash memory description in section 19, 20, ROM.
Bit 5—Clock Double (CKDBL): Controls the frequency division of clock signals supplied to
supporting modules.
Bit 5
CKDBL Description
0 The undivided system clock (ø) is supplied as the clock (øP) for supporting modules.
(Initial value)
1 The system clock (ø) is divided by two and supplied as the clock (øP) for supporting
modules.
Bit 4—Reserved: This bit is reserved, but it can be written and read. Its initial value is 0.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0)
Bits 1 and 0—Wait Count 1 and 0 (WC1/0)
These bits control wait-state insertion. For details, see section 5, Wait-State Controller.
Bit
Initial value
Read/Write
7
RAMS
0
R/W
6
RAM0
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
86
6.2 Oscillator Circuit
If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit
generates a system clock signal. Alternatively, an external clock signal can be applied to the
EXTAL pin.
1. Connecting an External Crystal
(1) Circuit Configuration: An external crystal can be connected as in the example in figure 6-2.
Table 6-1 indicates the appropriate damping resistance Rd. An AT-cut parallel resonance crystal
should be used.
Figure 6-2 Connection of Crystal Oscillator (Example)
Table 6-1 Damping Resistance
Frequency (MHz) 248101216
Rd max (Ω) 1 k 500 200 0 0 0
EXTAL
XTAL
C
L1
C
L2 C = C = 10 pF to 22 pF
L1 L2
Rd
87
(2) Crystal Oscillator: Figure 6-3 shows an equivalent circuit of the crystal resonator. The crystal
resonator should have the characteristics listed in table 6-2.
Figure 6-3 Equivalent Circuit of External Crystal
Table 6-2 External Crystal Parameters
Frequency (MHz) 248101216
Rs max (Ω) 500 120 80 70 60 50
C0 (pF) 7 pF max
Use a crystal with the same frequency as the desired system clock frequency (ø).
XTAL
LRs
C
L
C
0
EXTAL
AT-cut parallel resonating crystal
88
(3) Note on Board Design: When an external crystal is connected, other signal lines should be kept
away from the crystal circuit to prevent induction from interfering with correct oscillation. See
figure 6-4. The crystal and its load capacitors should be placed as close as possible to the XTAL and
EXTAL pins.
Figure 6-4 Notes on Board Design around External Crystal
XTAL
EXTAL
C
L2
C
L1
Not allowed Signal A Signal B
89
2. Input of External Clock Signal
(1) Circuit Configuration: An external clock signal can be input as shown in the examples in
figure 6-5. In example (b) in figure 6-5, the external clock signal should be kept high during
standby.
If the XTAL pin is left open, make sure the stray capacitance does not exceed 10 pF.
Figure 6-5 External Clock Input (Example)
EXTAL
XTAL
EXTAL
XTAL
74HC04
External clock input
Open
External clock input
(a) Connections with XTAL pin left open
(b) Connections with inverted clock input at XTAL pin
90
(2) External Clock Input
The external clock signal should have the same frequency as the desired system clock (ø). Clock
timing parameters are given in table 6-3 and figure 6-6.
Table 6-3 Clock Timing
VCC = 2.7 VCC = 4.0 VCC = 5.0 V
to 5.5 V to 5.5 V ±10%
Item Symbol Min Max Min Max Min Max Unit Test Conditions
Low pulse tEXL 40 — 30 — 20 — ns Figure 6-6
width of external
clock input
High pulse tEXH 40 — 30 — 20 — ns
width of external
clock input
External clock tEXr —10—10—5 ns
rise time
External clock tEXf —10—10—5 ns
fall time
Clock pulse tCL 0.3 0.7 0.3 0.7 0.3 0.7 tcyc ø ≥5 MHz Figure 22-4
width low 0.4 0.6 0.4 0.6 0.4 0.6 tcyc ø < 5 MHz
Clock pulse tCH 0.3 0.7 0.3 0.7 0.3 0.7 tcyc ø ≥5 MHz
width high 0.4 0.6 0.4 0.6 0.4 0.6 tcyc ø < 5 MHz
Figure 6-6 External Clock Input Timing
tEXH tEXL
tEXt
tEXr
VCC × 0.5
EXTAL
91
Table 6-4 lists the external clock output stabilization delay time. Figure 6-7 shows the timing for the
external clock output stabilization delay time. The oscillator and duty correction circuit have the
function of regulating the waveform of the external clock input to the EXTAL pin. When the specified
clock signal is input to the EXTAL pin, internal clock signal output is confirmed after the elapse of the
external clock output stabilization delay time (tDEXT). As clock signal output is not confirmed during
the tDEXT period, the reset signal should be driven low and the reset state maintained during this time.
Table 6-4 External Clock Output Stabilization Delay Time
Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VSS = AVSS = 0 V
Item Symbol Min Max Unit Notes
External clock output stabilization tDEXT*500 — µs Figure 6-7
delay time
Note: *tDEXT includes a 10 tcyc RES pulse width (tRESW).
Figure 6-7 External Clock Output Stabilization Delay Time
6.3 Duty Adjustment Circuit
When the clock frequency is 5 MHz or above, the duty adjustment circuit adjusts the duty cycle of
the signal from the oscillator circuit to generate the system clock (ø).
6.4 Prescaler
The clock for the on-chip supporting modules (øP) has either the same frequency as the system
clock (ø) or this frequency divided by two, depending on the CKDBL bit. The prescaler divides the
frequency of øPto generate internal clock signals with frequencies from øP/2 to øP/4096.
VCC
STBY
EXTAL
ø (internal and
external)
RES
tDEXT*
Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW).
2.7 V
VIH
92
Section 7 I/O Ports
7.1 Overview
The H8/3437 Series has eight 8-bit input/output ports, one 7-bit input/output port, and one 3-bit
input/output port, and are 8-bit input port.
Table 7-1 lists the functions of each port in each operating mode. As table 7-1 indicates, the port
pins are multiplexed, and the pin functions differ depending on the operating mode.
Each port has a data direction register (DDR) that selects input or output, and a data register (DR)
that stores output data. If bit manipulation instructions will be executed on the port data direction
registers, see “Notes on Bit Manipulation Instructions” in section 2.5.5, Bit Manipulations.
Ports 1, 2, 3, 4, 6, 9, A, and B can drive one TTL load and a 90-pF capacitive load. Ports 5 and 8
can drive one TTL load and a 30-pF capacitive load. Ports 1 and 2 can drive LEDs (with 10-mA
current sink). Ports 1 to 6, 8, 9, A, and B can drive a darlington transistor. Ports 1 to 3, 6, A, and B
have built-in MOS pull-up transistors.
For block diagrams of the ports, see appendix C, I/O Port Block Diagrams.
Pins P86in port 8, P97in port 9, and PA4, PA5, PA6, and PA7in port A can be driven to operate as
bus buffers. For details, see section 13, I2C Bus Interface.
93
Table 7-1 Port Functions
Expanded Single-Chip
Modes Mode
Port Description Pins Mode 1 Mode 2 Mode 3
Port 1 • 8-bit I/O port P17to P10/A7to A0Lower address Lower address General
• Can drive LEDs output (A7to A0) output (A7to A0) input/output
• Built-in input or general input
pull-ups
Port 2 • 8-bit I/O port P27to P20/A15 to A8Upper address Upper address General
• Can drive LEDs output (A15 to A8) output (A15 to A8) input/output
• Built-in input or general input
pull-ups
Port 3 • 8-bit I/O port P37to P30/ Data bus (D7to D0) HIF data bus
• Built-in input D7to D0/ (HDB7to
pull-ups HDB7to HDB0HDB0) or
• HIF data bus general input/
output
Port 4 • 8-bit I/O port P47/PW1PWM timer 0/1 output (PW0, PW1), or general
P46/PW0input/output
P45/TMRI1/HIRQ12 8-bit timer 1 input/output (TMCI1, TMO1, TMRI1), host
P44/TMO1/HIRQ1processor interrupt request output from HIF (HIRQ11,
P43/TMCI1/HIRQ11 HIRQ1, HIRQ12), or general input/output
P42/TMRI08-bit timer 0 input/output (TMCI0, TMO0, TMRI0) or
P41/TMO0general input/output
P40/TMCI0
Port 5 • 3-bit I/O port P52/SCK0Serial communication interface 0 input/output (TxD0,
P51/RxD0RxD0, SCK0) or general input/output
P50/TxD0
Port 6 • 8-bit I/O port P67/KEYIN7/IRQ716-bit free-running timer input/output (FTCI, FTOA, FTIA,
• Built-in input P66/KEYIN6/FTOB/IRQ6FTIB, FTIC, FTID, FTOB), key-sense interrupt input
pull-ups P65/KEYIN5/FTID (KEYIN7to KEYIN0), external interrupt input (IRQ7,
• Key-sense P64/KEYIN4/FTIC IRQ6), or general input/output
interrupt inputs P63/KEYIN3/FTIB
P62/KEYIN2/FTIA
P61/KEYIN1/FTOA
P60/KEYIN0/FTCI
Port 7 • 8-bit I/O port P77/AN7/DA1Analog input to A/D converter (AN7, AN6), analog output
P76/AN6/DA0from D/A converter (DA1, DA0), or general input
P75to P70/ Analog input to A/D converter (AN5to AN0) or general
AN5to AN0input
Port 8 • 7-bit I/O port P86/IRQ5/SCK1/SCL Serial communication interface 1 input/output (TxD1,
• Can drive a bus P85/IRQ4/RxD1/CS2RxD1, SCK1), HIF control input (CS2, IOW), I2C clock
line (P86)P8
4
/IRQ3/TxD1/IOW input/output (SCL), external interrupt input (IRQ5to
IRQ3), or general input/output
P83/IOR HIF control input/output (HA0, GA20, CS1, IOR), or
P82/CS1general input/output
P81/GA20
P80/HA0
94
Table 7-1 Port Functions (cont)
Expanded Single-Chip
Modes Mode
Port Description Pins Mode 1 Mode 2 Mode 3
Port 9 • 8-bit I/O port P97/WAIT/SDA Expanded data bus control input I2C data
• Can drive a bus (WAIT), I2C data input/output (SDA), input/output
line (P97) or general input/output (SDA) or
general input/
output
P96/ø System clock (ø) output øoutput or
general input
P95/AS Expanded data bus control output General
P94/WR (RD, WR, AS) input/output
P93/RD
P92/IRQ0HIF control input (ECS2, EIOW), trigger input to A/D
P91/IRQ1/EIOW converter (ADTRG), external interrupt input (IRQ2 to
P90/IRQ2/ECS2/ADTRG IRQ0), or general input/output
Port A • 8-bit I/O port PA7to PA0/ Key-sense interrupt input (KEYIN15 to KEYIN8) or
• Built-in input KEYIN15 to KEYIN8general input/output
pull-ups
• Key-sense
interrupt inputs
• Can drive bus
lines (PA4, PA5,
PA6, PA7)
Port B • 8-bit I/O port PB7to PB0/ HIF data bus (XDB7to XDB0) or General input/
• HIF data bus XDB7to XDB0general input/output output
• Built-in input
pull-up MOS
95
7.2 Port 1
7.2.1 Overview
Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7-1. The pin functions
differ depending on the operating mode.
Port 1 has built-in, programmable MOS input pull-up transistors that can be used in modes 2 and 3.
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and
darlington transistors.
Figure 7-1 Port 1 Pin Configuration
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
Port 1
Port 1 pins
A7 (output)
A6 (output)
A5 (output)
A4 (output)
A3 (output)
A2 (output)
A1 (output)
A0 (output)
Pin configuration
in mode 1
(expanded mode
with on-chip ROM
disabled)
A7 (output)/P17 (input)
A6 (output)/P16 (input)
A5 (output)/P15 (input)
A4 (output)/P14 (input)
A3 (output)/P13 (input)
A2 (output)/P12 (input)
A1 (output)/P11 (input)
A0 (output)/P10 (input)
Pin configuration
in mode 2
(expanded mode
with on-chip ROM
enabled)
P17 (input/output)
P16 (input/output)
P15 (input/output)
P14 (input/output)
P13 (input/output)
P12 (input/output)
P11 (input/output)
P10 (input/output)
Pin configuration in mode 3
(single-chip mode)
96
7.2.2 Register Configuration and Descriptions
Table 7-2 summarizes the port 1 registers.
Table 7-2 Port 1 Registers
Name Abbreviation Read/Write Initial Value Address
Port 1 data direction register P1DDR W H'FF (mode 1) H'FFB0
H'00 (modes 2 and 3)
Port 1 data register P1DR R/W H'00 H'FFB2
Port 1 input pull-up control P1PCR R/W H'00 H'FFAC
register
Port 1 Data Direction Register (P1DDR)
P1DDR controls the input/output direction of each pin in port 1.
Mode 1: The P1DDR values are fixed at 1. Port 1 consists of lower address output pins. P1DDR
values cannot be modified and are always read as 1.
In hardware standby mode, the address bus is in the high-impedance state.
Mode 2: A pin in port 1 is used for address output if the corresponding P1DDR bit is set to 1, and
for general input if this bit is cleared to 0.
Mode 3: A pin in port 1 is used for general output if the corresponding P1DDR bit is set to 1, and
for general input if this bit is cleared to 0.
In modes 2 and 3, P1DDR is a write-only register. Read data is invalid. If read, all bits always read
1. P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values, so if a transition to software standby mode occurs while a P1DDR bit is
set to 1, the corresponding pin remains in the output state.
Bit
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
7
P17DDR
1
—
0
W
6
P16DDR
1
—
0
W
5
P15DDR
1
—
0
W
4
P14DDR
1
—
0
W
3
P13DDR
1
—
0
W
0
P10DDR
1
—
0
W
2
P12DDR
1
—
0
W
1
P11DDR
1
—
0
W
97
Port 1 Data Register (P1DR)
P1DR is an 8-bit register that stores data for pins P17to P10. When a P1DDR bit is set to 1, if port 1
is read, the value in P1DR is obtained directly, regardless of the actual pin state. When a P1DDR bit
is cleared to 0, if port 1 is read the pin state is obtained.
P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Port 1 Input Pull-Up Control Register (P1PCR)
P1PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. If a
P1DDR bit is cleared to 0 (designating input) and the corresponding P1PCR bit is set to 1, the input
pull-up transistor is turned on.
P1PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Bit
Initial value
Read/Write
7
P17PCR
0
R/W
6
P16PCR
0
R/W
5
P15PCR
0
R/W
4
P14PCR
0
R/W
3
P13PCR
0
R/W
0
P10PCR
0
R/W
2
P12PCR
0
R/W
1
P11PCR
0
R/W
Bit
Initial value
Read/Write
7
P1
0
R/W
7
6
P1
0
R/W
6
5
P1
0
R/W
5
4
P1
0
R/W
4
3
P1
0
R/W
3
2
P1
0
R/W
2
1
P1
0
R/W
1
0
P1
0
R/W
0
98
7.2.3 Pin Functions in Each Mode
Port 1 has different pin functions in different modes. A separate description for each mode is given
below.
Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 is
automatically used for lower address output (A7to A0). Figure 7-2 shows the pin functions in
mode 1.
Figure 7-2 Pin Functions in Mode 1 (Port 1)
A7 (output)
A6 (output)
A5 (output)
A4 (output)
A3 (output)
A2 (output)
A1 (output)
A0 (output)
Port 1
99
Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower address
output pins and general input pins. Each pin becomes a lower address output pin if its P1DDR bit is
set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins are input pins.
To be used for address output, their P1DDR bits must be set to 1. Figure 7-3 shows the pin functions
in mode 2.
Figure 7-3 Pin Functions in Mode 2 (Port 1)
A7 (output)
A6 (output)
A5 (output)
A4 (output)
A3 (output)
A2 (output)
A1 (output)
A0 (output)
When P1DDR = 1
P17 (input)
P16 (input)
P15 (input)
P14 (input)
P13 (input)
P12 (input)
P11 (input)
P10 (input)
When P1DDR = 0
Port 1
100
Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected
individually. A pin becomes a general input pin when its P1DDR bit is cleared to 0 and a general
output pin when this bit is set to 1. Figure 7-4 shows the pin functions in mode 3.
Figure 7-4 Pin Functions in Mode 3 (Port 1)
7.2.4 Input Pull-Up Transistors
Port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The
pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or
3, set the corresponding P1PCR bit to 1 and clear the corresponding P1DDR bit to 0. P1PCR is
cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software
standby mode, the previous state is maintained.
Table 7-3 indicates the states of the input pull-up transistors in each operating mode.
Table 7-3 States of Input Pull-Up Transistors (Port 1)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off Off Off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P1PCR = 1 and P1DDR = 0, but off otherwise.
P17 (input/output)
P16 (input/output)
P15 (input/output)
P14 (input/output)
P13 (input/output)
P12 (input/output)
P11 (input/output)
P10 (input/output)
Port 1
101
7.3 Port 2
7.3.1 Overview
Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7-5. The pin functions
differ depending on the operating mode.
Port 2 has built-in, programmable MOS input pull-up transistors that can be used in modes 2 and 3.
Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and
darlington transistors.
Figure 7-5 Port 2 Pin Configuration
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
Port 2
Port 2 pins
A15 (output)
A14 (output)
A13 (output)
A12 (output)
A11 (output)
A10 (output)
A9 (output)
A8 (output)
Pin configuration
in mode 1
(expanded mode
with on-chip ROM
disabled)
A15 (output)/P27 (input)
A14 (output)/P26 (input)
A13 (output)/P25 (input)
A12 (output)/P24 (input)
A11 (output)/P23 (input)
A10 (output)/P22 (input)
A9 (output)/P21 (input)
A8 (output)/P20 (input)
Pin configuration
in mode 2
(expanded mode
with on-chip ROM
enabled)
P27 (input/output)
P26 (input/output)
P25 (input/output)
P24 (input/output)
P23 (input/output)
P22 (input/output)
P21 (input/output)
P20 (input/output)
Pin configuration in mode 3
(single-chip mode)
102
7.3.2 Register Configuration and Descriptions
Table 7-4 summarizes the port 2 registers.
Table 7-4 Port 2 Registers
Name Abbreviation Read/Write Initial Value Address
Port 2 data direction register P2DDR W H'FF (mode 1) H'FFB1
H'00 (modes 2 and 3)
Port 2 data register P2DR R/W H'00 H'FFB3
Port 2 input pull-up P2PCR R/W H'00 H'FFAD
control register
Port 2 Data Direction Register (P2DDR)
P2DDR controls the input/output direction of each pin in port 2.
Mode 1: The P2DDR values are fixed at 1. Port 2 consists of upper address output pins. P2DDR
values cannot be modified and are always read as 1.
In hardware standby mode, the address bus is in the high-impedance state.
Mode 2: A pin in port 2 is used for address output if the corresponding P2DDR bit is set to 1, and
for general input if this bit is cleared to 0.
Mode 3: A pin in port 2 is used for general output if the corresponding P2DDR bit is set to 1, and
for general input if this bit is cleared to 0.
In modes 2 and 3, P2DDR is a write-only register. Read data is invalid. If read, all bits always read
1. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values, so if a transition to software standby mode occurs while a P2DDR bit is
set to 1, the corresponding pin remains in the output state.
Bit
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
7
P27DDR
1
—
0
W
6
P26DDR
1
—
0
W
5
P25DDR
1
—
0
W
4
P24DDR
1
—
0
W
3
P23DDR
1
—
0
W
0
P20DDR
1
—
0
W
2
P22DDR
1
—
0
W
1
P21DDR
1
—
0
W
103
Port 2 Data Register (P2DR)
P2DR is an 8-bit register that stores data for pins P27to P20. When a P2DDR bit is set to 1, if port 2
is read, the value in P2DR is obtained directly, regardless of the actual pin state. When a P2DDR bit
is cleared to 0, if port 2 is read the pin state is obtained.
P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Port 2 Input Pull-Up Control Register (P2PCR)
P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. If a
P2DDR bit is cleared to 0 (designating input) and the corresponding P2PCR bit is set to 1, the input
pull-up transistor is turned on.
P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Bit
Initial value
Read/Write
7
P27PCR
0
R/W
6
P26PCR
0
R/W
5
P25PCR
0
R/W
4
P24PCR
0
R/W
3
P23PCR
0
R/W
0
P20PCR
0
R/W
2
P22PCR
0
R/W
1
P21PCR
0
R/W
Bit
Initial value
Read/Write
7
P2
0
R/W
7
6
P2
0
R/W
6
5
P2
0
R/W
5
4
P2
0
R/W
4
3
P2
0
R/W
3
2
P2
0
R/W
2
1
P2
0
R/W
1
0
P2
0
R/W
0
104
7.3.3 Pin Functions in Each Mode
Port 2 has different pin functions in different modes. A separate description for each mode is given
below.
Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 is
automatically used for upper address output (A15 to A8). Figure 7-6 shows the pin functions in
mode 1.
Figure 7-6 Pin Functions in Mode 1 (Port 2)
A15 (output)
A14 (output)
A13 (output)
A12 (output)
A11 (output)
A10 (output)
A9 (output)
A8 (output)
Port 2
105
Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper address
output pins and general input pins. Each pin becomes an upper address output pin if its P2DDR bit
is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins are input pins.
To be used for address output, their P2DDR bits must be set to 1. Figure 7-7 shows the pin functions
in mode 2.
Figure 7-7 Pin Functions in Mode 2 (Port 2)
A15 (output)
A14 (output)
A13 (output)
A12 (output)
A11 (output)
A10 (output)
A9 (output)
A8 (output)
When P2DDR = 1
P27 (input)
P26 (input)
P25 (input)
P24 (input)
P23 (input)
P22 (input)
P21 (input)
P20 (input)
When P2DDR = 0
Port 2
106
Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected
individually. A pin becomes a general input pin when its P2DDR bit is cleared to 0, and a general
output pin when this bit is set to 1. Figure 7-8 shows the pin functions in mode 3.
Figure 7-8 Pin Functions in Mode 3 (Port 2)
7.3.4 Input Pull-Up Transistors
Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The
pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or
3, set the corresponding P2PCR bit to 1 and clear the corresponding P2DDR bit to 0. P2PCR is
cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software
standby mode, the previous state is maintained.
Table 7-5 indicates the states of the input pull-up transistors in each operating mode.
Table 7-5 States of Input Pull-Up Transistors (Port 2)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off Off Off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0, but off otherwise.
P27 (input/output)
P26 (input/output)
P25 (input/output)
P24 (input/output)
P23 (input/output)
P22 (input/output)
P21 (input/output)
P20 (input/output)
Port 2
107
7.4 Port 3
7.4.1 Overview
Port 3 is an 8-bit input/output port that is multiplexed with the data bus and host interface data bus.
Figure 7-9 shows the pin configuration of port 3. The pin functions differ depending on the
operating mode.
Port 3 has built-in, programmable MOS input pull-up transistors that can be used in mode 3.
Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor.
Figure 7-9 Port 3 Pin Configuration
P37/D7/HDB7
P36/D6/HDB6
P35/D5/HDB5
P34/D4/HDB4
P33/D3/HDB3
P32/D2/HDB2
P31/D1/HDB1
P30/D0/HDB0
Port 3
Port 3 pins
D7 (input/output)
D6 (input/output)
D5 (input/output)
D4 (input/output)
D3 (input/output)
D2 (input/output)
D1 (input/output)
D0 (input/output)
Pin configuration in mode 1
(expanded mode with on-chip
ROM disabled) and mode 2
(expanded mode with on-chip
ROM enabled)
P37 (input/output)
P36 (input/output)
P35 (input/output)
P34 (input/output)
P33 (input/output)
P32 (input/output)
P31 (input/output)
P30 (input/output)
Pin configuration in mode 3 (single-chip mode)
Master mode
HDB7 (input/output)
HDB6 (input/output)
HDB5 (input/output)
HDB4 (input/output)
HDB3 (input/output)
HDB2 (input/output)
HDB1 (input/output)
HDB0 (input/output)
Slave mode
108
7.4.2 Register Configuration and Descriptions
Table 7-6 summarizes the port 3 registers.
Table 7-6 Port 3 Registers
Name Abbreviation Read/Write Initial Value Address
Port 3 data direction register P3DDR W H'00 H'FFB4
Port 3 data register P3DR R/W H'00 H'FFB6
Port 3 input pull-up control P3PCR R/W H'00 H'FFAE
register
Port 3 Data Direction Register (P3DDR)
P3DDR is an 8-bit register that controls the input/output direction of each pin in port 3. P3DDR is a
write-only register. Read data is invalid. If read, all bits always read 1.
Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded
mode with on-chip ROM enabled), the input/output directions designated by P3DDR are ignored.
Port 3 automatically consists of the input/output pins of the 8-bit data bus (D7to D0).
The data bus is in the high-impedance state during reset, and during hardware and software standby.
Mode 3: A pin in port 3 is used for general output if the corresponding P3DDR bit is set to 1, and
for general input if this bit is cleared to 0. P3DDR is initialized to H'00 by a reset and in hardware
standby mode. In software standby mode it retains its existing values, so if a transition to software
standby mode occurs while a P3DDR bit is set to 1, the corresponding pin remains in the output
state.
Bit
Initial value
Read/Write
7
P3 DDR
0
W
7
6
P3 DDR
0
W
6
5
P3 DDR
0
W
5
4
P3 DDR
0
W
4
3
P3 DDR
0
W
3
2
P3 DDR
0
W
2
1
P3 DDR
0
W
1
0
P3 DDR
0
W
0
109
Port 3 Data Register (P3DR)
P3DR is an 8-bit register that stores data for pins P37to P30. When a P3DDR bit is set to 1, if port 3
is read, the value in P3DR is obtained directly, regardless of the actual pin state. When a P3DDR bit
is cleared to 0, if port 3 is read the pin state is obtained.
P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Port 3 Input Pull-Up Control Register (P3PCR)
P3PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. If a
P3DDR bit is cleared to 0 (designating input) and the corresponding P3PCR bit is set to 1, the input
pull-up transistor is turned on.
P3PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
The input pull-ups cannot be used in slave mode (when the host interface is enabled).
Bit
Initial value
Read/Write
7
P37PCR
0
R/W
6
P36PCR
0
R/W
5
P35PCR
0
R/W
4
P34PCR
0
R/W
3
P33PCR
0
R/W
0
P30PCR
0
R/W
2
P32PCR
0
R/W
1
P31PCR
0
R/W
Bit
Initial value
Read/Write
7
P3
0
R/W
7
6
P3
0
R/W
6
5
P3
0
R/W
5
4
P3
0
R/W
4
3
P3
0
R/W
3
2
P3
0
R/W
2
1
P3
0
R/W
1
0
P3
0
R/W
0
110
7.4.3 Pin Functions in Each Mode
Port 3 has different pin functions in different modes. A separate description for each mode is given
below.
Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and
mode 2 (expanded mode with on-chip ROM enabled), port 3 is automatically used for the
input/output pins of the data bus (D7to D0). Figure 7-10 shows the pin functions in modes 1 and 2.
Figure 7-10 Pin Functions in Modes 1 and 2 (Port 3)
D7 (input/output)
D6 (input/output)
D5 (input/output)
D4 (input/output)
D3 (input/output)
D2 (input/output)
D1 (input/output)
D0 (input/output)
Port 3
Modes 1 and 2
111
Mode 3: In mode 3 (single-chip mode), when the host interface enable bit (HIE) is cleared to 0 in
the system control register (SYSCR), port 3 is a general-purpose input/output port. A pin becomes
an output pin when its P3DDR bit is set to 1, and an input pin when this bit is cleared to 0.
When the HIE bit is set to 1, selecting slave mode, port 3 becomes the host interface data bus
(HDB7to HDB0). P3DR and P3DDR should be cleared to H'00 in slave mode. For details, see
section 14, Host Interface.
Figure 7-11 shows the pin functions in mode 3.
Figure 7-11 Pin Functions in Mode 3 (Port 3)
7.4.4 Input Pull-Up Transistors
Port 3 has built-in programmable input pull-up transistors that are available in mode 3. The pull-up
for each bit can be turned on and off individually. To turn on an input pull-up in mode 3, set the
corresponding P3PCR bit to 1 and clear the corresponding P3DDR bit to 0. P3PCR is cleared to
H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby
mode, the previous state is maintained.
Table 7-7 indicates the states of the input pull-up transistors in each operating mode.
Table 7-7 States of Input Pull-Up Transistors (Port 3)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off Off Off
2 Off Off Off Off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P3PCR = 1 and P3DDR = 0, but off otherwise.
P37 (input/output)/HDB7 (input/output)
P36 (input/output)/HDB6 (input/output)
P35 (input/output)/HDB5 (input/output)
P34 (input/output)/HDB4 (input/output)
P33 (input/output)/HDB3 (input/output)
P32 (input/output)/HDB2 (input/output)
P31 (input/output)/HDB1 (input/output)
P30 (input/output)/HDB0 (input/output)
Port 3
112
7.5 Port 4
7.5.1 Overview
Port 4 is an 8-bit input/output port that is multiplexed with input/output pins (TMRI0, TMRI1,
TMCI0, TMCI1, TMO0, TMO1) of 8-bit timers 0 and 1 and output pins (PW0, PW1) of PWM timers
0 and 1. In slave mode, P43to P45output host interrupt requests. Pins not used by timers or for host
interrupt requests are available for general input/output.
Figure 7-12 shows the pin configuration of port 4.
Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor.
Figure 7-12 Port 4 Pin Configuration
P47/PW1
P46/PW0
P45/TMRI1/HIRQ12
P44/TMO1/HIRQ1
P43/TMCI1/HIRQ11
P42/TMRI0
P41/TMO0
P40/TMCI0
Port 4
Port 4 pins
P47 (input/output)/PW1 (output)
P46 (input/output)/PW0 (output)
P45 (input/output)/TMRI1 (input)
P44 (input/output)/TMO1 (output)
P43 (input/output)/TMCI1 (input)
P42 (input/output)/TMRI0 (input)
P41 (input/output)/TMO0 (output)
P40 (input/output)/TMCI0 (input)
Pin configuration in modes 1 to 3
Master mode
P47 (input/output)/PW1 (output)
P46 (input/output)/PW0 (output)
HIRQ12 (output)/TMRI1 (input)
HIRQ1 (output)/TMO1 (output)
HIRQ11 (output)/TMCI1 (input)
P42 (input/output)/TMRI0 (input)
P41 (input/output)/TMO0 (output)
P40 (input/output)/TMCI0 (input)
Slave mode
113
7.5.2 Register Configuration and Descriptions
Table 7-8 summarizes the port 4 registers.
Table 7-8 Port 4 Registers
Name Abbreviation Read/Write Initial Value Address
Port 4 data direction register P4DDR W H'00 H'FFB5
Port 4 data register P4DR R/W H'00 H'FFB7
Port 4 Data Direction Register (P4DDR)
P4DDR is an 8-bit register that controls the input/output direction of each pin in port 4. A pin
functions as an output pin if the corresponding P4DDR bit is set to 1, and as an input pin if this bit is
cleared to 0.
P4DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values, so if a transition to software standby mode occurs while a P4DDR bit is
set to 1, the corresponding pin remains in the output state.
If a transition to software standby mode occurs while port 4 is being used by an on-chip supporting
module (for example, for 8-bit timer output), the on-chip supporting module will be initialized, so
the pin will revert to general-purpose input/output, controlled by P4DDR and P4DR.
Bit
Initial value
Read/Write
7
P4 DDR
0
W
7
6
P4 DDR
0
W
6
5
P4 DDR
0
W
5
4
P4 DDR
0
W
4
3
P4 DDR
0
W
3
2
P4 DDR
0
W
2
1
P4 DDR
0
W
1
0
P4 DDR
0
W
0
114
Port 4 Data Register (P4DR)
P4DR is an 8-bit register that stores data for pins P47to P40. When a P4DDR bit is set to 1, if port 4
is read, the value in P4DR is obtained directly, regardless of the actual pin state. When a P4DDR bit
is cleared to 0, if port 4 is read the pin state is obtained. This also applies to pins used by on-chip
supporting modules.
P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Bit
Initial value
Read/Write
7
P4
0
R/W
7
6
P4
0
R/W
6
5
P4
0
R/W
5
4
P4
0
R/W
4
3
P4
0
R/W
3
2
P4
0
R/W
2
1
P4
0
R/W
1
0
P4
0
R/W
0
115
7.5.3 Pin Functions
Port 4 has different pin functions depending on whether the chip is or is not operating in slave
mode. Table 7-9 indicates the pin functions of port 4.
Table 7-9 Port 4 Pin Functions
Pin Pin Functions and Selection Method
P47/PW1Bit OE in TCR of PWM timer 1 and bit P47DDR select the pin function as follows
OE 0 1
P47DDR 0 1 0 1
Pin function P47input P47output PW1output
P46/PW0Bit OE in TCR of PWM timer 0 and bit P46DDR select the pin function as follows
OE 0 1
P46DDR 0 1 0 1
Pin function P46input P46output PW0output
P45/TMRI1/ Bit P45DDR and the operating mode select the pin function as follows
HIRQ12 P45DDR 0 1
Operating mode — Not slave mode Slave mode
Pin function P45input P45output HIRQ12 output
TMRI1input
TMRI1input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of
8-bit timer 1
P44/TMO1/ Bits OS3 to OS0 in TCSR of 8-bit timer 1, bit P44DDR, and the operating mode
HIRQ1select the pin function as follows
OS3 to 0 All 0 Not all 0
P44DDR 0 1 —
Operating mode — Not slave mode Slave mode —
Pin function P44input P44output HIRQ1output TMO1output
116
Table 7-9 Port 4 Pin Functions (cont)
Pin Pin Functions and Selection Method
P43/TMCI1/ Bit P43DDR and the operating mode select the pin function as follows
HIRQ11 P43DDR 0 1
Operating mode — Not slave mode Slave mode
Pin function P43input P43output HIRQ11 output
TMCI1input
TMCI1input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 1 select an
external clock source
P42/TMRI0P42DDR 0 1
Pin function P42input P42output
TMRI0input
TMRI0input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of
8-bit timer 0
P41/TMO0Bits OS3 to OS0 in TCSR of 8-bit timer 0 and bit P41DDR select the pin function as
follows
OS3 to 0 All 0 Not all 0
P41DDR 0 1 0 1
Pin function P41input P41output TMO0output
P40/TMCI0P40DDR 0 1
Pin function P40input P40output
TMCI0input
TMCI0input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 0 select an
external clock source
117
7.6 Port 5
7.6.1 Overview
Port 5 is a 3-bit input/output port that is multiplexed with input/output pins (TxD0, RxD0, SCK0) of
serial communication interface 0. The port 5 pin functions are the same in all operating modes.
Figure 7-13 shows the pin configuration of port 5.
Pins in port 5 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington
transistor.
Figure 7-13 Port 5 Pin Configuration
7.6.2 Register Configuration and Descriptions
Table 7-10 summarizes the port 5 registers.
Table 7-10 Port 5 Registers
Name Abbreviation Read/Write Initial Value Address
Port 5 data direction register P5DDR W H'F8 H'FFB8
Port 5 data register P5DR R/W H'F8 H'FFBA
P52 (input/output)/SCK0 (input/output)
P51 (input/output)/RxD0 (input)
P50 (input/output)/TxD0 (output)
Port 5 pins
Port 5
118
Port 5 Data Direction Register (P5DDR)
P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin
functions as an output pin if the corresponding P5DDR bit is set to 1, and as an input pin if this bit is
cleared to 0.
P5DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P5DDR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it
retains its existing values, so if a transition to software standby mode occurs while a P5DDR bit is
set to 1, the corresponding pin remains in the output state.
If a transition to software standby mode occurs while port 5 is being used by the SCI, the SCI will
be initialized, so the pin will revert to general-purpose input/output, controlled by P5DDR and
P5DR.
Port 5 Data Register (P5DR)
P5DR is an 8-bit register that stores data for pins P52to P50. Bits 7 to 3 are reserved. They cannot
be modified, and are always read as 1.
When a P5DDR bit is set to 1, if port 5 is read, the value in P5DR is obtained directly, regardless of
the actual pin state. When a P5DDR bit is cleared to 0, if port 5 is read the pin state is obtained. This
also applies to pins used as SCI pins.
P5DR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
P5
0
R/W
2
1
P5
0
R/W
1
0
P5
0
R/W
0
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
P5 DDR
0
W
2
1
P5 DDR
0
W
1
0
P5 DDR
0
W
0
119
7.6.3 Pin Functions
Port 5 has the same pin functions in each operating mode. All pins can also be used as SCI0
input/output pins. Table 7-11 indicates the pin functions of port 5.
Table 7-11 Port 5 Pin Functions
Pin Pin Functions and Selection Method
P52/SCK0Bit C/Ain SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0, and bit P52DDR
select the pin function as follows
CKE1 0 1
C/A01—
CKE0 0 1 — —
P52DDR 0 1 — — —
Pin function P52P52SCK0SCK0SCK0
input output output output input
P51/RxD0Bit RE in SCR of SCI0 and bit P51DDR select the pin function as follows
RE 0 1
P51DDR 0 1 —
Pin function P51input P51output RxD0input
P50/TxD0Bit TE in SCR of SCI0 and bit P50DDR select the pin function as follows
TE 0 1
P50DDR 0 1 —
Pin function P50input P50output TxD0output
120
7.7 Port 6
7.7.1 Overview
Port 6 is an 8-bit input/output port that is multiplexed with input/output pins (FTOA, FTOB, FTIA
to FTID, FTCI) of the 16-bit free-running timer (FRT), with key-sense input pins, and with IRQ6
and IRQ7input pins. The port 6 pin functions are the same in all operating modes. Figure 7-14
shows the pin configuration of port 6.
Port 6 has built-in, programmable MOS input pull-up transistors.
Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor.
Figure 7-14 Port 6 Pin Configuration
P67 (input/output)/IRQ7 (input)/KEYIN7 (input)
P66 (input/output)/FTOB (output)/IRQ6 (input)/KEYIN6 (input)
P65 (input/output)/FTID (input)/KEYIN5 (input)
P64 (input/output)/FTIC (input)/KEYIN4 (input)
P63 (input/output)/FTIB (input)/KEYIN3 (input)
P62 (input/output)/FTIA (input)/KEYIN2 (input)
P61 (input/output)/FTOA (output)/KEYIN1 (input)
P60 (input/output)/FTCI (input)/KEYIN0 (input)
Port 6
Port 6 pins
121
7.7.2 Register Configuration and Descriptions
Table 7-12 summarizes the port 6 registers.
Table 7-12 Port 6 Registers
Name Abbreviation Read/Write Initial Value Address
Port 6 data direction register P6DDR W H'00 H'FFB9
Port 6 data register P6DR R/W H'00 H'FFBB
Port 6 input pull-up control KMPCR R/W H'00 H'FFF2
register
Port 6 Data Direction Register (P6DDR)
P6DDR is an 8-bit register that controls the input/output direction of each pin in port 6. A pin
functions as an output pin if the corresponding P6DDR bit is set to 1, and as an input pin if this bit is
cleared to 0.
P6DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P6DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values, so if a transition to software standby mode occurs while a P6DDR bit is
set to 1, the corresponding pin remains in the output state.
If a transition to software standby mode occurs while port 6 is being used by the free-running timer,
the timer will be initialized, so the pin will revert to general-purpose input/output, controlled by
P6DDR and P6DR.
Bit
Initial value
Read/Write
7
P67DDR
0
W
6
P66DDR
0
W
5
P65DDR
0
W
4
P64DDR
0
W
3
P63DDR
0
W
2
P62DDR
0
W
1
P61DDR
0
W
0
P60DDR
0
W
122
Port 6 Data Register (P6DR)
P6DR is an 8-bit register that stores data for pins P67to P60. When a P6DDR bit is set to 1, if port 6
is read, the value in P6DR is obtained directly, regardless of the actual pin state. When a P6DDR bit
is cleared to 0, if port 6 is read the pin state is obtained. This also applies to pins used as FRT pins.
P6DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Port 6 Input Pull-Up Control Register (KMPCR)
KMPCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 6. If a
P6DDR bit is cleared to 0 (designating input) and the corresponding KMPCR bit is set to 1, the
input pull-up transistor is turned on.
KMPCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Bit
Initial value
Read/Write
7
KM7PCR
0
R/W
6
KM6PCR
0
R/W
5
KM5PCR
0
R/W
4
KM4PCR
0
R/W
3
KM3PCR
0
R/W
0
KM0PCR
0
R/W
2
KM2PCR
0
R/W
1
KM1PCR
0
R/W
Bit
Initial value
Read/Write
7
P67
0
R/W
6
P66
0
R/W
5
P65
0
R/W
4
P64
0
R/W
3
P63
0
R/W
2
P62
0
R/W
1
P61
0
R/W
0
P60
0
R/W
123
7.7.3 Pin Functions
Port 6 has the same pin functions in all operating modes. The pins are multiplexed with FRT
input/output, IRQ6and IRQ7input, and key-sense input. Table 7-13 indicates the pin functions of
port 6.
Table 7-13 Port 6 Pin Functions
Pin Pin Functions and Selection Method
P67/IRQ7/
KEYIN7P67DDR 0 1
Pin function P67input P67output
IRQ7input or KEYIN7input
IRQ7input is usable when bit IRQ7E is set to 1 in IER
P66/FTOB/ Bit OEB in TOCR of the FRT and bit P66DDR select the pin function as follows
IRQ6/KEYIN6OEB 0 1
P66DDR 0 1 0 1
Pin function P66input P66output FTOB output
IRQ6input or KEYIN6input
IRQ6input is usable when bit IRQ6E is set to 1 in IER
P65/FTID/
KEYIN5P65DDR 0 1
Pin function P65input P65output
FTID input or KEYIN5input
P64/FTIC/
KEYIN4P64DDR 0 1
Pin function P64input P64output
FTIC input or KEYIN4input
124
Table 7-13 Port 6 Pin Functions (cont)
Pin Pin Functions and Selection Method
P63/FTIB/
KEYIN3P63DDR 0 1
Pin function P63input P63output
FTIB input or KEYIN3input
P62/FTIA/
KEYIN2P62DDR 0 1
Pin function P62input P62output
FTIA input or KEYIN2input
P61/FTOA/ Bit OEA in TOCR of the FRT and bit P61DDR select the pin function as follows
KEYIN1OEA 0 1
P61DDR 0 1 0 1
Pin function P61input P61output FTOA output
KEYIN1input
P60/FTCI/
KEYIN0P60DDR 0 1
Pin function P60input P60output
FTCI input or KEYIN0input
FTCI input is usable when bits CKS1 to CKS0 in TCR of the FRT select an
external clock source
125
7.7.4 Input Pull-Up Transistors
Port 6 has built-in programmable input pull-up transistors. The pull-up for each bit can be turned on
and off individually. To turn on an input pull-up, set the corresponding KMPCR bit to 1 and clear
the corresponding P6DDR bit to 0. KMPCR is cleared to H'00 by a reset and in hardware standby
mode, turning all input pull-ups off. In software standby mode, the previous state is maintained.
Table 7-14 indicates the states of the input pull-up transistors in each operating mode.
Table 7-14 States of Input Pull-Up Transistors (Port 6)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off On/off On/off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if KMPCR = 1 and P6DDR = 0, but off otherwise.
126
7.8 Port 7
7.8.1 Overview
Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter and analog
output pins for the D/A converter. The pin functions are the same in all modes. Figure 7-15 shows
the pin configuration of port 7.
Figure 7-15 Port 7 Pin Configuration
P77 (input)/AN7 (input)/DA1 (output)
P76 (input)/AN6 (input)/DA0 (output)
P75 (input)/AN5 (input)
P74 (input)/AN4 (input)
P73 (input)/AN3 (input)
P72 (input)/AN2 (input)
P71 (input)/AN1 (input)
P70 (input)/AN0 (input)
Port 7
Port 7 pins
127
7.8.2 Register Configuration and Descriptions
Table 7-15 summarizes the port 7 registers. Port 7 is an input port, so there is no data direction
register.
Table 7-15 Port 7 Register
Name Abbreviation Read/Write Initial Value Address
Port 7 input data register P7PIN R Undetermined H'FFBE
Note: The port 7 input data register (P7PIN) has the same address as the port B data direction
register (PBDDR).
Port 7 Input Data Register (P7PIN)
When P7PIN is read, the pin states are always read. P7PIN is a read-only register and cannot be
written to. Write access results in writing to PBDDR.
Bit
Initial value
Read/Write
0
P70
—*
R
Note: *
1
P71
—*
R
2
P72
—*
R
3
P73
—*
R
4
P74
—*
R
5
P75
—*
R
6
P76
—*
R
7
P77
—*
R
Depends on the levels of pins P77 to P70.
128
7.9 Port 8
7.9.1 Overview
Port 8 is a 7-bit input/output port that is multiplexed with host interface (HIF) input pins (HA0,
GA20, CS1, IOR, IOW, CS2), with input/output pins (TxD1, RxD1, SCK1) of serial communication
interface 1, with the I2C clock input/output pin (SCL), and with interrupt input pins (IRQ5to IRQ3).
Figure 7-16 shows the pin configuration of port 8. The configuration of the pin functions of pins P85
and P84will depend on the value of bit STAC in STCR. Pins P86and P83to P80are unaffected by
bit STAC.
Pins in port 8 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington
transistor. Pin P86can be driven as a bus buffer, as shown in section 13, I2C Bus Interface.
Figure 7-16 Port 8 Pin Configuration
P86/SCK1/IRQ5/SCL
P85/RxD1/IRQ4/CS2
P84/TxD1/IRQ3/IOW
P83/IOR
P82/CS1
P81/GA20
P80/HA0
Port 8
Port 8 pins
P86 (input/output)/IRQ5 (input)/SCK1 (input/output)
P85 (input/output)/IRQ4 (input)/RxD1 (input)
P84 (input/output)/IRQ3 (input)/TxD1 (output)
P83 (input/output)
P82 (input/output)
P81 (input/output)
P80 (input/output)
Pin configuration in master mode,
or when STAC bit is 1
Pin configuration in slave mode
When STAC bit is 0
P86 (input/output)/IRQ5 (input)/SCK1 (input/output)/SCL (input/output)
IRQ4 (input)/CS2 (input)
IRQ3 (input)/IOW (input)
IOR (input)
CS1 (input)
P81 (input/output)/GA20 (output)
HA0 (input)
129
7.9.2 Register Configuration and Descriptions
Table 7-16 summarizes the port 8 registers.
Table 7-16 Port 8 Registers
Name Abbreviation Read/Write Initial Value Address
Port 8 data direction register P8DDR W H'80 H'FFBD
Port 8 data register P8DR R/W H'80 H'FFBF
Note: The port 8 data direction register (P8DDR) has the same address as the port B input data
register (PBPIN).
Port 8 Data Direction Register (P8DDR)
P8DDR is an 8-bit register that controls the input/output direction of each pin in port 8. A pin
functions as an output pin if the corresponding P8DDR bit is set to 1, and as an input pin if this bit is
cleared to 0. P8DDR is a write-only register. Read data is invalid. If read, all bits always read 1. Bit
7 is a reserved bit that always reads 1.
P8DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode
P8DDR retains its existing values, so if a transition to software standby mode occurs while a
P8DDR bit is set to 1, the corresponding pin remains in the output state.
7
—
1
—
6
P86DDR
0
W
5
P85DDR
0
W
4
P84DDR
0
W
3
P83DDR
0
W
2
P82DDR
0
W
1
P81DDR
0
W
0
P80DDR
0
W
Bit
Initial value
Read/Write
130
Port 8 Data Register (P8DR)
P8DR is an 8-bit register that stores data for pins P86to P80. Bit 7 is a reserved bit that always reads
1.
When a P8DDR bit is set to 1, if port 8 is read, the value in P8DR is obtained directly, regardless of
the actual pin state. When a P8DDR bit is cleared to 0, if port 8 is read the pin state is obtained. This
also applies to pins used by on-chip supporting modules.
P8DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Bit
Initial value
Read/Write
7
—
1
—
6
P86
0
R/W
5
P85
0
R/W
4
P84
0
R/W
3
P83
0
R/W
2
P82
0
R/W
1
P81
0
R/W
0
P80
0
R/W
131
7.9.3 Pin Functions
Pins P86to P80are multiplexed with HIF input/output, SCI1 input/output, I2C clock input/output,
and IRQ5to IRQ3input. Table 7-17 indicates the functions of pins P86to P80.
Table 7-17 Port 8 Pin Functions
Pin Pin Functions and Selection Method
P86/IRQ5/ Bit C/Ain SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, bit ICE in ICCR,
SCK1/SCL and bit P86DDR select the pin function as follows
ICE 0 1
CKE1 0 1 —
C/A01——
CKE0 0 1 — — —
P86DDR0 1 ————
Pin function P86P86SCK1SCK1SCK1SCL
input output output output input input/
output
IRQ5input
IRQ5input is usable when bit IRQ5E is set to 1 in IER
P85/IRQ4/ Bit RE in SCR of SCI1, bit STAC in STCR, bit P85DDR, and the operating mode
CS2/RxD1select the pin function as follows
Operating
mode Slave mode Not slave mode
STAC 0 1 —
RE — 0 1 0 1
P85DDR — 0 1 — 0 1 —
Pin function CS2P85P85RxD1P85P85RxD1
input input output input input output input
IRQ4input
IRQ4input is usable when bit IRQ4E is set to 1 in IER
132
Table 7-17 Port 8 Pin Functions
Pin Pin Functions and Selection Method
P84/IRQ3/ Bit TE in SCR of SCI1, bit STAC in STCR, bit P84DDR, and the operating mode
IOW/TxD1select the pin function as follows
Operating
mode Slave mode Not slave mode
STAC 0 1 —
TE — 0 1 0 1
P84DDR — 0 1 — 0 1 —
Pin function IOW P84P84TxD1P84P84TxD1
input input output output input output output
IRQ3input
IRQ3input is usable when bit IRQ3E is set to 1 in IER
P83/IOR Bit P83DDR and the operating mode select the pin function as follows
Operating mode Slave mode Not slave mode
P83DDR — 0 1
Pin function IOR input P83input P83output
P82/CS1Bit P82DDR and the operating mode select the pin function as follows
Operating mode Slave mode Not slave mode
P82DDR — 0 1
Pin function CS1input P82input P82output
P81/GA20 Bit P81DDR and the operating mode select the pin function as follows
P81DDR 0 1
FGA20E — 0 1
Operating mode — Not slave mode Slave mode
Pin function P81input P81output GA20 output
P80/HA0Bit P80DDR and the operating mode select the pin function as follows
Operating mode Slave mode Not slave mode
P80DDR — 0 1
Pin function HA0input P80input P80output
133
7.10 Port 9
7.10.1 Overview
Port 9 is an 8-bit input/output port that is multiplexed with interrupt input pins (IRQ0to IRQ2),
input/output pins for bus control signals (RD, WR, AS, WAIT), an input pin (ADTRG) for the A/D
converter, an output pin (ø) for the system clock, host interface (HIF) input pins (ECS2, EIOW), and
the I2C data input/output pin (SDA). Figure 7-17 shows the pin configuration of port 9. The
functions of pins P91and P90are configured according to bit STAC in STCR. Pins P97to P92are
unaffected by bit STAC.
Pins in port 9 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor. Pin P97can be driven as a bus buffer, as shown in section 13, I2C Bus Interface.
Figure 7-17 Port 9 Pin Configuration
P97/WAIT/SDA
P96/ø
P95/AS
P94/WR
P93/RD
P92/IRQ0
Port 9
Port 9 pins
P97 (input/output)/WAIT (input)/SDA (input/output)
ø (output)
AS (output)
WR (output)
RD (output)
P92 (input/output)/IRQ0 (input)
Pin configuration in mode 1 (expanded mode
with on-chip ROM disabled) and mode 2
(expanded mode with on-chip ROM enabled)
P97 (input/output)/SDA (input/output)
P96 (input)/ø (output)
P95 (input/output)
P94 (input/output)
P93 (input/output)
P92 (input/output)/IRQ0 (input)
Pin configuration in mode 3 (single-chip mode)
134
Figure 7-17 Port 9 Pin Configuration (cont)
7.10.2 Register Configuration and Descriptions
Table 7-18 summarizes the port 9 registers.
Table 7-18 Port 9 Registers
Name Abbreviation Read/Write Initial Value Address
Port 9 data direction register P9DDR W H'40 (modes 1 and 2) H'FFC0
H'00 (mode 3)
Port 9 data register P9DR R/W*1Undetermined*2H'FFC1
Notes: 1. Bit 6 is read-only.
2. Bit 6 is undetermined. Other bits are initially 0.
P91/IRQ1/EIOW
P90/IRQ2/ADTRG/ECS2
Port 9
P91 (input/output)/IRQ1 (input)
P90 (input/output)/IRQ2 (input)/ADTRG (input)
Pin configuration in master mode,
or when STAC bit is 0
Pin configuration in slave mode
when STAC bit is 1
IRQ1 (input)/EIOW (input)
IRQ2 (input)/ECS2 (input)
135
Port 9 Data Direction Register (P9DDR)
P9DDR is an 8-bit register that controls the input/output direction of each pin in port 9. A pin
functions as an output pin if the corresponding P9DDR bit is set to 1, and as an input pin if this bit is
cleared to 0. In modes 1 and 2, P96DDR is fixed at 1 and cannot be modified.
P9DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P9DDR is initialized by a reset and in hardware standby mode. The initial value is H'40 in modes 1
and 2, and H'00 in mode 3. In software standby mode P9DDR retains its existing values, so if a
transition to software standby mode occurs while a P9DDR bit is set to 1, the corresponding pin
remains in the output state.
Port 9 Data Register (P9DR)
P9DR is an 8-bit register that stores data for pins P97to P90. When a P9DDR bit is set to 1, if port 9
is read, the value in P9DR is obtained directly, regardless of the actual pin state, except for P96.
When a P9DDR bit is cleared to 0, if port 9 is read the pin state is obtained. This also applies to pins
used by on-chip supporting modules and for bus control signals. P96always returns the pin state.
P9DR pins other than P96are initialized to 0 by a reset and in hardware standby mode. In software
standby mode it retains its existing values.
Bit
Initial value
Read/Write
7
P97
0
R/W
6
P96
—*
R
5
P95
0
R/W
4
P94
0
R/W
3
P93
0
R/W
2
P92
0
R/W
1
P91
0
R/W
0
P90
0
R/W
Note: * Determined by the level at pin P96.
7
P97DDR
0
W
0
W
6
P96DDR
1
—
0
W
5
P95DDR
0
W
0
W
4
P94DDR
0
W
0
W
3
P93DDR
0
W
0
W
2
P92DDR
0
W
0
W
1
P91DDR
0
W
0
W
0
P90DDR
0
W
0
W
Bit
Modes 1, 2
Initial value
Read/Write
Mode 3
Initial value
Read/Write
136
7.10.3 Pin Functions
Port 9 has one set of pin functions in modes 1 and 2, and a different set of pin functions in mode 3.
The pins are multiplexed with IRQ0to IRQ2input, bus control signal input/output, A/D converter
input, system clock (ø) output, host interface input (ECS2, EIOW), and I2C data input/output
(SDA). Table 7-19 indicates the pin functions of port 9.
Table 7-19 Port 9 Pin Functions
Pin Pin Functions and Selection Method
P97/WAIT/SDA Bit ICE in ICCR, bit P97DDR, the wait mode as determined by WSCR, and the
operating mode select the pin function as follows
Operating mode Modes 1 and 2 Mode 3
Wait mode WAIT WAIT not used —
used
ICE — 0 1 0 1
P97DDR —01—0 1—
Pin function WAIT P97P97SDA P97P97SDA
input input output input/ input output input/
output output
P96/ø Bit P96DDR and the operating mode select the pin function as follows
Operating mode Modes 1 and 2 Mode 3
P96DDR Always 1 0 1
Pin function ø output P96input ø output
P95/AS Bit P95DDR and the operating mode select the pin function as follows
Operating mode Modes 1 and 2 Mode 3
P95DDR — 0 1
Pin function AS output P95input P95output
P94/WR Bit P94DDR and the operating mode select the pin function as follows
Operating mode Modes 1 and 2 Mode 3
P94DDR — 0 1
Pin function WR output P94input P94output
137
Table 7-19 Port 9 Pin Functions (cont)
Pin Pin Functions and Selection Method
P93/RD Bit P93DDR and the operating mode select the pin function as follows
Operating mode Modes 1 and 2 Mode 3
P93DDR — 0 1
Pin function RD output P93input P93output
P92/IRQ0P92DDR 0 1
Pin function P92input P92output
IRQ0input
IRQ0input can be used when bit IRQ0E is set to 1 in IER
P91/IRQ1/ Bit STAC in STCR, bit P91DDR, and the operating mode select the pin function as
EIOW follows
Operating mode Slave mode Not slave mode
STAC 0 1 —
P91DDR 0 1 — 0 1
Pin function P91input P91output EIOW input P91input P91output
IRQ1input
IRQ1input can be used when bit IRQ1E is set to 1 in IER
P90/IRQ2/ Bit STAC in STCR, bit P90DDR, and the operating mode select the pin function as
ADTRG/ECS2follows
Operating mode Slave mode Not slave mode
STAC 0 1 —
P90DDR 0 1 — 0 1
Pin function P90input P90output ECS2input P90input P90output
IRQ2input and IRQ2input IRQ2input and
ADTRG input ADTRG input
IRQ2input can be used when bit IRQ2E is set to 1 in IER
ADTRG input can be used when bit TRGE is set to 1 in ADCR
138
7.11 Port A
7.11.1 Overview
Port A is an 8-bit input/output port that is multiplexed with key-sense input pins. The port A pin
functions are the same in all operating modes. Figure 7-18 shows the pin configuration of port A.
Port A has built-in, programming MOS input pull-up transistors.
Pins in port A can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor. Pins PA4, PA5, PA6, and PA7can be driven as bus buffers, as shown in section 13, I2C
Bus Interface.
Figure 7-18 Port A Pin Configuration
7.11.2 Register Configuration and Descriptions
Table 7-20 summarizes the port A registers.
Table 7-20 Port A Registers
Name Abbreviation Read/Write Initial Value Address
Port A data direction register PADDR W H'00 H'FFAB
Port A output data register PAODR R/W H'00 H'FFAA
Port A input data register PAPIN R Undetermined H'FFAB
Note: The data direction register (PADDR) and input data register (PAPIN) have the same address.
PA7 (input/output)/KEYIN15 (input)
PA6 (input/output)/KEYIN14 (input)
PA5 (input/output)/KEYIN13 (input)
PA4 (input/output)/KEYIN12 (input)
PA3 (input/output)/KEYIN11 (input)
PA2 (input/output)/KEYIN10 (input)
PA1 (input/output)/KEYIN9 (input)
PA0 (input/output)/KEYIN8 (input)
Port A
Port A pins
139
Port A Data Direction Register (PADDR)
PADDR is an 8-bit register that controls the input/output direction of each pin in port A. A pin
functions as an output pin if the corresponding PADDR bit is set to 1, and as an input pin if this bit
is cleared to 0.
PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values, so if a transition to software standby mode occurs while a PADDR bit is
set to 1, the corresponding pin remains in the output state.
Port A Output Data Register (PAODR)
PAODR is an 8-bit register that stores data for pins PA7to PA0. PAODR can always be written to
and read, regardless of the PADDR settings.
PAODR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Port A Input Data Register (PAPIN)
When PAPIN is read, the pin states are always read.
Bit
Initial value
Read/Write
0
PA0
—*
R
Note: *
1
PA1
—*
R
2
PA2
—*
R
3
PA3
—*
R
4
PA4
—*
R
5
PA5
—*
R
6
PA6
—*
R
7
PA7
—*
R
Depends on the levels of pins PA7 to PA0.
Bit
Initial value
Read/Write
7
PA7
0
R/W
6
PA6
0
R/W
5
PA5
0
R/W
4
PA4
0
R/W
3
PA3
0
R/W
2
PA2
0
R/W
1
PA1
0
R/W
0
PA0
0
R/W
Bit
Initial value
Read/Write
7
PA7DDR
0
W
6
PA6DDR
0
W
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
0
PA0DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
140
7.11.3 Pin Functions in Each Mode
Port A has the same pin functions in all operating modes. Table 7-21 indicates the pin functions of
port A.
Table 7-21 Port A Pin Functions
Pin Pin Functions and Selection Method
PA7/KEYIN15 PA7DDR 0 1
Pin function PA7input PA7output
KEYIN15 input
This pin is driven as a bus buffer when bit IICS is set to 1 in STCR
PA6/KEYIN14 PA6DDR 0 1
Pin function PA6input PA6output
KEYIN14 input
This pin is driven as a bus buffer when bit IICS is set to 1 in STCR
PA5/KEYIN13 PA5DDR 0 1
Pin function PA5input PA5output
KEYIN13 input
This pin is driven as a bus buffer when bit IICS is set to 1 in STCR
PA4/KEYIN12 PA4DDR 0 1
Pin function PA4input PA4output
KEYIN12 input
This pin is driven as a bus buffer when bit IICS is set to 1 in STCR
141
Table 7-21 Port A Pin Functions (cont)
Pin Pin Functions and Selection Method
PA3/KEYIN11 PA3DDR 0 1
Pin function PA3input PA3output
KEYIN11 input
PA2/KEYIN10 PA2DDR 0 1
Pin function PA2input PA2output
KEYIN10 input
PA1/KEYIN9PA1DDR 0 1
Pin function PA1input PA1output
KEYIN9input
PA0/KEYIN8PA0DDR 0 1
Pin function PA0input PA0output
KEYIN8input
7.11.4 Input Pull-Up Transistors
Port A has built-in programmable input pull-up transistors that are available in all modes.
An input pull-up transistor is turned on if 1 is written in the corresponding PAODR bit while the
corresponding PADDR bit is cleared to 0. The input pull-ups are turned off by a reset and in
hardware standby mode.
Table 7-22 indicates the states of the input pull-up transistors in each operating mode.
Table 7-22 States of Input Pull-Up Transistors (Port A)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off On/off On/off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if PAODR = 1 and PADDR = 0, but off otherwise.
142
7.12 Port B
7.12.1 Overview
Port B is an 8-bit input/output port that is multiplexed with the host interface data bus. The pin
functions differ depending on the operating mode. Figure 7-19 shows the pin configuration of port
B.
Port B has program-controllable built-in MOS input pull-up transistors.
Pins in port B can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor.
Figure 7-19 Port B Pin Configuration
PB7/XDB7
PB6/XDB6
PB5/XDB5
PB4/XDB4
PB3/XDB3
PB2/XDB2
PB1/XDB1
PB0/XDB0
Port B
Port B pins
PB7 (input/output)
PB6 (input/output)
PB5 (input/output)
PB4 (input/output)
PB3 (input/output)
PB2 (input/output)
PB1 (input/output)
PB0 (input/output)
Pin configuration in mode 1
(expanded mode with on-chip ROM
disabled) and mode 2 (expanded
mode with on-chip ROM enabled)
PB7 (input/output)
PB6 (input/output)
PB5 (input/output)
PB4 (input/output)
PB3 (input/output)
PB2 (input/output)
PB1 (input/output)
PB0 (input/output)
Pin configuration in mode 3
(single-chip mode)
Master mode
XDB7 (input/output)
XDB6 (input/output)
XDB5 (input/output)
XDB4 (input/output)
XDB3 (input/output)
XDB2 (input/output)
XDB1 (input/output)
XDB0 (input/output)
Slave mode
143
7.12.2 Register Configuration and Descriptions
Table 7-23 summarizes the port B registers.
Table 7-23 Port B Registers
Name Abbreviation Read/Write Initial Value Address
Port B data direction register PBDDR W H'00 H'FFBE
Port B output data register PBODR R/W H'00 H'FFBC
Port B input data register PBPIN R Undetermind H'FFBD
Note: The port B data direction register (PBDDR) and port 7 input data register 7 (P7PIN) have the
same address.
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit register that controls the input/output direction of each pin in port B. A pin
functions as an output pin if the corresponding PBDDR bit is set to 1, and as an input pin if this bit
is cleared to 0.
PBDDR is a write-only register. Read data is invalid. If read, the values of the port 7 data input
register (P7PIN) are returned, indicating the pin levels of port 7.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values, so if a transition to software standby mode occurs while a PBDDR bit is
set to 1, the corresponding pin remains in the output state.
Bit
Initial value
Read/Write
7
PB DDR
0
W
7
6
PB DDR
0
W
6
5
PB DDR
0
W
5
4
PB DDR
0
W
4
3
PB DDR
0
W
3
2
PB DDR
0
W
2
1
PB DDR
0
W
1
0
PB DDR
0
W
0
144
Port B Output Data Register (PBODR)
PBODR is an 8-bit register that stores data for pins PB7to PB0. PBODR can always be written to
and read, regardless of the PBDDR settings.
PBODR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Port B Input Data Register (PBPIN)
When PBPIN is read, the pin states are always read.
Bit
Initial value
Read/Write
0
PB0
—*
R
Note: *
1
PB1
—*
R
2
PB2
—*
R
3
PB3
—*
R
4
PB4
—*
R
5
PB5
—*
R
6
PB6
—*
R
7
PB7
—*
R
Depends on the levels of pins PB7 to PB0.
Bit
Initial value
Read/Write
7
PB
0
R/W
7
6
PB
0
R/W
6
5
PB
0
R/W
5
4
PB
0
R/W
4
3
PB
0
R/W
3
2
PB
0
R/W
2
1
PB
0
R/W
1
0
PB
0
R/W
0
145
7.12.3 Pin Functions in Each Mode
Port B has different pin functions in different modes. A separate description for each mode is given
below.
Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and
mode 2 (expanded mode with on-chip ROM enabled), when the host interface enable bit (HIE) is
cleared to 0 in the system control register (SYSCR), port B is a general-purpose input/output port.
When the HIE bit is set to 1, selecting slave mode, port B becomes the host interface data bus
(XDB7to XDB0). PBODR and PBDDR should be cleared to H'00 in slave mode. For details, see
section 14, Host Interface.
Figure 7-20 shows the pin functions in modes 1 and 2.
Figure 7-20 Pin Functions in Modes 1 and 2 (Port B)
PB7 (input/output)/XDB7 (input/output)
PB6 (input/output)/XDB6 (input/output)
PB5 (input/output)/XDB5 (input/output)
PB4 (input/output)/XDB4 (input/output)
PB3 (input/output)/XDB3 (input/output)
PB2 (input/output)/XDB2 (input/output)
PB1 (input/output)/XDB1 (input/output)
PB0 (input/output)/XDB0 (input/output)
Port B
146
Pin Functions in Mode 3: In mode 3 (single-chip mode), each pin can be designated for general
input or output. A pin becomes an output pin when its PBDDR bit is set to 1, and an input pin when
this bit is cleared to 0. Figure 7-21 shows the pin functions in mode 3.
Figure 7-21 Pin Functions in Mode 3 (Port B)
7.12.4 Input Pull-Up Transistors
Port B has built-in programmable input pull-up transistors that are available in mode 3. The pull-up
for each bit can be turned on and off individually.
An input pull-up transistor is turned on in mode 3 if 1 is written in the corresponding PBODR bit
while the corresponding PBDDR bit is cleared to 0.
The input pull-ups are turned off by a reset and in hardware standby mode. In software standby
mode, the previous state is maintained.
Table 7-24 indicates the states of the input pull-up transistors in each operating mode.
Table 7-24 States of Input Pull-Up Transistors (Port B)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off On/off On/off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if PBDR = 1 and PBDDR = 0, but off otherwise.
PB7 (input/output)
PB6 (input/output)
PB5 (input/output)
PB4 (input/output)
PB3 (input/output)
PB2 (input/output)
PB1 (input/output)
PB0 (input/output)
Port B
Mode 3
147
Section 8 16-Bit Free-Running Timer
8.1 Overview
The H8/3437 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-
running counter as a time base. Applications of the FRT module include rectangular-wave output
(up to two independent waveforms), input pulse width measurement, and measurement of external
clock periods.
8.1.1 Features
The features of the free-running timer module are listed below.
• Selection of four clock sources
The free-running counter can be driven by an internal clock source (øP/2, øP/8, or øP/32), or an
external clock input (enabling use as an external event counter).
• Two independent comparators
Each comparator can generate an independent waveform.
• Four input capture channels
The current count can be captured on the rising or falling edge (selectable) of an input signal.
The four input capture registers can be used separately, or in a buffer mode.
• Counter can be cleared under program control
The free-running counters can be cleared on compare-match A.
• Seven independent interrupts
Compare-match A and B, input capture A to D, and overflow interrupts are requested
independently.
149
8.1.2 Block Diagram
Figure 8-1 shows a block diagram of the free-running timer.
Figure 8-1 Block Diagram of 16-Bit Free-Running Timer
External
clock source
Internal
clock sources
Clock select
Comparator A
OCRA (H/L)
Comparator B
OCRB (H/L)
Bus interface
Internal
data bus
øP/2
øP/8
øP/32
FTCI
Compare-
match A
Clear
Clock
FTOA
FTOB
Overflow
ICRA (H/L)
Compare-
match B
Capture
FRC (H/L)
TCSR
FTIA
FTIB
FTIC
FTID
Control
logic
Module data bus
TIER
TCR
TOCR
Interrupt signals
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Legend
FRC:
OCRA, B:
ICRA, B, C, D:
TCSR:
Free-running counter (16 bits)
Output compare register A, B (16 bits)
Input capture register A, B, C, D (16 bits)
Timer control/status register (8 bits)
TIER:
TCR:
TOCR:
Timer interrupt enable register (8 bits)
Timer control register (8 bits)
Timer output compare control
register (8 bits)
ICRB (H/L)
ICRC (H/L)
ICRD (H/L)
150
8.1.3 Input and Output Pins
Table 8-1 lists the input and output pins of the free-running timer module.
Table 8-1 Input and Output Pins of Free-Running Timer Module
Name Abbreviation I/O Function
Counter clock input FTCI Input Input of external free-running counter clock
signal
Output compare A FTOA Output Output controlled by comparator A
Output compare B FTOB Output Output controlled by comparator B
Input capture A FTIA Input Trigger for capturing current count into input
capture register A
Input capture B FTIB Input Trigger for capturing current count into input
capture register B
Input capture C FTIC Input Trigger for capturing current count into input
capture register C
Input capture D FTID Input Trigger for capturing current count into input
capture register D
8.1.4 Register Configuration
Table 8-2 lists the registers of the free-running timer module.
Table 8-2 Register Configuration
Initial
Name Abbreviation R/W Value Address
Timer interrupt enable register TIER R/W H'01 H'FF90
Timer control/status register TCSR R/(W)*1H'00 H'FF91
Free-running counter (high) FRC (H) R/W H'00 H'FF92
Free-running counter (low) FRC (L) R/W H'00 H'FF93
Output compare register A/B (high)*2OCRA/B (H) R/W H'FF H'FF94*2
Output compare register A/B (low)*2OCRA/B (L) R/W H'FF H'FF95*2
Timer control register TCR R/W H'00 H'FF96
Timer output compare control register TOCR R/W H'E0 H'FF97
Input capture register A (high) ICRA (H) R H'00 H'FF98
Input capture register A (low) ICRA (L) R H'00 H'FF99
Notes: 1. Software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits.
2. OCRA and OCRB share the same addresses. Access is controlled by the OCRS
bit in TOCR.
151
Table 8-2 Register Configuration (cont.)
Initial
Name Abbreviation R/W Value Address
Input capture register B (high) ICRB (H) R H'00 H'FF9A
Input capture register B (low) ICRB (L) R H'00 H'FF9B
Input capture register C (high) ICRC (H) R H'00 H'FF9C
Input capture register C (low) ICRC (L) R H'00 H'FF9D
Input capture register D (high) ICRD (H) R H'00 H'FF9E
Input capture register D (low) ICRD (L) R H'00 H'FF9F
8.2 Register Descriptions
8.2.1 Free-Running Counter (FRC)
FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a
clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the
timer control register (TCR).
When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status
register (TCSR) is set to 1.
Because FRC is a 16-bit register, a temporary register (TEMP) is used when FRC is written or read.
See section 8.3, CPU Interface, for details.
FRC is initialized to H'0000 by a reset and in the standby modes.
Bit
Initial
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
value
WriteRead/
152
8.2.2 Output Compare Registers A and B (OCRA and OCRB)
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output compare
flag (OCFA or OCFB) is set in the timer control/status register (TCSR).
In addition, if the output enable bit (OEA or OEB) in the timer output compare control register
(TOCR) is set to 1, when the output compare register and FRC values match, the logic level selected
by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or
FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match.
OCRA and OCRB share the same address. They are differentiated by the OCRS bit in TOCR. A
temporary register (TEMP) is used for write access, as explained in
section 8.3, CPU Interface.
OCRA and OCRB are initialized to H'FFFF by a reset and in the standby modes.
8.2.3 Input Capture Registers A to D (ICRA to ICRD)
There are four input capture registers A to D, each of which is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected, the
current FRC value is copied to the corresponding input capture register (ICRA to ICRD).* At the
same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status register
(TCSR) is set to 1. The input capture edge is selected by the input edge select bits (IEDGA to
IEDGD) in the timer control register (TCR).
Note: * The FRC contents are transferred to the input capture register regardless of the value of the
input capture flag (ICFA/B/C/D).
Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in
TCR is set to 1, ICRC is used as a buffer register for ICRA as shown in figure 8-2. When an FTIA
input is received, the old ICRA contents are moved into ICRC, and the new FRC count is copied
into ICRA.
Bit
Initial
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
value
WriteRead/
Bit
Initial
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
value
WriteRead/
153
Figure 8-2 Input Capture Buffering (Example)
Similarly, when the BUFEB bit in TCR is set to 1, ICRD is used as a buffer register for ICRB.
When input capture is buffered, if the two input edge bits are set to different values (IEDGA ≠
IEDGC or IEDGB ≠IEDGD), then input capture is triggered on both the rising and falling edges of
the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =
IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge. See table 8-3.
Table 8-3 Buffered Input Capture Edge Selection (Example)
IEDGA IEDGC Input Capture Edge
0 0 Captured on falling edge of input capture A (FTIA) (Initial value)
0 1 Captured on both rising and falling edges of input capture A (FTIA)
10
1 1 Captured on rising edge of input capture A (FTIA)
Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when
they are read. See section 8.3, CPU Interface, for details.
To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock
periods (1.5·ø). When triggering is enabled on both edges, the input capture pulse width should be at
least 2.5 system clock periods.
The input capture registers are initialized to H'0000 by a reset and in the standby modes.
BUFEA:
IEDGA:
IEDGC:
ICRC:
ICRA:
FRC:
Buffer enable A
Input edge select A
Input edge select C
Input capture register C
Input capture register A
Free-running counter
BUFEA
IEDGA IEDGC
FTIA Edge detect and
capture signal
generating circuit
FRCICRC ICRA
154
8.2.4 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit readable/writable register that enables and disables interrupts.
TIER is initialized to H'01 by a reset and in the standby modes.
Bit 7—Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input
capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register
(TCSR) is set to 1.
Bit 7
ICIAE Description
0 Input capture interrupt request A (ICIA) is disabled. (Initial value)
1 Input capture interrupt request A (ICIA) is enabled.
Bit 6—Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input
capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Bit 6
ICIBE Description
0 Input capture interrupt request B (ICIB) is disabled. (Initial value)
1 Input capture interrupt request B (ICIB) is enabled.
Bit 5—Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input
capture interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.
Bit 5
ICICE Description
0 Input capture interrupt request C (ICIC) is disabled. (Initial value)
1 Input capture interrupt request C (ICIC) is enabled.
Bit
Initial value
Read/Write
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
3
OCIAE
0
R/W
0
—
1
—
2
OCIBE
0
R/W
1
OVIE
0
R/W
R/W
155
Bit 4—Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input
capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.
Bit 4
ICIDE Description
0 Input capture interrupt request D (ICID) is disabled. (Initial value)
1 Input capture interrupt request D (ICID) is enabled.
Bit 3—Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request output
compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 3
OCIAE Description
0 Output compare interrupt request A (OCIA) is disabled. (Initial value)
1 Output compare interrupt request A (OCIA) is enabled.
Bit 2—Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request output
compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Bit 2
OCIBE Description
0 Output compare interrupt request B (OCIB) is disabled. (Initial value)
1 Output compare interrupt request B (OCIB) is enabled.
Bit 1—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a free-
running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit 1
OVIE Description
0 Timer overflow interrupt request (FOVI) is disabled. (Initial value)
1 Timer overflow interrupt request (FOVI) is enabled.
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
156
8.2.5 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and partially writable register that contains the seven interrupt flags and
specifies whether to clear the counter on compare-match A (when the FRC and OCRA values
match).
TCSR is initialized to H'00 by a reset and in the standby modes.
Timing is described in section 8.4, Operation.
Bit 7—Input Capture Flag A (ICFA): This status bit is set to 1 to flag an input capture A event. If
BUFEA = 0, ICFA indicates that the FRC value has been copied to ICRA. If BUFEA = 1, ICFA
indicates that the old ICRA value has been moved into ICRC and the new FRC value has been
copied to ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7
ICFA Description
0 To clear ICFA, the CPU must read ICFA after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when an FTIA input signal causes the FRC value to be copied to
ICRA.
Bit 6—Input Capture Flag B (ICFB): This status bit is set to 1 to flag an input capture B event. If
BUFEB = 0, ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = 1, ICFB
indicates that the old ICRB value has been moved into ICRD and the new FRC value has been
copied to ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6
ICFB Description
0To clear ICFB, the CPU must read ICFB after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when an FTIB input signal causes the FRC value to be copied to
ICRB.
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)*
6
ICFB
0
R/(W)*
5
ICFC
0
4
ICFD
0
3
OCFA
0
0
OCLRA
0
R/W
2
OCFB
0
R/(W)*
1
OVF
0
R/(W)*
R/(W)*
R/(W)*R/(W)*
Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits.
157
Bit 5—Input Capture Flag C (ICFC): This status bit is set to 1 to flag input of a rising or falling
edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of the FRC
count in ICRC. When BUFEA = 1, however, the FRC count is not captured, so ICFC becomes
simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as a general-
purpose interrupt signal (which can be enabled or disabled by the ICICE bit).
ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5
ICFC Description
0 To clear ICFC, the CPU must read ICFC after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when an FTIC input signal is received.
Bit 4—Input Capture Flag D (ICFD): This status bit is set to 1 to flag input of a rising or falling
edge of FTID as selected by the IEDGD bit. When BUFEB = 0, this indicates capture of the FRC
count in ICRD. When BUFEB = 1, however, the FRC count is not captured, so ICFD becomes
simply an external interrupt flag. In other words, the buffer mode frees FTID for use as a general-
purpose interrupt signal (which can be enabled or disabled by the ICIDE bit).
ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 4
ICFD Description
0 To clear ICFD, the CPU must read ICFD after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when an FTID input signal is received.
Bit 3—Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches
the OCRA value. This flag must be cleared by software. It is set by hardware, however, and cannot
be set by software.
Bit 3
OCFA Description
0 To clear OCFA, the CPU must read OCFA after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when FRC = OCRA.
158
Bit 2—Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches
the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot
be set by software.
Bit 2
OCFB Description
0 To clear OCFB, the CPU must read OCFB after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when FRC = OCRB.
Bit 1—Timer Overflow Flag (OVF): This status flag is set to 1 when FRC overflows (changes
from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however, and
cannot be set by software.
Bit 1
OVF Description
0 To clear OVF, the CPU must read OVF after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when FRC changes from H'FFFF to H'0000.
Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear FRC at compare-match A
(when the FRC and OCRA values match).
Bit 0
CCLRA Description
0 The FRC is not cleared. (Initial value)
1 The FRC is cleared at compare-match A.
8.2.6 Timer Control Register (TCR)
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in the standby modes.
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
4
IEDGD
0
3
BUFEA
0
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
R/W
R/W R/W
159
Bit 7—Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input
capture A signal (FTIA).
Bit 7
IEDGA Description
0 Input capture A events are recognized on the falling edge of FTIA. (Initial value)
1 Input capture A events are recognized on the rising edge of FTIA.
Bit 6—Input Edge Select B (IEDGB): This bit selects the rising or falling edge of the input
capture B signal (FTIB).
Bit 6
IEDGB Description
0 Input capture B events are recognized on the falling edge of FTIB. (Initial value)
1 Input capture B events are recognized on the rising edge of FTIB.
Bit 5—Input Edge Select C (IEDGC): This bit selects the rising or falling edge of the input
capture C signal (FTIC).
Bit 5
IEDGC Description
0 Input capture C events are recognized on the falling edge of FTIC. (Initial value)
1 Input capture C events are recognized on the rising edge of FTIC.
Bit 4—Input Edge Select D (IEDGD): This bit selects the rising or falling edge of the input
capture D signal (FTID).
Bit 4
IEDGD Description
0 Input capture D events are recognized on the falling edge of FTID. (Initial value)
1 Input capture D events are recognized on the rising edge of FTID.
Bit 3—Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 3
BUFEA Description
0 ICRC is used for input capture C. (Initial value)
1 ICRC is used as a buffer register for input capture A.
160
Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2
BUFEB Description
0 ICRD is used for input capture D. (Initial value)
1 ICRD is used as a buffer register for input capture B.
Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for FRC. External clock pulses are counted on the rising edge of signals
input to pin FTCI.
Bit 1 Bit 0
CKS1 CKS0 Description
00 ø
P
/2 internal clock source (Initial value)
01 ø
P
/8 internal clock source
10 ø
P
/32 internal clock source
1 1 External clock source (rising edge)
8.2.7 Timer Output Compare Control Register (TOCR)
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, and switches access between output compare registers A and B.
TOCR is initialized to H'E0 by a reset and in the standby modes.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
When this address is accessed, the OCRS bit selects which register is accessed. This bit does not
affect the operation of OCRA or OCRB.
Bit 4
OCRS Description
0 OCRA is selected. (Initial value)
1 OCRB is selected.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
4
OCRS
0
3
OEA
0
0
OLVLB
0
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
R/W
—R/W
161
Bit 3—Output Enable A (OEA): This bit enables or disables output of the output compare A
signal (FTOA).
Bit 3
OEA Description
0 Output compare A output is disabled. (Initial value)
1 Output compare A output is enabled.
Bit 2—Output Enable B (OEB): This bit enables or disables output of the output compare B signal
(FTOB).
Bit 2
OEB Description
0 Output compare B output is disabled. (Initial value)
1 Output compare B output is enabled.
Bit 1—Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin
when the FRC and OCRA values match.
Bit 1
OLVLA Description
0 A 0 logic level is output for compare-match A. (Initial value)
1 A 1 logic level is output for compare-match A.
Bit 0—Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin
when the FRC and OCRB values match.
Bit 0
OLVLB Description
0 A 0 logic level is output for compare-match B. (Initial value)
1 A 1 logic level is output for compare-match B.
162
8.3 CPU Interface
The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture
registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When the
CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the access
is performed using an 8-bit temporary register (TEMP).
These registers are written and read as follows:
• Register Write
When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when
the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all
16 bits are written in the register simultaneously.
• Register Read
When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower
byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP.
Programs that access these registers should normally use word access. Equivalently, they may
access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be
transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed.
Figure 8-3 shows the data flow when FRC is accessed. The other registers are accessed in the same
way. As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower
bytes directly, without using TEMP.
Coding Examples
To write the contents of general register R0 to OCRA: MOV.W R0, @OCRA
To transfer the contents of ICRA to general register R0: MOV.W @ICRA, R0
163
Figure 8-3 (a) Write Access to FRC (when CPU Writes H'AA55)
CPU writes
data H'AA
(1) Upper byte write
(2) Lower byte write
CPU writes
data H'55
Bus
interface
Bus
interface
Module data bus
Module data bus
TEMP
[H'AA]
FRCH
[ ] FRCL
[ ]
TEMP
[H'AA]
FRCH
[H'AA] FRCL
[H'55]
164
Figure 8-3 (b) Read Access to FRC (when FRC Contains H'AA55)
CPU reads
data H'AA
(1) Upper byte read
(2) Lower byte read
CPU reads
data H'55
Bus
interface
Bus
interface
Module data bus
Module data bus
TEMP
[H'55]
FRCH
[H'AA] FRCL
[H'55]
TEMP
[H'55]
FRCH
[ ] FRCL
[ ]
165
8.4 Operation
8.4.1 FRC Increment Timing
FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source. The clock source is selected by bits CKS0 and CKS1 in TCR.
Internal Clock: The internal clock sources (øP/2, øP/8, øP/32) are created from the system clock (ø)
by a prescaler. FRC increments on a pulse generated from the falling edge of the prescaler output.
See figure 8-4.
Figure 8-4 Increment Timing for Internal Clock Source
N – 1
FRC clock
pulse
ø
FRC
Internal
clock
N N + 1
166
External Clock: If external clock input is selected, FRC increments on the rising edge of the FTCI
clock signal. Figure 8-5 shows the increment timing.
The pulse width of the external clock signal must be at least 1.5 system clock (ø) periods. The
counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
Figure 8-5 Increment Timing for External Clock Source
N + 1N
FRC clock
pulse
ø
FRC
FTCI
167
8.4.2 Output Compare Timing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB)
in TOCR is output at the output compare pin (FTOA or FTOB). Figure 8-6 shows the timing of this
operation for compare-match A.
Figure 8-6 Timing of Output Compare A
N + 1NN + 1N
N
OCRA
ø
Internal compare-
match A signal
FRC
OLVLA
FTOA
Clear*
Note: * Cleared by software
N
168
8.4.3 FRC Clear Timing
If the CCLRA bit in TCSR is set to 1, the FRC is cleared when compare-match A occurs. Figure 8-7
shows the timing of this operation.
Figure 8-7 Clearing of FRC by Compare-Match A
N H'0000
FRC
ø
Internal compare-
match A signal
169
8.4.4 Input Capture Timing
(1) Input Capture Timing: An internal input capture signal is generated from the rising or falling
edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding
IEDGx bit in TCR. Figure 8-8 shows the usual input capture timing when the rising edge is selected
(IEDGx = 1).
Figure 8-8 Input Capture Timing (Usual Case)
If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal arrives,
the internal input capture signal is delayed by one state. Figure 8-9 shows the timing for this case.
Figure 8-9 Input Capture Timing (1-State Delay Due to ICRA/B/C/D Read)
Internal input
capture signal
ø
Input at FTI pin
T1T2T3
ICR upper byte read cycle
Internal input
capture signal
ø
Input data
FTI pin
170
(2) Buffered Input Capture Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB.
Figure 8-10 shows how input capture operates when ICRA and ICRC are used in buffer mode and
IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and
IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
Figure 8-10 Buffered Input Capture with Both Edges Selected
n n + 1 N N + 1
MnnN
mM Mn
ø
FTIA
Internal input
capture signal
FRC
ICRA
ICRC
171
When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if
the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to ICRC,
however.
In buffered input capture, if the upper byte of either of the two registers to which data will be
transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives, input
capture is delayed by one system clock (ø). Figure 8-11 shows the timing when BUFEA = 1.
Figure 8-11 Input Capture Timing (1-State Delay, Buffer Mode)
Internal input
capture signal
ø
Input at
FTIA pin
T1T2T3
Read cycle:
CPU reads upper byte of ICRA or ICRC
172
8.4.5 Timing of Input Capture Flag (ICF) Setting
The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. Figure
8-12 shows the timing of this operation.
Figure 8-12 Setting of Input Capture Flag
ICF
ø
FRC
Internal input
capture signal
N
NICR
173
8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB)
The output compare flags are set to 1 by an internal compare-match signal generated when the FRC
value matches the OCRA or OCRB value. This compare-match signal is generated at the last state
in which the two values match, just before FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 8-13 shows the timing of the setting of the output
compare flags.
Figure 8-13 Setting of Output Compare Flags
OCRA or OCRB
ø
Internal compare-
match signal
FRC N N + 1
N
OCFA or OCFB
174
8.4.7 Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).
Figure 8-14 shows the timing of this operation.
Figure 8-14 Setting of Overflow Flag (OVF)
8.5 Interrupts
The free-running timer can request seven interrupts (three types): input capture A to D (ICIA, ICIB,
ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt can
be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt
controller for each interrupt. Table 8-4 lists information about these interrupts.
Table 8-4 Free-Running Timer Interrupts
Interrupt Description Priority
ICIA Requested by ICFA High
ICIB Requested by ICFB
ICIC Requested by ICFC
ICID Requested by ICFD
OCIA Requested by OCFA
OCIB Requested by OCFB
FOVI Requested by OVF Low
H'FFFF H'0000
Internal overflow
signal
ø
FRC
OVF
175
8.6 Sample Application
In the example below, the free-running timer is used to generate two square-wave outputs with a
50% duty cycle and arbitrary phase relationship. The programming is as follows:
(1) The CCLRA bit in TCSR is set to 1.
(2) Each time a compare-match interrupt occurs, software inverts the corresponding output level bit
in TOCR (OLVLA or OLVLB).
Figure 8-15 Square-Wave Output (Example)
FRC
Clear counter
H'FFFF
OCRA
OCRB
H'0000
FTOA
FTOB
176
8.7 Application Notes
Application programmers should note that the following types of contention can occur in the free-
running timer.
(1) Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the T3state of a write cycle to the lower byte of the free-running counter, the clear signal
takes priority and the write is not performed.
Figure 8-16 shows this type of contention.
Figure 8-16 FRC Write-Clear Contention
T1T2T3
Write cycle:
CPU write to lower byte of FRC
Internal address
bus FRC address
Internal write
signal
ø
FRC clear signal
FRC N H'0000
177
(2) Contention between FRC Write and Increment: If an FRC increment pulse is generated
during the T3state of a write cycle to the lower byte of the free-running counter, the write takes
priority and FRC is not incremented.
Figure 8-17 shows this type of contention.
Figure 8-17 FRC Write-Increment Contention
T1T2T3
Write cycle:
CPU write to lower byte of FRC
Internal address bus
Internal write signal
ø
FRC clock pulse
FRC N M
Write data
FRC address
178
(3) Contention between OCR Write and Compare-Match: If a compare-match occurs during the
T3state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the
compare-match signal is inhibited.
Figure 8-18 shows this type of contention.
Figure 8-18 Contention between OCR Write and Compare-Match
T1T2T3
Write cycle:
CPU write to lower byte of OCRA or OCRB
Internal address bus
Internal write signal
ø
FRC
OCRA or OCRB N M
Write data
OCR address
N N + 1
Compare-match
A or B signal Inhibited
179
(4) Increment Caused by Changing of Internal Clock Source: When an internal clock source is
changed, the changeover may cause FRC to increment. This depends on the time at which the clock
select bits (CKS1 and CKS0) are rewritten, as shown in table 8-5.
The pulse that increments FRC is generated at the falling edge of the internal clock source. If clock
sources are changed when the old source is high and the new source is low, as in case no. 3 in table
8-5, the changeover generates a falling edge that triggers the FRC increment clock pulse.
Switching between an internal and external clock source can also cause FRC to increment.
Table 8-5 Effect of Changing Internal Clock Sources
No. Description Timing
1 Low →low:
CKS1 and CKS0 are
rewritten while both
clock sources are low.
2 Low →high:
CKS1 and CKS0 are
rewritten while old
clock source is low and
new clock source is high.
180
N + 1
Old clock
source
New clock
source
FRC clock
pulse
FRC
CKS rewrite
N
N + 1 N + 2
Old clock
source
New clock
source
FRC clock
pulse
FRC
CKS rewrite
N
Table 8-5 Effect of Changing Internal Clock Sources (cont)
No. Description Timing
3 High →low:
CKS1 and CKS0 are
rewritten while old
clock source is high and
new clock source is low.
4 High →high:
CKS1 and CKS0 are
rewritten while both
clock sources are high.
Note: *The switching of clock sources is regarded as a falling edge that increments FRC.
181
N + 1N N + 2
*
Old clock
source
New clock
source
FRC clock
pulse
FRC
CKS rewrite
N + 1 N + 2N
Old clock
source
New clock
source
FRC clock
pulse
CKS rewrite
FRC
Section 9 8-Bit Timers
9.1 Overview
The H8/3437 Series includes an 8-bit timer module with two channels (numbered 0 and 1). Each
channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that
are constantly compared with the TCNT value to detect compare-match events. One of the many
applications of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary
duty cycle.
9.1.1 Features
The features of the 8-bit timer module are listed below.
• Selection of seven clock sources
The counters can be driven by one of six internal clock signals or an external clock input
(enabling use as an external event counter).
• Selection of three ways to clear the counters
The counters can be cleared on compare-match A or B, or by an external reset signal.
• Timer output controlled by two time constants
The timer output signal in each channel is controlled by two independent time constants,
enabling the timer to generate output waveforms with an arbitrary duty cycle, or PWM
waveforms.
• Three independent interrupts
Compare-match A and B and overflow interrupts can be requested independently.
183
9.1.2 Block Diagram
Figure 9-1 shows a block diagram of one channel in the 8-bit timer module.
Figure 9-1 Block Diagram of 8-Bit Timer (1 Channel)
External
clock source
TMCI
TMO
TMRI
Internal
clock sources Channel 0 Channel 1
øP/2
øP/8
øP/32
øP/64
øP/256
øP/1024
øP/2
øP/8
øP/64
øP/128
øP/1024
øP/2048
Clock
Overflow
Clear
Compare-match B
Control
logic
Clock select TCORA
Comparator A
TCNT
Comparator B
TCORB
TCSR
TCR
Module data bus
Bus interface
Internal
data bus
CMIA
CMIB
OVI
Interrupt signals
TCR:
TCSR:
TCORA:
TCORB:
TCNT:
Timer control register (8 bits)
Timer control status register (8 bits)
Time constant register A (8 bits)
Time constant register B (8 bits)
Timer counter
Compare-match A
184
9.1.3 Input and Output Pins
Table 9-1 lists the input and output pins of the 8-bit timer.
Table 9-1 Input and Output Pins of 8-Bit Timer
Abbreviation*
Name Channel 0 Channel 1 I/O Function
Timer output TMO0TMO1Output Output controlled by compare-match
Timer clock input TMCI0TMCI1Input External clock source for the counter
Timer reset input TMRI0TMRI1Input External reset signal for the counter
Note: *In this manual, the channel subscript has been deleted, and only TMO TMCI, and TMRI are
used.
9.1.4 Register Configuration
Table 9-2 lists the registers of the 8-bit timer module. Each channel has an independent set of
registers.
Table 9-2 8-Bit Timer Registers
Channel Name Abbreviation R/W Initial Value Address
0 Timer control register TCR R/W H'00 H'FFC8
Timer control/status register TCSR R/(W)*H'10 H'FFC9
Time constant register A TCORA R/W H'FF H'FFCA
Time constant register B TCORB R/W H'FF H'FFCB
Timer counter TCNT R/W H'00 H'FFCC
1 Timer control register TCR R/W H'00 H'FFD0
Timer control/status register TCSR R/(W)*H'10 H'FFD1
Time constant register A TCORA R/W H'FF H'FFD2
Time constant register B TCORB R/W H'FF H'FFD3
Timer counter TCNT R/W H'00 H'FFD4
0, 1 Serial/timer control register STCR R/W H'00 H'FFC3
Note: *Software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits.
185
9.2 Register Descriptions
9.2.1 Timer Counter (TCNT)
Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an
internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer
control register (TCR). The CPU can always read or write the timer counter.
The timer counter can be cleared by an external reset input or by an internal compare-match signal
generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer
control register select the method of clearing.
When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to 1.
The timer counters are initialized to H'00 by a reset and in the standby modes.
9.2.2 Time Constant Registers A and B (TCORA and TCORB)
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared
with the constants written in these registers (except during the T3state of a write cycle to TCORA
or TCORB). When a match is detected, the corresponding compare-match flag (CMFA or CMFB)
is set in the timer control/status register (TCSR).
The timer output signal is controlled by these compare-match signals as specified by output select
bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).
TCORA and TCORB are initialized to H'FF by a reset and in the standby modes.
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
186
9.2.3 Timer Control Register (TCR)
TCR is an 8-bit readable/writable register that selects the clock source and the time at which the
timer counter is cleared, and enables interrupts.
TCR is initialized to H'00 by a reset and in the standby modes.
For timing diagrams, see section 9.3, Operation.
Bit 7—Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer control/status
register (TCSR) is set to 1.
Bit 7
CMIEB Description
0 Compare-match interrupt request B (CMIB) is disabled. (Initial value)
1 Compare-match interrupt request B (CMIB) is enabled.
Bit 6—Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in TCSR is set to 1.
Bit 6
CMIEA Description
0 Compare-match interrupt request A (CMIA) is disabled. (Initial value)
1 Compare-match interrupt request A (CMIA) is enabled.
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
187
Bit 5—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in TCSR is set to 1.
Bit 5
OVIE Description
0 The timer overflow interrupt request (OVI) is disabled. (Initial value)
1 The timer overflow interrupt request (OVI) is enabled.
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or B or by an external reset input (TMRI).
Bit 4 Bit 3
CCLR1 CCLR0 Description
0 0 Not cleared. (Initial value)
0 1 Cleared on compare-match A.
1 0 Cleared on compare-match B.
1 1 Cleared on rising edge of external reset input signal.
188
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and ICKS0
in the serial/timer control register (STCR) select the internal or external clock source for the timer
counter. Six internal clock sources, derived by prescaling the system clock, are available for each
timer channel. For internal clock sources the counter is incremented on the falling edge of the
internal clock. For an external clock source, these bits can select whether to increment the counter
on the rising or falling edge of the clock input (TMCI), or on both edges.
TCR STCR
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 0 — — No clock source (timer stopped) (Initial value)
001 —0 ø
P
/8 internal clock, counted on falling edge
001 —1 ø
P
/2 internal clock, counted on falling edge
010 —0 ø
P
/64 internal clock, counted on falling edge
010 —1 ø
P
/32 internal clock, counted on falling edge
011 —0 ø
P
/1024 internal clock, counted on falling edge
011 —1 ø
P
/256 internal clock, counted on falling edge
1 0 0 — — No clock source (timer stopped)
1 0 1 — — External clock source, counted on rising edge
1 1 0 — — External clock source, counted on falling edge
1 1 1 — — External clock source, counted on both rising
and falling edges
1 0 0 0 — — No clock source (timer stopped) (Initial value)
001 0 —ø
P
/8 internal clock, counted on falling edge
001 1 —ø
P
/2 internal clock, counted on falling edge
010 0 —ø
P
/64 internal clock, counted on falling edge
010 1 —ø
P
/128 internal clock, counted on falling edge
011 0 —ø
P
/1024 internal clock, counted on falling edge
011 1 —ø
P
/2048 internal clock, counted on falling edge
1 0 0 — — No clock source (timer stopped)
1 0 1 — — External clock source, counted on rising edge
1 1 0 — — External clock source, counted on falling edge
1 1 1 — — External clock source, counted on both rising
and falling edges
189
9.2.4 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and partially writable register that indicates compare-match and overflow
status and selects the effect of compare-match events on the timer output signal.
TCSR is initialized to H'10 by a reset and in the standby modes.
Bit 7—Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count matches
the time constant set in TCORB. CMFB must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 7
CMFB Description
0 To clear CMFB, the CPU must read CMFB after it has been set to 1 (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when TCNT = TCORB.
Bit 6—Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count matches
the time constant set in TCORA. CMFA must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 6
CMFA Description
0 To clear CMFA, the CPU must read CMFA after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when TCNT = TCORA.
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
190
Bit 5—Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows
(changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however, and
cannot be set by software.
Bit 5
OVF Description
0 To clear OVF, the CPU must read OVF after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when TCNT changes from H'FF to H'00.
Bit 4—Reserved: This bit is always read as 1. It cannot be written.
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of TCOR–TCNT
compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of
compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on
the output level.
If compare-match A and B occur simultaneously, any conflict is resolved according to the following
priority order: toggle > 1 output > 0 output.
When all four output select bits are cleared to 0 the timer output signal is disabled.
After a reset, the timer output is 0 until the first compare-match event.
Bit 3 Bit 2
OS3 OS2 Description
0 0 No change when compare-match B occurs. (Initial value)
0 1 Output changes to 0 when compare-match B occurs.
1 0 Output changes to 1 when compare-match B occurs.
1 1 Output inverts (toggles) when compare-match B occurs.
Bit 1 Bit 0
OS1 OS0 Description
0 0 No change when compare-match A occurs. (Initial value)
0 1 Output changes to 0 when compare-match A occurs.
1 0 Output changes to 1 when compare-match A occurs.
1 1 Output inverts (toggles) when compare-match A occurs.
191
9.2.5 Serial/Timer Control Register (STCR)
STCR is an 8-bit readable/writable register that controls the I2C bus interface and host interface,
controls the operating mode of the serial communication interface, and selects internal clock sources
for the timer counters.
STCR is initialized to H'00 by a reset.
Bits 7 to 4—I2C Control (IICS, IICD, IICX, IICE): These bits control operation of the I2C bus
interface. For details, see section 13, I2C Bus Interface.
Bit 3—Slave Input Switch (STAC): Controls the switching of the host interface input pins. For
details, see section 14, Host Interface.
Bit 2—Multiprocessor Enable (MPE): Controls the operating mode of serial communication
interfaces 0 and 1. For details, see section 12, Serial Communication Interface.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1 and ICKS0): These bits and bits
CKS2 to CKS0 in the TCR select clock sources for the timer counters. For details, see section
9.2.3, Timer Control Register.
Bit
Initial value
Read/Write
7
IICS
0
R/W
6
IICD
0
R/W
5
IICX
0
R/W
4
IICE
0
R/W
3
STAC
0
R/W
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
192
9.3 Operation
9.3.1 TCNT Increment Timing
The timer counter increments on a pulse generated once for each period of the selected (internal or
external) clock source.
Internal Clock: Internal clock sources are created from the system clock by a prescaler. The
counter increments on an internal TCNT clock pulse generated from the falling edge of the prescaler
output, as shown in figure 9-2. Bits CKS2 to CKS0 of TCR and bits ICKS1 and ICKS0 of STCR
can select one of the six internal clocks.
Figure 9-2 Count Timing for Internal Clock Input
N – 1
TCNT clock
pulse
ø
TCNT
Internal
clock
N N + 1
193
External Clock: If external clock input (TMCI) is selected, the timer counter can increment on the
rising edge, the falling edge, or both edges of the external clock signal. Figure 9-3 shows
incrementation on both edges of the external clock signal.
The external clock pulse width must be at least 1.5 system clock (ø) periods for incrementation on a
single edge, and at least 2.5 system clock periods for incrementation on both edges. The counter will
not increment correctly if the pulse width is shorter than these values.
Figure 9-3 Count Timing for External Clock Input
N – 1 NN + 1
TCNT clock
pulse
ø
TCNT
External clock
source (TMCI)
194
9.3.2 Compare-Match Timing
1. Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are
set to 1 by an internal compare-match signal generated when the timer count matches the time
constant in TCORA or TCORB. The compare-match signal is generated at the last state in which the
match is true, just before the timer counter increments to a new value.
Accordingly, when the timer count matches one of the time constants, the compare-match signal is
not generated until the next period of the clock source. Figure 9-4 shows the timing of the setting of
the compare-match flags.
Figure 9-4 Setting of Compare-Match Flags
TCOR
ø
Internal compare-
match signal
TCNT N
N
N + 1
CMF
195
2. Output Timing: When a compare-match event occurs, the timer output changes as specified by
the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain the
same, change to 0, change to 1, or toggle.
Figure 9-5 shows the timing when the output is set to toggle on compare-match A.
Figure 9-5 Timing of Timer Output
3. Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in TCR, the
timer counter can be cleared when compare-match A or B occurs. Figure 9-6 shows the timing of
this operation.
Figure 9-6 Timing of Compare-Match Clear
TCNT
ø
Internal compare-
match signal
N H'00
Timer output
(TMO)
ø
Internal compare-
match A signal
196
9.3.3 External Reset of TCNT
When the CCLR1 and CCLR0 bits in TCR are both set to 1, the timer counter is cleared on the
rising edge of an external reset input. Figure 9-7 shows the timing of this operation. The timer reset
pulse width must be at least 1.5 system clock (ø) periods.
Figure 9-7 Timing of External Reset
9.3.4 Setting of TCSR Overflow Flag (OVF)
The overflow flag (OVF) is set to 1 when the timer count overflows (changes from H'FF to H'00).
Figure 9-8 shows the timing of this operation.
Figure 9-8 Setting of Overflow Flag (OVF)
H'FF H'00
Internal overflow
signal
ø
TCNT
OVF
Internal clear
pulse
ø
TCNT
External reset
input (TMRI)
N – 1 N H'00
197
9.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt can be enabled or disabled by an enable bit
in TCR. Independent signals are sent to the interrupt controller for each interrupt. Table 9-3 lists
information about these interrupts.
Table 9-3 8-Bit Timer Interrupts
Interrupt Description Priority
CMIA Requested by CMFA High
CMIB Requested by CMFB
OVI Requested by OVF Low
9.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle.
The control bits are set as follows:
(1) In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when
its value matches the constant in TCORA.
(2) In TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-match
A and to 0 on compare-match B.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a
pulse width determined by TCORB. No software intervention is required.
Figure 9-9 Example of Pulse Output
TCNT
Clear counter
H'FF
TCORA
TCORB
H'00
TMO pin
198
9.6 Application Notes
Application programmers should note that the following types of contention can occur in the 8-bit
timer.
9.6.1 Contention between TCNT Write and Clear
If an internal counter clear signal is generated during the T3state of a write cycle to the timer
counter, the clear signal takes priority and the write is not performed.
Figure 9-10 shows this type of contention.
Figure 9-10 TCNT Write-Clear Contention
T1T2T3
Write cycle: CPU writes to TCNT
Internal address
bus TCNT address
Internal write
signal
ø
Counter clear
signal
TCNT N H'00
199
9.6.2 Contention between TCNT Write and Increment
If a timer counter increment pulse is generated during the T3state of a write cycle to the timer
counter, the write takes priority and the timer counter is not incremented.
Figure 9-11 shows this type of contention.
Figure 9-11 TCNT Write-Increment Contention
T1T2T3
Write cycle: CPU writes to TCNT
Internal address bus
Internal write signal
ø
TCNT clock pulse
TNCT N M
Write data
TCNT address
200
9.6.3 Contention between TCOR Write and Compare-Match
If a compare-match occurs during the T3state of a write cycle to TCOR, the write takes priority and
the compare-match signal is inhibited.
Figure 9-12 shows this type of contention.
Figure 9-12 Contention between TCOR Write and Compare-Match
T1T2T3
Write cycle: CPU writes to TCOR
Internal address bus
Internal write signal
ø
TCNT
TCOR N M
TCOR write data
TCOR address
N N + 1
Compare-match
A or B signal
Inhibited
201
9.6.4 Contention between Compare-Match A and Compare-Match B
If identical time constants are written in TCORA and TCORB, causing compare-match A and B to
occur simultaneously, any conflict between the output selections for compare-match A and B is
resolved by following the priority order in table 9-4.
Table 9-4 Priority of Timer Output
Output Selection Priority
Toggle High
1 output
0 output
No change Low
9.6.5 Increment Caused by Changing of Internal Clock Source
When an internal clock source is changed, the changeover may cause the timer counter to
increment. This depends on the time at which the clock select bits (CKS1, CKS0) are rewritten, as
shown in table 9-5.
The pulse that increments the timer counter is generated at the falling edge of the internal clock
source signal. If clock sources are changed when the old source is high and the new source is low,
as in case no. 3 in table 9-5, the changeover generates a falling edge that triggers the TCNT clock
pulse and increments the timer counter.
Switching between an internal and external clock source can also cause the timer counter to
increment.
202
Table 9-5 Effect of Changing Internal Clock Sources
No. Description Timing
1 Low →low*1
2 Low →high*2
Notes: 1. Including a transition from low to the stopped state (CKS1 = 0, CKS0 = 0), or a transition
from the stopped state to low.
2. Including a transition from the stopped state to high.
203
N + 1
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
N
N + 1 N + 2
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
N
Table 9-5 Effect of Changing Internal Clock Sources (cont)
No. Description Timing chart
3 High →low*1
4 High →high
Notes: 1. Including a transition from high to the stopped state.
2. The switching of clock sources is regarded as a falling edge that increments TCNT.
204
N + 1N N + 2
*2
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
N + 1 N + 2N
Old clock
source
New clock
source
TCNT clock
pulse
CKS rewrite
TCNT
Section 10 PWM Timers
10.1 Overview
The H8/3437 Series has an on-chip pulse-width modulation (PWM) timer module with two
independent channels (PWM0 and PWM1). Both channels are functionally identical. Each PWM
channel generates a rectangular output pulse with a duty cycle of 0 to 100%. The duty cycle is
specified in an 8-bit duty register (DTR).
10.1.1 Features
The PWM timer module has the following features:
• Selection of eight clock sources
• Duty cycles from 0 to 100% with 1/250 resolution
• Output with positive or negative logic and software enable/disable control
205
10.1.2 Block Diagram
Figure 10-1 shows a block diagram of one PWM timer channel.
Figure 10-1 Block Diagram of PWM Timer
Comparator
DTR
Bus interface
Internal
data bus
Pulse
TCR
TCNT
Compare-match
øP/2
øP/8
øP/32
øP/128
øP/256
øP/1024
øP/2048
øP/4096
Output
control
Clock Clock
select
Internal clock sources
TCR:
DTR:
TCNT:
Timer control register (8 bits)
Duty register (8 bits)
Timer counter (8 bits)
Module data bus
206
10.1.3 Input and Output Pins
Table 10-1 lists the output pins of the PWM timer module. There are no input pins.
Table 10-1 Output Pins of PWM Timer Module
Name Abbreviation I/O Function
PWM0 output PW0Output Pulse output from PWM timer channel 0.
PWM1 output PW1Output Pulse output from PWM timer channel 1.
10.1.4 Register Configuration
The PWM timer module has three registers for each channel as listed in table 10-2.
Table 10-2 PWM Timer Registers
Initial Address
Name Abbreviation R/W Value PWM0 PWM1
Timer control register TCR R/W H'38 H'FFA0 H'FFA4
Duty register DTR R/W H'FF H'FFA1 H'FFA5
Timer counter TCNT R/W H'00 H'FFA2 H'FFA6
207
10.2 Register Descriptions
10.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. When the output enable bit (OE) is set to 1 in TCR,
TCNT starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2
to CKS0). After counting from H'00 to H'F9, the count repeats from H'00. When TCNT changes
from H'00 to to H'01, the PWM output is placed in the 1 state, unless the DTR value is H'00, in
which case the duty cycle is 0% and the PWM output remains in the 0 state.
TCNT is initialized to H'00 at a reset and in the standby modes, and when the OE bit is cleared to 0.
10.2.2 Duty Register (DTR)
DTR is an 8-bit readable/writable register that specifies the duty cycle of the output pulse. Any duty
cycle from 0% to 100% can be output by setting the corresponding value in DTR. The resolution is
1/250. Writing 0 (H'00) in DTR gives a 0% duty cycle. Writing 125 (H'7D) gives a 50% duty cycle.
Writing 250 (H'FA) gives a 100% duty cycle.
The DTR and TCNT values are always compared. When the values match, the PWM output is
placed in the 0 state.
DTR is double-buffered. A new value written in DTR does not become valid until after the timer
count changes from H'F9 to H'00. While the OE bit is cleared to 0 in TCR, however, new values
written in DTR become valid immediately. When DTR is read, the value read is the currently valid
value.
DTR is initialized to H'FF by a reset and in the standby modes.
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
R/W
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
R/W
208
10.2.3 Timer Control Register (TCR)
TCR is an 8-bit readable/writable register that selects the clock input to TCNT and controls PWM
output.
TCR is initialized to H'38 by a reset and in standby mode.
Bit 7—Output Enable (OE): This bit enables the timer counter and the PWM output.
Bit 7
OE Description
0 PWM output is disabled. TCNT is cleared to H'00 and stopped. (Initial value)
1 PWM output is enabled. TCNT runs.
Bit 6—Output Select (OS): This bit selects positive or negative logic for the PWM output.
Bit 6
OS Description
0 Positive logic; positive-going PWM pulse, 1 = high (Initial value)
1 Negative logic; negative-going PWM pulse, 1 = low
Bits 5 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit
Initial value
Read/Write
7
0
R/W
6
OS
0
R/W
5
—
1
—
4
—
1
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
—
OE
209
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight internal
clock sources obtained by dividing the supporting-module clock (øP).
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Description
000 ø
P
/2 (Initial value)
001 ø
P
/8
010 ø
P
/32
011 ø
P
/128
100 ø
P
/256
101 ø
P
/1024
110 ø
P
/2048
111 ø
P
/4096
From the clock source frequency, the resolution, period, and frequency of the PWM output can be
calculated as follows.
Resolution = 1/clock source frequency
PWM period = resolution × 250
PWM frequency = 1/PWM period
If the øP clock frequency is 10 MHz, then the resolution, period, and frequency of the PWM output
for each clock source are as shown in table 10-3.
Table 10-3 PWM Timer Parameters for 10 MHz System Clock
Internal Clock Frequency Resolution PWM Period PWM Frequency
øP/2 200 ns 50 µs 20 kHz
øP/8 800 ns 200 µs 5 kHz
øP/32 3.2 µs 800 µs 1.25 kHz
øP/128 12.8 µs 3.2 ms 312.5 Hz
øP/256 25.6 µs 6.4 ms 156.3 Hz
øP/1024 102.4 µs 25.6 ms 39.1 Hz
øP/2048 204.8 µs 51.2 ms 19.5 Hz
øP/4096 409.6 µs 102.4 ms 9.8 Hz
210
10.3 Operation
10.3.1 Timer Increment
The PWM clock source is created by dividing the system clock (ø). The timer counter increments on
a TCNT clock pulse generated from the falling edge of the prescaler output as shown in figure 10-2.
Figure 10-2 TCNT Increment Timing
N – 1
TCNT clock
pulse
ø
TCNT
Prescaler
output
N N + 1
211
10.3.2 PWM Operation
Figure 10-3 is a timing chart of the PWM operation.
Figure 10-3 PWM Timing
N – 1 N + 1
(a) H'00 (b) H'01 H'02 NH'F9 (d) H'00 H'01
N(d) M
H'FF
(c)
(a)*
(e)*
(b) (c)
N written in DTR M written in DTR
ø
TCNT clock
pulses
OE
TCNT
DTR
(OS = 0)
PWM output
(OS = 1)
PWM 1 cycle
Note: * Used for port 4 input/output: state depends on values in data register and data direction register.
212
1. Positive Logic (OS = 0)
(1) When (OE = 0)—(a) in Figure 10-3: The timer count is held at H'00 and PWM output is
inhibited. [Pin 46(for PW0) or pin 47(for PW1) is used for port 4 input/output, and its state depends
on the corresponding port 4 data register and data direction register.] Any value (such as N in figure
10-3) written in the DTR becomes valid immediately.
(2) When (OE = 1)
i) The timer counter begins incrementing. The PWM output goes high when TCNT changes from
H'00 to H'01, unless DTR = H'00. [(b) in figure 10-3]
ii) When the count passes the DTR value, the PWM output goes low. [(c) in figure 10-3]
iii) If the DTR value is changed (by writing the data “M” in figure 10-3), the new value becomes
valid after the timer count changes from H'F9 to H'00. [(d) in figure 10-3]
2. Negative Logic (OS = 1)—(e) in Figure 10-3: The operation is the same except that high and
low are reversed in the PWM output. [(e) in figure 10-3]
10.4 Application Notes
Some notes on the use of the PWM timer module are given below.
(1) Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS)
should be made before the output enable bit (OE) is set to 1.
(2) If the DTR value is H'00, the duty cycle is 0% and PWM output remains constant at 0.
If the DTR value is H'FA to H'FF, the duty cycle is 100% and PWM output remains constant at
1.
(For positive logic, 0 is low and 1 is high. For negative logic, 0 is high and 1 is low.)
213
Section 11 Watchdog Timer
11.1 Overview
The H8/3437 Series has an on-chip watchdog timer (WDT) that can monitor system operation by
resetting the CPU or generating a nonmaskable interrupt if a system crash allows the timer count to
overflow.
When this watchdog function is not needed, the watchdog timer module can be used as an interval
timer. In interval timer mode, it requests an OVF interrupt at each counter overflow.
11.1.1 Features
• Selection of eight clock sources
• Selection of two modes:
— Watchdog timer mode
— Interval timer mode
• Counter overflow generates an interrupt request or reset:
— Reset or NMI request in watchdog timer mode
— OVF interrupt request in interval timer mode
215
11.1.2 Block Diagram
Figure 11-1 is a block diagram of the watchdog timer.
Figure 11-1 Block Diagram of Watchdog Timer
11.1.3 Register Configuration
Table 11-1 lists information on the watchdog timer registers.
Table 11-1 Register Configuration
Addresses
Name Abbreviation R/W Initial Value Write Read
Timer control/status register TCSR R/(W)*H'10 H'FFA8 H'FFA8
Timer counter TCNT R/W H'00 H'FFA8 H'FFA9
Note: *Software can write a 0 to clear the status flag bits, but cannot write 1.
Interrupt
control
Internal NMI
(Watchdog timer mode)
OVF (Interval
timer mode)
Interrupt
signals
Internal reset
Overflow TCNT
TCSR
Read/write
control
Internal
data bus
Clock
select
øP/2
øP/32
øP/64
øP/128
øP/256
øP/512
øP/2048
øP/4096
Internal clock source
Clock
TCNT:
TCSR: Timer counter
Timer control/status register
216
11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. When the timer enable bit (TME) in the timer
control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal
clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the count
overflows (changes from H'FF to H'00), an overflow flag (OVF) in TCSR is set to 1.
TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0.
Note: TCNT is more difficult to write to than other registers. See Section 11.2.3, Register Access,
for details.
11.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable/writable register that selects the timer mode and clock source and
performs other functions. (TCSR is write-protected by a password. See section 11.2.3, Register
Access, for details.)
Bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. Bits 2 to 0 are initialized
to 0 by a reset, but retain their values in the standby modes.
Bit
Initial value
Read/Write
7
OVF
0
R/(W*)
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Note: *Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit.
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
217
Bit 7—Overflow Flag (OVF): Indicates that the watchdog timer count has overflowed.
Bit 7
OVF Description
0 To clear OVF, the CPU must read OVF after it has been set to 1, (Initial value)
then write a 0 in this bit
1 Set to 1 when TCNT changes from H'FF to H'00
Bit 6—Timer Mode Select (WT/IT): Selects whether to operate in watchdog timer mode or
interval timer mode. When TCNT overflows, an OVF interrupt request is sent to the CPU in interval
timer mode. For watchdog timer mode, a reset or NMI interrupt is requested.
Bit 6
WT/IT Description
0 Interval timer mode (OVF request) (Initial value)
1 Watchdog timer mode (reset or NMI request)
Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5
TME Description
0 TCNT is initialized to H'00 and stopped (Initial value)
1 TCNT runs and requests a reset or an interrupt when it overflows
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
Bit 3: Reset or NMI Select (RST/NMI): Selects either an internal reset or the NMI function at
watchdog timer overflow.
Bit 3
RST/NMI Description
0 NMI function enabled (Initial value)
1 Reset function enabled
218
Bits 2–0—Clock Select (CKS2–CKS0): These bits select one of eight clock sources obtained by
dividing the system clock (ø).
The overflow interval is the time from when the watchdog timer counter begins counting from H'00
until an overflow occurs. In interval timer mode, OVF interrupts are requested at this interval.
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Clock Source Overflow Interval (øP= 10 MHz)
000 ø
P
/2 51.2 µs (Initial value)
001 ø
P
/32 819.2 µs
010 ø
P
/64 1.6 ms
011 ø
P
/128 3.3 ms
100 ø
P
/256 6.6 ms
101 ø
P
/512 13.1 ms
110 ø
P
/2048 52.4 ms
111 ø
P
/4096 104.9 ms
11.2.3 Register Access
The watchdog timer’s TCNT and TCSR registers are more difficult to write to than other registers.
The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: Word access is required. Byte data transfer instructions cannot be
used for write access.
The TCNT and TCSR registers have the same write address. The write data must be contained in
the lower byte of a word written at this address. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). See figure 11-2. The result of the access depicted in figure
11-2 is to transfer the write data from the lower byte to TCNT or TCSR.
Figure 11-2 Writing to TCNT and TCSR
Write dataH'5A
15 8 7 0
Write dataH'A5
15 8 7 0
H'FFA8
H'FFA8
Writing to TCNT
Writing to TCSR
219
Reading TCNT and TCSR: The read addresses are H'FFA8 for TCSR and H'FFA9 for TCNT, as
indicated in table 11-2.
These two registers are read like other registers. Byte access instructions can be used.
Table 11-2 Read Addresses of TCNT and TCSR
Read Address Register
H'FFA8 TCSR
H'FFA9 TCNT
11.3 Operation
11.3.1 Watchdog Timer Mode
The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in
TCSR. Thereafter, software should periodically rewrite the contents of the timer counter (normally
by writing H'00) to prevent the count from overflowing. If a program crash allows the timer count to
overflow, the entire chip is reset for 518 system clocks (518 ø), or an NMI interrupt is requested.
Figure 11-3 shows the operation.
NMI requests from the watchdog timer have the same vector as NMI requests from the NMI pin.
Avoid simultaneous handling of watchdog timer NMI requests and NMI requests from pin NMI.
A reset from the watchdog timer has the same vector as an external reset from the RES pin. The
reset source can be determined by the XRST bit in SYSCR.
Figure 11-3 Operation in Watchdog Timer Mode
H'FF
H'00
TCNT count
WDT overflow
WT/IT = 1
TME = 1 H'00 written
to TCNT
OVF = 1
Reset
518 ø
H'00 written
to TCNT
WT/IT = 1
TME = 1
Time t
220
11.3.2 Interval Timer Mode
Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1.
In interval timer mode, an OVF request is generated each time the timer count overflows. This
function can be used to generate OVF requests at regular intervals. See figure 11-4.
Figure 11-4 Operation in Interval Timer Mode
11.3.3 Setting the Overflow Flag
The OVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module requests
an internal reset, NMI, or OVF interrupt. The timing is shown in figure 11-5.
Figure 11-5 Setting the OVF Bit
H'FF H'00
ø
TCNT
Internal overflow
signal
OVF
H'FF
H'00
WT/IT = 0
TME = 1
Time t
OVF
request OVF
request OVF
request OVF
request OVF
request
TCNT count
221
11.4 Application Notes
11.4.1 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T3state of a write cycle to the timer counter,
the write takes priority and the timer counter is not incremented. See figure 11-6.
Figure 11-6 TCNT Write-Increment Contention
11.4.2 Changing the Clock Select Bits (CKS2 to CKS0)
Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value
of the clock select bits. If the clock select bits are modified while the watchdog timer is running, the
timer count may be incremented incorrectly.
11.4.3 Recovery from Software Standby Mode
TCSR bits, except bits 0–2, and the TCNT counter are reset when the chip recovers from software
standby mode. Re-initialize the watchdog timer as necessary to resume normal operation.
TCNT address
NM
Counter write data
Internal address bus
Internal write signal
TCNT clock pulse
TCNT
ø
T3
T2
T1
Write cycle (CPU writes to TCNT)
222
Section 12 Serial Communication Interface
12.1 Overview
The H8/3437 Series includes two serial communication interface channels (SCI0 and SCI1) for
transferring serial data to and from other chips. Either synchronous or asynchronous communication
can be selected.
12.1.1 Features
The features of the on-chip serial communication interface are:
• Asynchronous mode
The H8/3437 Series can communicate with a UART (Universal Asynchronous
Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip
that employs standard asynchronous serial communication. It also has a multiprocessor
communication function for communication with other processors. Twelve data formats are
available.
— Data length: 7 or 8 bits
— Stop bit length: 1 or 2 bits
— Parity: Even, odd, or none
— Multiprocessor bit: 1 or 0
— Error detection: Parity, overrun, and framing errors
— Break detection: When a framing error occurs, the break condition can be detected by
reading the level of the RxD line directly.
• Synchronous mode
The SCI can communicate with chips able to perform clocked synchronous data transfer.
— Data length: 8 bits
— Error detection: Overrun errors
• Full duplex communication
The transmitting and receiving sections are independent, so each channel can transmit and
receive simultaneously. Both the transmit and receive sections use double buffering, so
continuous data transfer is possible in either direction.
• Built-in baud rate generator
Any specified bit rate can be generated.
223
• Internal or external clock source
The SCI can operate on an internal clock signal from the baud rate generator, or an external
clock signal input at the SCK0 or SCK1 pin.
• Four interrupts
TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested independently.
224
12.1.2 Block Diagram
Figure 12-1 shows a block diagram of one serial communication interface channel.
Figure 12-1 Block Diagram of Serial Communication Interface
TDR
Bus interface
Internal
data bus
Parity
generate Clock
Parity check
TSR ø
øP/4
øP/16
øP/64
RxD
TxD
TXI
RXI
ERI
Interrupt signals
External clock source
Internal
clock
RDR
RSR
SCK
BRR
Communi-
cation
control
SSR
SCR
SMR Baud rate
generator
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
Receive shift register (8 bits)
Receive data register (8 bits)
Transmit shift register (8 bits)
Transmit data register (8 bits)
Serial mode register (8 bits)
Serial control register (8 bits)
Serial status register (8 bits)
Bit rate register (8 bits)
TEI
Module data bus
225
12.1.3 Input and Output Pins
Table 12-1 lists the input and output pins used by the SCI module.
Table 12-1 SCI Input/Output Pins
Channel Name Abbr. I/O Function
0 Serial clock input/output SCK0 Input/output SCI0 clock input and output
Receive data input RxD0 Input SCI0 receive data input
Transmit data output TxD0 Output SCI0 transmit data output
1 Serial clock input/output SCK1 Input/output SCI1 clock input and output
Receive data input RxD1 Input SCI1 receive data input
Transmit data output TxD1 Output SCI1 transmit data output
Note: In this manual, the channel subscript has been deleted, and only SCK, RxD, and TxD are
used.
226
12.1.4 Register Configuration
Table 12-2 lists the SCI registers. These registers specify the operating mode (synchronous or
asynchronous), data format and bit rate, and control the transmit and receive sections.
Table 12-2 SCI Registers
Channel Name Abbr. R/W Value Address
0 Receive shift register RSR —*1—*1—*1
Receive data register RDR R H'00 H'FFDD
Transmit shift register TSR —*1—*1—*1
Transmit data register TDR R/W H'FF H'FFDB
Serial mode register SMR*3R/W H'00 H'FFD8
Serial control register SCR R/W H'00 H'FFDA
Serial status register SSR R/(W)*2H'84 H'FFDC
Bit rate register BRR*3R/W H'FF H'FFD9
1 Receive shift register RSR —*1—*1—*1
Receive data register RDR R H'00 H'FF8D
Transmit shift register TSR —*1—*1—*1
Transmit data register TDR R/W H'FF H'FF8B
Serial mode register SMR R/W H'00 H'FF88
Serial control register SCR R/W H'00 H'FF8A
Serial status register SSR R/(W)*2H'84 H'FF8C
Bit rate register BRR R/W H'FF H'FF89
0 and 1 Serial/timer control register STCR R/W H'00 H'FFC3
Notes: 1. Cannot be read or written to.
2. Software can write a 0 to clear the flags in bits 7 to 3, but cannot write 1 in these bits.
3. SMR and BRR have the same addresses as I2C bus interface registers ICCR and ICSR.
For the access switching method and other details, see section 13, I2C Bus Interface.
227
12.2 Register Descriptions
12.2.1 Receive Shift Register (RSR)
RSR is a shift register that converts incoming serial data to parallel data. When one data character
has been received, it is transferred to the receive data register (RDR).
The CPU cannot read or write RSR directly.
12.2.2 Receive Data Register (RDR)
RDR stores received data. As each character is received, it is transferred from RSR to RDR,
enabling RSR to receive the next character. This double-buffering allows the SCI to receive data
continuously.
RDR is a read-only register. RDR is initialized to H'00 by a reset and in the standby modes.
12.2.3 Transmit Shift Register (TSR)
TSR is a shift register that converts parallel data to serial transmit data. When transmission of one
character is completed, the next character is moved from the transmit data register (TDR) to TSR
and transmission of that character begins. If the TDRE bit is still set to 1, however, nothing is
transferred to TSR.
The CPU cannot read or write TSR directly.
Bit
Read/Write
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit
Initial value
Read/Write
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Read/Write
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
228
12.2.4 Transmit Data Register (TDR)
TDR is an 8-bit readable/writable register that holds the next data to be transmitted. When TSR
becomes empty, the data written in TDR is transferred to TSR. Continuous data transmission is
possible by writing the next data in TDR while the current data is being transmitted from TSR.
TDR is initialized to H'FF by a reset and in the standby modes.
12.2.5 Serial Mode Register (SMR)
SMR is an 8-bit readable/writable register that controls the communication format and selects the
clock source of the on-chip baud rate generator. It is initialized to H'00 by a reset and in the standby
modes. For further information on the SMR settings and communication formats, see tables 12-5
and 12-7 in section 12.3, Operation.
Bit 7—Communication Mode (C/A): This bit selects asynchronous or synchronous
communication mode.
Bit 7
C/ADescription
0 Asynchronous communication (Initial value)
1 Synchronous communication
Bit
Initial value
Read/Write
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
229
Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode.
It is ignored in synchronous mode.
Bit 6
CHR Description
0 8 bits per character (Initial value)
1 7 bits per character (Bits 0 to 6 of TDR and RDR are used for transmitting and
receiving, respectively.)
Bit 5—Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode.
It is ignored in synchronous mode, and when a multiprocessor format is used.
Bit 5
PE Description
0 Transmit: No parity bit is added. (Initial value)
Receive: Parity is not checked.
1 Transmit: A parity bit is added.
Receive: Parity is checked.
Bit 4—Parity Mode (O/E): In asynchronous mode, when parity is enabled (PE = 1), this bit
selects even or odd parity.
Even parity means that a parity bit is added to the data bits for each character to make the total
number of 1’s even. Odd parity means that the total number of 1’s is made odd.
This bit is ignored when PE = 0, or when a multiprocessor format is used. It is also ignored in
synchronous mode.
Bit 4
O/EDescription
0 Even parity (Initial value)
1 Odd parity
230
Bit 3—Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in
synchronous mode.
Bit 3
STOP Description
0 One stop bit (Initial value)
Transmit: One stop bit is added.
Receive: One stop bit is checked to detect framing errors.
1 Two stop bits
Transmit: Two stop bits are added.
Receive: The first stop bit is checked to detect framing errors. If the second stop bit is a
space (0), it is regarded as the next start bit.
Bit 2—Multiprocessor Mode (MP): This bit selects the multiprocessor format in asynchronous
communication. When multiprocessor format is selected, the parity settings of the parity enable bit
(PE) and parity mode bit (O/E) are ignored. The MP bit is ignored in synchronous communication.
The MP bit is valid only when the MPE bit in the serial/timer control register (STCR) is set to 1.
When the MPE bit is cleared to 0, the multiprocessor communication function is disabled regardless
of the setting of the MP bit.
Bit 2
MP Description
0 Multiprocessor communication function is disabled. (Initial value)
1 Multiprocessor communication function is enabled.
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the clock source of the
on-chip baud rate generator.
Bit 1 Bit 0
CKS1 CKS0 Description
0 0 ø clock (Initial value)
01 ø
P
/4 clock
10 ø
P
/16 clock
11 ø
P
/64 clock
231
12.2.6 Serial Control Register (SCR)
SCR is an 8-bit readable/writable register that enables or disables various SCI functions.
It is initialized to H'00 by a reset and in the standby modes.
Bit 7—Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt
(TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR)
is set to 1.
Bit 7
TIE Description
0 The TDR-empty interrupt request (TXI) is disabled. (Initial value)
1 The TDR-empty interrupt request (TXI) is enabled.
Bit 6—Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt
(RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is
set to 1, and the receive error interrupt (ERI) requested when the overrun error (ORER), framing
error (FER), or parity error (PER) bit in the serial status register (SSR) is set to 1.
Bit 6
RIE Description
0 The receive-end interrupt (RXI) and receive-error (ERI) requests are (Initial value)
disabled.
1 The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled.
Bit 5—Transmit Enable (TE): This bit enables or disables the transmit function. When the
transmit function is enabled, the TxD pin is automatically used for output. When the transmit
function is disabled, the TxD pin can be used as a general-purpose I/O port.
Bit 5
TE Description
0 The transmit function is disabled. (Initial value)
The TxD pin can be used for general-purpose I/O.
1 The transmit function is enabled. The TxD pin is used for output.
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
232
Bit 4—Receive Enable (RE): This bit enables or disables the receive function. When the receive
function is enabled, the RxD pin is automatically used for input. When the receive function is
disabled, the RxD pin is available as a general-purpose I/O port.
Bit 4
RE Description
0 The receive function is disabled. The RxD pin can be (Initial value)
used for general-purpose I/O.
1 The receive function is enabled. The RxD pin is used for input.
Bit 3—Multiprocessor Interrupt Enable (MPIE): When serial data is received in a
multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receive-error
interrupt (ERI) until data with the multiprocessor bit set to 1 is received. It also enables or disables
the transfer of received data from RSR to RDR, and enables or disables setting of the RDRF, FER,
PER, and ORER bits in the serial status register (SSR).
The MPIE bit is ignored when the MP bit is cleared to 0, and in synchronous mode.
Clearing the MPIE bit to 0 disables the multiprocessor receive interrupt function. In this condition
data is received regardless of the value of the multiprocessor bit in the receive data.
Setting the MPIE bit to 1 enables the multiprocessor receive interrupt function. In this condition, if
the multiprocessor bit in the receive data is 0, the receive-end interrupt (RXI) and receive-error
interrupt (ERI) are disabled, the receive data is not transferred from RSR to RDR, and the RDRF,
FER, PER, and ORER bits in the serial status register (SSR) are not set. If the multiprocessor bit is
1, however, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0, the receive data is
transferred from RSR to RDR, the FER, PER, and ORER bits can be set, and the receive-end and
receive-error interrupts are enabled.
Bit 3
MPIE Description
0 The multiprocessor receive interrupt function is disabled. (Initial value)
(Normal receive operation)
1 The multiprocessor receive interrupt function is enabled. During the interval before data
with the multiprocessor bit set to 1 is received, the receive interrupt request (RXI) and
receive-error interrupt request (ERI) are disabled, the RDRF, FER, PER, and ORER bits
are not set in the serial status register (SSR), and no data is transferred from the RSR to
the RDR. The MPIE bit is cleared at the following times:
(1) When 0 is written in MPIE.
(2) When data with the multiprocessor bit set to 1 is received.
233
Bit 2—Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty
interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set
to 1.
Bit 2
TEIE Description
0 The TSR-empty interrupt request (TEI) is disabled. (Initial value)
1 The TSR-empty interrupt request (TEI) is enabled.
Bit 1—Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud
rate generator. When the external clock source is selected, the SCK pin is automatically used for
input of the external clock signal.
Bit 1
CKE1 Description
0 Internal clock source (Initial value)
When C/A= 1, the serial clock signal is output at the SCK pin.
When C/A= 0, output depends on the CKE0 bit.
1 External clock source. The SCK pin is used for input.
Bit 0—Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode,
this bit enables or disables serial clock output at the SCK pin.
This bit is ignored when the external clock is selected, or when synchronous mode is selected.
For further information on the communication format and clock source selection, see table 12-6 in
section 12.3, Operation.
Bit 0
CKE0 Description
0 The SCK pin is not used by the SCI (and is available as (Initial value)
a general-purpose I/O port).
1 The SCK pin is used for serial clock output.
234
12.2.7 Serial Status Register (SSR)
SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 by a reset
and in the standby modes.
Bit 7—Transmit Data Register Empty (TDRE): This bit indicates when transmit data can safely
be written in TDR.
Bit 7
TDRE Description
0 To clear TDRE, the CPU must read TDRE after it has been set to 1,
then write a 0 in this bit.
1 This bit is set to 1 at the following times: (Initial value)
(1) When TDR contents are transferred to TSR.
(2) When the TE bit in SCR is cleared to 0.
Bit 6—Receive Data Register Full (RDRF): This bit indicates when one character has been
received and transferred to RDR.
Bit 6
RDRF Description
0 To clear RDRF, the CPU must read RDRF after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when one character is received without error and
transferred from RSR to RDR.
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Note: * Software can write a 0 to clear the flags, but cannot write a 1 in these bits.
235
Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5
ORER Description
0 To clear ORER, the CPU must read ORER after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 if reception of the next character ends while
the receive data register is still full (RDRF = 1).
Bit 4—Framing Error (FER): This bit indicates a framing error during data reception in
asynchronous mode. It has no meaning in synchronous mode.
Bit 4
FER Description
0 To clear FER, the CPU must read FER after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 if a framing error occurs (stop bit = 0).
Bit 3—Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without parity
bits is used.
Bit 3
PER Description
0 To clear PER, the CPU must read PER after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when a parity error occurs (the parity of the received data does not
match the parity selected by the O/Ebit in SMR).
236
Bit 2—Transmit End (TEND): This bit indicates that the serial communication interface has
stopped transmitting because there was no valid data in TDR when the last bit of the current
character was transmitted. The TEND bit is also set to 1 when the TE bit in the serial control
register (SCR) is cleared to 0.
The TEND bit is a read-only bit and cannot be modified directly. To use the TEI interrupt, first start
transmitting data, which clears TEND to 0, then set TEIE to 1.
Bit 2
TEND Description
0 To clear TEND, the CPU must read TDRE after TDRE has
been set to 1, then write a 0 in TDRE
1 This bit is set to 1 when: (Initial value)
(1) TE = 0
(2) TDRE = 1 at the end of transmission of a character
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a
multiprocessor format in asynchronous communication mode. This bit retains its previous value in
synchronous mode, when a multiprocessor format is not used, or when the RE bit is cleared to 0
even if a multiprocessor format is used.
MPB can be read but not written.
Bit 1
MPB Description
0 Multiprocessor bit = 0 in receive data. (Initial value)
1 Multiprocessor bit = 1 in receive data.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted
in transmit data when a multiprocessor format is used in asynchronous communication mode. The
MPBT bit is double-buffered in the same way as TSR and TDR. The MPBT bit has no effect in
synchronous mode, or when a multiprocessor format is not used.
Bit 0
MPBT Description
0 Multiprocessor bit = 0 in transmit data. (Initial value)
1 Multiprocessor bit = 1 in transmit data.
237
238
12.2.8 Bit Rate Register (BRR)
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR, determines the bit rate
output by the baud rate generator.
BRR is initialized to H'FF by a reset and in the standby modes.
Tables 12-3 and 12-4 show examples of BRR settings.
Table 12-3 Examples of BRR Settings in Asynchronous Mode (When øP= ø)
ø Frequency (MHz)
1 1.2288 2 2.097152
Error Error Error Error
Bit Rate n N (%) n N (%) n N (%) n N (%)
110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 –0.04
150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21
300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21
600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21
1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 –0.70
2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14
4800 — — — 0 7 0 0 12 +0.16 0 13 –2.48
9600 — — — 0 3 0 — — — 0 6 –2.48
19200 — — — 0 1 0 — — — — — —
31250 0 0 0 — — — 0 1 0 — — —
38400 — — — 0 0 0 — — — — — —
Note: If possible, the error should be within 1%.
In the shaded section, if øP= ø/2, the bit rate is cut in half. In this case, BRR settings for the
desired bit rate should be referenced from the column of one-half the actual system clock
frequency (ø).
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
239
Table 12-3 Examples of BRR Settings in Asynchronous Mode (When øP= ø) (cont)
ø Frequency (MHz)
2.4576 3 3.6864 4
Error Error Error Error
Bit Rate n N (%) n N (%) n N (%) n N (%)
110 1 174 –0.26 2 52 +0.50 2 64 +0.70 2 70 +0.03
150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16
300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16
600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16
1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16
2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16
4800 0 15 0 0 19 –2.34 0 23 0 0 25 +0.16
9600 0 7 0 0 9 –2.34 0 11 0 0 12 +0.16
19200 0 3 0 0 4 –2.34 0 5 0 — — —
31250 — — — 0 2 0 — — — 0 3 0
38400 0 1 0 — — — 0 2 0 — — —
Table 12-3 Examples of BRR Settings in Asynchronous Mode (When øP= ø) (cont)
ø Frequency (MHz)
4.9152 5 6 6.144
Error Error Error Error
Bit Rate n N (%) n N (%) n N (%) n N (%)
110 2 86 +0.31 2 88 –0.25 2 106 –0.44 2 108 +0.08
150 1 255 0 2 64 +0.16 2 77 +0.16 2 79 0
300 1 127 0 1 129 +0.16 1 155 +0.16 1 159 0
600 0 255 0 1 64 +0.16 1 77 +0.16 1 79 0
1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0
2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0
4800 0 31 0 0 32 –1.36 0 38 +0.16 0 39 0
9600 0 15 0 0 15 +1.73 0 19 –2.34 0 19 0
19200 0 7 0 0 7 +1.73 0 9 –2.34 0 9 0
31250 0 4 –1.70 0 4 0 0 5 0 0 5 +2.40
38400 0 3 0 0 3 +1.73 0 4 –2.34 0 4 0
Note: If possible, the error should be within 1%.
In the shaded section, if øP= ø/2, the bit rate is cut in half. In this case, BRR settings for the
desired bit rate should be referenced from the column of one-half the actual system clock
frequency (ø).
240
Table 12-3 Examples of BRR Settings in Asynchronous Mode (When øP= ø) (cont)
ø Frequency (MHz)
7.3728 8 9.8304 10
Error Error Error Error
Bit Rate n N (%) n N (%) n N (%) n N (%)
110 2 130 –0.07 2 141 +0.03 2 174 –0.26 2 177 –0.25
150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16
300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16
600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16
1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16
2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16
4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16
9600 0 23 0 0 25 +0.16 0 31 0 0 32 –1.36
19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73
31250 — — — 0 7 0 0 9 –1.70 0 9 0
38400 0 5 0 — — — 0 7 0 0 7 +1.73
Table 12-3 Examples of BRR Settings in Asynchronous Mode (When øP= ø) (cont)
ø Frequency (MHz)
12 12.288 14.7456 16
Error Error Error Error
Bit Rate n N (%) n N (%) n N (%) n N (%)
110 2 212 +0.03 2 217 +0.08 3 64 +0.76 3 70 +0.03
150 2 155 +0.16 2 159 0 2 191 0 2 207 +0.16
300 2 77 +0.16 2 79 0 2 95 0 2 103 +0.16
600 1 155 +0.16 1 159 0 1 191 0 1 207 +0.16
1200 1 77 +0.16 1 79 0 1 95 0 1 103 +0.16
2400 0 155 +0.16 0 159 0 0 191 0 0 207 +0.16
4800 0 77 +0.16 0 79 0 0 95 0 0 103 +0.16
9600 0 38 +0.16 0 39 0 0 47 0 0 51 +0.16
19200 0 19 –2.34 0 19 0 0 23 0 0 25 +0.16
31250 0 11 0 0 11 +2.4 0 14 –1.7 0 15 0
38400 0 9 –2.34 0 9 0 0 11 0 0 12 +0.16
Note: If possible, the error should be within 1%.
In the shaded section, if øP= ø/2, the bit rate is cut in half. In this case, BRR settings for the
desired bit rate should be referenced from the column of one-half the actual system clock
frequency (ø).
B = F×106→N = F×106– 1
64 ×22n–1 ×(N + 1) 64 ×22n–1 ×B
B: Bit rate (bits/second)
N: BRR value (0 ≤N ≤255)
F: øP(MHz) when n ≠0, or ø (MHz) when n = 0
n: Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n CKS1 CKS0 Clock
000ø
101ø
P
/4
210ø
P
/16
311ø
P
/64
Bit rate error can be calculated with the formula below.
Error (%) =
{
F ×106– 1
}
×100
(N + 1) ×B ×64 ×22n–1
241
Table 12-4 Examples of BRR Settings in Synchronous Mode (When øP= ø)
ø Frequency (MHz)
124 581016
Bit Rate n N n N n N n NnNnNnN
100 ——————————————
250 1 249 2 124 2 249 — — 3 124 — — 3 249
500 1 124 1 249 2 124 — — 2 249 — — 3 124
1 k 0 249 1 124 1 249 — — 2 124 — — 2 249
2.5 k 0 99 0 199 1 99 1 124 1 199 1 249 2 99
5 k 0 49 0 99 0 199 0 249 1 99 1 124 1 199
10 k 0 24 0 49 0 99 0 124 0 199 0 249 1 99
25 k 0 9 0 19 0 39 0 49 0 79 0 99 0 159
50 k 0 4 0 9 0 19 0 24 0 39 0 49 0 79
100 k — — 0 4 0 9 — — 0 19 0 24 0 39
250 k 0 0*0103040709015
500 k 0 0*01——030407
1 M 0 0*——0 1 ——0 3
2.5 M 0 0*——
4 M 00*
Notes: In the shaded section, if øP= ø/2, the bit rate is cut in half. In this case, BRR settings for the
desired bit rate should be referenced from the column of one-half the actual system clock
frequency (ø).
Blank: No setting is available.
—: A setting is available, but the bit rate is inaccurate.
*: Continuous transfer is not possible.
B = F×106→N = F×106– 1
8×22n–1 ×(N + 1) 8 ×22n–1 ×B
B: Bit rate (bits per second)
N: BRR value (0 ≤N ≤255)
F: øP(MHz) when n ≠0, or ø (MHz) when n = 0
n: Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n CKS1 CKS0 Clock
000ø
101ø
P
/4
210ø
P
/16
311ø
P
/64
242
12.2.9 Serial/Timer Control Register (STCR)
STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the
TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset.
Bits 7 to 4—I2C Control (IICS, IICD, IICX, IICE): These bits control operation of the I2C bus
interface. For details, refer to section 13, I2C Bus Interface.
Bit 3—Slave Input Switch (STAC): Controls the input pin of the host interface. For details,
section 14, Host Interface.
Bit 2—Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication
function on channels SCI0 and SCI1.
Bit 2
MPE Description
0 The multiprocessor communication function is disabled, (Initial value)
regardless of the setting of the MP bit in SMR.
1 The multiprocessor communication function is enabled. The multi-processor format can
be selected by setting the MP bit in SMR to 1.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits select the clock
input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit Timers.
Bit
Initial value
Read/Write
7
IICS
0
R/W
6
IICD
0
R/W
5
IICX
0
R/W
4
IICE
0
R/W
3
STAC
0
R/W
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
243
12.3 Operation
12.3.1 Overview
The SCI supports serial data transfer in two modes. In asynchronous mode each character is
synchronized individually. In synchronous mode communication is synchronized with a clock
signal.
The selection of asynchronous or synchronous mode and the communication format depend on
SMR settings as indicated in table 12-5. The clock source depends on the settings of the C/Abit in
the SMR and the CKE1 and CKE0 bits in SCR as indicated in table 12-6.
Asynchronous Mode
• Data length: 7 or 8 bits can be selected.
• A parity bit or multiprocessor bit can be added, and stop bit lengths of 1 or 2 bits can be
selected. (These selections determine the communication format and character length.)
• Framing errors (FER), parity errors (PER), and overrun errors (ORER) can be detected in
receive data, and the line-break condition can be detected.
• SCI clock source: An internal or external clock source can be selected.
• Internal clock: The SCI is clocked by the on-chip baud rate generator and can output a clock
signal at the bit-rate frequency.
• External clock: The external clock frequency must be 16 times the bit rate. (The on-chip baud
rate generator is not used.)
Synchronous Mode
• Communication format: The data length is 8 bits.
• Overrun errors (ORER) can be detected in receive data.
• SCI clock source: An internal or external clock source can be selected.
• Internal clock: The SCI is clocked by the on-chip baud rate generator and outputs a serial clock
signal to external devices.
• External clock: The on-chip baud rate generator is not used. The SCI operates on the input
serial clock.
244
Table 12-5 Communication Formats Used by SCI
SMR Settings Communication Format
Multi- Stop-
Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data processor Parity Bit
C/ACHR MP PE STOP Mode Length Bit Bit Length
00000 Asynchronous 8 bits None None 1 bit
1mode 2 bits
1 0 Present 1 bit
1 2 bits
1 0 0 7 bits None 1 bit
1 2 bits
1 0 Present 1 bit
1 2 bits
0 1 — 0 Asynchronous 8 bits Present None 1 bit
1mode (multi- 2 bits
10
processor 7 bits 1 bit
1format) 2 bits
1 ———— Synchronous 8 bits None None
mode
Table 12-6 SCI Clock Source Selection
SMR SCR
Bit 7 Bit 1 Bit 0 Serial Transmit/Receive Clock
C/ACKE1 CKE0 Mode Clock Source SCK Pin Function
0 0 0 Async Internal Input/output port (not used by SCI)
1 Serial clock output at bit rate
1 0 External Serial clock input at 16 ×bit rate
1
1 0 0 Sync Internal Serial clock output
1
1 0 External Serial clock input
1
245
12.3.2 Asynchronous Mode
In asynchronous mode, each transmitted or received character is individually synchronized by
framing it with a start bit and stop bit.
Full duplex data transfer is possible because the SCI has independent transmit and receive sections.
Double buffering in both sections enables the SCI to be programmed for continuous data transfer.
Figure 12-2 shows the general format of one character sent or received in asynchronous mode. The
communication channel is normally held in the mark state (high). Character transmission or
reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the
least significant bit (LSB) comes first. The data bits are followed by the parity or multiprocessor bit,
if present, then the stop bit or bits (high) confirming the end of the frame.
In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the
center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
Figure 12-2 Data Format in Asynchronous Mode
D0 D1 DnStart bit
1 bit 7 or 8 bits
One unit of data (one character or frame)
Parity or
multipro-
cessor bit Stop bit
0 or 1 bit 1 or 2 bits
Idle state
(mark)
246
1. Data Format: Table 12-7 lists the data formats that can be sent and received in asynchronous
mode. Twelve formats can be selected by bits in the serial mode register (SMR).
Table 12-7 Data Formats in Asynchronous Mode
Notes: SMR: Serial mode register
S: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
2. Clock: In asynchronous mode it is possible to select either an internal clock created by the on-
chip baud rate generator, or an external clock input at the SCK pin. The selection is made by the
C/Abit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register
(SCR). Refer to table 12-6.
If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate.
If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used
for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the
center of the transmit data bits. Figure 12-3 shows the phase relationship between the output clock
and transmit data.
CHR
0
0
0
0
1
1
1
1
0
0
1
1
PE
0
0
1
1
0
0
1
1
—
—
—
—
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR Bits
123456789101112
S
S
S
S
S
S
S
S
S
S
S
S
8-bit data STOP
8-bit data STOP STOP
8-bit data PSTOP
8-bit data PSTOP STOP
7-bit data STOP
7-bit data STOP STOP
7-bit data PSTOP
7-bit data PSTOP STOP
8-bit data MPB STOP
8-bit data MPB STOP STOP
7-bit data MPB STOP
7-bit data MPB STOP STOP
247
Figure 12-3 Phase Relationship between Clock Output and Transmit Data
(Asynchronous Mode)
3. Transmitting and Receiving Data
• SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to 0
in the serial control register (SCR), then initialize the SCI following the procedure in figure 12-4.
Note: When changing the communication mode or format, always clear the TE and RE bits to 0
before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes
the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF,
PER, FER, and ORER flags and receive data register (RDR), which retain their previous
contents.
When an external clock is used, the clock should not be stopped during initialization or
subsequent operation. SCI operation becomes unreliable if the clock is stopped.
0 D0D1D2D3D4
One frame
D5 D6 D7 0/1 1 1
248
Figure 12-4 Sample Flowchart for SCI Initialization
Clear TE and RE bits to
0 in SCR
1 bit interval
elapsed?
Start transmitting or receiving
No
Yes
1.
2.
3.
4.
Select interrupts and the clock source in the
serial control register (SCR). Leave TE and RE
cleared to 0. If clock output is selected, in
asynchronous mode, clock output starts
immediately after the setting is made in SCR.
Select the communication format in the serial
mode register (SMR).
Write the value corresponding to the bit rate in
the bit rate register (BRR). This step is not
necessary when an external clock is used.
Wait for at least the interval required to transmit
or receive one bit, then set TE or RE in the serial
control register (SCR). Setting TE or RE enables
the SCI to use the TxD or RxD pin.
Also set the RIE, TIE, TEIE, and MPIE bits as
necessary to enable interrupts. The initial states
are the mark transmit state, and the idle receive
state (waiting for a start bit).
1
2
Set CKE1 and CKE0 bits in
SCR (leaving TE and RE
cleared to 0)
3
Set TE or RE to 1 in SCR,
and set RIE, TIE, TEIE, and
MPIE as necessary
4
Initialization
Set value in BRR
Select communication
format in SMR
249
• Transmitting Serial Data: Follow the procedure in figure 12-5 for transmitting serial data.
Figure 12-5 Sample Flowchart for Transmitting Serial Data
Start transmitting
Read TDRE bit in SSR
TDRE = 1?
Write transmit data in TDR
End of
transmission?
End
1
2
3
No
Yes
No
Yes
SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
SCI status check and transmit data write: read
the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the
transmit data register (TDR) and clear TDRE to 0.
If a multiprocessor format is selected, after
writing the transmit data write 0 or 1 in the
multiprocessor bit transfer (MPBT) in SSR.
Transition of the TDRE bit from 0 to 1 can be
reported by an interrupt.
To continue transmitting serial data: read the
TDRE bit to check whether it is safe to write; if
TDRE = 1, write data in TDR, then clear TDRE
to 0.
To end serial transmission: end of transmission
can be confirmed by checking transition of the
TEND bit from 0 to 1. This can be reported by
a TEI interrupt.
To output a break signal at the end of serial
transmission: set the DDR bit to 1 and clear the
DR bit to 0 (DDR and DR are I/O port registers),
then clear TE to 0 in SCR.
(a)
(b)
If using multiprocessor format,
select MPBT value in SSR
Clear TDRE bit to 0
Read TEND bit in SSR
TEND = 1? No
Yes
Output break
signal? No
Yes
Clear TE bit in SCR to 0
4
1.
2.
3.
4.
Initialize
Set DR = 0, DDR = 1
Serial transmission
250
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) is set to 1 in SCR, the SCI requests a
TXI interrupt (TDR-empty interrupt) at this time.
Serial transmit data are transmitted in the following order from the TxD pin:
(a) Start bit: One 0 bit is output.
(b) Transmit data: Seven or eight bits are output, LSB first.
(c) Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
(d) Stop bit: One or two 1 bits (stop bits) are output.
(e) Mark state: Output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, after loading new data
from TDR into TSR and transmitting the stop bit, the SCI begins serial transmission of the next
frame. If TDRE is 1, after setting the TEND bit to 1 in SSR and transmitting the stop bit, the
SCI continues 1-level output in the mark state, and if the TEIE bit (TSR-empty interrupt
enable) in SCR is set to 1, the SCI generates a TEI interrupt request (TSR-empty interrupt).
251
Figure 12-6 shows an example of SCI transmit operation in asynchronous mode.
Figure 12-6 Example of SCI Transmit Operation
(8-Bit Data with Parity and One Stop Bit)
1Start
bit
0 D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit Start
bit
0 D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit 1
Idle state
(mark)
TDRE
TEND
TXI
request TXI interrupt handler
writes data in TDR and
clears TDRE to 0
TXI
request
1 frame
TEI request
252
• Receiving Serial Data: Follow the procedure in figure 12-7 for receiving serial data.
Figure 12-7 Sample Flowchart for Receiving Serial Data
Start receiving
RDRF = 1?
Read receive data from RDR,
and clear RDRF bit to 0
in SSR
PER ∨ RER ∨
ORER = 1?
Clear RE to 0 in SCR
Finished
receiving?
End
Error handling
Start error handling
FER = 1?
Discriminate and
process error, and
clear flags
Return
Break?
Clear RE to 0
in SCR
End
1
2
No
Yes
Yes
No
No
Yes
4
1.
2.
3.
4.
SCI initialization: the receive data function of the RxD
pin is selected automatically.
To continue receiving serial data: read RDR and
clear RDRF to 0 before the stop bit of the current
frame is received.
SCI status check and receive data read: read the
serial status register (SSR), check that RDRF is set
to 1, then read receive data from the receive data
register (RDR) and clear RDRF to 0. Transition of
the RDRF bit from 0 to 1 can be reported by an RXI
interrupt.
Receive error handling and break detection: if a
receive error occurs, read the ORER, PER, and
FER bits in SSR to identify the error. After executing
the necessary error handling, clear ORER, PER, and
FER all to 0. Transmitting and receiving cannot
resume if ORER, PER, or FER remains set to 1.
When a framing error occurs, the RxD pin can be
read to detect the break state.
Yes
No
Yes
No
3
Initialize
Read ORER, PER, and
FER in SSR
Read RDRF bit in SSR
253
In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit.
2. Receive data is shifted into RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI makes the following checks:
(a) Parity check: The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in SMR.
(b) Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop
bit is checked.
(c) Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR.
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of the
checks fails (receive error), the SCI operates as indicated in table 12-8.
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1.
Be sure to clear the error flags.
4. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI
requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is set to
1 and the RIE bit in SCR is also set to 1, the SCI requests an ERI (receive-error) interrupt.
Table 12-8 Receive Error Conditions and SCI Operation
Receive error Abbreviation Condition Data Transfer
Overrun error ORER Receiving of next data ends Receive data not loaded from
while RDRF is still set to 1 RSR into RDR
in SSR
Framing error FER Stop bit is 0 Receive data loaded from
RSR into RDR
Parity error PER Parity of receive data differs Receive data loaded from
from even/odd parity setting RSR into RDR
in SMR
254
Figure 12-8 shows an example of SCI receive operation in asynchronous mode.
Figure 12-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
1Start
bit
0 D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit Start
bit
0 D0 D1 D7 0/1
Stop
bit
0
Data Parity
bit 1
Idle state
(mark)
RDRF
FER
1 frame
Framing error,
ERI request
RXI interrupt handler
reads data in RDR and
clears RDRF to 0
RXI
request
255
4. Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID.
A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the
receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending
cycles from data-sending cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants to
communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1.
After receiving data with the multiprocessor bit set to 1, the receiving processor with an ID
matching the received data continues to receive further incoming data. Multiple processors can send
and receive data in this way.
Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected.
For details see table 12-7.
256
Figure 12-9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
Transmitting
processor
Receiving
processor A
Serial communication line
Receiving
processor B Receiving
processor C Receiving
processor D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial data H'01 H'AA
(MPB = 1) (MPB = 0)
ID-sending cycle:
receiving processor address Data-sending cycle:
data sent to receiving
processor specified by ID
MPB: Multiprocessor bit
257
• Transmitting Multiprocessor Serial Data: See figures 12-5 and 12-6.
• Receiving Multiprocessor Serial Data: Follow the procedure in figure 12-10 for receiving
multiprocessor serial data.
Figure 12-10 Sample Flowchart for Receiving Multiprocessor Serial Data
Start receiving
Set MPIE bit to 1 in SCR
FER ∨
ORER = 1?
FER +
ORER = 1?
Finished
receiving?
Clear RE to 0 in SCR
End
Error handling FER = 1?
Discriminate and
process error, and
clear flags
Return
Break?
Clear RE bit to
0 in SCR
End
1
2
3
4
No
Yes
Yes
No
Yes
No
No
Yes
No
Yes
5
1. SCI initialization: the receive data function of the RxD pin is
selected automatically.
2. ID receive cycle: Set the MPIE bit in the serial control register
(SCR) to 1.
3. SCI status check and ID check: read the serial status register
(SSR), check that RDRF is set to 1, then read receive data
from the receive data register (RDR) and compare with the
processor’s own ID. Transition of the RDRF bit from 0 to
1 can be reported by an RXI interrupt. If the ID does not match
the receive data, set MPIE to 1 again and clear RDRF to 0.
If the ID matches the receive data, clear RDRF to 0.
4. SCI status check and data receiving: read SSR, check that
RDRF is set to 1, then read data from the receive data register
(RDR) and write 0 in the RDRF bit. Transition of the RDRF bit
from 0 to 1 can be reported by an RXI interrupt.
5. Receive error handling and break detection: if a receive error
occurs, read the ORER and FER bits in SSR to identify the error.
After executing the necessary error handling, clear both ORER
and FER to 0. Receiving cannot resume while ORER or FER
remains set to 1. When a framing error occurs, the RxD pin
can be read to detect the break state.
Yes
No
Yes
No
Initialize
Start error handling
Read RDRF bit in SSR
RDRF = 1?
Read ORER and FER
bits in SSR
Own ID? No
Yes
Read RDRF bit in SSR
RDRF = 1?
Read ORER and FER
bits in SSR
Read receive data from RDR
Read receive data from RDR
258
Figure 12-11 shows an example of an SCI receive operation using a multiprocessor format (8-bit
data with multiprocessor bit and one stop bit).
Figure 12-11 Example of SCI Receive Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
1Start
bit
0D0D1 D71
Stop
bit
1
Data (ID1) MPB Start
bit
0D0D1 D70
Stop
bit
1
Data (Data1) MPB 1
Idle state
(mark)
MPIE
RDRF
RDR value ID1
RXI requestMPB detection
MPIE = 0
RXI requestMPB detection
MPIE = 0
RXI handler reads
RDR data and clears
RDRF to 0
Not own ID, so
MPIE is set to
1 again
No RXI request,
RDR not updated
(Multiprocessor interrupt)
(a) Own ID does not match data
1Start
bit
0D0D1 D71
Stop
bit
1
Data (ID2) MPB Start
bit
0D0D1 D70
Stop
bit
1
Data (Data2) MPB 1
Idle state
(mark)
MPIE
RDRF
RDR value ID2
RXI handler reads
RDR data and clears
RDRF to 0
Own ID, so receiving
continues, with data
received at each RXI
MPIE set to
1 again
(Multiprocessor interrupt)
(b) Own ID matches data
Data 2
259
12.3.3 Synchronous Mode
(1) Overview: In synchronous mode, the SCI transmits and receives data in synchronization with
clock pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex
communication is possible. The transmitter and receiver are also double buffered, so continuous
transmitting or receiving is possible by reading or writing data while transmitting or receiving is in
progress.
Figure 12-12 shows the general format in synchronous serial communication.
Figure 12-12 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is sent on the communication line from one
falling edge of the serial clock to the next. Data is received in synchronization with the rising edge
of the serial clock.
In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB.
Serial clock
Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
LSB MSB
Don’t care Don’t care
One unit (character or frame) of serial data
**
Note: High except in continuous transmitting or receiving*
260
• Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor
bit can be added.
• Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected by clearing or setting the CKE1 bit in the serial control register
(SCR). See table 12-6.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains at the high level.
(2) Transmitting and Receiving Data
• SCI Initialization: The SCI must be initialized in the same way as in asynchronous mode. See
figure 12-4. When switching from asynchronous mode to synchronous mode, check that the ORER,
FER, and PER bits are cleared to 0. Transmitting and receiving cannot begin if ORER, FER, or PER
is set to 1.
261
• Transmitting Serial Data: Follow the procedure in figure 12-13 for transmitting serial data.
Figure 12-13 Sample Flowchart for Serial Transmitting
Start transmitting
Read TDRE bit in SSR
TDRE = 1?
Write transmit data in
TDR and clear TDRE bit to
0 in SSR
End of
transmission?
End
1
2
3
No
Yes
No
Yes
SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
SCI status check and transmit data write: read
the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the
transmit data register (TDR) and clear TDRE to 0.
Transition of the TDRE bit from 0 to 1 can be
reported by a TXI interrupt.
To continue transmitting serial data: read the
TDRE bit to check whether it is safe to write; if
TDRE = 1, write data in TDR, then clear TDRE
to 0.
To end serial transmission: end of transmission
can be confirmed by checking transition of the
TEND bit from 0 to 1. This can be reported by
a TEI interrupt.
(a)
(b)
Read TEND bit in SSR
TEND = 1? No
Yes
1.
2.
3.
Initialize
Clear TE bit to 0 in SCR
Serial transmission
262
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to 1, the SCI requests a
TXI interrupt (TDR-empty interrupt) at this time.
If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of
the TDRE bit to 0. If an external clock source is selected, the SCI outputs data in
synchronization with the input clock.
Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data
from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI
sets the TEND bit in SSR to 1, transmits the MSB, then holds the output in the MSB state. If
the TEIE bit (transmit-end interrupt enable) in SCR is set to 1, a TEI interrupt (TSR-empty
interrupt) is requested at this time.
4. After the end of serial transmission, the SCK pin is held at the high level.
263
Figure 12-14 shows an example of SCI transmit operation.
Figure 12-14 Example of SCI Transmit Operation
Serial clock
Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TXI
request
TDRE
TEND
TXI interrupt
handler writes
data in TDR and
clears TDRE to 0
TXI
request TEI
request
1 frame
264
• Receiving Serial Data: Follow the procedure in figure 12-15 for receiving serial data. When
switching from asynchronous mode to synchronous mode, be sure to check that PER and FER are
cleared to 0. If PER or FER is set to 1 the RDRF bit will not be set and both transmitting and
receiving will be disabled.
Figure 12-15 Sample Flowchart for Serial Receiving
Start receiving
Read ORER bit in SSR
ORER = 1?
RDRF = 1?
Read RDRF in SSR
Finished
receiving?
Clear RE to 0 in SCR
End
Error handling
1
2
3
Yes
No
No
Yes
No
Yes
4
1.
2.
3.
4.
SCI initialization: the receive data function of the
RxD pin is selected automatically.
Receive error handling: if a receive error occurs,
read the ORER bit in SSR then, after executing
the necessary error handling, clear ORER to 0.
Neither transmitting nor receiving can resume
while ORER remains set to 1. When clock
output mode is selected, receiving can be halted
temporarily by receiving one dummy byte and
causing an overrun error. When preparations
to receive the next data are completed, clear
the ORER bit to 0. This causes receiving to
resume, so return to the step marked 2 in the
flowchart.
SCI status check and receive data read: read
the serial status register (SSR), check that
RDRF is set to 1, then read receive data from
the receive data register (RDR) and clear RDRF
to 0. Transition of the RDRF bit from 0 to 1
can be reported by an RXI interrupt.
To continue receiving serial data: read RDR and
clear RDRF to 0 before the MSB (bit 7) of the
current frame is received.
Clear ORER to 0 in SSR
Return
Overrun error handling
Start error handling
Initialize
Read receive data
from RDR, and clear
RDRF bit to 0 in SSR
265
In receiving, the SCI operates as follows.
1. If an external clock is selected, data is input in synchronization with the input clock. If clock
output is selected, as soon as the RE bit is set to 1 the SCI begins outputting the serial clock and
inputting data. If clock output is stopped because the ORER bit is set to 1, output of the serial
clock and input of data resume as soon as the ORER bit is cleared to 0.
2. Receive data is shifted into RSR in order from LSB to MSB.
After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from
RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in
RDR. If the check does not pass (receive error), the SCI operates as indicated in
table 12-8.
Note: Both transmitting and receiving are disabled while a receive error flag is set. The RDRF
bit is not set to 1. Be sure to clear the error flag.
3. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI
requests an RXI (receive-end) interrupt. If the ORER bit is set to 1 and the RIE bit in SCR is set
to 1, the SCI requests an ERI (receive-error) interrupt.
When clock output mode is selected, clock output stops when the RE bit is cleared to 0 or the
ORER bit is set to 1. To prevent clock count errors, it is safest to receive one dummy byte and
generate an overrun error.
266
Figure 12-16 shows an example of SCI receive operation.
Figure 12-16 Example of SCI Receive Operation
Serial clock
Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RXI
request
RDRF
ORER
RXI interrupt
handler reads
data in RDR and
clears RDRF to 0
RXI
request Overrun error,
ERI request
1 frame
267
• Transmitting and Receiving Serial Data Simultaneously: Follow the procedure in figure
12-17 for transmitting and receiving serial data simultaneously. If clock output mode is selected,
output of the serial clock begins simultaneously with serial transmission.
Figure 12-17 Sample Flowchart for Serial Transmitting and Receiving
Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear
both TE and RE to 0, then set both TE and RE to 1.
Start
Read TDRE bit in SSR
TDRE = 1?
Write transmit data
in TDR and clear TDRE
bit to 0 in SSR
RDRF = 1?
Read ORER bit in SSR
End of
transmitting and receiv-
ing?
Clear TE and RE bits
to 0 in SCR
End
Error handling
1
2
3
No
Yes
Yes
Yes
No
Yes
4
1.
2.
3.
4.
5.
SCI initialization: the transmit data output function of
the TxD pin and receive data input function of the
RxD pin are selected, enabling simultaneous
transmitting and receiving.
SCI status check and transmit data write: read the
serial status register (SSR), check that the TDRE bit
is 1, then write transmit data in the transmit data
register (TDR) and clear TDRE to 0. Transition of the
TDRE bit from 0 to 1 can be reported by a TXI interrupt.
SCI status check and receive data read: read the
serial status register (SSR), check that the RDRF
bit is 1, then read receive data from the receive data
register (RDR) and clear RDRF to 0. Transition of
the RDRF bit from 0 to 1 can be reported by an RXI
interrupt.
Receive error handling: if a receive error occurs, read
the ORER bit in SSR then, after executing the
necessary error handling, clear ORER to 0. Neither
transmitting nor receiving can resume while ORER
remains set to 1.
To continue transmitting and receiving serial data:
read RDR and clear RDRF to 0 before the MSB
(bit 7) of the current frame is received. Also read the
TDRE bit and check that it is set to 1, indicating that
it is safe to write; then write data in TDR and clear
TDRE to 0 before the MSB (bit 7) of the current frame
is transmitted.
ORER = 1?
Read RDRF bit in SSR
5
No
No
Initialize
Read receive data
from RDR and clear
RDRF bit to 0 in SSR
268
12.4 Interrupts
The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 12-9 indicates the
source and priority of these interrupts. The interrupt sources can be enabled or disabled by the TIE,
RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for each
interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three sources:
overrun error, framing error, and parity error.
The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt indicates
that the SCI has stopped transmitting data.
Table 12-9 SCI Interrupt Sources
Interrupt Description Priority
ERI Receive-error interrupt (ORER, FER, or PER) High
RXI Receive-end interrupt (RDRF)
TXI TDR-empty interrupt (TDRE)
TEI TSR-empty interrupt (TEND) Low
12.5 Application Notes
Application programmers should note the following features of the SCI.
(1) TDR Write: The TDRE bit in SSR is simply a flag that indicates that the TDR contents have
been transferred to TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new
byte is written in TDR while the TDRE bit is 0, before the old TDR contents have been moved into
TSR, the old byte will be lost. Software should check that the TDRE bit is set to 1 before writing to
TDR.
(2) Multiple Receive Errors: Table 12-10 lists the values of flag bits in the SSR when multiple
receive errors occur, and indicates whether the RSR contents are transferred to RDR.
269
Table 12-10 SSR Bit States and Data Transfer when Multiple Receive Errors Occur
SSR Bits RSR →
Receive error RDRF ORER FER PER RDR*2
Overrun error 1*1100No
Framing error 0 0 1 0 Yes
Parity error 0 0 0 1 Yes
Overrun and framing errors 1*1110No
Overrun and parity errors 1*1101No
Framing and parity errors 0 0 1 1 Yes
Overrun, framing, and parity errors 1*1111No
Notes: 1. Set to 1 before the overrun error occurs.
2. Yes: The RSR contents are transferred to RDR.
No: The RSR contents are not transferred to RDR.
(3) Line Break Detection: When the RxD pin receives a continuous stream of 0’s in asynchronous
mode (line-break state), a framing error occurs because the SCI detects a 0 stop bit. The value H'00
is transferred from RSR to RDR. Software can detect the line-break state as a framing error
accompanied by H'00 data in RDR.
The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will occur.
(4) Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by the
SCI in asynchronous mode runs at 16 times the bit rate. The falling edge of the start bit is detected
by sampling the RxD input on the falling edge of this clock. After the start bit is detected, each bit
of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the
rising edge of the serial clock pulse at the center of the bit. See figure 12-18.
It follows that the receive margin can be calculated as in equation (1).
When the absolute frequency deviation of the clock signal is 0 and the clock duty cycle is 0.5, data
can theoretically be received with distortion up to the margin given by equation (2). This is a
theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.
270
Figure 12-18 Sampling Timing (Asynchronous Mode)
M = {(0.5 – 1/2N) – (D – 0.5)/N – (L – 0.5)F} ×100 [%] (1)
M: Receive margin
N: Ratio of basic clock to bit rate (N=16)
D: Duty factor of clock—ratio of high pulse width to low width (0.5 to 1.0)
L: Frame length (9 to 12)
F: Absolute clock frequency deviation
When D = 0.5 and F = 0
M = (0.5 –1/2 ×16) ×100 [%] = 46.875% (2)
12 4
0567893 2123456789 111 12 13 14 15 1610 13 14 1516 1210 11 3 4 5
Basic
clock
Sync
sampling
Data
sampling
D0 D1
Receive
data Start bit
–7.5 pulses +7.5 pulses
271
Section 13 I2C Bus Interface [Option]
An I2C bus interface is available as an option. Observe the following notes when using this option.
1. Please inform your Hitachi sales representative if you intend to use this option.
2. For mask-ROM versions, products that use this option have a “W” added to the product
number.
Examples: HD6433437WTF, HD6433434WF
3. The product number is identical for ZTAT and F-ZTAT versions. However, be sure to inform
your Hitachi sales representative if you will be using this option.
13.1 Overview
The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus)
interface functions. The register configuration that controls the I2C bus differs partly from the
Philips configuration, however.
The I2C bus interface uses only one data line (SDA) and one clock line (SCL) to transfer data, so it
can save board and connector space. Figure 13-1 shows typical I2C bus interface connections.
13.1.1 Features
• Conforms to Philips I2C bus interface
• Start and stop conditions generated automatically
• Selectable acknowledge output level when receiving
• Auto-loading of acknowledge bit when transmitting
• Selection of eight internal clocks (in master mode)
• Selection of acknowledgement mode, or serial mode without acknowledge bit
• Wait function: A wait can be inserted in acknowledgement mode by holding the SCL pin low
after a data transfer, before acknowledgement of the transfer.
• Three interrupt sources
— Data transfer end
— In slave receive mode: slave address matched, or general call address received
— In master transmit mode: bus arbitration lost
• Direct bus drive (pins SCL and SDA)
273
• In addition to pins SCL and SCA, four general port pins (PA4to PA7) can also drive the bus
• Pins P86/SCK1/SCL, P97/WAIT/SDA, and PA4/KEYIN12 to PA7/KEYIN15 (total of 6 pins) are
all powered by bus power supply VCCB, separate from VCC. When the bus drive function is
selected, all output is NMOS output.
Figure 13-1 I2C Bus Interface Connection Example
(When the H8/3437 is the Master Chip)
SCL in
SCL out
SDA in
SDA out
(Slave 1)
SCL
SDA
SCL in
SCL out
SDA in
SDA out
(Slave 2)
SCL
SDA
SCL in
SCL out
SDA in
SDA out
(Master)
SCL
SDA
SCL
SDA
VCC
VCC VCCB
VCCB
H8/3437
274
13.1.2 Block Diagram
Figure 13-2 shows a block diagram of the I2C bus interface.
Figure 13-2 Block Diagram of I2C Bus Interface
øPPS
Noise
canceler
Noise
canceler
Clock
control
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
Address
comparator
SAR
Interrupt
generator
ICDR
ICSR
ICMR
ICCR
Internal data bus
Interrupt
request
SCL
SDA
Legend
ICCR:
ICMR:
ICSR:
ICDR:
SAR:
PS:
I2C bus control register
I2C bus mode register
I2C bus status register
I2C bus data register
Slave address register
Prescaler
275
13.1.3 Input/Output Pins
Table 13-1 summarizes the input/output pins used by the I2C bus interface.
Table 13-1 Wait-State Controller Pins
Name Abbreviation I/O Function
Serial clock SCL Input/output Serial clock input/output
Serial data SDA Input/output Serial data input/output
13.1.4 Register Configuration
Table 13-2 summarizes the registers of the I2C bus interface.
Table 13-2 Register Configuration
Name Abbreviation R/W Initial Value Address*2
I2C bus control register ICCR R/W H'00 H'FFD8
I2C bus status register ICSR R/W H'30 H'FFD9
I2C bus data register ICDR R/W — H'FFDE
I2C bus mode register ICMR R/W H'38 H'FFDF*1
Slave address register SAR R/W H'00 H'FFDF*1
Serial timer control register STCR R/W H'00 H'FFC3
Notes: 1. The register that can be written or read depends on the ICE bit in the I2C bus control
register. The slave address register can be accessed when ICE = 0. The I2C bus mode
register can be accessed when ICE = 1.
2. The addresses assigned to the I2C bus interface registers are also assigned to other
registers. The accessible registers are selected with bit IICE in the serial/timer control
register (STCR).
276
13.2 Register Descriptions
13.2.1 I2C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting
and a receive data register when receiving. Transmitting is started by writing data in ICDR.
Receiving is started by reading data from ICDR.
ICDR is also used as a shift register, so it must not be written or read until data has been completely
transmitted or received. Read or write access while data is being transmitted or received may result
in incorrect data.
The ICDR value following a reset is undetermined.
13.2.2 Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first byte received after a start condition, the
chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR. SAR can be written and read only when the ICE bit is cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset.
Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
differing from the addresses of other slave devices connected to the I2C bus.
Bit
Initial value
Read/Write
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Bit
Initial value
Read/Write
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
0
ICDR0
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
277
Bit 0—Format Select (FS): Selects whether to use the addressing format or non-addressing format
in slave mode. The addressing format is used to recognize slave addresses.
Bit 0
FS Description
0 Addressing format, slave addresses recognized (Initial value)
1 Non-addressing format
13.2.3 I2C Bus Mode Register (ICMR)
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first,
performs wait control, and selects the transfer bit count. ICMR is assigned to the same address as
SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'38 by a reset.
Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or LSB-
first.
Bit 7
MLS Description
0 MSB-first (Initial value)
1 LSB-first
Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data
and the acknowledge bit, in acknowledgement mode. When WAIT is set to 1, after the fall of the
clock for the final data bit, a wait state begins (with SCL staying at the low level). When bit IRIC is
cleared in ICSR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0, data
and acknowledge bits are transferred consecutively with no wait inserted.
Bit 6
WAIT Description
0 Data and acknowledge transferred consecutively (Initial value)
1 Wait inserted between data and acknowledge
Bit
Initial value
Read/Write
7
MLS
0
R/W
6
WAIT
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
278
Bits 5 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0—Bit Counter (BC2 to BC0): BC2 to BC0 specify the number of bits to be transferred
next. When the ACK bit is cleared to 0 in ICCR (acknowledgement mode), the data is transferred
with one additional acknowledge bit. BC2 to BC0 settings should be made during an interval
between transfer frames. If BC2 to BC0 are set to a value other than 000, the setting should be made
while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge.
Bit 2 Bit 1 Bit 0 Bits/Frame
BC2 BC1 BC0 Serial Mode Acknowledgement Mode
0 0 0 8 9 (Initial value)
11 2
102 3
13 4
1004 5
15 6
106 7
17 8
279
13.2.4 I2C Bus Control Register (ICCR)
ICCR is an 8-bit readable/writable register that enables or disables the I2C bus interface, enables or
disables interrupts, and selects master or slave mode, transmit or receive, acknowledgement or serial
mode, and the clock frequency.
ICCR is initialized to H'00 by a reset.
Bit 7—I2C Bus Interface Enable (ICE): Selects whether or not to use the I2C bus interface. When
ICE is set to 1, the SCL and SDA signals are assigned to input/output pins and transfer operations
are enabled. When ICE is cleared to 0, the interface module is disabled.
The SAR register can be accessed when ICE is 0. The ICMR register can be accessed when ICE is
1.
Bit 7
ICE Description
0 Interface module disabled, with SCL and SDA signals in high-impedance state
(Initial value)
1 Interface module enabled for transfer operations (pins SCL and SDA are driving the bus*)
Note: *Pin SDA is multiplexed with the WAIT input pin. In expanded mode, WAIT input has priority
for this pin.
Bit 6—I2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C
bus interface to the CPU.
Bit 6
IEIC Description
0 Interrupts disabled (Initial value)
1 Interrupts enabled
Bit
Initial value
Read/Write
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACK
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
280
Bit 5—Master/Slave Select (MST)
Bit 4—Transmit/Receive Select (TRS)
MST selects whether the I2C bus interface operates in master mode or slave mode.
TRS selects whether the I2C bus interface operates in transmit mode or receive mode.
In master mode, when arbitration is lost, MST and TRS are both reset by hardware, causing a
transition to slave receive mode. In slave receive mode with the addressing format (FS = 0),
hardware automatically selects transmit or receive mode according to the R/W bit in the first byte
after a start condition.
MST and TRS select the operating mode as follows.
Bit 5 Bit 4
MST TRS Operating Mode
0 0 Slave receive mode (Initial value)
1 Slave transmit mode
1 0 Master receive mode
1 Master transmit mode
Bit 3—Acknowledgement Mode Select (ACK): Selects acknowledgement mode or serial mode. In
acknowledgement mode (ACK = 0), data is transferred in frames consisting of the number of data
bits selected by BC2 to BC0 in ICMR, plus an extra acknowledge bit. In serial mode (ACK = 1), the
number of data bits selected by BC2 to BC0 in ICMR is transferred as one frame.
Bit 3
ACK Description
0 Acknowledgement mode (Initial value)
1 Serial mode
281
Bits 2 to 0—Serial Clock Select (CKS2 to CKS0): These bits, together with the ICCX bit in the
STCR register, select the serial clock frequency in master mode. They should be set according to the
required transfer rate.
(STCR) Bit 2 Bit 1 Bit 0 Transfer Rate*
IICX CKS2 CKS1 CKS0 Clock øP= 4 MHz øP = 5 MHz øP = 8 MHz øP = 10 MHz øP = 16 MHz
0 000ø
P
/28 143 kHz 179 kHz 286 kHz 357 kHz 571 kHz
001ø
P
/40 100 kHz 125 kHz 200 kHz 250 kHz 400 kHz
010ø
P
/48 83.3 kHz 104 kHz 167 kHz 208 kHz 333 kHz
011ø
P
/64 62.5 kHz 78.1 kHz 125 kHz 156 kHz 250 kHz
100ø
P
/80 50.0 kHz 62.5 kHz 100 kHz 125 kHz 200 kHz
101ø
P
/100 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz 160 kHz
110ø
P
/112 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz
111ø
P
/128 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz
1 000ø
P
/56 71.4 kHz 89.3 kHz 143 kHz 179 kHz 286 kHz
001ø
P
/80 50.0 kHz 62.5 kHz 100 kHz 125 kHz 200 kHz
010ø
P
/96 41.7 kHz 52.1 kHz 83.3 kHz 104 kHz 167 kHz
011ø
P
/128 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz
100ø
P
/160 25.0 kHz 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz
101ø
P
/200 20.0 kHz 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz
110ø
P
/224 17.9 kHz 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz
111ø
P
/256 15.6 kHz 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz
Note: *øP= ø.
282
13.2.5 I2C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register with flags that indicate the status of the I2C bus interface.
It is also used for issuing start and stop conditions, and recognizing and controlling acknowledge
data.
ICSR is initialized to H'30 by a reset.
Bit 7—Bus Busy (BBSY): This bit can be read to check whether the I2C bus (SCL and SDA) is
busy or free. In master mode this bit is also used in issuing start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY
to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing
BBSY to 0.
To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, use a MOV instruction to write
0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode.
Bit 7
BBSY Description
0 Bus is free (Initial value)
This bit is cleared when a stop condition is detected.
1 Bus is busy
This bit is set when a start condition is detected.
Bit
Initial value
Read/Write
7
BBSY
0
R/W
6
IRIC
0
R/(W)*
5
SCP
1
W
4
—
1
—
3
AL
0
R/(W)*
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
Note: * Only 0 can be written, to clear the flag.
283
Bit 6—I2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface has
issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave
address or general call address is detected in slave receive mode, and when bus arbitration is lost in
master transmit mode. IRIC is set at different timings depending on the ACK bit in ICCR and
WAIT bit in ICMR. See the item on IRIC Set Timing and SCL Control in section 13.3.6
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
Bit 6
IRIC Description
0 Waiting for transfer, or transfer in progress (Initial value)
To clear this bit, the CPU must read IRIC when IRIC = 1, then write 0 in IRIC
1 Interrupt requested
This bit is set to 1 at the following times:
Master mode
• End of data transfer
• When bus arbitration is lost
Slave mode (when FS = 0)
• When the slave address is matched, and whenever a data transfer ends at the timing
of a retransmit start condition after address matching or a stop condition is detected
• When a general call address is detected, and whenever a data transfer ends at the timing
of a retransmit start condition after address detection or a stop condition is detected
Slave mode (when FS = 1)
• End of data transfer
Bit 5—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop
conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A start
condition for retransmit is issued in the same way. To issue a stop condition, write 0 in BBSY and 0
in SCP. This bit always reads 1. Written data is not stored.
Bit 5
SCP Description
0 Writing 0 issues a start or stop condition, in combination with BBSY
1 Reading always results in 1 (Initial value)
Writing is ignored
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
284
Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The I2C
bus interface monitors the bus. When two or more master devices attempt to seize the bus at nearly
the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL to 1 to
indicate that the bus has been taken by another master. At the same time, it sets the IRIC bit in ICSR
to generate an interrupt request.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset
automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode.
Bit 3
AL Description
0 Bus arbitration won (Initial value)
This bit is cleared to 0 at the following times:
• When ICDR data is written (transmit mode) or read (receive mode)
• When AL is read while AL = 1, then 0 is written in AL
1 Arbitration lost
This bit is set to 1 at the following times:
• If the internal SDA signal and bus line disagree at the rise of SCL in master transmit
mode
• If the internal SCL is high at the fall of SCL in master transmit mode
Bit 2—Slave Address Recognition Flag (AAS): When the addressing format is selected (FS = 0)
in slave receive mode, this flag is set to 1 if the first byte following a start condition matches bits
SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 2
AAS Description
0 Slave address or general call address not recognized (Initial value)
This bit is cleared to 0 at the following times:
• When ICDR data is written (transmit mode) or read (receive mode)
• When AAS is read while AAS = 1, then 0 is written in AAS
1 Slave address or general call address recognized
This bit is set to 1 at the following times:
• When the slave address or general call address is detected in slave receive mode
285
Bit 1—General Call Address Recognition Flag (ADZ): When the addressing format is selected
(FS = 0) in slave receive mode, this flag is set to 1 if the first byte following a start condition is the
general call address (H'00).
ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 1
ADZ Description
0 General call address not recognized (Initial value)
This bit is cleared to 0 at the following times:
• When ICDR data is written (transmit mode) or read (receive mode)
• When ADZ is read while ADZ = 1, then 0 is written in ADZ
1 General call address recognized
This bit is set to 1 when the general call address is detected in slave receive mode
Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data in acknowledgement mode. In
transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is
loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this
bit is sent to the transmitting device.
When this bit is read, if TRS = 1, the value loaded from the bus line is read. If TRS = 0, the value
set by internal software is read.
Bit 0
ACKB Description
0 Receive mode: 0 is output at acknowledge output timing (Initial value)
Transmit mode: indicates that the receiving device has acknowledged the data
1 Receive mode: 1 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has not acknowledged the data
286
287
13.2.6 Serial/Timer Control Register (STCR)
STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the
TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset.
Bit 7—I2C Extra Buffer Select (IICS): Makes bits 7 to 4 of port A into output buffers similar to
SCL and SDA. Used when an I2C bus interface is implemented by software alone.
Bit 7
IICS Description
0PA
7
to PA4are normal input/output pins (Initial value)
1PA
7
to PA4are input/output pins that can drive the bus
Bit 6—I2C Extra Buffer Reserve (IICD): This bit is reserved, but it can be written and read. Its
initial value is 0.
Bit 5—I2C Transfer Rate Select (IICX): This bit, in combination with bits CKS2 to CKS0 in
ICCR, selects the transfer rate in master mode. For details regarding the transfer rate, refer to
section 13.2.4, I2C Bus Control Register (ICCR).
Bit 4—I2C Master Enable (IICE): Controls CPU access to the data and control registers (ICCR,
ICSR, ICDR, ICMR/SAR) of the I2C bus interface.
Bit 4
IICE Description
0 CPU access to I2C bus interface data and control registers is disabled (Initial value)
1 CPU access to I2C bus interface data and control registers is enabled
Bit 3—Slave Input Switch (STAC): Switches host interface input pins. For details, see section 14,
Host Interface.
Bit 2—Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication
function on channels SCI0 and SCI1. For details, see section 12, Serial Communication Interface.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits select the clock
input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit Timers.
Bit
Initial value
Read/Write
7
IICS
0
R/W
6
IICD
0
R/W
5
IICX
0
R/W
4
IICE
0
R/W
3
STAC
0
R/W
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
13.3 Operation
13.3.1 I2C Bus Data Format
The I2C bus interface has three data formats: two addressing formats, shown as (a) and (b) in figure
13-3, and a non-addressing format, shown as (c) in figure 13-4. The first byte following a start
condition always consists of 8 bits. Figure 13-5 shows the I2C bus timing.
Figure 13-3 I2C Bus Data Formats (Addressing Formats)
S SLA R/W A DATA A A/A P
111 1
n7
1m
(a) Addressing format (FS = 0)
(b) Addressing format (retransmit start condition, FS = 0)
n: Bit count
(n = 1 to 8)
m: Frame count
(m ≥ 1)
S SLA R/W A DATA
111 n1
7
1m1
S SLA R/W A DATA A/A P
111 n2
7
1m2
11
1
A/A
n1 and n2: Bit count (n1 and n2 = 1 to 8)
m1 and m2: Frame count (m1 and m2 ≥ 1)
11
288
Figure 13-4 I2C Bus Data Format (Non-Addressing Format)
Legend
S: Start condition. The master device drives SDA from high to low while SCL is high.
SLA: Slave address, by which the master device selects a slave device.
R/W: Indicates the direction of data transfer: from the slave device to the master device when R/Wis 1, or from
the master device to the slave device when R/Wis 0.
A: Acknowledge. The receiving device (the slave in master transmit mode, or the master in master receive
mode) drives SDA low to acknowledge a transfer. If transfers need not be acknowledged, set the ACK bit
to 1 in ICCR to keep the interface from generating the acknowledge signal and its clock pulse.
DATA: Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or LSB-first format is
selected by bit MLS in ICMR.
P: Stop condition. The master device drives SDA from low to high while SCL is high.
Figure 13-5 I2C Bus Timing
SDA
SCL
S
1-7
SLA
8
R/W
9
A
1-7
DATA
89 1-7 89
A DATA A/AP
S DATA A DATA A A/A P
111
n8
1m
(c) Non-addressing format (FS = 1)
n: Bit count
(n = 1 to 8)
m: Frame count
(m ≥ 1)
11
289
13.3.2 Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The transmit procedure and operations in master
transmit mode are described below.
1. Set bits MLS and WAIT in ICMR and bits ACK and CKS2 to CKS0 in ICCR according to the
operating mode. Set bit ICE in ICCR to 1.
2. Read BBSY in ICSR, check that the bus is free, then set MST and TRS to 1 in ICCR to select
master transmit mode. After that, write 1 in BBSY and 0 in SCP. This generates a start
condition by causing a high-to-low transition of SDA while SCL is high.
3. Write data in ICDR. The master device outputs the written data together with a sequence of
transmit clock pulses at the timing shown in figure 13-6. If FS is 0 in SAR, the first byte
following the start condition contains a 7-bit slave address and indicates the transmit/receive
direction. The selected slave device (the device with the matching slave address) drives SDA
low at the ninth transmit clock pulse to acknowledge the data.
4. When one byte of data has been transmitted, IRIC is set to 1 in ICSR at the rise of the ninth
transmit clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. After one frame
has been transferred, SCL is automatically brought to the low level in synchronization with the
internal clock and held low.
5. Software clears IRIC to 0 in ICSR.
6. To continue transmitting, write the next transmit data in ICDR. Transmission of the next byte
will begin in synchronization with the internal clock.
Steps 4 to 6 can be repeated to transmit data continuously. To end the transmission, write 0 in
BBSY and 0 in SCP in ICSR. This generates a stop condition by causing a low-to-high transition of
SDA while SCL is high.
290
Figure 13-6 Timing in Master Transmit Mode
(MLS = WAIT = ACK = 0)
1987654321
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
A
SCL
SDA (master
output)
SDA (slave
output)
IRIC
User
processing 2. Write BBSY = 1
and SCP = 0
Interrupt
request
3. Write to ICDR 5. Clear IRIC 6. Write to ICDR
291
13.3.3 Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits the data. The receive procedure and operations in
master receive mode are described below. See also figure 13-7.
1. Clear TRS to 0 in ICCR to switch from transmit mode to receive mode.
2. Read ICDR to start receiving. When ICDR is read, a receive clock is output in synchronization
with the internal clock, and data is received. At the ninth clock pulse the master device drives
SDA low to acknowledge the data.
3. When one byte of data has been received, IRIC is set to 1 in ICSR at the rise of the ninth
receive clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. After one frame
has been transferred, SCL is automatically brought to the low level in synchronization with the
internal clock and held low.
4. Software clears IRIC to 0 in ICSR.
5. When ICDR is read, receiving of the next data starts in synchronization with the internal clock.
Steps 3 to 5 can be repeated to receive data continuously. To stop receiving, set TRS to 1, read
ICDR, then write write 0 in BBSY and 0 in SCP in ICSR. This generates a stop condition by
causing a low-to-high transition of SDA while SCL is high. If it is not necessary to acknowledge
each byte of data, set ACKB to 1 in ICSR before receiving starts.
292
Figure 13-7 Timing in Master Receive Mode
(MLS = WAIT = ACK = ACKB = 0)
98765432119
A
A
Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7
Interrupt
request Interrupt
request
Master
transmit
mode Master receive mode
SCL
SDA (slave
output)
SDA (master
output)
IRIC
User processing 2. Read ICDR 4. Clear IRIC 5. Read ICDR
293
13.3.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the
transmit clock and returns an acknowledge signal. The transmit procedure and operations in slave
transmit mode are described below.
1. Set bits MLS and WAIT in ICMR and bits MST, TRS, ACK, and CKS2 to CKS0 in ICCR
according to the operating mode. Set bit ICE in ICCR to 1, establishing slave receive mode.
2. After the slave device detects a start condition, if the first byte matches its slave address, at the
ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the same
time, IRIC is set to 1 in ICSR, generating an interrupt. If the eighth data bit (R/W) is 1, the TRS
bit is set to 1 in ICCR, automatically causing a transition to slave transmit mode. The slave
device holds SCL low from the fall of the transmit clock until data is written in ICDR.
3. Software clears IRIC to 0 in ICSR.
4. Write data in ICDR. The slave device outputs the written data serially in step with the clock
output by the master device, with the timing shown in figure 13-8.
5. When one byte of data has been transmitted, at the rise of the ninth transmit clock pulse IRIC is
set to 1 in ICSR. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. The slave device
holds SCL low from the fall of the transmit clock until data is written in ICDR. The master
device drives SDA low at the ninth clock pulse to acknowledge the data. The acknowledge
signal is stored in ACKB in ICSR, and can be used to check whether the transfer was carried
out normally.
6. Software clears IRIC to 0 in ICSR.
7. To continue transmitting, write the next transmit data in ICDR.
Steps 5 to 7 can be repeated to transmit continuously. To end the transmission, write H'FF in ICDR.
When a stop condition is detected (a low-to-high transition of SDA while SCL is high), BBSY will
be cleared to 0 in ICSR.
294
Figure 13-8 Timing in Slave Transmit Mode
(MLS = WAIT = ACK = 0)
Slave receive
mode Slave transmit mode
SCL (master
output)
SCL (slave
output)
SDA (slave
output)
SDA (master
output)
89 123456789 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
A
R/W A
Interrupt
request Interrupt
request
User processing 3. Clear IRIC 4. Write to ICDR 6. Clear IRIC 7. Write to ICDR
IRIC
295
13.3.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave
device returns an acknowledge signal. The receive procedure and operations in slave receive mode
are described below. See also figure 13-9.
1. Set bits MLS and WAIT in ICMR and bits MST, TRS, and ACK in ICCR according to the
operating mode. Set bit ICE in ICCR to 1, establishing slave receive mode.
2. A start condition output by the master device sets BBSY to 1 in ICSR.
3. After the slave device detects the start condition, if the first byte matches its slave address, at
the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the same
time, IRIC is set to 1 in ICSR. If IEIC is 1 in ICCR, a CPU interrupt is requested. The slave
device holds SCL low from the fall of the receive clock until it has read the data in ICDR.
4. Software clears IRIC to 0 in ICSR.
5. When ICDR is read, receiving of the next data starts.
Steps 4 and 5 can be repeated to receive data continuously. When a stop condition is detected (a
low-to-high transition of SDA while SCL is high), BBSY is cleared to 0 in ICSR.
Figure 13-9 Timing in Slave Receive Mode
(MLS = WAIT = ACK = ACKB = 0)
Start condition
SCL (master
output)
SCL (slave
output)
SDA (master
output
SDA (slave
output)
IRIC
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
Interrupt
request
4. Clear IRIC 5. Read ICDR
User processing
1987654321
296
13.3.6 IRIC Set Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR and
ACK bit in ICCR. SCL is automatically held low after one frame has been transferred; this timing is
synchronized with the internal clock. Figure 13-10 shows the IRIC set timing and SCL control.
Figure 13-10 IRIC Set Timing and SCL Control
(a) When WAIT = 0 and ACK = 0
SCL
SDA
IRIC
User processing Clear IRIC Write to ICDR (transmit)
or read ICDR (receive)
1A87
(b) When WAIT = 1 and ACK = 0
SCL
SDA
IRIC
User processing Clear IRIC Write to ICDR (transmit)
or read ICDR (receive)
Note: The ICDR write (transmit) or read (receive) following the clearing of IRIC
should be executed after the rise of SCL (ninth clock pulse).
SCL
SDA
IRIC
User processing
(c) When ACK = 1
Clear IRIC Write to ICDR (transmit)
or read ICDR (receive)
A871
871
297
13.3.7 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 13-11 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Figure 13-11 Block Diagram of Noise Canceler
t
Sampling clock
C
DQ
Latch
C
DQ
Latch
SCL or
SDA input
signal Match
detector Internal
SCL or
SDA
signal
Sampling
clock
t: System clock
298
13.3.8 Sample Flowcharts
Figures 13-12 to 13-15 show typical flowcharts for using the I2C bus interface in each mode.
Figure 13-12 Flowchart for Master Transmit Mode (Example)
1
2
3
4
5
6
7
8
9
10
Start
Initialize
Read BBSY in ICSR
No BBSY = 0?
Yes
Set MST = 1 and
TRS = 1 in ICCR
Write BBSY = 1
and SCP = 0 in ICSR
Write transmit data in ICDR
Read IRIC in ICSR
No
Yes
IRIC = 1?
Clear IRIC in ICSR
Read ACKB in ICSR
ACKB = 0? No
Yes No
Yes
Transmit mode?
Write transmit data in ICDR
Read IRIC in ICSR
IRIC = 1?
No
Yes
Clear IRIC in ICSR
Read ACKB in ICSR
End of transmission
(ACKB = 1)?
No
Yes
Write BBSY = 0
and SCP = 0 in ICSR
End
Master receive mode
299
1. Test the status of the SCL and SDA lines.
2. Select master transmit mode.
3. Generate a start condition.
4. Set transmit data for the first byte (slave address + R/W).
5. Wait for 1 byte to be transmitted.
6. Test for acknowledgement by the designated slave
device.
7. Set transmit data for the second and subsequent bytes.
8. Wait for 1 byte to be transmitted.
9. Test for end of transfer.
10. Generate a stop condition.
Figure 13-13 Flowchart for Master Receive Mode (Example)
Master receive mode
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Last receive?
Read ICDR
Read IRIC in ICSR
Clear IRIC in ICSR
IRIC = 1?
Yes
No
No
Yes
Set ACKB = 1 in ICSR
Read ICDR
Read IRIC in ICSR
IRIC = 1?
Clear IRIC in ICSR
Set TRS = 1 in ICCR
Read ICDR
Write BBSY = 0
and SCP = 0 in ICSR
End
1
2
3
4
5
6
7
8
9
10
Yes
No
300
1. Select receive mode.
2. Set acknowledgement data.
3. Start receiving. The first read is a dummy read.
4. Wait for 1 byte to be received.
5. Set acknowledgement data for the last receive.
6. Start the last receive.
7. Wait for 1 byte to be received.
8. Select transmit mode.
9. Read the last receive data (if ICDR is read
without selecting transmit mode, receive
operations will resume).
10. Generate a stop condition.
Figure 13-14 Flowchart for Slave Transmit Mode (Example)
Slave transmit mode
Write transmit data in ICDR
Read IRIC in ICSR
IRIC = 1?
Clear IRIC in ICSR
Read ACKB in ICSR
Write TRS = 0 in ICCR
End
of transmission
(ACKB = 1)?
Yes
No
No
Yes
End
1
2
3
Read ICDR 5
4
301
1. Set transmit data for the second and
subsequent bytes.
2. Wait for 1 byte to be transmitted.
3. Test for end of transfer.
4. Select slave receive mode.
5. Dummy read (to release the SCL line).
Figure 13-15 Flowchart for Slave Receive Mode (Example)
Start
Initialize
Set MST = 0
and TRS = 0 in ICCR
Write ACKB = 0 in ICSR
Read IRIC in ICSR
IRIC = 1? Yes
No
Clear IRIC in ICSR
Read AAS and ADZ in ICSR
AAS = 1
and ADZ = 0?
Read TRS in ICCR
TRS = 0?
No
Yes
No
Yes
Yes
No
Yes
Yes
No
No
1
2
3
4
5
6
7
8
Last receive?
Read ICDR
Read IRIC in ICSR
IRIC = 1?
Clear IRIC in ICSR
Set ACKB = 1 in ICSR
Read ICDR
Read IRIC in ICSR
Clear IRIC in ICSR
IRIC = 1?
Read ICDR
End
General call address processing
* Description omitted
Slave transmit mode
302
1. Select slave receive mode.
2. Wait for the first byte to be received.
3. Start receiving. The first read is a dummy read.
4. Wait for the transfer to end.
5. Set acknowledgement data for the last receive.
6. Start the last receive.
7. Wait for the transfer to end.
8. Read the last receive data.
13.4 Application Notes
• In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition.
• Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
1. Write access to ICDR when ICE = 1 and TRS = 1
2. Read access to ICDR when ICE = 1 and TRS = 0
• The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high-
speed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
the time determined by the input clock of the I2C bus interface, the high period of SCL is
extended. SCL rise time is determined by the pull-up resistance and load capacitance of the
SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and
load capacitance so that the SCL rise time falls below the values given in the table below.
tcyc Time Display
CKDBL IICX Display ø = 4 MHz ø = 5 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz
0 0 2.5tcyc Normal 625 ns 500 ns 312 ns 250 ns 156 ns
mode
High-speed 300 ns 300 ns 300 ns
mode
0 1 7.5tcyc Normal 1000 ns 1000 ns 937 ns 750 ns 468 ns
mode
1 0 High-speed 300 ns 300 ns 300 ns 300 ns 300 ns
mode
1 1 17.5tcyc Normal 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns
mode
High-speed 300 ns 300 ns 300 ns 300 ns 300 ns
mode
303
Section 14 Host Interface
14.1 Overview
The H8/3437 Series has an on-chip host interface (HIF) that provides a dual-channel parallel
interface between the on-chip CPU and a host processor. The host interface is available only when
the HIE bit is set to 1 in SYSCR. This mode is called slave mode, because it is designed for a
master-slave communication system in which the H8/3437-Series chip is slaved to a host processor.
The host interface consists of four 1-byte data registers, two 1-byte status registers, a 1-byte control
register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried out via
five control signals from the host processor (CS1, CS2or ECS2, HA0, IOR, and IOW or EIOW),
four output signals to the host processor (GA20, HIRQ1, HIRQ11, and HIRQ12), and an 8-bit
bidirectional command/data bus (HDB7to HDB0, or XDB7to XDB0). The CS1and CS2(or ECS2)
signals select one of the two interface channels.
Note: If one of the two interface channels will not be used, tie the unused CS pin to VCC. For
example, if interface channel 1 (IDR1, ODR1, STR1) is not used, tie CS1to VCC.
305
14.1.1 Block Diagram
Figure 14-1 is a block diagram of the host interface.
Figure 14-1 Host Interface Block Diagram
(Internal interrupt signals)
IBF2 IBF1
Control
logic
HDB7–HDB0/
XDB7–XDB0
IDR1
ODR1
STR1
IDR2
ODR2
STR2
HICR
Module data bus
Host data bus
Host
interrupt
request
Fast
A20
gate
control
Port 4
Port 8
Internal data bus Bus
interface
CS1
ECS2/CS2
IOR
EIOW/IOW
HA0
HIRQ1
HIRQ11
HIRQ12
GA20
Legend
IDR1:
IDR2:
ODR1:
ODR2:
STR1:
STR2:
HICR:
Input data register 1
Input data register 2
Output data register 1
Output data register 2
Status register 1
Status register 2
Host interface control register
306
14.1.2 Input and Output Pins
Table 14-1 lists the input and output pins of the host interface module.
Table 14-1 H/F Input/Output Pins
Name Abbreviation Port I/O Function
I/O read IOR P83Input Host interface read signal
I/O write*IOW P84Input Host interface write signal
EIOW P91
Chip select 1 CS1P82Input Host interface chip select signal for IDR1,
ODR1, STR1
Chip select 2*CS2P85Input Host interface chip select signal for IDR2,
ECS2P90ODR2, STR2
Command/data HA0P80Input Host interface address select signal
In host read access, this signal selects
the status registers (STR1, STR2) or data
registers (ODR1, ODR2). In host write
access to the data registers (IDR1, IDR2),
this signal indicates whether the host is
writing a command or data.
Data bus HDB7–HDB0P37–P30I/O Host interface data bus (single-chip
mode)
XDB7–XDB0PB7–PB0I/O Host interface data bus (expanded
modes)
Host interrupt 1 HIRQ1P44Output Interrupt output 1 to host
Host interrupt 11 HIRQ11 P43Output Interrupt output 11 to host
Host interrupt 12 HIRQ12 P45Output Interrupt output 12 to host
Gate A20 GA20 P81Output A20 gate control signal output
Note: *Selection between IOW and EIOW, and between CS2and ECS2, is by the STAC bit in
STCR. IOW and CS2are used when STAC is 0. EIOW and ECS2are used when STAC
is 1. In this manual, both are referred to as IOW and CS2.
307
14.1.3 Register Configuration
Table 14-2 lists the host interface registers.
Table 14-2 HIF Registers
R/W Master Address*4
Initial Slave
Name Abbreviation Slave Host Value Address*3CS1CS2HA0
System control SYSCR R/W*1— H'09 H'FFC4 — — —
register
Host interface HICR R/W — H'F8 H'FFF0 — — —
control register
Input data register 1 IDR1 R W — H'FFF4 0 1 0/1*5
Output data register 1 ODR1 R/W R — H'FFF5 0 1 0
Status register 1 STR1 R/(W)*2R H'00 H'FFF6 0 1 1
Input data register 2 IDR2 R W — H'FFFC 1 0 0
Output data register 2 ODR2 R/W R — H'FFFD 1 0 0/1*5
Status register 2 STR2 R/(W)*2R H'00 H'FFFE 1 0 1
Serial/timer control STCR R/W — H'00 H'FFC3 — — —
register
Notes: 1. Bit 3 is a read-only bit.
2. The user-defined bits (bits 7 to 4) are read/write accessible from the slave processor.
3. Address when accessed from the slave processor.
4. Pin inputs used in access from the host processor.
5. The HA0input discriminates between writing of commands and data.
308
14.2 Register Descriptions
14.2.1 System Control Register (SYSCR)
SYSCR is an 8-bit read/write register which controls chip operations. Host interface functions are
enabled or disabled by the HIE bit of SYSCR. See section 3.2, System Control Register, for
information on other SYSCR bits. SYSCR is initialized to H'09 by an external reset or during
standby mode.
Bit 1—Host Interface Enable (HIE): Enables or disables the host interface. When enabled, the
host interface handles host-slave data transfers, operating in slave mode.
Bit 1
HIE Description
0 The host interface is disabled (Initial value)
1 The host interface is enabled (slave mode)
14.2.2 Host Interface Control Register (HICR)
HICR is an 8-bit read/write register which controls host interface interrupts and the fast A20 gate
function. HICR is initialized to H'F8 by a reset or during standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit
Initial value
Slave Read/Write
Host Read/Write
7
—
1
—
—
6
—
1
—
—
5
—
1
—
—
4
—
1
—
—
3
—
1
—
—
0
FGA20E
0
R/W
—
2
IBFIE2
0
R/W
—
1
IBFIE1
0
R/W
—
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
309
Bit 2—Input Buffer Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2 interrupt to
the slave CPU.
Bit 2
IBFIE2 Description
0 IDR2 input buffer full interrupt is disabled (Initial value)
1 IDR2 input buffer full interrupt is enabled
Bit 1— Input Buffer Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1 interrupt to
the slave CPU.
Bit 1
IBFIE1 Description
0 IDR1 input buffer full interrupt is disabled (Initial value)
1 IDR1 input buffer full interrupt is enabled
Bit 0—Fast Gate A20 Enable (FGA20E): Enables or disables the fast A20 gate function. When the
fast A20 gate is disabled, a regular-speed A20 gate signal can be implemented by using software to
manipulate the P81output.
Bit 0
FGA20E Description
0 Disables fast A20 gate function (Initial value)
1 Enables fast A20 gate function
14.2.3 Input Data Register (IDR1)
IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host
processor. When CS1is low, information on the host data bus is written into IDR1 at the rising edge
of IOW. The HA0state is also latched into the C/Dbit in STR1 to indicate whether the written
information is a command or data.
The initial values of IDR1 after a reset or standby are undetermined.
Bit
Initial value
Slave Read/Write
Host Read/Write
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
0
IDR0
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
310
14.2.4 Output Data Register (ODR1)
ODR1 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the
host processor. The ODR1 contents are output on the host data bus when HA0is low, CS1is low,
and IOR is low.
The initial values of ODR1 after a reset or standby are undetermined.
14.2.5 Status Register (STR1)
STR1 is an 8-bit register that indicates status information during host interface processing. Bits 3, 1,
and 0 are read-only bits to both the host and slave processors.
STR1 is initialized to H'00 by a reset and in the standby modes.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D): Receives the HA0input when the host processor writes to IDR1,
and indicates whether IDR1 contains data or a command.
Bit 3
C/DDescription
0 Contents of IDR1 are data (Initial value)
1 Contents of IDR1 are a command
Bit
Initial value
Slave Read/Write
Host Read/Write
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
3
C/D
0
R
R
0
OBF
0
R
R
2
DBU
0
R/W
R
1
IBF
0
R
R
Bit
Initial value
Slave Read/Write
Host Read/Write
7
ODR7
—
R/W
R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
0
ODR0
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
311
Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR1. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR1.
Bit 1
IBF Description
0 This bit is cleared when the slave processor reads IDR1 (Initial value)
1 This bit is set when the host processor writes to IDR1
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to 0
when the host processor reads ODR1.
Bit 0
OBF Description
0 This bit is cleared when the host processor reads ODR1 (Initial value)
1 This bit is set when the slave processor writes to ODR1
Table 14-3 shows the conditions for setting and clearing the STR1 flags.
Table 14-3 Set/Clear Timing for STR1 Flags
Flag Setting Condition Clearing Condition
C/DRising edge of host’s write signal (IOW) Rising edge of host’s write signal (IOW)
when HA0is high when HA0is low
IBF Rising edge of host’s write signal (IOW) Falling edge of slave’s internal read signal
when writing to IDR1 (RD) when reading IDR1
OBF Falling edge of slave’s internal write Rising edge of host’s read signal (IOR)
signal (WR) when writing to ODR1 when reading ODR1
14.2.6 Input Data Register (IDR2)
IDR2 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host
processor. When CS2is low, information on the host data bus is written into IDR2 at the rising edge
of IOW. The HA0state is also latched into the C/Dbit in STR2 to indicate whether the written
information is a command or data.
The initial values of IDR2 after a reset or standby are undetermined.
Bit
Initial value
Slave Read/Write
Host Read/Write
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
0
IDR0
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
312
14.2.7 Output Data Register (ODR2)
ODR2 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the
host processor. The ODR2 contents are output on the host data bus when HA0is low, CS2is low,
and IOR is low.
The initial values of ODR2 after a reset or standby are undetermined.
14.2.8 Status Register (STR2)
STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3, 1,
and 0 are read-only bits to both the host and slave processors.
STR2 is initialized to H'00 by a reset and in the standby modes.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D): Receives the HA0input when the host processor writes to IDR2,
and indicates whether IDR2 contains data or a command.
Bit 3
C/DDescription
0 Contents of IDR2 are data (Initial value)
1 Contents of IDR2 are a command
Bit
Initial value
Slave Read/Write
Host Read/Write
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
3
C/D
0
R
R
0
OBF
0
R
R
2
DBU
0
R/W
R
1
IBF
0
R
R
Bit
Initial value
Slave Read/Write
Host Read/Write
7
ODR7
—
R/W
R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
0
ODR0
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
313
Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR2.
Bit 1
IBF Description
0 This bit is cleared when the slave processor reads IDR2 (Initial value)
1 This bit is set when the host processor writes to IDR2
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to 0
when the host processor reads ODR2.
Bit 0
OBF Description
0 This bit is cleared when the host processor reads ODR2 (Initial value)
1 This bit is set when the slave processor writes to ODR2
Table 14-4 shows the conditions for setting and clearing the STR2 flags.
Table 14-4 Set/Clear Timing for STR2 Flags
Flag Setting Condition Clearing Condition
C/DRising edge of host’s write signal (IOW) Rising edge of host’s write signal (IOW)
when HA0is high when HA0is low
IBF Rising edge of host’s write signal (IOW) Falling edge of slave’s internal read signal
when writing to IDR2 (RD) when reading IDR2
OBF Falling edge of slave’s internal write Rising edge of host’s read signal (IOR)
signal (WR) when writing to ODR2 when reading ODR2
314
14.2.9 Serial/Timer Control Register (STCR)
STCR is an 8-bit readable/writable register that controls the I2C bus interface and host interface,
controls the SCI operating mode, and selects the TCNT clock source in the 8-bit timers. STCR is
initialized to H'00 by a reset.
Bits 7 to 4—I2C Control (IICS, IICD, IICX, IICE): These bits are used to control the I2C bus
interface. For details, see section 13, I2C Bus Interface.
Bit 3—Slave Input Switch (STAC): Controls switching of host interface input pins. Settings of
this bit are valid only when the host interface is enabled (slave mode).
Bit 3
STAC Description
0 In port 8, P85switches over to CS2, and P84to IOW (Initial value)
1 In port 9, P91switches over to EIOW, and P90to ECS2
Bit 2—Multiprocessor Enable (MPE): Controls the operating mode of SCI0 and SCI1. For
details, see section 12, Serial Communication Interface.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): Together with bits CKS2
to CKS0 in TCR, these bits select timer counter clock inputs. For details, see section 9, 8-Bit
Timers.
Bit
Initial value
Read/Write
7
IICS
0
R/W
6
IICD
0
R/W
5
IICX
0
R/W
4
IICE
0
R/W
3
STAC
0
R/W
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
315
14.3 Operation
14.3.1 Host Interface Operation
The host interface is activated by setting the HIE bit (bit 1) to 1 in SYSCR, establishing slave mode.
Activation of the host interface (entry to slave mode) appropriates the related I/O lines in port 3 or B
(data), port 8 or 9 (control) and port 4 (host interrupt requests) for interface use.
For host interface read/write timing diagrams, see section 22.3.8, Host Interface Timing.
14.3.2 Control States
Table 14-5 indicates the slave operations carried out in response to host interface signals from the
host processor.
Table 14-5 Host Interface Operation
CS2CS1IOR IOW HA0Operation
1 0 0 0 0 Prohibited
1 0 0 0 1 Prohibited
1 0 0 1 0 Data read from output data register 1 (ODR1)
1 0 0 1 1 Status read from status register 1 (STR1)
1 0 1 0 0 Data write to input data register 1 (IDR1)
1 0 1 0 1 Command write to input data register 1 (IDR1)
1 0 1 1 0 Idle state
1 0 1 1 1 Idle state
0 1 0 0 0 Prohibited
0 1 0 0 1 Prohibited
0 1 0 1 0 Data read from output data register 2 (ODR2)
0 1 0 1 1 Status read from status register 2 (STR2)
0 1 1 0 0 Data write to input data register 2 (IDR2)
0 1 1 0 1 Command write to input data register 2 (IDR2)
0 1 1 1 0 Idle state
01111Idle state
316
14.3.3 A20 Gate
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086*-family CPU. In slave mode, a regular-speed A20 gate signal can be output
under software control, or a fast A20 gate signal can be output under hardware control. Fast A20 gate
output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0).
Note: * Intel microprocessor.
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1
command followed by data. When the slave processor receives data, it normally uses an interrupt
routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command,
software copies bit 1 of the data and outputs it at the gate A20 pin (P81/GA20).
Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast
A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. The initial output from
this pin will be a logic 1, which is the initial DR value. Afterward, the host processor can
manipulate the output from this pin by sending commands and data. This function is available only
when register IDR1 is accessed using CS1. Slave logic decodes the commands input from the host
processor. When an H'D1 host command is detected, bit 1 of the data following the host command
is output from the GA20 output pin. This operation does not depend on software or interrupts, and is
faster than the regular processing using interrupts. Table 14-6 lists the conditions that set and clear
GA20 (P81). Figure 14-2 describes the GA20 output in flowchart form. Table 14-7 indicates the
GA20 output signal values.
Table 14-6 GA20 (P81) Set/Clear Timing
Pin Name Setting Condition Clearing Condition
GA20 (P81) Rising edge of the host’s write signal Rising edge of the host’s write signal
(IOW) when bit 1 of the written data (IOW) when bit 1 of the written data is
is 1 and the data follows an H'D1 0 and the data follows an H'D1 host
host command command
317
Figure 14-2 GA20 Output
Start
Host write
H'D1 command
received?
Wait for next byte
Host write
Yes
Data byte?
Write bit 1 of data byte
to DR bit of P81/GA20
Yes
No
No
318
Table 14-7 Fast A20 Gate Output Signal
Internal CPU GA20
HA0Data/Command Interrupt Flag (PB1) Remarks
1 H'D1 command 0 Q Turn-on sequence
0 “1” data*101
1 H'FF command 0 Q (1)
1 H'D1 command 0 Q Turn-off sequence
0 “0” data*200
1 H'FF command 0 Q (0)
1 H'D1 command 0 Q Short turn-on sequence
0 “1” data*101
1/0 Command other than H'FF 1 Q (1)
and H'D1
1 H'D1 command 0 Q Short turn-off sequence
0 “0” data*200
1/0 Command other than H'FF 1 Q (0)
and H'D1
1 H'D1 command 0 Q Cancelled sequence
1 Command other than H'D1 1 Q
1 H'D1 command 0 Q Retriggered sequence
1 H'D1 command 0 Q
1 H'D1 command 0 Q Consecutively executed
0 Any data 0 1/0 sequences
1 H'D1 command 0 Q (1/0)
Notes: 1. Arbitrary data with bit 1 set to 1.
2. Arbitrary data with bit 1 cleared to 0.
319
14.4 Interrupts
14.4.1 IBF1, IBF2
The host interface can request two interrupts to the slave CPU: IBF1 and IBF2. They are input
buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is enabled
when the corresponding enable bit is set (table 14-8).
Table 14-8 Input Buffer Full Interrupts
Interrupt Description
IBF1 Requested when IBFIE1 is set to 1 and IDR1 is full
IBF2 Requested when IBFIE2 is set to 1 and IDR2 is full
14.4.2 HIRQ11, HIRQ1, and HIRQ12
In slave mode (when HIE = 1 in SYSCR), three bits in the port 4 data register (P4DR) can be used
as host interrupt request latches.
These three P4DR bits are cleared to 0 by the host processor’s read signal (IOR). If CS1and HA0
are low, when IOR goes low and the host reads ODR1, HIRQ1and HIRQ12 are cleared to 0. If CS2
and HA0are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to 0. To
generate a host interrupt request, normally on-chip software writes 1 to the corresponding bit. In
processing the interrupt, the host’s interrupt-handling routine reads the output data register (ODR1
or ODR2), and this clears the host interrupt latch to 0.
Table 14-9 indicates how these bits are set and cleared. Figure 14-3 shows the processing in
flowchart form.
Table 14-9 Host Interrupt Set/Clear Conditions
Host Interrupt
Signal Setting Condition Clearing Condition
HIRQ11 (P43) Slave CPU reads 0 from P4DR bit 3, Slave CPU writes 0 in P4DR bit 3, or
then writes 1 host reads output data register 2
HIRQ1(P44) Slave CPU reads 0 from P4DR bit 4, Slave CPU writes 0 in P4DR bit 4, or
then writes 1 host reads output data register 1
HIRQ12 (P45) Slave CPU reads 0 from P4DR bit 5, Slave CPU writes 0 in P4DR bit 5, or
then writes 1 host reads output data register 1
320
Figure 14-3 HIRQ Output Flowchart
14.5 Application Note
The host interface provides buffering of asynchronous data from the host and slave processors, but
an interface protocol must be followed to implement necessary functions and avoid data contention.
For example, if the host and slave processors try to access the same input or output data register
simultaneously, the data will be corrupted. Interrupts can be used to design a simple and effective
protocol.
Slave CPU Master CPU
Write to ODR
Write 1 to P4DR
P4DR = 0?
Yes
No
No
Yes
All bytes
transferred?
HIRQ output high
HIRQ output low
Interrupt initiation
ODR read
Hardware operations
Software operations
321
Section 15 A/D Converter
15.1 Overview
The H8/3437 Series includes a 10-bit successive-approximations A/D converter with a selection of
up to eight analog input channels.
15.1.1 Features
A/D converter features are listed below.
• 10-bit resolution
• Eight input channels
• Selectable analog conversion voltage range
The analog voltage conversion range can be programmed by input of an analog reference
voltage at the AVref pin.
• High-speed conversion
Conversion time: minimum 8.4 µs per channel (with 16-MHz system clock)
• Two conversion modes
Single mode: A/D conversion of one channel
Scan mode: continuous conversion on one to four channels
• Four 16-bit data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
• Sample-and-hold function
• A/D conversion can be externally triggered
• A/D interrupt requested at end of conversion
At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
323
15.1.2 Block Diagram
Figure 15-1 shows a block diagram of the A/D converter.
Figure 15-1 A/D Converter Block Diagram
Module data bus
Bus interface
Internal
data bus
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
ADCR
Successive-
approximations register
10-bit D/A
AVCC
AVref
AVSS
Analog
multi-
plexer
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
Sample-and-
hold circuit
Comparator
+
–
Control circuit
ADTRG
øP/8
øP/16
ADI
interrupt
signal
Legend
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
324
15.1.3 Input Pins
Table 15-1 lists the A/D converter’s input pins. The eight analog input pins are divided into two
groups: group 0 (AN0to AN3), and group 1 (AN4to AN7). AVCC and AVSS are the power supply
for the analog circuits in the A/D converter. AVref is the A/D conversion reference voltage.
Table 15-1 A/D Converter Pins
Pin Name Abbreviation I/O Function
Analog power supply pin AVCC Input Analog power supply
Analog ground pin AVSS Input Analog ground and reference voltage
Reference voltage pin AVref Input Analog reference voltage
Analog input pin 0 AN0Input Group 0 analog inputs
Analog input pin 1 AN1Input
Analog input pin 2 AN2Input
Analog input pin 3 AN3Input
Analog input pin 4 AN4Input Group 1 analog inputs
Analog input pin 5 AN5Input
Analog input pin 6 AN6Input
Analog input pin 7 AN7Input
A/D external trigger input pin ADTRG Input External trigger input for starting
A/D conversion
325
15.1.4 Register Configuration
Table 15-2 summarizes the A/D converter’s registers.
Table 15-2 A/D Converter Registers
Name Abbreviation R/W Initial Value Address
A/D data register A (high) ADDRAH R H'00 H'FFE0
A/D data register A (low) ADDRAL R H'00 H'FFE1
A/D data register B (high) ADDRBH R H'00 H'FFE2
A/D data register B (low) ADDRBL R H'00 H'FFE3
A/D data register C (high) ADDRCH R H'00 H'FFE4
A/D data register C (low) ADDRCL R H'00 H'FFE5
A/D data register D (high) ADDRDH R H'00 H'FFE6
A/D data register D (low) ADDRDL R H'00 H'FFE7
A/D control/status register ADCSR R/(W)*H'00 H'FFE8
A/D control register ADCR R/W H'7F H'FFE9
Note: *Only 0 can be written in bit 7, to clear the flag.
326
15.2 Register Descriptions
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bits 15 to 6—A/D Conversion Data (AD9 to AD0): 10-bit data giving an A/D conversion result.
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 0.
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register
corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte of
the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D data
register are reserved bits that always read 0. Table 15-3 indicates the pairings of analog input
channels and A/D data registers.
The CPU can always read the A/D data registers. The upper byte can be read directly, but the lower
byte is read through a temporary register (TEMP). For details see section 15.3, CPU Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 15-3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0 Group 1 A/D Data Register
AN0AN4ADDRA
AN1AN5ADDRB
AN2AN6ADDRC
AN3AN7ADDRD
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
327
15.2.2 A/D Control/Status Register (ADCSR)
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7
ADF Description
0 [Clearing condition] (Initial value)
Cleared by reading ADF while ADF = 1, then writing 0 in ADF
1 [Setting conditions]
1. Single mode: A/D conversion ends
2. Scan mode: A/D conversion ends in all selected channels
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end
of A/D conversion.
Bit 6
ADIE Description
0 A/D end interrupt request (ADI) is disabled (Initial value)
1 A/D end interrupt request (ADI) is enabled
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Bit 5
ADST Description
0 A/D conversion is stopped (Initial value)
1 1. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends
2. Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition to
standby mode
Bit
Initial value
Read/Write
7
ADF
0
R/(W)
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
*
Note: Only 0 can be written, to clear the flag.
*
328
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the
conversion mode.
Bit 4
SCAN Description
0 Single mode (Initial value)
1 Scan mode
Bit 3—Clock Select (CKS): Selects the A/D conversion time. When øP= ø/2, the conversion time
doubles. Clear the ADST bit to 0 before switching the conversion time.
Bit 3
CKS Description
0 Conversion time = 266 states (maximum) (when øP= ø) (Initial value)
1 Conversion time = 134 states (maximum) (when øP= ø)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group Selection Channel Selection Description
CH2 CH1 CH0 Single Mode Scan Mode
000AN
0
(initial value) AN0
01AN
1AN0, AN1
10AN
2AN0to AN2
11AN
3AN0to AN3
100AN
4AN4
01AN
5AN4, AN5
10AN
6AN4to AN6
11AN
7AN4to AN7
329
15.2.3 A/D Control Register (ADCR)
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'7F by a reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bit 7
TRGE Description
0 A/D conversion cannot be externally triggered (Initial value)
1 Enables start of A/D conversion by the external trigger input (ADTRG).
(A/D conversion can be started either by an external trigger or by software.)
Bits 6 to 0—Reserved: These bits cannot be modified, and are always read as 1.
Bit
Initial value
Read/Write
7
TRGE
0
R/W
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
330
15.3 CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 15-2 shows the data flow for access to an A/D data register.
Figure 15-2 A/D Data Register Access Operation (Reading H'AA40)
Upper-byte read
Bus interface Module data bus
CPU
(H'AA)
ADDRnH
(H'AA) ADDRnL
(H'40)
Lower-byte read
Bus interface Module data bus
CPU
(H'40)
ADDRnH
(H'AA) ADDRnL
(H'40)
TEMP
(H'40)
TEMP
(H'40)
(n = A to D)
(n = A to D)
331
15.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
15.4.1 Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST
bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends.
When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 15-3
shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1is selected (CH2 = CH1 = 0, CH0 =
1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time the
ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Execution of the A/D interrupt handling routine ends.
After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated.
332
333
Figure 15-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
ADIE
ADST
ADF
State of channel 0
(AN )
Set
Set Set
Clear Clear
Idle
Idle
Idle
Idle
A/D conversion (1) A/D conversion (2)
Idle
Read conversion result
A/D conversion result (1) Read conversion result
A/D conversion result (2)
Note: Vertical arrows ( ) indicate instructions executed by software.
0
1
2
3
A/D conversion
starts
*
*
*
*
*
*
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1
(AN )
State of channel 2
(AN )
State of channel 3
(AN )
Idle
15.4.2 Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel
in the group (AN0when CH2 = 0, AN4when CH2 = 1). When two or more channels are selected,
after conversion of the first channel ends, conversion of the second channel (AN1or AN5) starts
immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is
cleared to 0. The conversion results are transferred for storage into the A/D data registers
corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first
channel in the group. The ADST bit can be set at the same time as the mode or channel selection is
changed.
Typical operations when three channels in group 0 (AN0to AN2) are selected in scan mode are
described next. Figure 15-4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN0to AN2are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0to AN2) is completed, the ADF flag is set to 1
and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested at this time.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts
again from the first channel (AN0).
334
335
Figure 15-4 Example of A/D Converter Operation (Scan Mode, Channels AN0to AN2Selected)
ADST
ADF
State of channel 0
(AN )
0
1
2
3
Continuous A/D conversion
Set Clear*1
Clear*1
Idle
A/D conversion (1)
Idle
Idle
Idle
A/D conversion (4)
Idle
A/D conversion (2)
Idle A/D conversion (5) Idle
A/D conversion (3)
Idle
Idle
Transfer A/D conversion result (1) A/D conversion result (4)
A/D conversion result (2)
A/D conversion result (3)
1.
2.
A/D conversion time
Notes:
*2
*1
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1
(AN )
State of channel 2
(AN )
State of channel 3
(AN )
Vertical arrows ( ) indicate instructions executed by software.
Data currently being converted is ignored.
15.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tDafter the ADST bit is set to 1, then starts conversion. Figure 15-5 shows the A/D
conversion timing. Table 15-4 indicates the A/D conversion time.
As indicated in figure 15-5, the A/D conversion time includes tDand the input sampling time. The
length of tDvaries depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 15-4.
In scan mode, the values given in table 15-4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when
CKS = 1 (when øP= ø).
Figure 15-5 A/D Conversion Timing
ø
Address bus
Write signal
Input sampling
timing
ADF
(1)
(2)
tDtSPL
tCONV
Legend
(1):
(2):
t :
t :
t :
D
SPL
CONV
ADCSR write cycle
ADCSR address
Synchronization delay
Input sampling time
A/D conversion time
336
Table 15-4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Symbol Min Typ Max Min Typ Max
Synchronization delay tD10 — 17 6 — 9
Input sampling time*tSPL —80— — 40—
A/D conversion time*tCONV 259 — 266 131 — 134
Note: Values in the table are numbers of states.
*Values for when øP= ø. When øP= ø/2, values are double those given in the table.
15.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the
ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 15-6 shows the timing.
Figure 15-6 External Trigger Input Timing
ø
ADTRG
Internal trigger
signal
ADST
A/D conversion
337
15.5 Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
15.6 Application Notes
When using the A/D converter, note the following points:
Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins
ANnshould be in the range AVSS ≤ANn≤AVref. (n = 0 to 7)
AVCC and AVSS Input Voltages: AVSS should be equal to VSS. If the A/D converter is not used,
the values should be AVCC = VCC and AVSS = VSS
AVref Input Range: The analog reference voltage input at the AVref pin should be in the range
AVref ≤AVCC. If the A/D converter is not used, the value should be AVref = VCC.
338
Section 16 D/A Converter
16.1 Overview
The H8/3437 Series has an on-chip D/A converter module with two channels.
16.1.1 Features
Features of the D/A converter module are listed below.
• Eight-bit resolution
• Two-channel output
• Maximum conversion time: 10 µs (with 20-pF load capacitance)
• Output voltage: 0 V to AVref
339
16.1.2 Block Diagram
Figure 16-1 shows a block diagram of the D/A converter.
Figure 16-1 D/A Converter Block Diagram
Bus interface
Module data bus Internal data bus
8-bit D/A
DADR0
DADR1
DACR
Control
circuit
AVref
AVCC
DA0
DA1
AVSS
DACR:
DADR0:
DADR1:
D/A control register
D/A data register 0
D/A data register 1
340
16.1.3 Input and Output Pins
Table 16-1 lists the input and output pins used by the D/A converter module.
Table 16-1 Input and Output Pins of D/A Converter Module
Name Abbreviation I/O Function
Reference voltage pin AVref Input Reference voltage for analog circuits
Analog supply voltage AVCC Input Power supply and reference voltage for
analog circuits
Analog ground AVSS Input Ground and reference voltage for analog
circuits
Analog output 0 DA0Output Analog output channel 0
Analog output 1 DA1Output Analog output channel 1
16.1.4 Register Configuration
Table 16-2 lists the three registers of the D/A converter module.
Table 16-2 D/A Converter Registers
Name Abbreviation R/W Initial Value Address
D/A data register 0 DADR0 R/W H'00 H'FFF8
D/A data register 1 DADR1 R/W H'00 H'FFF9
D/A control register DACR R/W H'1F H'FFFA
341
16.2 Register Descriptions
16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1)
D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable and writable registers that store
data to be converted. When analog output is enabled, the value in the D/A data register is converted
and output continuously at the analog output pin.
The D/A data registers are initialized to H'00 by a reset and in the standby modes.
16.2.2 D/A Control Register (DACR)
DACR is an 8-bit readable and writable register that controls the operation of the D/A converter
module.
DACR is initialized to H'1F by a reset and in the standby modes.
Bit 7—D/A Output Enable 1 (DAOE1): Controls analog output from the D/A converter.
Bit 7
DAOE1 Description
0 Analog output at DA1is disabled.
1 D/A conversion is enabled on channel 1. Analog output is enabled at DA1.
Bit
Initial value
Read/Write
7
DAOE1
0
R/W
6
DAOE0
0
R/W
5
DAE
0
R/W
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
342
Bit 6—D/A Output Enable 0 (DAOE0): Controls analog output from the D/A converter.
Bit 6
DAOE0 Description
0 Analog output at DA0is disabled.
1 D/A conversion is enabled on channel 0. Analog output is enabled at DA0.
Bit 5—D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and
DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0. Channels
0 and 1 are controlled together when DAE = 1.
The decision to output the converted results is always controlled independently by DAOE0 and
DAOE1.
Bit 7 Bit 6 Bit 5
DAOE1 DAOE0 DAE D/A conversion
0 0 — Disabled on channels 0 and 1.
0 1 0 Enabled on channel 0.
Disabled on channel 1.
0 1 1 Enabled on channels 0 and 1.
1 0 0 Disabled on channel 0.
Enabled on channel 1.
1 0 1 Enabled on channels 0 and 1.
1 1 — Enabled on channels 0 and 1.
When the DAE bit is set to 1, analog power supply current drain is the same as during A/D and D/A
conversion, even if the DAOE0 and DAOE1 bits in DACR and the ADST bit in ADSCR are cleared
to 0.
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.
343
16.3 Operation
The D/A converter module has two built-in D/A converter circuits that can operate independently.
D/A conversion is performed continuously whenever enabled by the D/A control register. When a
new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The
converted result is output by setting the DAOE0 or DAOE1 bit to 1.
An example of conversion on channel 0 is given next. Figure 16-2 shows the timing.
(1) Software writes the data to be converted in DADR0.
(2) D/A conversion begins when the DAOE0 bit in DACR is set to 1. After a conversion delay,
analog output appears at the DA0 pin. The output value is AVref ×(DADR0 value)/256.
This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0.
(3) If a new value is written in DADR0, conversion begins immediately. Output of the converted
result begins after the conversion delay time.
(4) When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
Figure 16-2 D/A Conversion (Example)
DADR0
write cycle DACR
write cycle DADR0
write cycle DACR
write cycle
Address
Ø
DADR0
DAOE0
DA0
Conversion data (1) Conversion data (2)
High-impedance state
Conversion result (1) Conversion result (2)
tDCONVtDCONV
t : D/A conversion timeDCONV
344
Section 17 RAM
17.1 Overview
The H8/3437 and H8/3436 have 2 kbytes of on-chip static RAM. The H8/3434 has 1 kbyte. The
RAM is connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM
are performed in two states, enabling rapid data transfer and instruction execution.
The on-chip RAM is assigned to addresses H'F780 to H'FF7F in the address space of the H8/3437
and H8/3436, and addresses H'FB80 to H'FF7F in the address space of the H8/3434. The RAME bit
in the system control register (SYSCR) can enable or disable the on-chip RAM.
17.1.1 Block Diagram
Figure 17-1 is a block diagram of the on-chip RAM.
Figure 17-1 Block Diagram of On-Chip RAM (H8/3437)
H'FF7E
Internal data bus (upper 8 bits)
H'FF7F
H'F782
H'F780
H'F783
H'F781
Even address Odd address
On-chip RAM
Internal data bus (lower 8 bits)
345
17.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR)
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. See section 3.2, System
Control Register, for the other SYSCR bits.
Bit 0—RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit is
initialized to 1 on the rising edge of the RES signal. The RAME bit is not initialized in software
standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled.
1 On-chip RAM is enabled. (Initial value)
17.2 Operation
17.2.1 Expanded Modes (Modes 1 and 2)
If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3437 and H8/3436
and addresses H'FB80 to H'FF7F in the H8/3434 are directed to the on-chip RAM. If the RAME bit
is cleared to 0, accesses to these addresses are directed to the external data bus.
17.2.2 Single-Chip Mode (Mode 3)
If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3437 and H8/3436
and addresses H'FB80 to H'FF7F in the H8/3434 are directed to the on-chip RAM.
If the RAME bit is cleared to 0, the on-chip RAM data cannot be accessed. Attempted write access
has no effect. Attempted read access always results in H'FF data being read.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
2
NMIEG
0
R/W
1
HIE
0
R/W
0
RAME
1
R/W
346
Section 18 ROM (Mask ROM version/ZTAT version)
18.1 Overview
The size of the on-chip ROM is 60 kbytes in the H8/3437, 48 kbytes in the H8/3436, and 32 kbytes
in the H8/3434. The on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte data and
word data are accessed in two states, enabling rapid data transfer.
The on-chip ROM is enabled or disabled depending on the inputs at the mode pins (MD1and MD0).
See table 18-1.
Table 18-1 On-Chip ROM Usage in Each MCU Mode
Mode Pins
Mode MD1MD0On-chip ROM
Mode 1 (expanded mode) 0 1 Disabled (external addresses)
Mode 2 (expanded mode) 1 0 Enabled
Mode 3 (single-chip mode) 1 1 Enabled
The PROM versions (H8/3437 ZTAT and H8/3434 ZTAT) and flash-memory version (H8/3434
F-ZTAT ) can be set to PROM mode and programmed with a general-purpose PROM programmer.
In the H8/3437, the accessible ROM addresses are H'0000 to H'EF7F (61,312 bytes) in mode 2, and
H'0000 to H'F77F (63,360 bytes) in mode 3. For details, see section 3, MCU Operating Modes and
Address Space.
347
18.1.1 Block Diagram
Figure 18-1 is a block diagram of the on-chip ROM.
Figure 18-1 Block Diagram of On-Chip ROM (H8/3437 Single-Chip Mode)
H'F77E
Internal data bus (upper 8 bits)
H'F77F
H'0002
H'0000
H'0003
H'0001
Even address Odd address
On-chip ROM
Internal data bus (lower 8 bits)
348
18.2 PROM Mode (H8/3437, H8/3434)
18.2.1 PROM Mode Setup
In PROM mode the PROM versions of the H8/3437 and H8/3434 suspend the usual microcomputer
functions to allow the on-chip PROM to be programmed. The programming method is the same as
for the HN27C101.
To select PROM mode, apply the signal inputs listed in table 18-2.
Table 18-2 Selection of PROM Mode
Pin Input
Mode pin MD1Low
Mode pin MD0Low
STBY pin Low
Pins P63and P64High
18.2.2 Socket Adapter Pin Assignments and Memory Map
The H8/3437 and H8/3434 can be programmed with a general-purpose PROM programmer by
using a socket adapter to change the pin-out to 32 pins. See table 18-3. The same socket adapter can
be used for both the H8/3437 and H8/3434. Figure 18-2 shows the socket adapter pin assignments.
Table 18-3 Socket Adapter
Package Socket Adapter
100-pin QFP HS3437ESHS1H
100-pin TQFP HS3437ESNS1H
The PROM size is 60 kbytes for the H8/3437 and 32 kbytes for the H8/3434. Figures 18-3 and 18-4
show memory maps of the H8/3437 and H8/3434 in PROM mode. H'FF data should be specified for
unused address areas in the on-chip PROM.
When programming with a PROM programmer, limit the program address range to H'0000 to
H'F77F for the H8/3437 and H'0000 to H'7FFF for the H8/3434. Specify H'FF data for addresses
H'F780 and above (H8/3437) or H'8000 and above (H8/3434). If these addresses are programmed
by mistake, it may become impossible to program or verify the PROM data. The same problem may
occur if an attempt is made to program the chip in page programming mode. Note that the PROM
versions are one-time programmable (OTP) microcomputers, packaged in plastic packages, and
cannot be reprogrammed.
349
Figure 18-2 Socket Adapter Pin Assignments
FP-100B,
TFP-100B
1
7
82
83
84
85
86
87
88
89
79
78
77
76
75
74
73
72
67
66
65
64
63
62
61
60
25
24
23
29
32
37
36
4
9
59
6
5
8
46
15
70
71
92
Pin
RES
NMI
P3
P3
P3
P3
P3
P3
P3
P3
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
P9
P9
P9
P6
P6
AV
AVref
VCCB
VCC
VCC
MD
MD
STBY
AV
V
V
V
V
Pin
V
EA
EO
EO
EO
EO
EO
EO
EO
EO
EA
EA
EA
EA
EA
EA
EA
EA
EA
OE
EA
EA
EA
EA
EA
CE
EA
EA
PGM
V
V
HN27C101
(32 pins)
1
26
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
2
3
31
32
16
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
CC
0
1
SS
SS
SS
SS
SS
9
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
10
11
12
13
14
16
15
PP
CC
H8/3437, H8/3434 EPROM Socket
Note: All pins not listed in this figure should be left open.
Legend
V :
EO to EO :
EA to EA :
OE:
CE:
PGM:
PP
07
016
Programming power supply (12.5 V)
Data input/output
Address input
Output enable
Chip enable
Program enable
SS
350
Figure 18-3 H8/3437 Memory Map in PROM Mode
Figure 18-4 H8/3434 Memory Map in PROM Mode
H'7FFF H'7FFF
Undetermined
value output*If this address area is read in PROM
mode, the output data is not guaranteed.
H'1FFFF
Address in PROM modeAddress in MCU mode
H'0000 H'0000
On-chip
PROM
Note: *
H'F77F H'F77F
Undetermined
value output*
If this address area is read in PROM
mode, the output data is not guaranteed.
H'1FFFF
Address in PROM modeAddress in MCU mode
H'0000 H'0000
On-chip
PROM
Note: *
351
18.3 PROM Programming
The write, verify, and other sub-modes of the PROM mode are selected as shown in table 18-4.
Table 18-4 Selection of Sub-Modes in PROM Mode
Sub-Mode CE OE PGM VPP VCC EO7to EO0EA16 to EA0
Write Low High Low VPP VCC Data input Address input
Verify Low Low High VPP VCC Data output Address input
Programming Low Low Low VPP VCC High impedance Address input
inhibited Low High High
High Low Low
High High High
The H8/3437 and H8/3434 PROM have the same standard read/write specifications as the
HN27C101 EPROM. Page programming is not supported, however, so do not select page
programming mode. PROM programmers that provide only page programming cannot be used.
When selecting a PROM programmer, check that it supports a byte-at-a-time high-speed
programming mode. Be sure to set the address range to H'0000 to H'F77F for the H8/3437, and to
H'0000 to H'7FFF for the H8/3434.
352
18.3.1 Programming and Verification
An efficient, high-speed programming procedure can be used to program and verify PROM data.
This procedure programs data quickly without subjecting the chip to voltage stress and without
sacrificing data reliability. It leaves the data H'FF in unused addresses.
Figure 18-5 shows the basic high-speed programming flowchart.
Tables 18-5 and 18-6 list the electrical characteristics of the chip in PROM mode. Figure 18-6
shows a program/verify timing chart.
Figure 18-5 High-Speed Programming Flowchart
Start
Set program/verify mode
VCC = 6.0 V ±0.25 V,
VPP = 12.5 V ±0.3 V
Address = 0
→
Verify OK?
Program tOPW = 0.2n ms
Last address?
Set read mode
VCC = 5.0 V ±0.25 V,
VPP = VCC
Read all
addresses
End
Error
n < 25? Address + 1 address→
No Yes No
Yes
No
No go
Program tPW = 0.2 ms ±5%
n = 0
n + 1 n
Yes
Go
353
Table 18-5 DC Characteristics
(when VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25˚C ±5˚C)
Item Symbol Min Typ Max Unit Test Conditions
Input high EO7– EO0, VIH 2.4 — VCC + 0.3 V
voltage EA16 – EA0,
OE, CE, PGM
Input low EO7– EO0, VIL –0.3 — 0.8 V
voltage EA16 – EA0,
OE, CE, PGM
Output high EO7– EO0VOH 2.4 — — V IOH = –200 µA
voltage
Output low EO7– EO0VOL — — 0.45 V IOL = 1.6 mA
voltage
Input leakage EO7– EO0,|I
LI|——2 µAV
in = 5.25 V/0.5 V
current EA16 – EA0,
OE, CE, PGM
VCC current ICC — — 40 mA
VPP current IPP — — 40 mA
Table 18-6 AC Characteristics
(when VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25˚C ±5˚C)
Item Symbol Min Typ Max Unit Test Conditions
Address setup time tAS 2 — — µs See figure 18-6*
OE setup time tOES 2 ——µs
Data setup time tDS 2 ——µs
Address hold time tAH 0 ——µs
Data hold time tDH 2 ——µs
Data output disable time tDF — — 130 ns
VPP setup time tVPS 2 ——µs
Program pulse width tPW 0.19 0.20 0.21 ms
OE pulse width for tOPW 0.19 — 5.25 ms
overwrite-programming
VCC setup time tVCS 2 ——µs
CE setup time tCES 2 ——µs
Data output delay time tOE 0 — 150 ns
Note: *Input pulse level: 0.8 V to 2.2 V
Input rise/fall time ≤20 ns
Timing reference levels: input—1.0 V, 2.0 V; output—0.8 V, 2.0 V
354
Figure 18-6 PROM Program/Verify Timing
Address
Data
VPP
VCC
CE
PGM
OE
VPP
VCC
VCC
VCC
Write Verify
Input data Output data
tAS
tDS
tVPS
tVCS
tCES
tPW
tOPW
tDH
tOES tOE
tDF
tAH
+ 1
355
18.3.2 Notes on Programming
(1) Program with the specified voltages and timing. The programming voltage (VPP) is 12.5 V.
Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be
particularly careful about the PROM programmer’s overshoot characteristics.
If the PROM programmer is set to HN27C101 specifications, VPP will be 12.5 V.
(2) Before writing data, check that the socket adapter and chip are correctly mounted in the
PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM
programmer, socket adapter, and chip are not correctly aligned.
(3) Don’t touch the socket adapter or chip while writing. Touching either of these can cause
contact faults and write errors.
(4) Page programming is not supported. Do not select page programming mode.
(5) The H8/3437 PROM size is 60 kbytes. The H8/3434 PROM size is 32 kbytes. Set the address
range to H'0000 to H'F77F for the H8/3437, and to H'0000 to H'7FFF for the H8/3434. When
programming, specify H'FF data for unused address areas (H'F780 to H'1FFFF in the H8/3437,
H'8000 to H'1FFFF in the H8/3434).
356
18.3.3 Reliability of Programmed Data
An effective way to assure the data holding characteristics of the programmed chips is to bake them
at 150˚C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 18-7 shows the recommended screening procedure.
Figure 18-7 Recommended Screening Procedure
If a series of write errors occurs while the same PROM programmer is in use, stop programming
and check the PROM programmer and socket adapter for defects.
Please inform Hitachi of any abnormal conditions noted during programming or in screening of
program data after high-temperature baking.
Write and verify program
Read and check program
Mount
Bake with power off
125° to 150°C, 24 to 48Hr
357
Section 19 ROM (Flash memory 32 kbytes version)
19.1 Flash Memory Overview
19.1.1 Flash Memory Operating Principle
Table 19-1 illustrates the principle of operation of the H8/3434F’s on-chip flash memory.
Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws hot
electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a
programmed memory cell is therefore higher than that of an erased cell. Cells are erased by
grounding the gate and applying a high voltage to the source, causing the electrons stored in the
floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like an
EPROM cell, by driving the gate to the high level and detecting the drain current, which depends on
the threshold voltage. Erasing must be done carefully, because if a memory cell is overerased, its
threshold voltage may become negative, causing the cell to operate incorrectly.
Section 19.4.6 shows an optimal erase control flowchart and sample program.
Table 19-1 Principle of Memory Cell Operation
19.1.2 Mode Programming and Flash Memory Address Space
As its on-chip ROM, the H8/3434F has 32 kbytes of flash memory. The flash memory is connected
to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states.
The H8/3434F’s flash memory is assigned to addresses H'0000 to H'7FFF. The mode pins enable
either on-chip flash memory or external memory to be selected for this area. Table 19-2 summarizes
the mode pin settings and usage of the memory area.
Vd
Vg = VPP
Open Vd
Vg
Vs = VPP
Open Open
0 V
VPP
0 V
Vd 0 V
VCC
0 V
0 V
Vd 0 V
VPP
0 V
0 V
Program Erase Read
Memory
cell
Memory
array
359
360
Table 19-2 Mode Pin Settings and Flash Memory Area
Mode Pin Setting
Mode MD1MD0Memory Area Usage
Mode 0 0 0 Illegal setting
Mode 1 0 1 External memory area
Mode 2 1 0 On-chip flash memory area
Mode 3 1 1 On-chip flash memory area
19.1.3 Features
Features of the flash memory are listed below.
• Five flash memory operating modes
The flash memory has five operating modes: program mode, program-verify mode, erase mode,
erase-verify mode, and prewrite-verify mode.
• Block erase designation
Blocks to be erased in the flash memory address space can be selected by bit settings. The
address space includes a large-block area (four blocks with sizes from 4 kbytes to 8 kbytes) and
a small-block area (eight blocks with sizes from 128 bytes to 1 kbyte).
• Program and erase time
Programming one byte of flash memory typically takes 50 µs. Erasing all blocks (32 kbytes)
typically takes 1 s.
• Erase-program cycles
Flash memory contents can be erased and reprogrammed up to 100 times.
• On-board programming modes
These modes can be used to program, erase, and verify flash memory contents. There are two
modes: boot mode and user programming mode.
• Automatic bit-rate alignment
In boot-mode data transfer, the H8/3434F aligns its bit rate automatically to the host bit rate
(maximum 9600 bps).
• Flash memory emulation by RAM
Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates
in real time.
• PROM mode
As an alternative to on-board programming, the flash memory can be programmed and erased
in PROM mode, using a general-purpose PROM programmer. Program, erase, verify, and other
specifications are the same as for HN28F101 standard flash memory.
19.1.4 Block Diagram
Figure 19-1 shows a block diagram of the flash memory.
Figure 19-1 Flash Memory Block Diagram
FLMCR
EBR1
EBR2
H'0000
H'0002
H'0004
H'7FFC
H'7FFE
H'0001
H'0003
H'0005
H'7FFD
H'7FFF
MD1
MD0
Internal data bus (upper)
Internal data bus (lower)
Bus interface and control section Operating
mode
On-chip flash memory
(32 kbytes)
Upper byte
(even address) Lower byte
(odd address)
Legend
FLMCR:
EBR1:
EBR2:
Flash memory control register
Erase block register 1
Erase block register 2
8
8
361
19.1.5 Input/Output Pins
Flash memory is controlled by the pins listed in table 19-3.
Table 19-3 Flash Memory Pins
Pin Name Abbreviation Input/Output Function
Programming power FVPP Power supply Apply 12.0 V
Mode 1 MD1Input H8/3434F operating mode setting
Mode 0 MD0Input H8/3434F operating mode setting
Transmit data TxD1Output SCI1 transmit data output
Receive data RxD1Input SCI1 receive data input
The transmit data and receive data pins are used in boot mode.
19.1.6 Register Configuration
The flash memory is controlled by the registers listed in table 19-4.
Table 19-4 Flash Memory Registers
Name Abbreviation R/W Initial Value Address
Flash memory control register FLMCR R/W*2H'00*2H'FF80
Erase block register 1 EBR1 R/W*2H'F0*2H'FF82
Erase block register 2 EBR2 R/W*2H'00*2H'FF83
Wait-state control register*1WSCR R/W H'08 H'FFC2
Notes: Registers FLMCR, EBR1, and EBR2 are only valid when writing to or erasing flash memory,
and can only be accessed while 12 V is being applied to the FVPP pin.
When 12 V is not applied to the FVPP pin, in mode 2 addresses H'FF80 to H'FF83 are
external address space, and in mode 3 these addresses cannot be modified and always read
H'FF.
1. The wait-state control register controls the insertion of wait states by the wait-state
controller, frequency division of clock signals for the on-chip supporting modules by the
clock pulse generator, and emulation of flash-memory updates by RAM in on-board
programming mode.
2. In modes 2 and 3 (on-chip flash memory enabled), the initial value is H'00 for FLMCR and
EBR2, and H'F0 for EBR1. In mode 1 (on-chip flash memory disabled), these registers
cannot be modified and always read H'FF.
362
19.2 Flash Memory Register Descriptions
19.2.1 Flash Memory Control Register (FLMCR)
FLMCR is an 8-bit register that controls the flash memory operating modes. Transitions to program
mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this
register. FLMCR is initialized to H'00 by a reset, in the standby modes, and when 12 V is not
applied to FVPP. When 12 V is applied to the FVPP pin, a reset or entry to a standby mode initializes
FLMCR to H'80.
Bit 7—Programming Power (VPP): This status flag indicates that 12 V is applied to the FVPP pin.
Refer to section 19.7, Flash Memory Programming and Erasing Precautions (5), for details on use.
Bit 7
VPP Description
0 Cleared when 12 V is not applied to FVPP (Initial value)
1 Set when 12 V is applied to FVPP
Bits 6 to 4—Reserved: Read-only bits, always read as 0.
Bit 3—Erase-Verify Mode (EV):*1 Selects transition to or exit from erase-verify mode.
Bit 3
EV Description
0 Exit from erase-verify mode (Initial value)
1 Transition to erase-verify mode
Bit 2—Program-Verify Mode (PV):*1 Selects transition to or exit from program-verify mode.
Bit 2
PV Description
0 Exit from program-verify mode (Initial value)
1 Transition to program-verify mode
Bit
Initial value*
Read/Write
7
VPP
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
EV
0
R/W*
0
P
0
R/W*
2
PV
0
R/W*
1
E
0
R/W*
Note: * The initial value is H’00 in modes 2 and 3 (on-chip flash memory enabled). In mode 1
(on-chip flash memory disabled), this register cannot be modified and always reads H’FF.
For information on accessing this register, refer to in section 19.7, Flash Memory
Programming and Erasing Precautions (11).
363
Bit 1—Erase Mode (E):*1, *2 Selects transition to or exit from erase mode.
Bit 1
E Description
0 Exit from erase mode (Initial value)
1 Transition to erase mode
Bit 0—Program Mode (P):*1, *2 Selects transition to or exit from program mode.
Bit 0
P Description
0 Exit from program mode (Initial value)
1 Transition to program mode
Notes: 1. Do not set two or more of these bits simultaneously. Do not release or shut off the VCC
or VPP power supply when these bits are set.
2. Set the P or E bit according to the instructions given in section 19.4, Programming and
Erasing Flash Memory.
Set the watchdog timer beforehand to make sure that these bits do not remain set for
longer than the specified times.
For notes on use, see section 19.7, Flash Memory Programming and Erasing
Precautions.
19.2.2 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that designates large flash-memory blocks for programming and erasure.
EBR1 is initialized to H'F0 by a reset, in the standby modes, and when 12 V is not applied to FVPP
pin. When a bit in EBR1 is set to 1, the corresponding block is selected and can be programmed and
erased. Figure 19-2 and table 19-6 show details of a block map.
Bits 7 to 4—Reserved: These bits cannot be modified, and are always read as 1.
Bit
Initial value*
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
LB3
0
R/W*
0
LB0
0
R/W*
2
LB2
0
R/W*
1
LB1
0
R/W*
Note:
*The initial value is H'F0 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip
ROM disabled), this register cannot be modified and always reads H'FF.
For information on accessing this register, refer to in section 19.7, Flash Memory
Programming and Erasing Precautions (11).
364
Bits 3 to 0—Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be
programmed and erased.
Bits 3 to 0
LB3 to LB0 Description
0 Block (LB3 to LB0) is not selected (Initial value)
1 Block (LB3 to LB0) is selected
19.2.3 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that designates small flash-memory blocks for programming and erasure.
EBR2 is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FVPP
pin. When a bit in EBR2 is set to 1, the corresponding block is selected and can be programmed and
erased. Figure 19-2 and table 19-6 show a block map.
Bits 7 to 0—Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be
programmed and erased.
Bits 7 to 0
SB7 to SB0 Description
0 Block (SB7 to SB0) is not selected (Initial value)
1 Block (SB7 to SB0) is selected
Bit
Initial value*
Read/Write
7
SB7
0
R/W*
6
SB6
0
R/W*
5
SB5
0
R/W*
4
SB4
0
R/W*
3
SB3
0
R/W*
0
SB0
0
R/W*
2
SB2
0
R/W*
1
SB1
0
R/W*
Note:
*The initial value is H'00 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip
ROM disabled), this register cannot be modified and always reads H'FF.
For information on accessing this register, refer to in section 19.7, Flash Memory
Programming and Erasing Precautions (11).
365
19.2.4 Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that enables flash-memory updates to be emulated in
RAM. It also controls frequency division of clock signals supplied to the on-chip supporting
modules and insertion of wait states by the wait-state controller.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—RAM Select and RAM0 (RAMS and RAM0): These bits are used to reassign an
area to RAM (see table 19-5). These bits are write-enabled and their initial value is 0. They are
initialized by a reset and in hardware standby mode. They are not initialized in software standby
mode.
If only one of bits 7 and 6 is set, part of the RAM area can be overlapped onto the small-block flash
memory area. In that case, access is to RAM, not flash memory, and all flash memory blocks are
write/erase-protected (emulation protect*1). In this state, the mode cannot be changed to program or
erase mode, even if the P bit or E bit in the flash memory control register (FLMCR) is set (although
verify mode can be selected). Therefore, clear both of bits 7 and 6 before programming or erasing
the flash memory area.
If both of bits 7 and 6 are set, part of the RAM area can be overlapped onto the small-block flash
memory area, but this overlapping begins only when an interrupt signal is input while 12 V is being
applied to the FVPP pin. Up until that point, flash memory is accessed. Use this setting for interrupt
handling while flash memory is being programmed or erased.*2
Table 19-5 RAM Area Reassignment*3
Bit 7 Bit 6
RAMS RAM0 RAM Area ROM Area
0 0 None —
0 1 H'FC80 to H'FCFF H'0080 to H'00FF
1 0 H'FC80 to H'FD7F H'0080 to H'017F
1 1 H'FC00 to H'FC7F H'0000 to H'007F
Bit
Initial value
Read/Write
7
RAMS
0
R/W
6
RAM0
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
366
Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to the on-
chip supporting modules. For details, see section 6, Clock Pulse Generator.
Bit 4—Reserved: This bit is reserved, but it can be written and read. Its initial value is 0.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1, WMS0)
Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0)
These bits control insertion of wait states by the wait-state controller. For details, see section 5,
Wait-State Controller.
Notes: 1. For details on emulation protect, see section 19.4.8, Protect Modes.
2. For details on interrupt handling during programming and erasing of flash memory, see
section 19.4.9, Interrupt Handling during Flash Memory Programming and Erasing.
3. RAM area that overlaps flash memory.
367
Figure 19-2 Erase Block Map
H'0000
H'01FF
H'0200
H'03FF
H'0400
H'07FF
H'0800
H'0BFF
H'0C00
H'0FFF
H'0000
H'0FFF
H'1000
H'1FFF
H'2000
H'3FFF
H'4000
H'5FFF
H'6000
H'7FFF
Small block
area
(4 kbytes)
Large block
area
(28 kbytes)
SB7 to SB0
4 kbytes
LB0
4 kbytes
LB1
8 kbytes
LB2
8 kbytes
LB3
8 kbytes
SB0 128 bytes
SB1 128 bytes
SB2 128 bytes
SB3 128 bytes
SB4
512 bytes
SB5
1 kbyte
SB6
1 kbyte
SB7
1 kbyte
368
Table 19-6 Erase Blocks and Corresponding Bits
Register Bit Block Address Size
EBR1 0 LB0 H'1000 to H'1FFF 4 kbytes
1 LB1 H'2000 to H'3FFF 8 kbytes
2 LB2 H'4000 to H'5FFF 8 kbytes
3 LB3 H'6000 to H'7FFF 8 kbytes
EBR2 0 SB0 H'0000 to H'007F 128 bytes
1 SB1 H'0080 to H'00FF 128 bytes
2 SB2 H'0100 to H'017F 128 bytes
3 SB3 H'0180 to H'01FF 128 bytes
4 SB4 H'0200 to H'03FF 512 bytes
5 SB5 H'0400 to H'07FF 1 kbyte
6 SB6 H'0800 to H'0BFF 1 kbyte
7 SB7 H'0C00 to H'0FFF 1 kbyte
19.3 On-Board Programming Modes
When an on-board programming mode is selected, the on-chip flash memory can be programmed,
erased, and verified. There are two on-board programming modes: boot mode, and user program
mode. These modes are selected by inputs at the mode pins (MD1and MD0) and FVPP pin. Table
19-7 indicates how to select the on-board programming modes. For details on applying voltage VPP,
refer to section 19.7, Flash Memory Programming and Erasing Precautions (5).
Table 19-7 On-Board Programming Mode Selection
Mode Selections FVPP MD1MD0Notes
Boot mode Mode 2 12 V*12 V*0 0: VIL
Mode 3 12 V*11: VIH
User program mode Mode 2 1 0
Mode 3 1 1
Note: *For details on the timing of 12 V application, see notes 6 to 8 in the Notes on Use of Boot
Mode at the end of this section.
In boot mode, the mode control register (MDCR) can be used to monitor the mode (mode 2
or 3) in the same way as in normal mode.
Example: Set the mode pins for mode 2 boot mode (MD1= 12 V, MD0= 0 V).
If the mode select bits of MDCR are now read, they will indicate mode 2 (MDS1 = 1, MDS0
= 0).
369
19.3.1 Boot Mode
To use boot mode, a user program for programming and erasing the flash memory must be provided
in advance on the host machine (which may be a personal computer). Serial communication
interface channel 1 is used in asynchronous mode (see figure 19-3). If the H8/3434F is placed in
boot mode, after it comes out of reset, a built-in boot program is activated. This program starts by
measuring the low period of data transmitted from the host and setting the bit rate register (BRR)
accordingly. The H8/3434F’s built-in serial communication interface (SCI) can then be used to
download the user program from the host machine. The user program is stored in on-chip RAM.
After the program has been stored, execution branches to address H'FBE0 in the on-chip RAM, and
the program stored on RAM is executed to program and erase the flash memory.
Figure 19-3 Boot-Mode System Configuration
HOST
Receive data to be programmed
Transmit verification data
H8/3434F
RxD1
TxD1
SCI
370
371
Boot-Mode Execution Procedure:
Figure 19-4 shows the boot-mode execution procedure.
Figure 19-4 Boot Mode Flowchart
Start
Program H8/3434F pins for boot mode,
and reset
Host transmits H'00 data continuously
at desired bit rate
H8/3434F measures low period
of H'00 data transmitted from host
H8/3434F computes bit rate and
sets bit rate register
After completing bit-rate alignment, H8/3434F
sends one H'00 data byte to host to indicate
that alignment is completed
Host checks that this byte, indicating
completion of bit-rate alignment, is received
normally, then transmits one H'55 byte
After receiving H'55, H8/3434F sends part of
the boot program to RAM
H8/3434F transfers one user program
byte to RAM*2
H8/3434F calculates number of bytes left
to be transferred (N = N – 1)
All bytes transferred?
(N = 0?)
All data = H'FF?
Erase all flash
memory blocks*3
After transferring the user program to RAM,
H8/3434F transmits one H'AA data byte to host
No
Yes
Yes
No
1
2
3
4
5
6
7
9
H8/3434F branches to the RAM boot
area (H'FC00 to H'FF2F), then checks the
data in the user area of flash memory
H8/3434F receives two bytes indicating byte
length (N) of program to be downloaded
to on-chip RAM*1
8
After checking that all data in flash memory is H'FF,
H8/3434F transmits one H'AA data byte to host
H8/3434F branches to H'FBE0 in RAM area and
executes user program downloaded into RAM
10
1. Program the H8/3434F pins for boot mode, and start
the H8/3434F from a reset.
2. Set the host’s data format to 8 bits + 1 stop bit,
select the desired bit rate (2400, 4800, or 9600 bps),
and transmit H'00 data continuously.
3. The H8/3434F repeatedly measures the low period
of the RxD1pin and calculates the host’s
asynchronous-communication bit rate.
4. When SCI bit-rate alignment is completed, the
H8/3434F transmits one H'00 data byte to indicate
completion of alignment.
5. The host should receive the byte transmitted from
the H8/3434F to indicate that bit-rate alignment is
completed, check that this byte is received normally,
then transmit one H'55 byte.
6. After receiving H'55, H8/3434F sends part of the
boot program to H'FB80 to H'FBDF and H'FC00 to
H'FF2F of RAM.
7. After branching to the boot program area (H'FC00 to
H'FF2F) in RAM, the H8/3434F checks whether the
flash memory already contains any programmed
data. If so, all blocks are erased.
8. After the H8/3434F transmits one H'AA data byte,
the host transmits the byte length of the user
program to be transferred to the H8/3434F. The byte
length must be sent as two-byte data, upper byte
first and lower byte second. After that, the host
proceeds to transmit the user program. As
verification, the H8/3434F echoes each byte of the
received byte-length data and user program back to
the host.
9. The H8/3434F stores the received user program in
on-chip RAM in a 910-byte area from H'FBE0 to
H'FF6D.
10. After transmitting one H'AA data byte, the H8/3434F
branches to address H'FBE0 in on-chip RAM and
executes the user program stored in the area from
H'FBE0 to H'FF6D.
Notes: 1. The user can use 910 bytes of RAM. The
number of bytes transferred must not exceed
910 bytes. Be sure to transmit the byte length
in two bytes, upper byte first and lower byte
second. For example, if the byte length of the
program to be transferred is 256 bytes
(H'0100), transmit H'01 as the upper byte,
followed by H'00 as the lower byte.
2. The part of the user program that controls the
flash memory should be coded according to
the flash memory program/erase algorithms
given later.
3. If a memory cell malfunctions and cannot be
erased, the H8/3434F transmits one H'FF
byte to report an erase error, halts erasing,
and halts further operations.
Automatic Alignment of SCI Bit Rate
Figure 19-5 Measurement of Low Period in Data Transmitted from Host
When started in boot mode, the H8/3434F measures the low period in asynchronous SCI data
transmitted from the host (figure 19-5). The data format is eight data bits, one stop bit, and no parity
bit. From the measured low period (9 bits), the H8/3434F computes the host’s bit rate. After
aligning its own bit rate, the H8/3434F sends the host 1 byte of H'00 data to indicate that bit-rate
alignment is completed. The host should check that this alignment-completed indication is received
normally and send one byte of H'55 back to the H8/3434F. If the alignment-completed indication is
not received normally, the H8/3434F should be reset, then restarted in boot mode to measure the
low period again. There may be some alignment error between the host’s and H8/3434F’s bit rates,
depending on the host’s bit rate and the H8/3434F’s system clock frequency. To have the SCI
operate normally, set the host’s bit rate to 2400, 4800, or 9600 bps*1. Table 19-8 lists typical host
bit rates and indicates the clock-frequency ranges over which the H8/3434F can align its bit rate
automatically. Boot mode should be used within these frequency ranges*2.
Table 19-8 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by
H8/3434F
System Clock Frequencies Permitting
Host Bit Rate*1Automatic Bit-Rate Alignment by H8/3434F
9600 bps 8 MHz to 16 MHz
4800 bps 4 MHz to 16 MHz
2400 bps 2 MHz to 16 MHz
Notes: 1. Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be
used.
2. Although the H8/3434F may also perform automatic bit-rate alignment with bit rate and
system clock combinations other than those shown in table 19-8, there will be a slight
difference between the bit rates of the host and the H8/3434F, and subsequent transfer
will not be performed normally. Therefore, only a combination of bit rate and system
clock frequency within one of the ranges shown in table 19-8 can be used for boot mode
execution.
D0 D1 D2 D3 D4 D5 D6 D7
Start
bit Stop
bit
This low period (9 bits) is measured (H'00 data)
High for at
least 1 bit
372
RAM Area Allocation in Boot Mode: In boot mode, the 96 bytes from H'FB80 to H'FBDF and the
18 bytes from H'FF6E to H'FF7F are reserved for use by the boot program, as shown in figure 19-6.
The user program is transferred into the area from H'FBE0 to H'FF6D (910 bytes). The boot
program area can be used after the transition to execution of the user program transferred into RAM.
If a stack area is needed, set it within the user program.
Figure 19-6 RAM Areas in Boot Mode
User program
transfer area
(910 bytes)
Boot program
area* (18 bytes)
Boot program
area*
(96 bytes)
This area cannot be used until the H8/3434F starts to
execute the user program transferred to RAM (until it has
branched to H’FBE0 in RAM). Note that even after the
branch to the user program, the boot program area
(H’FB80 to H’FBDF, H’FF6E to H’FF7F) still contains the
boot program.
Note also that 16 bytes (H’FB80 to H’FB8F) of this area
cannot be used if an interrupt handling routine is executed
within the boot program. For details see section 19.4.9,
Interrupt Handling during Flash Memory Programming and
Erasing.
*
H'FB80
H'FBE0
H'FF6E
Note:
H'FF7F
373
Notes on Use of Boot Mode
1. When the H8/3434F comes out of reset in boot mode, it measures the low period of the input at
the SCI’s RxD1pin. The reset should end with RxD1high. After the reset ends, it takes about
100 states for the H8/3434F to get ready to measure the low period of the RxD1input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF),
all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, e.g. the first time on-board programming is performed, or if the update program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RxD1and TxD1pins should be pulled up on-board.
5. Before branching to the user program (at address H'FBE0 in the RAM area), the H8/3434F
terminates transmit and receive operations by the on-chip SCI (by clearing the RE and TE bits
of the serial control register to 0 in channel 1), but the auto-aligned bit rate remains set in bit
rate register BRR. The transmit data output pin (TxD1) is in the high output state (in port 8, the
bits P84DDR of the port 8 data direction register and P84DR of the port 8 data register are set
to 1).
At this time, the values of general registers in the CPU are undetermined. Thus these registers
should be initialized immediately after branching to the user program. Especially in the case of
the stack pointer, which is used implicitly in subroutine calls, the stack area used by the user
program should be specified.
There are no other changes to the initialized values of other registers.
6. Boot mode can be entered by starting from a reset after 12 V is applied to the MD1and FVPP
pins according to the mode setting conditions listed in table 19-7. Note the following points
when turning the VPP power on.
When reset is released (at the rise from low to high), the H8/3434F checks for 12-V input at the
MD1and FVPP pins. If it detects that these pins are programmed for boot mode, it saves that
status internally. The threshold point of this voltage-level check is in the range from
approximately VCC + 2 V to 11.4 V, so boot mode will be entered even if the applied voltage is
insufficient for programming or erasure (11.4 V to 12.6 V). When the boot program is
executed, the VPP power supply must therefore be stabilized within the range of 11.4 V to
12.6 V before the branch to the RAM area occurs. See figure 19-20.
Make sure that the programming voltage VPP does not exceed 12.6 V during the transition to
boot mode (at the reset release timing) and does not go outside the range of 12 V ± 0.6 V while
in boot mode. Boot mode will not be executed correctly if these limits are exceeded. In
addition, make sure that VPP is not released or shut off while the boot program is executing or
374
the flash memory is being programmed or erased.*1
Boot mode can be released by driving the reset pin low, waiting at least ten system clock
cycles, then releasing the application of 12 V to the MD1and FVPP pins and releasing the reset.
The settings of external pins must not change during operation in boot mode.
During boot mode, if input of 12 V to the MD1pin stops but no reset input occurs at the RES
pin, the boot mode state is maintained within the chip and boot mode continues (but do not stop
applying 12 V to the FVPP pin during boot mode*1).
If a watchdog timer reset occurs during boot mode, this does not release the internal mode state,
but the internal boot program is restarted.
Therefore, to change from boot mode to another mode, the boot-mode state within the chip
must be released by a reset input at the RES pin before the mode transition can take place.
7. If the input level of the MD1pin is changed during a reset (e.g., from 0 V to 5 V then to 12 V
while the input to the RES pin is low), the resultant switch in the microcontroller’s operating
mode will affect the bus control output signals (AS, RD, and WR) and the status of ports that
can be used for address output*2.
Therefore, either set these pins so that they do not output signals during the reset, or make sure
that their output signals do not collide with other signals outside the microcontroller.
8. When applying 12 V to the MD1and FVPP pins, make sure that peak overshoot does not exceed
the rated limit of 13 V.
Also, be sure to connect a decoupling capacitor to the FVPP and MD1pins.
Notes: 1. For details on applying, releasing, and shutting off VPP, see note (5) in section 19.7,
Flash Memory Programming and Erasing Precautions.
2. These ports output low-level address signals if the mode pins are set to mode 1
during the reset. In all other modes, these ports are in the high-impedance state. The
bus control output signals are high if the mode pins are set for mode 1 or 2 during the
reset. In mode 3, they are at high impedance.
375
19.3.2 User Program Mode
When set to user program mode, the H8/3434F can erase and program its flash memory by
executing a user program. On-board updates of the on-chip flash memory can be carried out by
providing on-board circuits for supplying VPP and data, and storing an update program in part of the
program area.
To select user program mode, select a mode that enables the on-chip ROM (mode 2 or 3) and apply
12 V to the FVPP pin, either during a reset, or after the reset has ended (been released) but while
flash memory is not being accessed. In user program mode, the on-chip supporting modules operate
as they normally would in mode 2 or 3, except for the flash memory. However, hardware standby
mode cannot be set while 12 V is applied to the FVPP pin.
The flash memory cannot be read while it is being programmed or erased, so the update program
must either be stored in external memory, or transferred temporarily to the RAM area and executed
in RAM.
376
User Program Mode Execution Procedure (Example)*1: Figure 19-7 shows the execution
procedure for user program mode when the on-board update routine is executed in RAM.
Figure 19-7 User Program Mode Operation (Example)
Notes: 1. Do not apply 12 V to the FVPP pin during normal operation. To prevent flash memory
from being accidentally programmed or erased due to program runaway etc., apply 12 V
to FVPP only when programming or erasing flash memory. Overprogramming or
overerasing due to program runaway can cause memory cells to malfunction. While
12 V is applied, the watchdog timer should be running and enabled to halt runaway
program execution, so that program runaway will not lead to overprogramming or
overerasing. For details on applying, releasing, and shutting off VPP, see section 19.7,
Flash Memory Programming and Erasing Precautions (5).
2. After the update is finished, when input of 12 V to the FVPP pin is released, the flash
memory read setup time (tFRS) must elapse before any program in flash memory is
executed. This is the required setup time from when the FVPP pin reaches the (VCC +
2 V) level after 12 V is released until flash memory can be read.
Set MD1 and MD0 to 10 or 11
(apply VIH to VCC to MD1)
Start from reset
Branch to flash memory on-board
update routine in RAM
FVPP = 12 V
(user program mode)
Execute flash memory
on-board update routine in RAM
(update flash memory)
1
2
3
4
5
Branch to flash memory
on-board update program
Transfer on-board update routine
into RAM
6
7
8
Release FVPP
(exit user program mode)
Branch to application program
in flash memory*2
377
Procedure
The flash memory on-board update program
is written in flash memory ahead of time by
the user.
1. Set MD1and MD0of the H8/3434F to 10
or 11, and start from a reset.
2. Branch to the flash memory on-board
update program in flash memory.
3. Transfer the on-board update routine into
RAM.
4. Branch to the on-board update routine
that was transferred into RAM.
5. Apply 12 V to the FVPP pin, to enter user
program mode.
6. Execute the flash memory on-board
update routine in RAM, to perform an on-
board update of the flash memory.
7. Change the voltage at the FVPP pin from
12 V to VCC, to exit user program mode.
8. After the on-board update of flash
memory ends, execution branches to an
application program in flash memory.
378
19.4 Programming and Erasing Flash Memory
The H8/3434F’s on-chip flash memory is programmed and erased by software, using the CPU. The
flash memory can operate in program mode, erase mode, program-verify mode, erase-verify mode,
or prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV, and EV
bits in the flash memory control register (FLMCR).
The flash memory cannot be read while being programmed or erased. The program that controls the
programming and erasing of the flash memory must be stored and executed in on-chip RAM or in
external memory. A description of each mode is given below, with recommended flowcharts and
sample programs for programming and erasing.
For details on programming and erasing, refer to section 19.7, Flash Memory Programming and
Erasing Precautions.
19.4.1 Program Mode
To write data into the flash memory, follow the programming algorithm shown in figure 19-8. This
programming algorithm can write data without subjecting the device to voltage stress or impairing
the reliability of programmed data.
To program data, first specify the area to be written in flash memory with erase block registers
EBR1 and EBR2, then write the data to the address to be programmed, as in writing to RAM. The
flash memory latches the address and data in an address latch and data latch. Next set the P bit in
FLMCR, selecting program mode. The programming duration is the time during which the P bit is
set. A software timer should be used to provide a programming duration of about 10 to 20 µs. The
value of N, the number of attempts, should be set so that the total programming time does not
exceed 1 ms. Programming for too long a time, due to program runaway for example, can cause
device damage. Before selecting program mode, set up the watchdog timer so as to prevent
overprogramming.
19.4.2 Program-Verify Mode
In program-verify mode, after data has been programmed in program mode, the data is read to
check that it has been programmed correctly.
After the programming time has elapsed, exit programming mode (clear the P bit to 0) and select
program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is
applied to the memory cells at the latched address. If the flash memory is read in this state, the data
at the latched address will be read. After selecting program-verify mode, wait 4 µs or more before
reading, then compare the programmed data with the verify data. If they agree, exit program-verify
mode and program the next address. If they do not agree, select program mode again and repeat the
same program and program-verify sequence. Do not repeat the program and program-verify
sequence more than 50 times* for the same bit.
Note: * Keep the total programming time under 1 ms for each bit.
19.4.3 Programming Flowchart and Sample Program
Flowchart for Programming One Byte
Figure 19-8 Programming Flowchart
Start
n = 1
Enable watchdog timer*2
Select program mode
(P bit = 1 in FLMCR)
Wait (x) µs*4
Clear P bit
Disable watchdog timer
Select program-verify mode
(PV bit = 1 in FLMCR)
Wait (tVS1) µs*4
Verify*3 (read memory) No go
OK
Clear PV bit
End (1-byte data programmed)
End of programming
Clear PV bit
Programming error
n≥ N?*4
n + 1 → n
No
End of verification
Write data to flash memory (flash
memory latches write
address and data)*1
Set erase block register
(set bit of block to be programmed to 1)
Yes
Clear erase block register
(clear bit of programmed block to 0)
379
Notes: 1. Write the data to be
programmed with a byte
transfer instruction.
2. Set the timer overflow interval
to the shortest value (CKS2,
CKS1, CKS0 all cleared to 0).
3. Read the memory data to be
verified with a byte transfer
instruction.
4. x: 10 to 20 µs
tVS1: 4 µs or more
N: 50 (set N so that total
programming time
does not exceed 1 ms)
Sample Program for Programming One Byte: This program uses the following registers.
R0H: Specifies blocks to be erased.
R1H: Stores data to be programmed.
R1L: Stores data to be read.
R3: Stores address to be programmed. Valid addresses are H'0000 to H'7FFF.
R4: Sets program and program-verify timing loop counters, and also stores register setting value.
R5: Sets program timing loop counter.
R6L: Used for program-verify fail count.
Arbitrary data can be programmed at an arbitrary address by setting the address in R3 and the data
in R1H.
The setting of #a and #b values depends on the clock frequency. Set #a and #b values according to
tables 19-9 (1) and (2).
FLMCR: .EQU H’FF80
EBR1: .EQU H’FF82
EBR2: .EQU H’FF83
TCSR: .EQU H’FFA8
.ALIGN 2
PRGM: MOV.B #H’**, R0H ;
MOV.B R0H, @EBR*:8 ; Set EBR*
MOV.B #H’00, R6L ; Program-verify fail counter
MOV.W #H’a, R5 ; Set program loop counter
MOV.B R1H, @R3 ; Dummy write
PRGMS: INC R6L ; Program-verify fail counter + 1 →R6L
MOV.W #H’A578, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set program loop counter
BSET #0, @FLMCR:8 ; Set P bit
LOOP1: SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOP1 ; Wait loop
BCLR #0, @FLMCR:8 ; Clear P bit
MOV.W #H’A500, R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
MOV.B #H’b , R4H ; Set program-verify loop counter
BSET #2, @FLMCR:8 ; Set PV bit
LOOP2: DEC R4H ;
BNE LOOP2 ; Wait loop
MOV.B @R3, R1L ; Read programmed address
CMP.B R1H, R1L ; Compare programmed data with read data
BEQ PVOK ; Program-verify decision
BCLR #2, @FLMCR:8 ; Clear PV bit
380
CMP.B #H’32, R6L ; Program-verify executed 50 times?
BEQ NGEND ; If program-verify executed 50 times, branch to NGEND
BRA PRGMS ; Program again
PVOK: BCLR #2, @FLMCR:8 ; Clear PV bit
MOV.B #H’00, R6L ;
MOV.B R6L, @EBR*:8 ; Clear EBR*
One byte programmed
NGEND: Programming error
19.4.4 Erase Mode
To erase the flash memory, follow the erasing algorithm shown in figure 19-9. This erasing
algorithm can erase data without subjecting the device to voltage stress or impairing the reliability
of programmed data.
To erase flash memory, before starting to erase, first place all memory data in all blocks to be erased
in the programmed state (program all memory data to H'00). If all memory data is not in the
programmed state, follow the sequence described later (figure 19-10) to program the memory data
to zero. Select the flash memory areas to be erased with erase block registers 1 and 2 (EBR1 and
EBR2). Next set the E bit in FLMCR, selecting erase mode. The erase time is the time during which
the E bit is set. To prevent overerasing, use a software timer to divide the erase time into repeated
10 ms intervals, and perform erase operations a maximum of 3000 times so that the total erase time
does not exceed 30 seconds. Overerasing, due to program runaway for example, can give memory
cells a negative threshold voltage and cause them to operate incorrectly. Before selecting erase
mode, set up the watchdog timer so as to prevent overerasing.
19.4.5 Erase-Verify Mode
In erase-verify mode, after data has been erased, it is read to check that it has been erased correctly.
After the erase time has elapsed, exit erase mode (clear the E bit to 0) and select erase-verify mode
(set the EV bit to 1). Before reading data in erase-verify mode, write H'FF dummy data to the
address to be read. This dummy write applies an erase-verify voltage to the memory cells at the
latched address. If the flash memory is read in this state, the data at the latched address will be read.
After the dummy write, wait 2 µs or more before reading. When performing the initial dummy
write, wait 4 µs or more after selecting erase-verify mode. If the read data has been successfully
erased, perform an erase-verify (dummy write, wait 2 µs or more, then read) for the next address. If
the read data has not been erased, select erase mode again and repeat the same erase and erase-
verify sequence through the last address, until all memory data has been erased to 1. Do not repeat
the erase and erase-verify sequence more than 3000 times, however.
381
382
19.4.6 Erasing Flowchart and Sample Program
Flowchart for Erasing One Block
Figure 19-9 Erasing Flowchart
Start
Write 0 data in all addresses
to be erased (prewrite)*1
n = 1
Set erase block register
(set bit of block to be erased to 1)
Enable watchdog timer*2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms*5
Clear E bit
Disable watchdog timer
Set top address in block
as verify address
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tVS1) µs*5
Dummy write to verify address*3
(flash memory latches address)
Verify*4 (read data H'FF?)
Last address?
Address + 1 → address Yes
OK
No go
No
Yes
Clear EV bit
Clear erase block register
(clear bit of erased block to 0)
End of block erase
Clear EV bit
Erase error
n≥ N?*5
Erase-verify ends
Erasing ends
n + 1 → n
No
Wait (tVS2) µs*5
Notes: 1. Program all addresses to be erased
by following the prewrite flowchart.
2. Set the watchdog timer overflow
interval to the value indicated in table
19-10.
3. For the erase-verify dummy write,
write H'FF with a byte transfer
instruction.
4. Read the data to be verified with a
byte transfer instruction. When
erasing two or more blocks, clear the
bits of erased blocks in the erase
block registers, so that only unerased
blocks will be erased again.
5. x: 10 ms
tVS1: 4 µs or more
tVS2: 2 µs or more
N: 3000
Prewrite Flowchart
Figure 19-10 Prewrite Flowchart
End of prewrite
n≥ N?*4
n + 1 → n
No
Start
Set start address*5
Write H'00 to flash memory
(Flash memory latches
write address and write data)*1
Enable watchdog timer*2
Select program mode
( P bit = 1 in FLMCR)
Wait (x) µs*4
Disable watchdog timer
Wait (tVS1) µs*4
Prewrite verify*3
(read data = H'00?) No go
No
Yes
Clear P bit End of programming
Programming error
Address + 1 → address
OK
Yes
Set erase block register
(set bit of block to be programmed to 1)
Clear erase block register
(clear bit of programmed block to 0)
n = 1
Last address?*5
383
Notes: 1. Use a byte transfer instruction.
2. Set the timer overflow interval to
the shortest value (CKS2, CKS1,
CKS0 all cleared to 0).
3. In prewrite-verify mode P, E, PV,
and EV are all cleared to 0 and
12 V is applied to FVPP. Read the
data with a byte transfer instruction.
4. x: 10 to 20 µs
tVS1: 4 µs or more
N: 50 (set N so that total
programming time does not
exceed 1 ms)
5 Start and last addresses shall be
top and last addresses of the block
to be erased.
Sample Block-Erase Program: This program uses the following registers.
R0: Specifies block to be erased, and also stores address used in prewrite and erase-verify.
R1H: Stores data to be read, and also used for dummy write.
R2: Stores last address of block to be erased.
R3: Stores address used in prewrite and erase-verify.
R4: Sets timing loop counters for prewrite, prewrite-verify, erase, and erase-verify, and also
stores register setting value.
R5: Sets prewrite and erase timing loop counters.
R6L: Used for prewrite-verify and erase-verify fail count.
The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a,
#b, #c, #d, and #e values according tables 19-9 (1) and (2), and 19-10. Erase block registers (EBR1
and EBR2) should be set according to sections 19.2.2 and 19.2.3. #BLKSTR and #BLKEND are
the top and last addresses of the block to be erased. Set #BLKSTR and #BLKEND according to
figure 19-2.
384
FLMCR: .EQU H’FF80
EBR1: .EQU H’FF82
EBR2: .EQU H’FF83
TCSR: .EQU H’FFA8
.ALIGN 2
MOV.B #H’**, ROH ;
MOV.B ROH, @EBR*:8 ; Set EBR*
; #BLKSTR is top address of block to be erased.
; #BLKEND is last address of block to be erased.
MOV.W #BLKSTR, R0 ; Top address of block to be erased
MOV.W #BLKEND, R2 ; Last address of block to be erased
ADDS #1, R2 ; Last address of block to be erased + 1 →R2
; Execute prewrite
MOV.W R0, R3 ; Top address of block to be erased
PREWRT: MOV.B #H’00, R6L ; Prewrite-verify fail counter
MOV.W #H’a, R5 ; Set prewrite loop counter
PREWRS: INC R6L ; Prewrite-verify fail counter + 1 →R6L
MOV.B #H’00 R1H ;
MOV.B R1H, @R3 ; Write H’00
MOV.W #H’A578, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set prewrite loop counter
BSET #0, @FLMCR:8 ; Set P bit
LOOPR1: SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOPR1 ; Wait loop
BCLR #0, @FLMCR:8 ; Clear P bit
MOV.W #H’A500, R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
MOV.B #H’c, R4H ; Set prewrite-verify loop counter
LOOPR2: DEC R4H ;
BNE LOOPR2 ; Wait loop
MOV.B @R3, R1H ; Read data = H’00?
BEQ PWVFOK ; If read data = H’00 branch to PWVFOK
CMP.B #H’32, R6L ; Prewrite-verify executed 50 times?
BEQ ABEND1 ; If prewrite-verify executed 50 times, branch to ABEND1
BRA PREWRS ; Prewrite again
ABEND1: Programming error
PWVFOK: ADDS #1, R3 ; Address + 1 →R3
CMP.W R2, R3 ; Last address?
BNE PREWRT ; If not last address, prewrite next address
385
;Execute erase
ERASES: MOV.W #H’0000,R6 ; Erase-verify fail counter
MOV.W #H’d, R5 ; Set erase loop count
ERASE: ADDS #1, R6 ; Erase-verify fail counter + 1 →R6
MOV.W #H’e, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set erase loop counter
BSET #1, @FLMCR:8 ; Set E bit
LOOPE: NOP
NOP
NOP
NOP
SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOPE ; Wait loop
BCLR #1, @FLMCR:8 ; Clear E bit
MOV.W #H’A500,R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
; Execute erase-verify
MOV.W R0, R3 ; Top address of block to be erased
MOV.B #H’b, R4H ; Set erase-verify loop counter
BSET #3, @FLMCR:8 ; Set EV bit
LOOPEV: DEC R4H ;
BNE LOOPEV ; Wait loop
EVR2: MOV.B #H’FF, R1H ;
MOV.B R1H, @R3 ; Dummy write
MOV.B #H’c, R4H ; Set erase-verify loop counter
LOOPDW: DEC R4H ;
BNE LOOPDW ; Wait loop
MOV.B @R3+, R1H ; Read
CMP.B #H’FF, R1H ; Read data = H’FF?
BNE RERASE ; If read data ≠H’FF, branch to RERASE
CMP.W R2, R3 ; Last address of block?
BNE EVR2
BRA OKEND
RERASE: BCLR #3, @FLMCR:8 ; Clear EV bit
SUBS #1, R3 ; Erase-verify address – 1 →R3
BRER: MOV.W #H’0BB8,R4 ;
CMP.W R4, R6 ; Erase-verify executed 3000 times?
BNE ERASE ; If erase-verify not executed 3000 times, erase again
BRA ABEND2 ; If erase-verify executed 3000 times, branch to ABEND2
OKEND: BCLR #3, @FLMCR:8 ; Clear EV bit
MOV.B #H’00, R6L ;
MOV.B R6L, @EBR*:8 ; Clear EBR*
One block erased
ABEND2: Erase error
386
387
Flowchart for Erasing Multiple Blocks
Figure 19-11 Multiple-Block Erase Flowchart
Start
Write 0 data to all addresses to be
erased (prewrite)*1
n = 1
Set erase block registers
(set bits of blocks to be erased to 1)
Enable watchdog timer*2
Select erase mode (E bit = 1 in FLMCR)
Wait (X) ms*5
Clear E bit
Disable watchdog timer
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tVS1) µs*5
Set top address of block as
verify address
Dummy write to verify address*3
(flash memory latches address)
Erase-verify
next block
Verify*4
(read data H'FF?)
Last address
in block?
Address + 1 → address
Clear EBR bit of erased block
All erased blocks
verified?
Clear EV bit
All blocks erased?
(EBR1 = EBR2 = 0?)
End of erase
n≥ N?*5
Erase error n + 1 → n
No
Yes
No
No
Yes
No
Yes
No go
OK
Erasing
ends
All erased blocks
verified?
Erase-verify next block
Yes
No
Yes
Wait (tVS2) µs*5
Notes: 1. Program all addresses to be
erased by following the prewrite
flowchart.
2. Set the watchdog timer overflow
interval to the value indicated in
table 19-10.
3. For the erase-verify dummy write,
write H'FF with a byte transfer
instruction.
4. Read the data to be verified with a
byte transfer instruction. When
erasing two or more blocks, clear
the bits of erased blocks in the
erase block register, so that only
unerased blocks will be erased
again.
5. X: 10 ms
tVS1: 4 µs or more
tVS2: 2 µs or more
N: 3000
Sample Multiple-Block Erase Program: This program uses the following registers.
R0: Specifies blocks to be erased (set as explained below), and also stores address used in
prewrite and erase-verify.
R1H: Used to test bits 8 to 11 of R0 stores register read data, and also used for dummy write.
R1L: Used to test bits 0 to 11 of R0.
R2: Specifies address where address used in prewrite and erase-verify is stored.
R3: Stores address used in prewrite and erase-verify.
R4: Stores last address of block to be erased.
R5: Sets prewrite and erase timing loop counters.
R6L: Used for prewrite-verify and erase-verify fail count.
Arbitrary blocks can be erased by setting bits in R0. Write R0 with a word transfer instruction.
A bit map of R0 and a sample setting for erasing specific blocks are shown next.
Example: to erase blocks LB2, SB7, and SB0
R0 is set as follows:
MOV.W #H’0481,R0
MOV.W R0, @EBR1
The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a,
#b, #c, #d, and #e values according to tables 19-9 (1), (2), and 19-10.
— — — — LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit
R0
Corresponds to EBR1 Corresponds to EBR2
Setting 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1
— — — — LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit
R0
Corresponds to EBR1 Corresponds to EBR2
Note: Clear bits 15, 14, 13, and 12 to 0.
388
Notes: 1. In this sample program, the stack pointer (SP) is set at address FF80. As the stack area,
on-chip RAM addresses FF7E and FF7F are used. Therefore, when executing this
sample program, addresses FF7E and FF7F should not be used. In addition, the on-chip
RAM should not be disabled.
2. In this sample program, the program written in a ROM area (including external space)
is transferred into the RAM area and executed in the RAM to which the program is
transferred. #RAMSTR in the program is the starting destination address in RAM to
which the program is transferred. #RAMSTR must be set to an even number.
3. When executing this sample program in the on-chip ROM area or external space,
#RAMSTR should be set to #START.
FLMCR: .RQU H’FF80
EBR1: .EQU H’FF82
EBR2: .EQU H’FF83
TCSR: .EQU H’FFA8
STACK: .EQU H’FF80
.ALIGN 2
START: MOV.W #STACK, SP ; Set stack pointer
; Set the bits in R0 following the description on the previous page. This program is a sample program to erase
; all blocks. MOV.W #H’0FFF, R0 ; Select blocks to be erased (R0: EBR1/EBR2)
MOV.W R0, @EBR1 ; Set EBR1/EBR2
; #RAMSTR is starting destination address to which program is transferred in RAM.
; Set #RAMSTR to even number.
MOV.W #RAMSTR, R2 ; Starting transfer destination address (RAM)
MOV.W #ERVADR, R3 ;
ADD.W R3, R2 ; #RAMSTR + #ERVADR →R2
MOV.W #START, R3 ;
SUB.W R3, R2 ; Address of data area used in RAM
MOV.B #H’00, R1L : Used to test R1L bit in R0
PRETST: CMP.B #H’0C, R1L ; R1L = H’0C?
BEQ ERASES ; If finished checking all R0 bits, branch to ERASES
CMP.B #H’08, R1L ;
BMI EBR2PW ; Test EBR1 if R1L ≥8, or EBR2 if R1L < 8
MOV.B R1L, R1H ;
SUBX #H’08, R1H ; R1L – 8 →R1H
BTST R1H, R0H ; Test R1H bit in EBR1 (R0H)
BNE PREWRT ; If R1H bit in EBR1 (R0H) is 1, branch to PREWRT
BRA PWADD1 ; If R1H bit in EBR1 (R0H) is 0, branch to PWADD1
EBR2PW: BTST R1L, R0L ; Test R1L bit in EBR2 (R0L)
BNE PREWRT ; If R1L bit in EBR2 (R0H) is 1, branch to PREWRT
PWADD1: INC R1L ; R1L + 1 →R1L
MOV.W @R2+, R3 ; Dummy-increment R2
BRA PRETST ;
; Execute prewrite
389
PREWRT: MOV.W @R2+, R3 ; Prewrite starting address
PREW: MOV.B #H’00, R6L ; Prewrite-verify fail counter
MOV.W #H’a, R5 ; Prewrite-verify loop counter
PREWRS: INC R6L ; Prewrite-verify fail counter + 1 →R6L
MOV.B #H’00 R1H ;
MOV.B R1H, @R3 ; Write H’00
MOV.W #H’A578, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set prewrite loop counter
BSET #0, @FLMCR:8 ; Set P bit
LOOPR1: SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOPR1 ; Wait loop
BCLR #0, @FLMCR:8 ; Clear P bit
MOV.W #H’A500, R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
MOV.B #H’c, R4H ; Set prewrite-verify loop counter
LOOPR2: DEC R4H ;
BNE LOOPR2 ; Wait loop
MOV.B @R3, R1H ; Read data = H’00?
BEQ PWVFOK ; If read data = H’00 branch to PWVFOK
CMP.B #H’32, R6L ; Prewrite-verify executed 50 times?
BEQ ABEND1 ; If prewrite-verify executed 50 times, branch to ABEND1
BRA PREWRS ; Prewrite again
ABEND1: Programming error
PWVFOK: ADDS #1, R3 ; Address + 1 →R3
MOV.W @R2, R4 ; Top address of next block
CMP.W R4, R3 ; Last address?
BNE PREW ; If not last address, prewrite next address
PWADD2: INC R1L ; Used to test R1L+1 bit in R0
BRA PRETST ; Branch to PRETST
; Execute erase
ERASES: MOV.W #H’0000, R6 ; Erase-verify fail counter
MOV.W #H’d, R5 ; Set erase loop count
ERASE: ADDS #1, R6 ; Erase-verify fail counter + 1 →R6
MOV.W #H’e, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set erase loop counter
BSET #1, @FLMCR:8 ; Set E bit
LOOPE: NOP
NOP
NOP
NOP
SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOPE ; Wait loop
BCLR #1, @FLMCR:8 ; Clear E bit
390
391
MOV.W #H’A500, R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
; Execute erase-verify
EVR: MOV.W #RAMSTR, R2 ; Starting transfer destination address (RAM)
MOV.W #ERVADR, R3 ;
ADD.W R3, R2 ; #RAMSTR + #ERVADR →R2
MOV.W #START, R3 ;
SUB.W R3, R2 ; Address of data area used in RAM
MOV.B #H’00, R1L ; Used to test R1L bit in R0
MOV.B #H’b, R4H ; Set erase-verify loop counter
BSET #3, @FLMCR:8 ; Set EV bit
LOOPEV: DEC R4H ;
BNE LOOPEV ; Wait loop
EBRTST: CMP.B #H’0C, R1L ; R1L = H’0C?
BEQ HANTEI ; If finished checking all R0 bits, branch to HANTEI
CMP.B #H’08, R1L ;
BMI EBR2EV ; Test EBR1 if R1L ≥8, or EBR2 if R1L < 8
MOV.B R1L, R1H ;
SUBX #H’08, R1H ; R1L – 8 →R1H
BTST R1H, R0H ; Test R1H bit in EBR1 (R0H)
BNE ERSEVF ; If R1H bit in EBR1 (R0H) is 1, branch to ERSEVF
BRA ADD01 ; If R1H bit in EBR1 (R0H) is 0, branch to ADD01
EBR2EV: BTST R1L, R0L ; Test R1L bit in EBR2 (R0L)
BNE ERSEVF ; If R1L bit in EBR2 (R0H) is 1, branch to ERSEVF
ADD01: INC R1L ; R1L + 1 →R1L
MOV.W @R2+, R3 ; Dummy-increment R2
BRA EBRTST ;
ERASE1: BRA ERASE ; Branch to ERASE via Erase 1
ERSEVF: MOV.W @R2+, R3 ; Top address of block to be erase-verified
EVR2: MOV.B #H’FF, R1H ;
MOV.B R1H, @R3 ; Dummy write
MOV.B #H’c, R4H ; Set erase-verify loop counter
LOOPEP: DEC R4H ;
BNE LOOPEP ; Wait loop
MOV.B @R3+, R1H ; Read
CMP.B #H’FF, R1H ; Read data = H’FF?
BNE BLKAD ; If read data ≠H’FF branch to BLKAD
MOV.W @R2, R4 ; Top address of next block
CMP.W R4, R3 ; Last address of block?
BNE EVR2
CMP.B #H’08, R1L ;
BMI SBCLR ; Test EBR1 if R1L ≥8, or EBR2 if R1L < 8
MOV.B R1L, R1H ;
SUBX #H’08, R1H ; R1L – 8 →R1H
BCLR R1H, R0H ; Clear R1H bit in EBR1 (R0H)
BRA BLKAD ;
SBCLR: BCLR R1L, R0L ; Clear R1L bit in EBR2 (R0L)
BLKAD: INC R1L ; R1L + 1 → R1L
BRA EBRTST ;
HANTEI: BCLR #3, @FLMCR:8 ; Clear EV bit
MOV.W R0, @EBR1 ;
BEQ EOWARI ; If EBR1/EBR2 is all 0, erasing ended normally
BRER: MOV.W #H’0BB8, R4 ;
CMP.W R4, R6 ; Erase-verify executed 3000 times?
BNE ERASE1 ; If erase-verify not executed 3000 times, erase again
BRA ABEND2 ; If erase-verify executed 3000 times, branch to ABEND2
;———< Block address table used in erase-verify> ———
.ALIGN 2
ERVADR: .DATA.W H’0000 ; SB0
.DATA.W H’0080 ; SB1
.DATA.W H’0100 ; SB2
.DATA.W H’0180 ; SB3
.DATA.W H’0200 ; SB4
.DATA.W H’0400 ; SB5
.DATA.W H’0800 ; SB6
.DATA.W H’0C00 ; SB7
.DATA.W H’1000 ; LB0
.DATA.W H’2000 ; LB1
.DATA.W H’4000 ; LB2
.DATA.W H’6000 ; LB3
.DATA.W H’8000 ; FLASH END
EOWARI: Erase end
ABEND2: Erase error
392
Loop Counter Values in Programs and Watchdog Timer Overflow Interval Settings:
The setting of #a, #b, #c, #d, and #e values in the programs depends on the clock frequency.
Tables 19-9 (1) and (2) indicate sample loop counter settings for typical clock frequencies.
However, #e is set according to table 19-10.
As a software loop is used, calculated values including percent errors may not be the same as actual
values. Therefore, the values are set so that the total programming time and total erase time do not
exceed 1 ms and 30 s, respectively.
The maximum number of writes in the program, N, is set to 50.
Programming and erasing in accordance with the flowcharts is achieved by setting #a, #b, #c, and
#d in the programs as shown in tables 19-9 (1) and (2). #e should be set as shown in table 19-10.
Wait state insertion is inhibited in these programs. If wait states are to be used, the setting should be
made after the program ends. The setting value for the watchdog timer (WDT) overflow time is
calculated based on the number of instructions between starting and stopping of the WDT, including
the write time and erase time. Therefore, no other instructions should be added between starting
and stopping of the WDT in this program example.
Table 19-9 (1) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with
Program Running in the On-Chip Memory (RAM)
Clock Frequency
f = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz
Time Counter Counter Counter Counter
Variable Setting Setting Value Setting Value Setting Value Setting Value
a(f) Programming time 20 µs H’0028 H’0019 H’0014 H’0005
b(f) tvs1 4 µs H’0B H’07 H’06 H’02
c(f) tvs2 2 µ s H’06 H’04 H’03 H’01
d(f) Erase time 10 ms H’2710 H’186A H’1388 H’04E2
393
394
Table 19-9 (2) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with
Program Running in the External Device
Clock Frequency
f = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz
Time Counter Counter Counter Counter
Variable Setting Setting Value Setting Value Setting Value Setting Value
a(f) Programming time 20 µs H’000D H’0008 H’0006 H’0001
b(f) tvs1 4 µs H’04 H’03 H’02 H’01
c(f) tvs2 2 µs H’02 H’02 H’01 H’01
d(f) Erase time 10 ms H’0D05 H’0823 H’0682 H’01A0
Formula: When using a clock frequency not shown in tables 19-9 (1) and (2), follow the formula
below. The calculation is based on a clock frequency of 10 MHz.
After calculating a(f) and d(f) in the decimal system, omit the first decimal figures, and convert them
to the hexadecimal system, so that a(f) and d(f) are set to 20 µs or less and 10 ms or less, respectively.
After calculating b(f) and c(f) in the decimal system, raise the first decimal figures, and convert them
to the hexadecimal system, so that b(f) and c(f) are set to 4 µs or more and 2 µs or more, respectively.
Clock Frequency f [MHz]
a (f) to d (f) = ×a (f = 10) to d (f = 10)
10
Examples for a program running in on-chip memory (RAM) at a clock frequency of 12 MHz:
12
a (f) = ×25 = 30 ≈30 = H'001E
10
12
b (f) = ×7 = 8.4 ≈9 = H'09
10
12
c (f) = ×4 = 4.8 ≈5 = H'05
10
12
d (f) = ×6250 = 7500 ≈7500 = H'1D4C
10
Table 19-10 Watchdog Timer Overflow Interval Settings
(#e Setting Value According to Clock Frequency)
Variable
Clock Frequency [MHz] e (f)
10 MHz ≤frequency ≤16 MHz H'A57F
2 MHz ≤frequency < 10 MHz H'A57E
395
19.4.7 Prewrite Verify Mode
Prewrite-verify mode is a verify mode used when programming all bits to equalize their threshold
voltages before erasing them.
Program all flash memory to H'00 by writing H'00 using the prewrite algorithm shown in figure
19-10. H'00 should also be written when using RAM for flash memory emulation (when prewriting
a RAM area). (This also applies when using RAM to emulate flash memory erasing with an
emulator or other support tool.) After the necessary programming time has elapsed, exit program
mode (by clearing the P bit to 0) and select prewrite-verify mode (leave the P, E, PV, and EV bits
all cleared to 0). In prewrite-verify mode, a prewrite-verify voltage is applied to the memory cells at
the read address. If the flash memory is read in this state, the data at the read address will be read.
After selecting prewrite-verify mode, wait 4 µs or more before reading.
Note: For a sample prewriting program, see the prewrite subroutine in the sample erasing program.
19.4.8 Protect Modes
Flash memory can be protected from programming and erasing by software or hardware methods.
These two protection modes are described below.
Software Protection: Prevents transitions to program mode and erase mode even if the P or E bit is
set in the flash memory control register (FLMCR). Details are as follows.
Function
Protection Description Program Erase Verify*1
Block Individual blocks can be protected from erasing Disabled Disabled Enabled
protect and programming by the erase block registers
(EBR1 and EBR2). If H'F0 is set in EBR1 and
H'00 in EBR2, all blocks are protected from
erasing and programming.
Emulation When the RAMS or RAM0 bit, but not both, is Disabled Disabled*3Enabled
protect*2set in the wait-state control register (WSCR),
all blocks are protected from programming and
erasing.
Notes: 1. Three modes: program-verify, erase-verify, and prewrite-verify.
2. Except in RAM areas overlapped onto flash memory.
3. All blocks are erase-disabled. It is not possible to specify individual blocks.
396
Hardware Protection: Suspends or disables the programming and erasing of flash memory, and
resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2).
Details of hardware protection are as follows.
Function
Protection Description Program Erase Verify*1
Programing When 12 V is not applied to the FVPP pin, Disabled Disabled*2Disabled
voltage (VPP) FLMCR, EBR1, and EBR2 are initialized,
protect disabling programming and erasing. To obtain
this protection, VPP should not exceed VCC.*3
Reset and When a reset occurs (including a watchdog Disabled Disabled*2Disabled
standby timer reset) or standby mode is entered,
protect FLMCR, EBR1, and EBR2 are initialized,
disabling programming and erasing. Note that
RES input does not ensure a reset unless the
RES pin is held low for at least 20 ms at
power-up (to enable the oscillator to settle),
or at least ten system clock cycles (10ø) during
operation.
Interrupt To prevent damage to the flash memory, if Disabled Disabled*2Enabled
protect interrupt input occurs while flash memory is
being programmed or erased, programming or
erasing is aborted immediately. The settings in
FLMCR, EBR1, and EBR2 are retained. This type
of protection can be cleared only by a reset.
Notes: 1. Three modes: program-verify, erase-verify, and prewrite-verify.
2. All blocks are erase-disabled. It is not possible to specify individual blocks.
3. For details, see section 19.7, Flash Memory Programming and Erasing Precautions.
19.4.9 Interrupt Handling during Flash Memory Programming and Erasing
If an interrupt occurs*1 while flash memory is being programmed or erased (while the P or E bit of
FLMCR is set), the following operating states can occur.
• If an interrupt is generated during programming or erasing, programming or erasing is aborted to
protect the flash memory. Since memory cell values after a forced interrupt are indeterminate,
the system will not operate correctly after such an interrupt.
• Program runaway may result because the vector table could not be read correctly in interrupt
exception handling during programming or erasure*2.
For NMI interrupts while flash memory is being programmed or erased, these malfunction and
runaway problems can be prevented by using the RAM overlap function with the settings described
below.
1. Do not store the NMI interrupt-handling routine*3 in the flash memory area (H'0000 to
H'7FFF). Store it elsewhere (in RAM, for example).
2. Set the NMI interrupt vector in address H'FC06 in RAM (corresponding to H'0006 in flash
memory).
3. After the above settings, set both the RAMS and RAM0 bits to 1 in WSCR.*4
Due to the setting of step 3, if an interrupt signal is input while 12 V is applied to the FVPP pin, the
RAM overlap function is enabled and part of the RAM (H'FC00 to H'FC7F) is overlapped onto the
small-block area of flash memory (H'0000 to H'007F). As a result, when an interrupt is input, the
vector is read from RAM, not flash memory, so the interrupt is handled normally even if flash
memory is being programmed or erased. This can prevent malfunction and runaway.
Notes: 1. When the interrupt mask bit (I) of the condition control register (CCR) is set to 1, all
interrupts except NMI are masked. For details see (2) in section 2.2.2, Control
Registers.
2. The vector table might not be read correctly for one of the following reasons:
• If flash memory is read while it is being programmed or erased (while the P or E bit
of FLMCR is set), the correct value cannot be read.
• If no value has been written for the NMI entry in the vector table yet, NMI exception
handling will not be executed correctly.
3. This routine should be programmed so as to prevent microcontroller runaway.
4. For details on WSCR settings, see section 19.2.4, Wait-State Control Register.
Notes on Interrupt Handling in Boot Mode
In boot mode, the settings described above concerning NMI interrupts are carried out, and NMI
interrupt handling (but not other interrupt handling) is enabled while the boot program is executing.
Note the following points concerning the user program.
• If interrupt handling is required
— Load the NMI vector (H'FB80) into address H'FC06 in RAM (the 38th byte of the
transferred user program should be H'FB80).
— The interrupt handling routine used by the boot program is stored in addresses H'FB80 to
H'FB8F in RAM. Make sure that the user program does not overwrite this area.
• If interrupt handling is not required
Since the RAMS and RAM0 bits remain set to 1 in WSCR, make sure that the user program
disables the RAM overlap by clearing the RAMS and RAM0 bits both to 0.
397
19.5 Flash Memory Emulation by RAM
Erasing and programming flash memory takes time, which can make it difficult to tune parameters
and other data in real time. If necessary, real-time updates of flash memory can be emulated by
overlapping the small-block flash-memory area with part of the RAM (H'FC00 to H'FD7F). This
RAM reassignment is performed using bits 7 and 6 of the wait-state control register (WSCR). See
figure 19-12.
After a flash memory area has been overlapped by RAM, the RAM area can be accessed from two
address areas: the overlapped flash memory area, and the original RAM area (H'FC00 to H'FD7F).
Table 19-11 indicates how to reassign RAM.
Wait-State Control Register (WSCR)*2
Table 19-11 RAM Area Selection
Bit 7 Bit 6
RAMS RAM0 RAM Area ROM Area
0 0 None —
0 1 H'FC80 to H'FCFF H'0080 to H'00FF
1 0 H'FC80 to H'FD7F H'0080 to H'017F
1 1 H'FC00 to H'FC7F H'0000 to H'007F
Bit
Initial value*1
Read/Write
7
RAMS
0
R/W
6
RAM0
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
Notes: 1.
2.
WSCR is initialized by a reset and in hardware standby mode. It is not initialized in
software standby mode.
For details of WSCR settings, see section 19.2.4, Wait-State Control Register (WSCR).
398
Example of Emulation of Real-Time Flash-Memory Update
Figure 19-12 Example of RAM Overlap
H'007F
H'0080
H'00FF
H'0100
H'0000
H'7FFF
H'FB80
H'FC80
H'FCFF
H'FF7F
Small-block
area (SB1)
Flash memory
address space
Overlapped
RAM
Overlapped RAM
On-chip
RAM area
399
Procedure
1. Overlap part of RAM (H'FC80 to H'FCFF) onto the area requiring real-time update (SB1).
(Set WSCR bits 7 and 6 to 01.)
2. Perform real-time updates in the overlapping RAM.
3. After finalization of the update data, clear the RAM overlap (by clearing the RAMS and
RAM0 bits).
4. Read the data written in RAM addresses H'FC80 to H'FCFF out externally, then program
the flash memory area, using this data as part of the program data.
Notes on Use of RAM Emulation Function
• Notes on Applying, Releasing, and Shutting Off the Programming Voltage (VPP)
Care is necessary to avoid errors in programming and erasing when applying, releasing, and
shutting off VPP, just as in the on-board programming modes. In particular, even if the
emulation function is being used, make sure that the watchdog timer is set when the P or E bit of
the flash memory control register (FLMCR) has been set, to prevent errors in programming and
erasing due to program runaway while VPP is applied.
For details see section 19.7, Flash Memory Programming and Erasing Precautions (5).
400
19.6 Flash Memory PROM Mode (H8/3434F)
19.6.1 PROM Mode Setting
The on-chip flash memory of the H8/3434F can be programmed and erased not only in the on-board
programming modes but also in PROM mode, using a general-purpose PROM programmer.
19.6.2 Socket Adapter and Memory Map
Programs can be written and verified by attaching a special 100-pin/32-pin socket adapter to the
PROM programmer. Table 19-12 gives ordering information for the socket adapter. Figure 19-13
shows a memory map in PROM mode. Figure 19-14 shows the socket adapter pin interconnections.
Table 19-12 Socket Adapter
Microcontroller Package Socket Adapter
HD64F3434F16 100-pin QFP HS3434ESHF1H
HD64F3434TF16 100-pin TQFP HS3434ESNF1H
Figure 19-13 Memory Map in PROM Mode
H8/3434F H'0000
H'7FFF
H'0000
H'7FFF
On-chip ROM area
MCU mode PROM mode
1 output
H'1FFFF
401
Figure 19-14 Wiring of Socket Adapter
H8/3434F
Pin Name
FP-100B, TFP-100B
8
7
18
19
22
82
83
84
85
86
87
88
89
79
78
77
76
75
74
73
72
67
66
65
64
63
62
61
60
24, 25, 29,
32, 16
5, 6, 23,35
36, 37
4, 9, 59
46
15, 70, 71, 92
1
2, 3
Other pins
1
26
2
3
31
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
32
16
HN28F101 (32 Pins)
Pin No.
Pin Name
VPP
FA9
FA16
FA15
WE
FO0
FO1
FO2
FO3
FO4
FO5
FO6
FO7
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
OE
FA10
FA11
FA12
FA13
FA14
CE
VCC
VSS
Socket Adapter Pin No.
STBY/FVPP
NMI
P95
P94
P93
P30
P31
P32
P33
P34
P35
P36
P37
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P91, P90, P63,
P64, P97
MD1, MD0, P92, P67
AVref, AVCC
VCCB, VCC
AVSS
VSS
RES
XTAL, EXTAL
NC (OPEN)
Power-on
reset circuit
Oscillator circuit
Legend
VPP:
FO7 to FO0:
FA16 to FA0:
OE:
CE:
WE:
Programming power supply
Data input/output
Address input
Output enable
Chip enable
Write enable
402
19.6.3 Operation in PROM Mode
The program/erase/verify specifications in PROM mode are the same as for the standard HN28F101
flash memory. However, since the H8/3434F does not support product name recognition mode, the
programmer cannot be automatically set with the device name. Table 19-13 indicates how to select
the various operating modes.
Table 19-13 Operating Mode Selection in PROM Mode
Pins
Mode FVPP VCC CE OE WE D7to D0A16 to A0
Read Read VCC VCC L L H Data output Address input
Output VCC VCC L H H High impedance
disable
Standby VCC VCC H X X High impedance
Command Read VPP VCC L L H Data output
write Output VPP VCC L H H High impedance
disable
Standby VPP VCC H X X High impedance
Write VPP VCC L H L Data input
Note: Be sure to set the FVPP pin to VCC in these states. If it is set to 0 V, hardware standby mode
will be entered, even when in PROM mode, resulting in incorrect operation.
Legend
L: Low level
H: High level
VPP:V
PP level
VCC:V
CC level
X: Don’t care
VH: 11.5 V ≤VH ≤12.5 V
403
Table 19-14 PROM Mode Commands
1st Cycle 2nd Cycle
Command Cycles Mode Address Data Mode Address Data
Memory read 1 Write X H'00 Read RA Dout
Erase setup/erase 2 Write X H'20 Write X H'20
Erase-verify 2 Write EA H'A0 Read X EVD
Auto-erase setup/ 2 Write X H'30 Write X H'30
auto-erase
Program setup/ 2 Write X H'40 Write PA PD
program
Program-verify 2 Write X H'C0 Read X PVD
Reset 2 Write X H'FF Write X H'FF
PA: Program address
EA: Erase-verify address
RA: Read address
PD: Program data
PVD: Program-verify output data
EVD: Erase-verify output data
404
High-Speed, High-Reliability Programming: Unused areas of the H8/3434F flash memory
contain H'FF data (initial value). The H8/3434F flash memory uses a high-speed, high-reliability
programming procedure. This procedure provides enhanced programming speed without subjecting
the device to voltage stress and without sacrificing the reliability of programmed data. Figure 19-15
shows the basic high-speed, high-reliability programming flowchart. Tables 19-15 and 19-16 list the
electrical characteristics during programming.
Figure 19-15 High-Speed, High-Reliability Programming
Start
Set VPP = 12.0 V ±0.6 V
Address = 0
n = 0
Program command
Program setup command
n + 1 → n
Wait (25 µs)
Program-verify command
Wait (6 µs)
Address + 1 → address
Verification?
Last address?
Set VPP = VCC
End Fail
n = 20?
No go
No
Yes
Go
Yes
No
405
High-Speed, High-Reliability Erasing: The H8/3434F flash memory uses a high-speed, high-
reliability erasing procedure. This procedure provides enhanced erasing speed without subjecting
the device to voltage stress and without sacrificing data reliability . Figure 19-16 shows the basic
high-speed, high-reliability erasing flowchart. Tables 19-15 and 19-16 list the electrical
characteristics during erasing.
Figure 19-16 High-Speed, High-Reliability Erasing
Start
Program all bits to 0*
Address = 0
n = 0
Wait (10 ms)
Erase setup/erase command
n + 1 → n
Erase-verify command
Wait (6 µs)
Address + 1 → address
Verification?
Last address?
End Fail
n = 3000?
No go
No
Yes
Go
Yes
No
Follow the high-speed, high-reliability programming flowchart in programming all bits. If some bits
are already programmed to 0, program only the bits that have not yet been programmed.
Note: *
406
Table 19-15 DC Characteristics in PROM Mode
(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta= 25°C ±5°C)
Item Symbol Min Typ Max Unit Test Conditions
Input high FO7to FO0, VIH 2.2 — VCC + 0.3 V
voltage FA16 to FA0,
OE, CE, WE
Input low FO7to FO0, VIL –0.3 — 0.8 V
voltage FA16 to FA0,
OE, CE, WE
Output high FO7to FO0VOH 2.4 — — V IOH = –200 µA
voltage
Output low FO7to FO0VOL — — 0.45 V IOL = 1.6 mA
voltage
Input leakage FO7to FO0, | ILI | — — 2 µA Vin = 0 to VCC
current FA16 to FA0,
OE, CE, WE
VCC current Read ICC —4080 mA
Program ICC —4080 mA
Erase ICC —4080 mA
FVPP current Read IPP — — 10 µA VPP = 2.7 V to
5.5 V
—1020 mAV
PP = 12.6 V
Program IPP —2040 mAV
PP = 12.6 V
Erase IPP —2040 mAV
PP = 12.6 V
407
Table 19-16 AC Characteristics in PROM Mode
(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta= 25°C ±5°C)
Item Symbol Min Typ Max Unit Test Conditions
Command write cycle tCWC 120 — — ns Figure 19-17
Address setup time tAS 0 ——nsFigure 19-18*
Address hold time tAH 60——nsFigure 19-19
Data setup time tDS 50——ns
Data hold time tDH 10——ns
CE setup time tCES 0 ——ns
CE hold time tCEH 0 ——ns
V
PP setup time tVPS 100 — — ns
VPP hold time tVPH 100 — — ns
WE programming pulse width tWEP 70——ns
WE programming pulse high time tWEH 40——ns
OE setup time before command write tOEWS 0 ——ns
OE setup time before verify tOERS 6 ——µs
Verify access time tVA — — 500 ns
OE setup time before status polling tOEPS 120 — — ns
Status polling access time tSPA — — 120 ns
Program wait time tPPW 25——ns
Erase wait time tET 9—11ms
Output disable time tDF 0 — 40 ns
Total auto-erase time tAET 0.5 — 30 s
Note: CE, OE, and WE should be high during transitions of VPP from 5 V to 12 V and from 12 V to
5V.
*Input pulse level: 0.45 V to 2.4 V
Input rise time and fall time ≤10 ns
Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output
408
Figure 19-17 Auto-Erase Timing
Figure 19-18 High-Speed, High-Reliability Programming Timing
tVPH
tVPS
tCEH
tCES
tOEWS tWEP tCEH
tCES
tCWC
tWEP
tDS tDH tDS tDH
tAS tAH
tPPW
tCES
tWEH
tCEH
tWEP tOERS
tDH
tDS
tVA tDF
Command
input
Command
input
Data
input
Command
input
Command
input
Valid data
output
Data
input
Program setup Program Program-verify
Valid address
Address
5.0 V
12 V
5.0 V
VCC
VPP
CE
OE
WE
I/O7
I/O0 to I/O6
Note: Program-verify data output values may be intermediate between 1 and 0 before programming has been completed.
Valid data
output
Auto-erase setup Auto-erase and status polling
Address
Command
input
Status polling
Command
input
Command
input Command
input
5.0 V
12 V
5.0 V
VCC
VPP
CE
OE
WE
I/O7
I/O0 to I/O6
tVPS tVPH
tCEH tCES
tCES
tOEWS tWEP tCEH
tCES
tCWC
tWEP
tOEPS
tAET
tWEH
tDS tDH tDS tDH tSPA tDF
409
Figure 19-19 Erase Timing
Address
5.0 V
12 V
5.0 V
VCC
VPP
CE
OE
WE
I/O0 to I/O7
Erase setup Erase Erase-verify
Valid address
Command
input Command
input Command
input
Valid data
output
tVPS tVPH
tAS tAH
tOEWS tCWC
tCES tWEP
tCEH
tDH
tDS
tWEH
tDS tDH tDS tDH
tVA
tDF
tCES tWEP
tCEH tCES
tET tWEP
tCEH
tOERS
Note: Erase-verify data output values may be intermediate between 1 and 0 before erasing has been completed.
410
19.7 Flash Memory Programming and Erasing Precautions
Read these precautions before using PROM mode, on-board programming mode, or flash memory
emulation by RAM.
(1) Program with the specified voltages and timing.
The rated programming voltage (VPP) of the flash memory is 12.0 V.
If the PROM programmer is set to Hitachi HN28F101 specifications, VPP will be 12.0 V. Applying
voltages in excess of the rating can permanently damage the device. Take particular care to ensure
that the PROM programmer peak overshoot does not exceed the rated limit of 13 V.
(2) Before programming, check that the chip is correctly mounted in the PROM
programmer. Overcurrent damage to the device can result if the index marks on the PROM
programmer socket, socket adapter, and chip are not correctly aligned.
(3) Don’t touch the socket adapter or chip while programming. Touching either of these can
cause contact faults and write errors.
(4) Set H'FF as the PROM programmer buffer data for addresses H'8000 to H'1FFFF. The
H8/3434F PROM size is 32 kbytes. Addresses H'8000 to H'1FFFF always read H'FF, so if H'FF
is not specified as programmer data, a verify error will occur.
(5) Notes on applying, releasing, and shutting off the programming voltage (VPP)
Note: In this section, the application, release, and shutting-off of VPP are defined as follows.
Application: A rise in voltage from VCC to 12 V ± 0.6 V.
Release: A drop in voltage from 12 V ± 0.6 V to VCC.
Shut-off: No applied voltage (floating).
• Apply the programming voltage (VPP) after the rise of VCC, and release VPP before shutting off
VCC.
To prevent unintended programming or erasing of flash memory, in these power-on and power-
off timings, the application, release, and shutting-off of VPP must take place when the
microcontroller is in a stable operating condition as defined below.
Stable operating condition
— The VCC voltage must be stabilized within the rated voltage range (VCC = 2.7 V to 5.5 V)
If VPP is applied, released, or shut off while the microcontroller’s VCC voltage is not within
the rated voltage range (VCC = 2.7 to 5.5 V), since microcontroller operation is unstable, the
flash memory may be programmed or erased by mistake. This can occur even if VCC = 0 V.
411
To prevent changes in the VCC power supply when VPP is applied, be sure that the power
supply is adequately decoupled with inserting bypass capacitors.
— Clock oscillation must be stabilized (the oscillation settling time must have elapsed), and
oscillation must not be stopped
When turning on VCC power, hold the RES pin low during the oscillation settling time
(tOSC1 = 20 ms), and do not apply VPP until after this time.
— The microcontroller must be in the reset state, or in a state in which a reset has ended
normally (reset has been released) and flash memory is not being accessed
Apply or release VPP either in the reset state, or when the CPU is not accessing flash
memory (when a program in on-chip RAM or external memory is executing). Flash memory
cannot be read normally at the instant when VPP is applied or released. Do not read flash
memory while VPP is being applied or released.
For a reset during operation, apply or release VPP only after the RES pin has been held low
for at least ten system clock cycles (10ø).
— The P and E bits must be cleared in the flash memory control register (FLMCR)
When applying or releasing VPP, make sure that the P or E bit is not set by mistake.
— No program runaway
When VPP is applied, program execution must be supervised, e.g. by the watchdog timer.
These power-on and power-off timing requirements should also be satisfied in the event of a
power failure and in recovery from a power failure. If these requirements are not satisfied,
overprogramming or overerasing may occur due to program runaway etc., which could cause
memory cells to malfunction.
• The VPP flag is set and cleared by a threshold decision on the voltage applied to the FVPP pin.
The threshold level is between approximately VCC + 2 V to 11.4 V.
When this flag is set, it becomes possible to write to the flash memory control register (FLMCR)
and the erase block registers (EBR1 and EBR2), even though the VPP voltage may not yet have
reached the programming voltage range of 12.0 ± 0.6 V.
Do not actually program or erase the flash memory until VPP has reached the programming
voltage range.
The programming voltage range for programming and erasing flash memory is 12.0 ± 0.6 V
(11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range.
When not programming or erasing the flash memory, ensure that the VPP voltage does not
412
exceed the VCC voltage. This will prevent unintended programming and erasing.
In this chip, the same pin is used for STBY and FVPP. When this pin is driven low, a transition
is made to hardware standby mode. This happens not only in the normal operating modes
(modes 1, 2, and 3), but also when programming the flash memory with a PROM programmer.
When programming with a PROM programmer, therefore, use a programmer which sets this pin
to the VCC level when not programming (FVPP=12 V).
Figure 19-20 VPP Power-On and Power-Off Timing
(6) Do not apply 12 V to the FVPP pin during normal operation.
To prevent accidental programming or erasing due to microcontroller program runaway etc.,
apply 12 V to the VPP pin only when the flash memory is programmed or erased, or when flash
tOSC1
2.7 to 5.5 V
12 ± 0.6 V
VCC + 2 V to 11.4 V
VCCV
12 ± 0.6 V
VCCV
0 µs min
0 µs min
0 µs min
0 to VCCV
0 to VCCV
Min 10ø
(when RES is low)
ø
VCC
VPP
VPP
RES
Boot mode
User program
mode
Timing at which boot
program branches
to RAM area
Periods during which the VPP flag is being set or
cleared and flash memory must not be accessed
413
memory is emulated by RAM. Overprogramming or overerasing due to program runaway can
cause memory cells to malfunction. Avoid system configurations in which 12 V is always
applied to the FVPP pin.
While 12 V is applied, the watchdog timer should be running and enabled to halt runaway
program execution, so that program runaway will not lead to overprogramming or overerasing.
(7) Design a current margin into the programming voltage (VPP) power supply. Ensure that
VPP will not depart from 12.0 ±0.6 V (11.4 V to 12.6 V) during programming or erasing.
Programming and erasing may become impossible outside this range.
(8) Ensure that peak overshoot does not exceed the rated value at the FVPP and MD1pins.
Connect decoupling capacitors as close to the FVPP and MD1pins as possible.
Also connect decoupling capacitors to the MD1pin in the same way when boot mode is used.
Figure 19-21 VPP Power Supply Circuit Design (Example)
(9) Use the recommended algorithms for programming and erasing flash memory. These
algorithms are designed to program and erase without subjecting the device to voltage stress
and without sacrificing the reliability of programmed data.
Before setting the program (P) or erase (E) bit in the flash memory control register (FLMCR),
set the watchdog timer to ensure that the P or E bit does not remain set for more than the
specified time.
(10)For details on interrupt handling while flash memory is being programmed or erased, see the
notes on NMI interrupt handling in section 19.4.9, Interrupt Handling during Flash Memory
Programming and Erasing.
0.01 µF1.0 µF
12 V MD1
0.01 µF1.0 µF
12 V FVPP
H8/3434F
414
415
(11)Cautions on Accessing Flash Memory Control Registers
(a) Flash memory control register access state in each operating mode
The H8/3434F has flash memory control registers located at addresses H'FF80 (FLMCR),
H'FF82 (EBR1), and H'FF83 (EBR2). These registers can only be accessed when 12 V is
applied to the flash memory program power supply pin, FVPP.
Table 19-17 shows the area accessed for the above addresses in each mode, when 12 V is
and is not applied to FVPP.
Table 19-17 Area Accessed in Each Mode with 12V Applied and Not Applied to FVpp
Mode 1 Mode 2 Mode 3
12 V applied Reserved area Flash memory control Flash memory control
to FVPP (always H'FF) register (initial value H'80) register (initial value H'80)
12 V not applied External address External address space Reserved area
to FVPP space (always H'FF)
(b) When a flash memory control register is accessed in mode 2 (expanded mode with on-chip
ROM enabled)
When a flash memory control register is accessed in mode 2, it can be read or written to if
12 V is being applied to FVPP, but if not, external address space will be accessed. It is
therefore essential to confirm that 12 V is being applied to the FVPP pin before accessing
these registers.
(c) To check for 12 V application/non-application in mode 3 (single-chip mode)
When address H'FF80 is accessed in mode 3, if 12 V is being applied to FVPP, FLMCR is
read/written to, and its initial value after reset is H'80. When 12 V is not being applied to
FVPP, FLMCR is a reserved area that cannot be modified and always reads H'FF. Since bit
7 (corresponding to the VPP bit) is set to 1 at this time regardless of whether 12 V is applied
to FVPP, application or release of 12 V to FVpp cannot be determined simply from the 0 or
1 status of this bit. A byte data comparison is necessary to check whether 12V is being
applied. The relevant coding is shown below.
LABEL1: MOV.B @H’FF80, R1L
CMP.B #H’FF, R1L
BEQ LABEL1
Sample program for detection of 12 V application to FVpp (mode 3)
Table 19-18 DC Characteristics of Flash Memory
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, AVREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, VPP = 12.0 ± 0.6 V, Ta= –20°C to +75°C (regular specifications),
Ta= –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
High-voltage FVPP, MD1VHVCC + 2 — 11.4 V
(12 V)
threshold
level*
FVPP current During read IPP — — 10 µA VPP = 2.7 to 5.5 V
—1020mAV
PP = 12.6 V
During — 20 40 mA
programming
During — 20 40 mA
erasure
Note: *The listed voltages describe the threshold level at which high-voltage application is
recognized. In boot mode and while flash memory is being programmed or erased, the
applied voltage should be 12.0 V ± 0.6 V.
416
Table 19-19 AC Characteristics of Flash Memory
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, AVREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, VPP = 12.0 ± 0.6 V, Ta= –20°C to +75°C (regular specifications),
Ta= –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
Programming time*1,*2tP— 50 1000 µs
Erase time*1,*3tE— 1 30 s
Number of writing/erasing count
NWEC — — 100 Times
Verify setup time 1*1tVS1 4——µs
Verify setup time 2*1tVS2 2——µs
Flash memory read setup tFRS 50 — — µs VCC ≥4.5 V
time*4100 — — VCC < 4.5 V
Notes: 1. Set the times following the programming/erasing algorithm shown in section 19.
2. The programming time is the time during which a byte is programmed or the P bit in the
flash memory control register (FLMCR) is set. It does not include the program-verify time.
3. The erase time is the time during which all 32-kbyte blocks are erased or the E bit in the
flash memory control register (FLMCR) is set . It does not include the prewrite time
before erasure or erase-verify time.
4. After power-on when using an external colck source, after return from standby mode, or
after switching the programming voltage (VPP) from 12 V to VCC, make sure that this
read setup time has elapsed before reading flash memory.
When VPP is released, the flash memory read setup time is defined as the period from
when the FVPP pin has reached VCC + 2 V until flash memory can be read.
417
Section 20 ROM (Flash memory 60 kbytes version)
20.1 Flash Memory Overview
20.1.1 Flash Memory Operating Principle
Table 20-1 illustrates the principle of operation of the H8/3437F’s on-chip flash memory.
Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws hot
electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a
programmed memory cell is therefore higher than that of an erased cell. Cells are erased by
grounding the gate and applying a high voltage to the source, causing the electrons stored in the
floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like an
EPROM cell, by driving the gate to the high level and detecting the drain current, which depends on
the threshold voltage. Erasing must be done carefully, because if a memory cell is overerased, its
threshold voltage may become negative, causing the cell to operate incorrectly.
Section 20.4.6 shows an optimal erase control flowchart and sample program.
Table 20-1 Principle of Memory Cell Operation
20.1.2 Mode Programming and Flash Memory Address Space
As its on-chip ROM, the H8/3437F has 60 kbytes of flash memory. The flash memory is connected
to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states.
The H8/3437F’s flash memory is assigned to addresses H'0000 to H'EF7F in mode 2, and addresses
H'0000 to H'F77F in mode 3. The mode pins enable either on-chip flash memory or external
memory to be selected for this area. Table 20-2 summarizes the mode pin settings and usage of the
memory area.
Vd
Vg = VPP
Open Vd
Vg
Vs = VPP
Open Open
0 V
VPP
0 V
Vd 0 V
VCC
0 V
0 V
Vd 0 V
VPP
0 V
0 V
Program Erase Read
Memory
cell
Memory
array
419
420
Table 20-2 Mode Pin Settings and Flash Memory Area
Mode Pin Setting
Mode MD1MD0Memory Area Usage
Mode 0 0 0 Illegal setting
Mode 1 0 1 External memory area
Mode 2 1 0 On-chip flash memory area (H'0000 to H'EF7F)
Mode 3 1 1 On-chip flash memory area (H'0000 to H'F77F)
20.1.3 Features
Features of the flash memory are listed below.
• Five flash memory operating modes
The flash memory has five operating modes: program mode, program-verify mode, erase mode,
erase-verify mode, and prewrite-verify mode.
• Block erase designation
Blocks to be erased in the flash memory address space can be selected by bit settings. The
address space includes a large-block area (eight blocks with sizes from 2 kbytes to 12 kbytes)
and a small-block area (eight blocks with sizes from 128 bytes to 1 kbyte).
• Program and erase time
Programming one byte of flash memory typically takes 50 µs. Erasing all blocks (60 kbytes)
typically takes 1 s.
• Erase-program cycles
Flash memory contents can be erased and reprogrammed up to 100 times.
• On-board programming modes
These modes can be used to program, erase, and verify flash memory contents. There are two
modes: boot mode and user programming mode.
• Automatic bit-rate alignment
In boot-mode data transfer, the H8/3437F aligns its bit rate automatically to the host bit rate
(maximum 9600 bps).
• Flash memory emulation by RAM
Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates
in real time.
• PROM mode
As an alternative to on-board programming, the flash memory can be programmed and erased
in PROM mode, using a general-purpose PROM programmer. Program, erase, verify, and other
specifications are the same as for HN28F101 standard flash memory.
20.1.4 Block Diagram
Figure 20-1 shows a block diagram of the flash memory.
Figure 20-1 Flash Memory Block Diagram
FLMCR
EBR1
EBR2
H'0000
H'0002
H'0004
H'F77C
H'F77E
H'0001
H'0003
H'0005
H'F77D
H'F77F
MD1
MD0
Internal data bus (upper)
Internal data bus (lower)
Bus interface and control section Operating
mode
On-chip flash memory
(60 kbytes)
Upper byte
(even address) Lower byte
(odd address)
Legend
FLMCR:
EBR1:
EBR2:
Flash memory control register
Erase block register 1
Erase block register 2
8
8
421
20.1.5 Input/Output Pins
Flash memory is controlled by the pins listed in table 20-3.
Table 20-3 Flash Memory Pins
Pin Name Abbreviation Input/Output Function
Programming power FVPP Power supply Apply 12.0 V
Mode 1 MD1Input H8/3437F operating mode setting
Mode 0 MD0Input H8/3437F operating mode setting
Transmit data TxD1Output SCI1 transmit data output
Receive data RxD1Input SCI1 receive data input
The transmit data and receive data pins are used in boot mode.
20.1.6 Register Configuration
The flash memory is controlled by the registers listed in table 20-4.
Table 20-4 Flash Memory Registers
Name Abbreviation R/W Initial Value Address
Flash memory control register FLMCR R/W*2H'00*2FF80
Erase block register 1 EBR1 R/W*2H'00*2FF82
Erase block register 2 EBR2 R/W*2H'00*2FF83
Wait-state control register*1WSCR R/W H'08 FFC2
Notes: Registers FLMCR, EBR1, and EBR2 are only valid when writing to or erasing flash memory,
and can only be accessed while 12 V is being applied to the FVpp pin. When 12 V is not
applied to the FVpp pin, in mode 2 addresses H'FF80 to H'FF83 are external address space,
and in mode 3 these addresses cannot be modified and always read H'FF.
1. The wait-state control register controls the insertion of wait states by the wait-state
controller, frequency division of clock signals for the on-chip supporting modules by the
clock pulse generator, and emulation of flash-memory updates by RAM in on-board
programming mode.
2. In modes 2 and 3 (on-chip flash memory enabled), the initial value is H'00 for FLMCR,
EBR1 and EBR2. In mode 1 (on-chip flash memory disabled), these registers cannot be
modified and always read H'FF.
422
423
20.2 Flash Memory Register Descriptions
20.2.1 Flash Memory Control Register (FLMCR)
FLMCR is an 8-bit register that controls the flash memory operating modes. Transitions to program
mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this
register. FLMCR is initialized to H'00 by a reset, in the standby modes, and when 12 V is not
applied to FVPP. When 12 V is applied to the FVPP pin, a reset or entry to a standby mode initializes
FLMCR to H'80.
Bit 7—Programming Power (VPP): This status flag indicates that 12 V is applied to the FVPP pin.
Refer to section 20.7, Flash Memory Programming and Erasing Precautions (5), for details on use.
Bit 7
VPP Description
0 Cleared when 12 V is not applied to FVPP (Initial value)
1 Set when 12 V is applied to FVPP
Bits 6 to 4—Reserved: Read-only bits, always read as 0.
Bit 3—Erase-Verify Mode (EV):*1 Selects transition to or exit from erase-verify mode.
Bit 3
EV Description
0 Exit from erase-verify mode (Initial value)
1 Transition to erase-verify mode
Bit 2—Program-Verify Mode (PV):*1 Selects transition to or exit from program-verify mode.
Bit 2
PV Description
0 Exit from program-verify mode (Initial value)
1 Transition to program-verify mode
Bit
Initial value*
Read/Write
7
VPP
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
EV
0
R/W*
0
P
0
R/W*
2
PV
0
R/W*
1
E
0
R/W*
Note: * The initial value is H’00 in modes 2 and 3 (on-chip flash memory enabled). In mode 1
(on-chip flash memory disabled), this register cannot be modified and always reads H’FF.
For information on accessing this register, refer to in section 20.7, Flash Memory
Programming and Erasing Precautions (11).
Bit 1—Erase Mode (E):*1, *2 Selects transition to or exit from erase mode.
Bit 1
E Description
0 Exit from erase mode (Initial value)
1 Transition to erase mode
Bit 0—Program Mode (P):*1, *2 Selects transition to or exit from program mode.
Bit 0
P Description
0 Exit from program mode (Initial value)
1 Transition to program mode
Notes: 1. Do not set two or more of these bits simultaneously. Do not release or shut off the VCC
or VPP power supply when these bits are set.
2. Set the P or E bit according to the instructions given in section 20.4, Programming and
Erasing Flash Memory.
Set the watchdog timer beforehand to make sure that these bits do not remain set for
longer than the specified times.
For notes on use, see section 20.7, Flash Memory Programming and Erasing
Precautions.
20.2.2 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that designates large flash-memory blocks for programming and erasure.
EBR1 is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FVPP
pin. When a bit in EBR1 is set to 1, the corresponding block is selected and can be programmed and
erased. Figure 20-2 and table 20-6 show details of a block map.
Bit
Initial value*1
Read/Write
7
LB7
0
R/W*1, *2
6
LB6
0
R/W*1
5
LB5
0
R/W*1
4
LB4
0
R/W*1
3
LB3
0
R/W*1
0
LB0
0
R/W*1
2
LB2
0
R/W*1
1
LB1
0
R/W*1
Notes: *1
*2
The initial value is H'00 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip
ROM disabled), this register cannot be modified and always reads H'FF.
This bit cannot be modified in mode 2.
For information on accessing this register, refer to in section 20.7, Flash Memory
Programming and Erasing Precautions (11).
424
Bits 7 to 0—Large Block 7 to 0 (LB7 to LB0): These bits select large blocks (LB7 to LB0) to be
programmed and erased.
Bits 7 to 0
LB7 to LB0 Description
0 Block (LB7 to LB0) is not selected (Initial value)
1 Block (LB7 to LB0) is selected
20.2.3 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that designates small flash-memory blocks for programming and erasure.
EBR2 is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FVPP
pin. When a bit in EBR2 is set to 1, the corresponding block is selected and can be programmed and
erased. Figure 20-2 and table 20-6 show a block map.
Bits 7 to 0—Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be
programmed and erased.
Bits 7 to 0
SB6 to SB0 Description
0 Block (SB7 to SB0) is not selected (Initial value)
1 Block (SB7 to SB0) is selected
Bit
Initial value*
Read/Write
7
SB7
0
R/W*
6
SB6
0
R/W*
5
SB5
0
R/W*
4
SB4
0
R/W*
3
SB3
0
R/W*
0
SB0
0
R/W*
2
SB2
0
R/W*
1
SB1
0
R/W*
Note:
*The initial value is H'00 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip
ROM disabled), this register cannot be modified and always reads H'FF.
For information on accessing this register, refer to in section 20.7, Flash Memory
Programming and Erasing Precautions (11).
425
20.2.4 Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that enables flash-memory updates to be emulated in
RAM. It also controls frequency division of clock signals supplied to the on-chip supporting
modules and insertion of wait states by the wait-state controller.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—RAM Select and RAM0 (RAMS and RAM0): These bits are used to reassign an
area to RAM (see table 20-5). These bits are write-enabled and their initial value is 0. They are
initialized by a reset and in hardware standby mode. They are not initialized in software standby
mode.
If only one of bits 7 and 6 is set, part of the RAM area can be overlapped onto the small-block flash
memory area. In that case, access is to RAM, not flash memory, and all flash memory blocks are
write/erase-protected (emulation protect*1). In this state, the mode cannot be changed to program or
erase mode, even if the P bit or E bit in the flash memory control register (FLMCR) is set (although
verify mode can be selected). Therefore, clear both of bits 7 and 6 before programming or erasing
the flash memory area.
If both of bits 7 and 6 are set, part of the RAM area can be overlapped onto the small-block flash
memory area, but this overlapping begins only when an interrupt signal is input while 12 V is being
applied to the FVPP pin. Up until that point, flash memory is accessed. Use this setting for interrupt
handling while flash memory is being programmed or erased.*2
Table 20-5 RAM Area Reassignment*3
Bit 7 Bit 6
RAMS RAM0 RAM Area ROM Area
0 0 None —
0 1 H'F880 to H'F8FF H'0080 to H'00FF
1 0 H'F880 to H'F97F H'0080 to H'017F
1 1 H'F800 to H'F87F H'0000 to H'007F
Bit
Initial value
Read/Write
7
RAMS
0
R/W
6
RAM0
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
426
Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to the on-
chip supporting modules. For details, see section 6, Clock Pulse Generator.
Bit 4—Reserved: This bit is reserved, but it can be written and read. Its initial value is 0.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1, WMS0)
Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0)
These bits control insertion of wait states by the wait-state controller. For details, see section 5,
Wait-State Controller.
Notes: 1. For details on emulation protect, see section 20.4.8, Protect Modes.
2. For details on interrupt handling during programming and erasing of flash memory, see
section 20.4.9, Interrupt Handling during Flash Memory Programming and Erasing.
3. RAM area that overlaps flash memory.
427
Figure 20-2 Erase Block Map
H'0000
H'01FF
H'0200
H'03FF
H'0400
H'07FF
H'0800
H'0BFF
H'0C00
H'0FFF
H'0000
H'0FFF
H'1000
H'1FFF
H'2000
H'3FFF
H'4000
H'5FFF
H'6000
H'7FFF
H'8000
H'9FFF
H'A000
H'BFFF
H'C000
H'EF7F
H'EF80
H'F77F
Small block
area
(4 kbytes)
Large block
area
(58 kbytes)
SB7 to SB0
4 kbytes
LB0
4 kbytes
LB1
8 kbytes
LB2
8 kbytes
LB3
8 kbytes
LB5
8 kbytes
LB4
8 kbytes
LB6
12 kbytes
LB7
2 kbytes
SB0 128 bytes
SB1 128 bytes
SB2 128 bytes
SB3 128 bytes
SB4
512 bytes
SB5
1 kbyte
SB6
1 kbyte
SB7
1 kbyte
428
Table 20-6 Erase Blocks and Corresponding Bits
Register Bit Block Address Size
EBR1 0 LB0 H'1000 to H'1FFF 4 kbytes
1 LB1 H'2000 to H'3FFF 8 kbytes
2 LB2 H'4000 to H'5FFF 8 kbytes
3 LB3 H'6000 to H'7FFF 8 kbytes
4 LB4 H'8000 to H'9FFF 8 kbytes
5 LB5 H'A000 to H'BFFF 8 kbytes
6 LB6 H'C000 to H'EF7F 12 kbytes
7 LB7 H'EF80 to H'F77F 2 kbytes
EBR2 0 SB0 H'0000 to H'007F 128 bytes
1 SB1 H'0080 to H'00FF 128 bytes
2 SB2 H'0100 to H'017F 128 bytes
3 SB3 H'0180 to H'01FF 128 bytes
4 SB4 H'0200 to H'03FF 512 bytes
5 SB5 H'0400 to H'07FF 1 kbyte
6 SB6 H'0800 to H'0BFF 1 kbyte
7 SB7 H'0C00 to H'0FFF 1 kbyte
20.3 On-Board Programming Modes
When an on-board programming mode is selected, the on-chip flash memory can be programmed,
erased, and verified. There are two on-board programming modes: boot mode, and user program
mode. These modes are selected by inputs at the mode pins (MD1and MD0) and FVPP pin. Table
20-7 indicates how to select the on-board programming modes. For details on applying voltage VPP,
refer to section 20.7, Flash Memory Programming and Erasing Precautions (5).
429
Table 20-7 On-Board Programming Mode Selection
Mode Selections FVPP MD1MD0Notes
Boot mode Mode 2 12 V*12 V*0 0: VIL
Mode 3 12 V*11: VIH
User program mode Mode 2 1 0
Mode 3 1 1
Note: *For details on the timing of 12 V application, see notes 6 to 8 in the Notes on Use of Boot
Mode at the end of this section.
In boot mode, the mode control register (MDCR) can be used to monitor the mode (mode 2
or 3) in the same way as in normal mode.
Example: Set the mode pins for mode 2 boot mode (MD1= 12 V, MD0= 0 V).
If the mode select bits of MDCR are now read, they will indicate mode 2 (MDS1 = 1, MDS0
= 0).
20.3.1 Boot Mode
To use boot mode, a user program for programming and erasing the flash memory must be provided
in advance on the host machine (which may be a personal computer). Serial communication
interface channel 1 is used in asynchronous mode (see figure 20-3). If the H8/3437F is placed in
boot mode, after it comes out of reset, a built-in boot program is activated. This program starts by
measuring the low period of data transmitted from the host and setting the bit rate register (BRR)
accordingly. The H8/3437F’s built-in serial communication interface (SCI) can then be used to
download the user program from the host machine. The user program is stored in on-chip RAM.
After the program has been stored, execution branches to address H'F7E0 in the on-chip RAM, and
the program stored on RAM is executed to program and erase the flash memory.
Figure 20-3 Boot-Mode System Configuration
HOST
Receive data to be programmed
Transmit verification data
H8/3437F
RxD1
TxD1
SCI
430
431
Boot-Mode Execution Procedure:
Figure 20-4 shows the boot-mode execution procedure.
Figure 20-4 Boot Mode Flowchart
Start
Program H8/3437F pins for boot mode,
and reset
Host transmits H'00 data continuously
at desired bit rate
H8/3437F measures low period
of H'00 data transmitted from host
H8/3437F computes bit rate and
sets bit rate register
After completing bit-rate alignment, H8/3437F
sends one H'00 data byte to host to indicate
that alignment is completed
Host checks that this byte, indicating
completion of bit-rate alignment, is received
normally, then transmits one H'55 byte
After receiving H'55, H8/3437F sends part of
the boot program to RAM
H8/3437F transfers one user program
byte to RAM*2
H8/3437F calculates number of bytes left
to be transferred (N = N – 1)
All bytes transferred?
(N = 0?)
All data = H'FF?*4
Erase all flash
memory blocks*3, *4
After transferring the user program to RAM,
H8/3437F transmits one H'AA data byte to host
No
Yes
Yes
No
1
2
3
4
5
6
7
9
H8/3437F branches to the RAM boot
area (H'F800 to H'FF2F), then checks the
data in the user area of flash memory
H8/3437F receives two bytes indicating byte
length (N) of program to be downloaded
to on-chip RAM*1
8
After checking that all data in flash memory is H'FF,
H8/3437F transmits one H'AA data byte to host
H8/3437F branches to H'F7E0 in RAM area and
executes user program downloaded into RAM
10
1. Program the H8/3437F pins for boot mode, and start
the H8/3437F from a reset.
2. Set the host’s data format to 8 bits + 1 stop bit,
select the desired bit rate (2400, 4800, or 9600 bps),
and transmit H'00 data continuously.
3. The H8/3437F repeatedly measures the low period
of the RxD1pin and calculates the host’s
asynchronous-communication bit rate.
4. When SCI bit-rate alignment is completed, the
H8/3437F transmits one H'00 data byte to indicate
completion of alignment.
5. The host should receive the byte transmitted from
the H8/3437F to indicate that bit-rate alignment is
completed, check that this byte is received normally,
then transmit one H'55 byte.
6. After receiving H'55, H8/3437F sends part of the
boot program to H'F780 to H'F7DF and H'F800 to
H'FF2F of RAM.
7. After branching to the boot program area (H'F800 to
H'FF2F) in RAM, the H8/3437F checks whether the
flash memory already contains any programmed
data. If so, all blocks are erased.
8. After the H8/3437F transmits one H'AA data byte,
the host transmits the byte length of the user
program to be transferred to the H8/3437F. The byte
length must be sent as two-byte data, upper byte
first and lower byte second. After that, the host
proceeds to transmit the user program. As
verification, the H8/3437F echoes each byte of the
received byte-length data and user program back to
the host.
9. The H8/3437F stores the received user program in
on-chip RAM in a 1934-byte area from H'F7E0 to
H'FF6D.
10. After transmitting one H'AA data byte, the H8/3437F
branches to address H'F7E0 in on-chip RAM and
executes the user program stored in the area from
H'F7E0 to H'FF6D.
Notes: 1. The user can use 1934 bytes of RAM. The
number of bytes transferred must not exceed
1934 bytes. Be sure to transmit the byte
length in two bytes, upper byte first and lower
byte second. For example, if the byte length
of the program to be transferred is 256 bytes
(H'0100), transmit H'01 as the upper byte,
followed by H'00 as the lower byte.
2. The part of the user program that controls the
flash memory should be coded according to
the flash memory write/erase algorithms
given later.
3. If a memory cell malfunctions and cannot be
erased, the H8/3437F transmits one H'FF
byte to report an erase error, halts erasing,
and halts further operations.
4. H'0000 to H'EF7F in mode 2 and H'0000 to
H'F77F in mode 3.
Automatic Alignment of SCI Bit Rate
Figure 20-5 Measurement of Low Period in Data Transmitted from Host
When started in boot mode, the H8/3437F measures the low period in asynchronous SCI data
transmitted from the host (figure 20-5). The data format is eight data bits, one stop bit, and no parity
bit. From the measured low period (9 bits), the H8/3437F computes the host’s bit rate. After
aligning its own bit rate, the H8/3437F sends the host 1 byte of H'00 data to indicate that bit-rate
alignment is completed. The host should check that this alignment-completed indication is received
normally and send one byte of H'55 back to the H8/3437F. If the alignment-completed indication is
not received normally, the H8/3437F should be reset, then restarted in boot mode to measure the
low period again. There may be some alignment error between the host’s and H8/3437F’s bit rates,
depending on the host’s bit rate and the H8/3437F’s system clock frequency. To have the SCI
operate normally, set the host’s bit rate to 2400, 4800, or 9600 bps*1. Table 20-8 lists typical host
bit rates and indicates the clock-frequency ranges over which the H8/3437F can align its bit rate
automatically. Boot mode should be used within these frequency ranges*2.
Table 20-8 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by
H8/3437F
System Clock Frequencies Permitting
Host Bit Rate*1Automatic Bit-Rate Alignment by H8/3437F
9600 bps 8 MHz to 16 MHz
4800 bps 4 MHz to 16 MHz
2400 bps 2 MHz to 16 MHz
Notes: 1. Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be
used.
2. Although the H8/3437F may also perform automatic bit-rate alignment with bit rate and
system clock combinations other than those shown in table 20-8, there will be a slight
difference between the bit rates of the host and the H8/3437F, and subsequent transfer
will not be performed normally. Therefore, only a combination of bit rate and system
clock frequency within one of the ranges shown in table 20-8 can be used for boot mode
execution.
D0 D1 D2 D3 D4 D5 D6 D7
Start
bit Stop
bit
This low period (9 bits) is measured (H'00 data)
High for at
least 1 bit
432
RAM Area Allocation in Boot Mode: In boot mode, the 96 bytes from H'F780 to H'F7DF and the
18 bytes from H'FF6E to H'FF7F are reserved for use by the boot program, as shown in figure 20-6.
The user program is transferred into the area from H'F7E0 to H'FF6D (1934 bytes). The boot
program area can be used after the transition to execution of the user program transferred into RAM.
If a stack area is needed, set it within the user program.
Figure 20-6 RAM Areas in Boot Mode
User program
transfer area
(1934 bytes)
Boot program
area* (18 bytes)
Boot program
area*
(96 bytes)
This area cannot be used until the H8/3437F starts to
execute the user program transferred to RAM (until it has
branched to H’F7E0 in RAM). Note that even after the
branch to the user program, the boot program area
(H’F780 to H’F7DF, H’FF6E to H’FF7F) still contains the
boot program.
Note also that 16 bytes (H’F780 to H’F78F) of this area
cannot be used if an interrupt handling routine is executed
within the boot program. For details see section 20.4.9,
Interrupt Handling during Flash Memory Programming and
Erasing.
*
H'F780
H'F7E0
H'FF6E
Note:
H'FF7F
433
Notes on Use of Boot Mode
1. When the H8/3437F comes out of reset in boot mode, it measures the low period of the input at
the SCI’s RxD1pin. The reset should end with RxD1high. After the reset ends, it takes about
100 states for the H8/3437F to get ready to measure the low period of the RxD1input.
2. In boot mode, if any data has been programmed into the flash memory (if all data*3is not
H'FF), all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, e.g. the first time on-board programming is performed, or if the update program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RxD1and TxD1pins should be pulled up on-board.
5. Before branching to the user program (at address H'F7E0 in the RAM area), the H8/3437F
terminates transmit and receive operations by the on-chip SCI (by clearing the RE and TE bits
of the serial control register to 0 in channel 1), but the auto-aligned bit rate remains set in bit
rate register BRR. The transmit data output pin (TxD1) is in the high output state (in port 8, the
bits P84DDR of the port 8 data direction register and P84DR of the port 8 data register are set
to 1).
At this time, the values of general registers in the CPU are undetermined. Thus these registers
should be initialized immediately after branching to the user program. Especially in the case of
the stack pointer, which is used implicitly in subroutine calls, the stack area used by the user
program should be specified.
There are no other changes to the initialized values of other registers.
6. Boot mode can be entered by starting from a reset after 12 V is applied to the MD1and FVPP
pins according to the mode setting conditions listed in table 20-7. Note the following points
when turning the VPP power on.
When reset is released (at the rise from low to high), the H8/3437F checks for 12-V input at the
MD1and FVPP pins. If it detects that these pins are programmed for boot mode, it saves that
status internally. The threshold point of this voltage-level check is in the range from
approximately VCC + 2 V to 11.4 V, so boot mode will be entered even if the applied voltage is
insufficient for programming or erasure (11.4 V to 12.6 V). When the boot program is
executed, the VPP power supply must therefore be stabilized within the range of 11.4 V to
12.6 V before the branch to the RAM area occurs. See figure 20-20.
Make sure that the programming voltage VPP does not exceed 12.6 V during the transition to
boot mode (at the reset release timing) and does not go outside the range of 12 V ± 0.6 V while
in boot mode. Boot mode will not be executed correctly if these limits are exceeded. In
addition, make sure that VPP is not released or shut off while the boot program is executing or
434
the flash memory is being programmed or erased.*1
Boot mode can be released by driving the reset pin low, waiting at least ten system clock
cycles, then releasing the application of 12 V to the MD1and FVPP pins and releasing the reset.
The settings of external pins must not change during operation in boot mode.
During boot mode, if input of 12 V to the MD1pin stops but no reset input occurs at the RES
pin, the boot mode state is maintained within the chip and boot mode continues (but do not stop
applying 12 V to the FVPP pin during boot mode*1).
If a watchdog timer reset occurs during boot mode, this does not release the internal mode state,
but the internal boot program is restarted.
Therefore, to change from boot mode to another mode, the boot-mode state within the chip
must be released by a reset input at the RES pin before the mode transition can take place.
7. If the input level of the MD1pin is changed during a reset (e.g., from 0 V to 5 V then to 12 V
while the input to the RES pin is low), the resultant switch in the microcontroller’s operating
mode will affect the bus control output signals (AS, RD, and WR) and the status of ports that
can be used for address output*2.
Therefore, either set these pins so that they do not output signals during the reset, or make sure
that their output signals do not collide with other signals outside the microcontroller.
8. When applying 12 V to the MD1and FVPP pins, make sure that peak overshoot does not exceed
the rated limit of 13 V.
Also, be sure to connect a decoupling capacitor to the FVPP and MD1pins.
Note: 1. For details on applying, releasing, and shutting off VPP, see note (5) in section 20.7,
Flash Memory Programming and Erasing Precautions.
2. These ports output low-level address signals if the mode pins are set to mode 1
during the reset. In all other modes, these ports are in the high-impedance state. The
bus control output signals are high if the mode pins are set for mode 1 or 2 during the
reset. In mode 3, they are at high impedance.
3. H’0000 to H’EF7F in mode 2 and H’0000 to H’F77F in mode 3.
435
20.3.2 User Program Mode
When set to user program mode, the H8/3437F can erase and program its flash memory by
executing a user program. On-board updates of the on-chip flash memory can be carried out by
providing on-board circuits for supplying VPP and data, and storing an update program in part of the
program area.
To select user program mode, select a mode that enables the on-chip ROM (mode 2 or 3) and apply
12 V to the FVPP pin, either during a reset, or after the reset has ended (been released) but while
flash memory is not being accessed. In user program mode, the on-chip supporting modules operate
as they normally would in mode 2 or 3, except for the flash memory. However, hardware standby
mode cannot be set while 12 V is applied to the FVPP pin.
The flash memory cannot be read while it is being programmed or erased, so the update program
must either be stored in external memory, or transferred temporarily to the RAM area and executed
in RAM.
436
User Program Mode Execution Procedure (Example)*1: Figure 20-7 shows the execution
procedure for user program mode when the on-board update routine is executed in RAM.
Figure 20-7 User Program Mode Operation (Example)
Notes: 1. Do not apply 12 V to the FVPP pin during normal operation. To prevent flash memory
from being accidentally programmed or erased due to program runaway etc., apply 12 V
to FVPP only when programming or erasing flash memory. Overprogramming or
overerasing due to program runaway can cause memory cells to malfunction. While
12 V is applied, the watchdog timer should be running and enabled to halt runaway
program execution, so that program runaway will not lead to overprogramming or
overerasing. For details on applying, releasing, and shutting off VPP, see section 20.7,
Flash Memory Programming and Erasing Precautions (5).
2. After the update is finished, when input of 12 V to the FVPP pin is released, the flash
memory read setup time (tFRS) must elapse before any program in flash memory is
executed. This is the required setup time from when the FVPP pin reaches the (VCC +
2 V) level after 12 V is released until flash memory can be read.
Set MD1 and MD0 to 10 or 11
(apply VIH to VCC to MD1)
Start from reset
Branch to flash memory on-board
update routine in RAM
FVPP = 12 V
(user program mode)
Execute flash memory
on-board update routine in RAM
(update flash memory)
1
2
3
4
5
Branch to flash memory
on-board update program
Transfer on-board update routine
into RAM
6
7
8
Release FVPP
(exit user program mode)
Branch to application program
in flash memory*2
437
Procedure
The flash memory on-board update program
is written in flash memory ahead of time by
the user.
1. Set MD1and MD0of the H8/3437F to 10
or 11, and start from a reset.
2. Branch to the flash memory on-board
update program in flash memory.
3. Transfer the on-board update routine into
RAM.
4. Branch to the on-board update routine
that was transferred into RAM.
5. Apply 12 V to the FVPP pin, to enter user
program mode.
6. Execute the flash memory on-board
update routine in RAM, to perform an on-
board update of the flash memory.
7. Change the voltage at the FVPP pin from
12 V to VCC, to exit user program mode.
8. After the on-board update of flash
memory ends, execution branches to an
application program in flash memory.
20.4 Programming and Erasing Flash Memory
The H8/3437F’s on-chip flash memory is programmed and erased by software, using the CPU. The
flash memory can operate in program mode, erase mode, program-verify mode, erase-verify mode,
or prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV, and EV
bits in the flash memory control register (FLMCR).
The flash memory cannot be read while being programmed or erased. The program that controls the
programming and erasing of the flash memory must be stored and executed in on-chip RAM or in
external memory. A description of each mode is given below, with recommended flowcharts and
sample programs for programming and erasing.
For details on programming and erasing, refer to section 20.7, Flash Memory Programming and
Erasing Precautions.
20.4.1 Program Mode
To write data into the flash memory, follow the programming algorithm shown in figure 20-8. This
programming algorithm can write data without subjecting the device to voltage stress or impairing
the reliability of programmed data.
To program data, first specify the area to be written in flash memory with erase block registers
EBR1 and EBR2, then write the data to the address to be programmed, as in writing to RAM. The
flash memory latches the address and data in an address latch and data latch. Next set the P bit in
FLMCR, selecting program mode. The programming duration is the time during which the P bit is
set. The total programming time does not exceed 1 ms. Programming for too long a time, due to
program runaway for example, can cause device damage. Before selecting program mode, set up the
watchdog timer so as to prevent overprogramming. For details of the programming method, refer to
section 20.4.3, Programming Flowchart and Sample Programs.
20.4.2 Program-Verify Mode
In program-verify mode, after data has been programmed in program mode, the data is read to
check that it has been programmed correctly.
After the programming time has elapsed, exit programming mode (clear the P bit to 0) and select
program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is
applied to the memory cells at the latched address. If the flash memory is read in this state, the data
at the latched address will be read. After selecting program-verify mode, wait 4 µs or more before
reading, then compare the programmed data with the verify data. If they agree, exit program-verify
mode and program the next address. If they do not agree, select program mode again and repeat the
same program and program-verify sequence. Do not repeat the program and program-verify
sequence more than 6 times* for the same bit.
Note: * Keep the total programming time under 1 ms for each bit.
438
20.4.3 Programming Flowchart and Sample Program
Flowchart for Programming One Byte
Figure 20-8 Programming Flowchart
Start
n = 1
Enable watchdog timer*2
Select program mode
(P bit = 1 in FLMCR)
Wait (x) µs*4
Clear P bit
Disable watchdog timer
Select program-verify mode
(PV bit = 1 in FLMCR)
Wait (tvs1)µs*5
Verify*3 (read memory) No go
OK
Clear PV bit
End (1-byte data programmed)
End of programming
Clear PV bit
Programming error
n≥ N?*5
n + 1 → n
Double programming time
(x × 2→x)
No
End of verification
Write data to flash memory (flash
memory latches write
address and data)*1
Set erase block register
(set bit of block to be programmed to 1)
Yes
Clear erase block register
(clear bit of programmed block to 0)
439
Notes: 1. Write the data to be programmed with a
byte transfer instruction.
2. Set the timer overflow interval as follows.
CKS2=0, CKS1=0, CKS0=1
3. Read the memory data to be verified with a
byte transfer instruction.
4. Programming time x, which is determined
by the initial time x 2n-1 (n=1,2,3,4,5,6),
increases in proportion to n. Thus, set the
initial time to 15.8 µs or less to make total
programming time 1 ms or less.
5. tVS1: 4 µs or more
N: 6 (set N so that total programming
time does not exceed 1 ms)
Sample Program for Programming One Byte: This program uses the following registers.
R0H: Specifies blocks to be erased.
R1H: Stores data to be programmed.
R1L: Stores data to be read.
R3: Stores address to be programmed. Valid address specifications are H'0000 to H'EF7F in
mode 2, and H'0000 to H'F77F in mode 3.
R4: Sets program and program-verify timing loop counters, and also stores register setting value.
R5: Sets program timing loop counter.
R6L: Used for program-verify fail count.
Arbitrary data can be programmed at an arbitrary address by setting the address in R3 and the data
in R1H.
The setting of #a and #b values depends on the clock frequency. Set #a and #b values according to
tables 20-9 (1) and (2).
FLMCR: .EQU H’FF80
EBR1: .EQU H’FF82
EBR2: .EQU H’FF83
TCSR: .EQU H’FFA8
.ALIGN 2
PRGM: MOV.B #H’**, R0H ;
MOV.B R0H, @EBR*:8 ; Set EBR*
MOV.B #H’00, R6L ; Program-verify fail counter
MOV.W #H’a, R5 ; Set program loop counter
MOV.B R1H, @R3 ; Dummy write
PRGMS: INC R6L ; Program-verify fail counter + 1 →R6L
MOV.W #H’A579, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set program loop counter
BSET #0, @FLMCR:8 ; Set P bit
LOOP1: SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOP1 ; Wait loop
BCLR #0, @FLMCR:8 ; Clear P bit
MOV.W #H’A500, R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
MOV.B #H’b , R4H ; Set program-verify loop counter
BSET #2, @FLMCR:8 ; Set PV bit
LOOP2: DEC R4H ;
BNE LOOP2 ; Wait loop
MOV.B @R3, R1L ; Read programmed address
CMP.B R1H, R1L ; Compare programmed data with read data
BEQ PVOK ; Program-verify decision
BCLR #2, @FLMCR:8 ; Clear PV bit
440
CMP.B #H’06, R6L ; Program-verify executed 6 times?
BEQ NGEND ; If program-verify executed 6 times, branch to NGEND
ADD.W R5, R5 ; Programming time ×2
BRA PRGMS ; Program again
PVOK: BCLR #2, @FLMCR:8 ; Clear PV bit
MOV.B #H’00, R6L ;
MOV.B R6L, @EBR*:8 ; Clear EBR*
One byte programmed
NGEND: Programming error
20.4.4 Erase Mode
To erase the flash memory, follow the erasing algorithm shown in figure 20-9. This erasing
algorithm can erase data without subjecting the device to voltage stress or impairing the reliability
of programmed data.
To erase flash memory, before starting to erase, first place all memory data in all blocks to be erased
in the programmed state (program all memory data to H'00). If all memory data is not in the
programmed state, follow the sequence described later (figure 20-10) to program the memory data
to zero. Select the flash memory areas to be erased with erase block registers 1 and 2 (EBR1 and
EBR2). Next set the E bit in FLMCR, selecting erase mode. The erase time is the time during which
the E bit is set. To prevent overerasing, use a software timer to divide the time for a single erase,
and ensure that the total time does not exceed 30 seconds. For the time for a single erase, refer to
section 20.4.6, Erase Flowchart and Sample Programs. Overerasing, due to program runaway for
example, can give memory cells a negative threshold voltage and cause them to operate incorrectly.
Before selecting erase mode, set up the watchdog timer so as to prevent overerasing.
20.4.5 Erase-Verify Mode
In erase-verify mode, after data has been erased, it is read to check that it has been erased correctly.
After the erase time has elapsed, exit erase mode (clear the E bit to 0) and select erase-verify mode
(set the EV bit to 1). Before reading data in erase-verify mode, write H'FF dummy data to the
address to be read. This dummy write applies an erase-verify voltage to the memory cells at the
latched address. If the flash memory is read in this state, the data at the latched address will be read.
After the dummy write, wait 2 µs or more before reading. When performing the initial dummy
write, wait 4 µs or more after selecting erase-verify mode. If the read data has been successfully
erased, perform an erase-verify (dummy write, wait 2 µs or more, then read) for the next address. If
the read data has not been erased, select erase mode again and repeat the same erase and erase-
verify sequence through the last address, until all memory data has been erased to 1. Do not repeat
the erase and erase-verify sequence more than 602 times, however.
441
442
20.4.6 Erasing Flowchart and Sample Program
Flowchart for Erasing One Block
Figure 20-9 Erasing Flowchart
Start
Write 0 data in all addresses
to be erased (prewrite)*1
n = 1
Set erase block register
(set bit of block to be erased to 1)
Enable watchdog timer*2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms*5
Clear E bit
Disable watchdog timer
Set top address in block
as verify address
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tvs1)µs*6
Dummy write to verify address*3
(flash memory latches address)
Verify*4 (read data=H'FF?)
Last address?
Address + 1 → address
Yes
OK
No go
No
No
Yes
Yes
Clear EV bit
Clear erase block register
(clear bit of erased block to 0)
End of block erase
Clear EV bit
Erase error
n≥ N?*6
n> 4?
Erase-verify ends
Erasing
ends
n + 1 → n
Double erase time
(x × 2→x)
No
Wait (tvs2)µs*6
Notes: 1. Program all addresses to be erased by
following the prewrite flowchart.
2. Set the watchdog timer overflow interval
to the value indicated in table 20-10.
3. For the erase-verify dummy write, write
H'FF with a byte transfer instruction.
4. Read the data to be verified with a byte
transfer instruction. When erasing two or
more blocks, clear the bits of erased
blocks in the erase block registers, so
that only unerased blocks will be erased
again.
5. The erase time x is successively
incremented by the initial set value x 2n-1
(n=1,2,3,4). After fourth erasing, the
erase time is fixed. An initial value of
6.25 ms or less should be set, and the
time for one erasure should be 50 ms or
less.
6. tVS1: 4 µs or more
tVS2: 2 µs or more
N: 602 (Set N so that total erase time
does not exceed 30s.)
Prewrite Flowchart
Figure 20-10 Prewrite Flowchart
End of prewrite
n≥ N?*5
n + 1 → n
Address + 1→Address
Double programming time
No
Start
Set start address*6
n = 1
Write H'00 to flash memory
(flash memory latches write address
and write data)*1
Enable watchdog timer*2
Select program mode
(P bit = 1 in FLMCR)
Wait (x) µs*4
Clear P bit
Disable watchdog timer
Wait (tvs1)µs*5
Prewrite verify*3
(read data = H'00?)
Last address?*6
No go
No
Yes
End of
programming
Programming error
OK Yes
Set erase block register
(set bit block to be programmed to 1)
Clear erase block register
(clear bit of programmed block to 0)
(x × 2→x)
443
Notes: 1. Use a byte transfer instruction.
2. Set the timer overflow interval as follows.
CKS2 = 0, CKS1 = 0, CKS0 = 1
3. In prewrite-verify mode P, E, PV, and EV
are all cleared to 0 and 12 V is applied to
FVPP. Read the data with a byte transfer
instruction.
4. Programming time x, which is determined
by the inital time x 2n-1 (n=1,2,3,4,5,6),
increases in proportion to n. Thus, set the
initial time to 15.8 µs or less to make total
programming time 1 ms or less.
5. tVS1: 4 µs or more
N: 6 (set N so that total programming
time does not exceed 1 ms)
6. Start and last addresses shall be top and
last addresses of the block to be erased.
Sample Block-Erase Program: This program uses the following registers.
R0: Specifies block to be erased, and also stores address used in prewrite and erase-verify.
R1H: Stores data to be read, and also used for dummy write.
R2: Stores last address of block to be erased.
R3: Stores address used in prewrite and erase-verify.
R4: Sets timing loop counters for prewrite, prewrite-verify, erase, and erase-verify, and also
stores register setting value.
R5: Sets prewrite and erase timing loop counters.
R6L: Used for prewrite-verify and erase-verify fail count.
The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a,
#b, #c, #d, and #e values according tables 20-9 (1) and (2), and 20-10. Erase block registers (EBR1
and EBR2) should be set according to sections 20.2.2 and 20.2.3. #BLKSTR and #BLKEND are
the top and last addresses of the block to be erased. Set #BLKSTR and #BLKEND according to
figure 20-2.
444
FLMCR: .EQU H’FF80
EBR1: .EQU H’FF82
EBR2: .EQU H’FF83
TCSR: .EQU H’FFA8
.ALIGN 2
MOV.B #H’**, ROH ;
MOV.B ROH, @EBR*:8 ; Set EBR*
; #BLKSTR is top address of block to be erased.
; #BLKEND is last address of block to be erased.
MOV.W #BLKSTR, R0 ; Top address of block to be erased
MOV.W #BLKEND, R2 ; Last address of block to be erased
ADDS #1, R2 ; Last address of block to be erased + 1 →R2
; Execute prewrite
MOV.W R0, R3 ; Top address of block to be erased
PREWRT: MOV.B #H’00, R6L ; Prewrite-verify fail counter
MOV.W #H’a, R5 ; Set prewrite loop counter
PREWRS: INC R6L ; Prewrite-verify fail counter + 1 →R6L
MOV.B #H’00 R1H ;
MOV.B R1H, @R3 ; Write H’00
MOV.W #H’A579, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set prewrite loop counter
BSET #0, @FLMCR:8 ; Set P bit
LOOPR1: SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOPR1 ; Wait loop
BCLR #0, @FLMCR:8 ; Clear P bit
MOV.W #H’A500, R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
MOV.B #H’c, R4H ; Set prewrite-verify loop counter
LOOPR2: DEC R4H ;
BNE LOOPR2 ; Wait loop
MOV.B @R3, R1H ; Read data = H’00?
BEQ PWVFOK ; If read data = H’00 branch to PWVFOK
CMP.B #H’06, R6L ; Prewrite-verify executed 6 times?
BEQ ABEND1 ; If prewrite-verify executed 6 times, branch to ABEND1
ADD.W R5 R5 ; Programming time ×2
BRA PREWRS ; Prewrite again
ABEND1: Programming error
PWVFOK: ADDS #1, R3 ; Address + 1 →R3
CMP.W R2, R3 ; Last address?
BNE PREWRT ; If not last address, prewrite next address
445
446
;Execute erase
ERASES: MOV.W #H’0000,R6 ; Erase-verify fail counter
MOV.W #H’d, R5 ; Set erase loop count
ERASE: ADDS #1, R6 ; Erase-verify fail counter + 1 →R6
MOV.W #H’e, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set erase loop counter
BSET #1, @FLMCR:8 ; Set E bit
LOOPE: NOP
NOP
NOP
NOP
SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOPE ; Wait loop
BCLR #1, @FLMCR:8 ; Clear E bit
MOV.W #H’A500,R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
; Execute erase-verify
MOV.W R0, R3 ; Top address of block to be erased
MOV.B #H’b, R4H ; Set erase-verify loop counter
BSET #3, @FLMCR:8 ; Set EV bit
LOOPEV: DEC R4H ;
BNE LOOPEV ; Wait loop
EVR2: MOV.B #H’FF, R1H ;
MOV.B R1H, @R3 ; Dummy write
MOV.B #H’c, R4H ; Set erase-verify loop counter
LOOPDW: DEC R4H ;
BNE LOOPDW ; Wait loop
MOV.B @R3+, R1H ; Read
CMP.B #H’FF, R1H ; Read data = H’FF?
BNE RERASE ; If read data ≠H’FF, branch to RERASE
CMP.W R2, R3 ; Last address of block?
BNE EVR2
BRA OKEND
RERASE: BCLR #3, @FLMCR:8 ; Clear EV bit
SUBS #1, R3 ; Erase-verify address – 1 →R3
MOV.W #H’0004,R4 ;
CMP.W R4 R6 ; Erase-verify fail count executed 4 times?
BPL BRER ; If R6≥4, branch to BRER (branch until R6 is 4 to 602)
ADD.W R5, R5 ; If R6<4, Erase time ×2 (execute when R6 is 1, 2, or 3)
BRER: MOV.W #H’025A,R4 ;
CMP.W R4, R6 ; Erase-verify executed 602 times?
BNE ERASE ; If erase-verify not executed 602 times, erase again
BRA ABEND2 ; If erase-verify executed 602 times, branch to ABEND2
OKEND: BCLR #3, @FLMCR:8 ; Clear EV bit
MOV.B #H’00, R6L ;
MOV.B R6L, @EBR*:8 ; Clear EBR*
One block erased
ABEND2: Erase error
447
Flowchart for Erasing Multiple Blocks
Figure 20-11 Multiple-Block Erase Flowchart
Start
Write 0 data to all addresses to be
erased (prewrite)*1
n = 1
Set erase block registers
(set bits of block to be erased to 1)
Enable watchdog timer*2
Select erase mode (E bit = 1 in FLMCR)
Wait (x)ms*5
Clear E bit
Disable watchdog timer
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tvs1)µs*6
Set top address of block as
verify address
Dummy write to verify address*3
(flash memory latches address)
Erase-verify
next block
Verify*4
(read data = H'FF?)
Last address
in block?
Address + 1 → Address
Clear EBR bit of erased block
All erased blocks
verified?
Clear EV bit
All blocks erased?
(EBR1 = EBR2 = 0?)
End of erase
n≥ N?*6
Erase error n + 1 → n
Double Erase time
No
Yes
No
No
Yes
No
Yes
No go
OK
Erasing
ends
All erased blocks
verified?
Erase-verify next block
Yes
Yes
No
Yes
Wait (tvs2)µs*6
n≥ 4?
No
(x × 2→x)
Notes: 1. Program all addresses to be
erased by following the prewrite
flowchart.
2. Set the watchdog timer overflow
interval to the value indicated in
table 20-10.
3. For the erase-verify dummy write,
write H'FF with a byte transfer
instruction.
4. Read the data to be verified with a
byte transfer instruction. When
erasing two or more blocks, clear
the bits of erased blocks in the
erase block register, so that only
unerased blocks will be erased
again.
5. The erase time x is successively
incremented by the initial set value
x 2 n–1 (n=1,2,3,4). After fourth
erasing, the erase time is fixed. An
initial value of 6.25 ms or less
should be set, and the time for one
erasure should be 50 ms or less.
6. tVS1: 4 µs or more
tVS2: 2 µs or more
N: 602 (Set N so that total
erase time does not exceed
30s.)
Sample Multiple-Block Erase Program: This program uses the following registers.
R0: Specifies blocks to be erased (set as explained below), and also stores address used in
prewrite and erase-verify.
R1H: Used to test bits 8 to 15 of R0 stores register read data, and also used for dummy write.
R1L: Used to test bits 0 to 15 of R0.
R2: Specifies address where address used in prewrite and erase-verify is stored.
R3: Stores address used in prewrite and erase-verify.
R4: Stores last address of block to be erased.
R5: Sets prewrite and erase timing loop counters.
R6L: Used for prewrite-verify and erase-verify fail count.
Arbitrary blocks can be erased by setting bits in R0. Write R0 with a word transfer instruction.
A bit map of R0 and a sample setting for erasing specific blocks are shown next.
Example: to erase blocks LB2, SB7, and SB0
R0 is set as follows:
MOV.W #H’0481,R0
MOV.W R0, @EBR1
The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a,
#b, #c, #d, and #e values according to tables 20-9 (1), (2), and 20-10.
LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit
R0
Corresponds to EBR1 Corresponds to EBR2
Setting 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1
LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit
R0
Corresponds to EBR1 Corresponds to EBR2
448
Notes: 1. In this sample program, the stack pointer (SP) is set at address FF80. As the stack area,
on-chip RAM addresses FF7E and FF7F are used. Therefore, when executing this
sample program, addresses FF7E and FF7F should not be used. In addition, the on-chip
RAM should not be disabled.
2. In this sample program, the program written in a ROM area (including external space)
is transferred into the RAM area and executed in the RAM to which the program is
transferred. #RAMSTR in the program is the starting destination address in RAM to
which the program is transferred. #RAMSTR must be set to an even number.
3. When executing this sample program in the on-chip ROM area or external space,
#RAMSTR should be set to #START.
FLMCR: .RQU H’FF80
EBR1: .EQU H’FF82
EBR2: .EQU H’FF83
TCSR: .EQU H’FFA8
STACK: .EQU H’FF80
.ALIGN 2
START: MOV.W #STACK, SP ; Set stack pointer
; Set the bits in R0 following the description on the previous page. This program is a sample program to erase
; all blocks. MOV.W #H’FFFF, R0 ; Select blocks to be erased (R0: EBR1/EBR2)
MOV.W R0, @EBR1 ; Set EBR1/EBR2
; #RAMSTR is starting destination address to which program is transferred in RAM.
; Set #RAMSTR to even number.
MOV.W #RAMSTR, R2 ; Starting transfer destination address (RAM)
MOV.W #ERVADR, R3 ;
ADD.W R3, R2 ; #RAMSTR + #ERVADR →R2
MOV.W #START, R3 ;
SUB.W R3, R2 ; Address of data area used in RAM
MOV.B #H’00, R1L : Used to test R1L bit in R0
PRETST: CMP.B #H’10, R1L ; R1L = H’10?
BEQ ERASES ; If finished checking all R0 bits, branch to ERASES
CMP.B #H’08, R1L ;
BMI EBR2PW ; Test EBR1 if R1L ≥8, or EBR2 if R1L < 8
MOV.B R1L, R1H ;
SUBX #H’08, R1H ; R1L – 8 →R1H
BTST R1H, R0H ; Test R1H bit in EBR1 (R0H)
BNE PREWRT ; If R1H bit in EBR1 (R0H) is 1, branch to PREWRT
BRA PWADD1 ; If R1H bit in EBR1 (R0H) is 0, branch to PWADD1
EBR2PW: BTST R1L, R0L ; Test R1L bit in EBR2 (R0L)
BNE PREWRT ; If R1L bit in EBR2 (R0H) is 1, branch to PREWRT
PWADD1: INC R1L ; R1L + 1 →R1L
MOV.W @R2+, R3 ; Dummy-increment R2
BRA PRETST ;
; Execute prewrite
449
PREWRT: MOV.W @R2+, R3 ; Prewrite starting address
PREW: MOV.B #H’00, R6L ; Prewrite-verify fail counter
MOV.W #H’a, R5 ; Prewrite-verify loop counter
PREWRS: INC R6L ; Prewrite-verify fail counter + 1 →R6L
MOV.B #H’00 R1H ;
MOV.B R1H, @R3 ; Write H’00
MOV.W #H’A579, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set prewrite loop counter
BSET #0, @FLMCR:8 ; Set P bit
LOOPR1: SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOPR1 ; Wait loop
BCLR #0, @FLMCR:8 ; Clear P bit
MOV.W #H’A500, R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
MOV.B #H’c, R4H ; Set prewrite-verify loop counter
LOOPR2: DEC R4H ;
BNE LOOPR2 ; Wait loop
MOV.B @R3, R1H ; Read data = H’00?
BEQ PWVFOK ; If read data = H’00 branch to PWVFOK
CMP.B #H’06, R6L ; Prewrite-verify executed 6 times?
BEQ ABEND1 ; If prewrite-verify executed 6 times, branch to ABEND1
ADD.W R5, R5 ; Programming time ×2
BRA PREWRS ; Prewrite again
ABEND1: Programming error
PWVFOK: ADDS #1, R3 ; Address + 1 →R3
MOV.W @R2, R4 ; Top address of next block
CMP.W R4, R3 ; Last address?
BNE PREW ; If not last address, prewrite next address
PWADD2: INC R1L ; Used to test R1L+1 bit in R0
BRA PRETST ; Branch to PRETST
; Execute erase
ERASES: MOV.W #H’0000, R6 ; Erase-verify fail counter
MOV.W #H’d, R5 ; Set erase loop count
ERASE: ADDS #1, R6 ; Erase-verify fail counter + 1 →R6
MOV.W #H’e, R4 ;
MOV.W R4, @TCSR ; Start watchdog timer
MOV.W R5, R4 ; Set erase loop counter
BSET #1, @FLMCR:8 ; Set E bit
LOOPE: NOP
NOP
NOP
NOP
SUBS #1, R4 ;
MOV.W R4, R4 ;
BNE LOOPE ; Wait loop
450
451
BCLR #1, @FLMCR:8 ; Clear E bit
MOV.W #H’A500, R4 ;
MOV.W R4, @TCSR ; Stop watchdog timer
; Execute erase-verify
EVR: MOV.W #RAMSTR, R2 ; Starting transfer destination address (RAM)
MOV.W #ERVADR, R3 ;
ADD.W R3, R2 ; #RAMSTR + #ERVADR →R2
MOV.W #START, R3 ;
SUB.W R3, R2 ; Address of data area used in RAM
MOV.B #H’00, R1L ; Used to test R1L bit in R0
MOV.B #H’b, R4H ; Set erase-verify loop counter
BSET #3, @FLMCR:8 ; Set EV bit
LOOPEV: DEC R4H ;
BNE LOOPEV ; Wait loop
EBRTST: CMP.B #H’10, R1L ; R1L = H’10?
BEQ HANTEI ; If finished checking all R0 bits, branch to HANTEI
CMP.B #H’08, R1L ;
BMI EBR2EV ; Test EBR1 if R1L ≥8, or EBR2 if R1L < 8
MOV.B R1L, R1H ;
SUBX #H’08, R1H ; R1L – 8 →R1H
BTST R1H, R0H ; Test R1H bit in EBR1 (R0H)
BNE ERSEVF ; If R1H bit in EBR1 (R0H) is 1, branch to ERSEVF
BRA ADD01 ; If R1H bit in EBR1 (R0H) is 0, branch to ADD01
EBR2EV: BTST R1L, R0L ; Test R1L bit in EBR2 (R0L)
BNE ERSEVF ; If R1L bit in EBR2 (R0H) is 1, branch to ERSEVF
ADD01: INC R1L ; R1L + 1 →R1L
MOV.W @R2+, R3 ; Dummy-increment R2
BRA EBRTST ;
ERASE1: BRA ERASE ; Branch to ERASE via Erase 1
ERSEVF: MOV.W @R2+, R3 ; Top address of block to be erase-verified
EVR2: MOV.B #H’FF, R1H ;
MOV.B R1H, @R3 ; Dummy write
MOV.B #H’c, R4H ; Set erase-verify loop counter
LOOPEP: DEC R4H ;
BNE LOOPEP ; Wait loop
MOV.B @R3+, R1H ; Read
CMP.B #H’FF, R1H ; Read data = H’FF?
BNE BLKAD ; If read data ≠H’FF branch to BLKAD
MOV.W @R2, R4 ; Top address of next block
CMP.W R4, R3 ; Last address of block?
BNE EVR2 ;
CMP.B #H’08, R1L ;
BMI SBCLR ; Test EBR1 if R1L ≥8, or EBR2 if R1L < 8
MOV.B R1L, R1H ;
SUBX #H’08, R1H ; R1L – 8 →R1H
BCLR R1H, R0H ; Clear R1H bit in EBR1 (R0H)
BRA BLKAD ;
SBCLR: BCLR R1L, R0L ; Clear R1L bit in EBR2 (R0L)
BLKAD: INC R1L ; R1L + 1 → R1L
BRA EBRTST ;
HANTEI: BCLR #3, @FLMCR:8 ; Clear EV bit
MOV.W R0, @EBR1 ;
BEQ EOWARI ; If EBR1/EBR2 is all 0, erasing ended normally
MOV.W #H’0004, R4 ;
CMP.W R4, R6 ; Erase-verify fail count executed 4 times?
BPL BRER ; If R6≥4, branch to BRER (branch until R6 is 4 to 602)
ADD.W R5, R5 ; If R6<4, Erase time ×2 (execute when R6 is 1, 2, or 3)
BRER: MOV.W #H’025A, R4 ;
CMP.W R4, R6 ; Erase-verify executed 602 times?
BNE ERASE1 ; If erase-verify not executed 602 times, erase again
BRA ABEND2 ; If erase-verify executed 602 times, branch to ABEND2
;———< Block address table used in erase-verify> ———
.ALIGN 2
ERVADR: .DATA.W H’0000 ; SB0
.DATA.W H’0080 ; SB1
.DATA.W H’0100 ; SB2
.DATA.W H’0180 ; SB3
.DATA.W H’0200 ; SB4
.DATA.W H’0400 ; SB5
.DATA.W H’0800 ; SB6
.DATA.W H’0C00 ; SB7
.DATA.W H’1000 ; LB0
.DATA.W H’2000 ; LB1
.DATA.W H’4000 ; LB2
.DATA.W H’6000 ; LB3
.DATA.W H’8000 ; LB4
.DATA.W H’A000 ; LB5
.DATA.W H’C000 ; LB6
.DATA.W H’EF80 ; LB7
.DATA.W H’F780 ; FLASH END
EOWARI: Erase end
ABEND2: Erase error
452
Loop Counter Values in Programs and Watchdog Timer Overflow Interval Settings:
The setting of #a, #b, #c, #d, and #e values in the programs depends on the clock frequency.
Tables 20-9 (1) and (2) indicate sample loop counter settings for typical clock frequencies.
However, #e is set according to table 20-10.
As a software loop is used, calculated values including percent errors may not be the same as actual
values. Therefore, the values are set so that the total programming time and total erase time do not
exceed 1 ms and 30 s, respectively.
The maximum number of writes in the program, N, is set to 6.
Programming and erasing in accordance with the flowcharts is achieved by setting #a, #b, #c, and
#d in the programs as shown in tables 20-9 (1) and (2). #e should be set as shown in table 20-10.
Wait state insertion is inhibited in these programs. If wait states are to be used, the setting should be
made after the program ends. The setting value for the watchdog timer (WDT) overflow time is
calculated based on the number of instructions between starting and stopping of the WDT, including
the write time and erase time. Therefore, no other instructions should be added between starting
and stopping of the WDT in this program example.
Table 20-9 (1) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with
Program Running in the On-Chip Memory (RAM)
Clock Frequency
f = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz
Time Counter Counter Counter Counter
Variable Setting Setting Value Setting Value Setting Value Setting Value
a(f) Programming time 15.8 µs H'001F H'0013 H'000F H'0003
(initial setting value)
b(f) tvs1 4 µs H'0B H'07 H'06 H'02
c(f) tvs2 2 µ s H'06 H'04 H'03 H'01
d(f) Erase time 6.25 ms H'1869 H'0F42 H'0C34 H'030D
(initial setting value)
453
454
Table 20-9 (2) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with
Program Running in the External Device
Clock Frequency
f = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz
Time Counter Counter Counter Counter
Variable Setting Setting Value Setting Value Setting Value Setting Value
a(f) Programming time 15.8 µs H'000A H'0006 H'0005 H'0001
(initial setting value)
b(f) tvs1 4 µs H'04 H'03 H'02 H'01
c(f) tvs2 2 µs H'02 H'02 H'01 H'01
d(f) Erase time 6.25 ms H'0823 H'0516 H'0411 H'0104
(initial setting value)
Formula: When using a clock frequency not shown in tables 20-9 (1) and (2), follow the formula
below. The calculation is based on a clock frequency of 10 MHz.
After calculating a(f) and d(f) in the decimal system, omit the first decimal figures, and convert them
to the hexadecimal system, so that a(f) and d(f) are set to 15.8 µs or less and 6.25 ms or less,
respectively.
After calculating b(f) and c(f) in the decimal system, raise the first decimal figures, and convert them
to the hexadecimal system, so that b(f) and c(f) are set to 4 µs or more and 2 µs or more, respectively.
Clock Frequency f [MHz]
a (f) to d (f) = ×a (f = 10) to d (f = 10)
10
Examples for a program running in on-chip memory (RAM) at a clock frequency of 12 MHz:
12
a (f) = ×19 = 22.8 ≈22 = H'0016
10
12
b (f) = ×7 = 8.4 ≈9 = H'09
10
12
c (f) = ×4 = 4.8 ≈5 = H'05
10
12
d (f) = ×3906 = 4687.2 ≈4687 = H'124F
10
Table 20-10 Watchdog Timer Overflow Interval Settings
(#e Setting Value According to Clock Frequency)
Variable
Clock Frequency [MHz] e (f)
10 MHz ≤frequency ≤16 MHz H'A57F
2 MHz ≤frequency < 10 MHz H'A57E
455
20.4.7 Prewrite Verify Mode
Prewrite-verify mode is a verify mode used when programming all bits to equalize their threshold
voltages before erasing them.
To program all bits, follow the prewrite algorithm shown in figure 20-10. The procedure is to
program all flash memory data to H’00 by using H’00 write data. H’00 should also be written when
using RAM for flash memory emulation (when prewriting a RAM area). (This also applies when
using RAM to emulate flash memory erasing with an emulator or other support tool.) After the
necessary programming time has elapsed, exit program mode (by clearing the P bit to 0) and select
prewrite-verify mode (leave the P, E, PV, and EV bits all cleared to 0). In prewrite-verify mode, a
prewrite-verify voltage is applied to the memory cells at the read address. If the flash memory is
read in this state, the data at the read address will be read. After selecting prewrite-verify mode, wait
4 µs or more before reading.
Note: For a sample prewriting program, see the prewrite subroutine in the sample erasing program.
20.4.8 Protect Modes
Flash memory can be protected from programming and erasing by software or hardware methods.
These two protection modes are described below.
Software Protection: Prevents transitions to program mode and erase mode even if the P or E bit is
set in the flash memory control register (FLMCR). Details are as follows.
Function
Protection Description Program Erase Verify*1
Block Individual blocks can be protected from erasing Disabled Disabled Enabled
protect and programming by the erase block registers
(EBR1 and EBR2). If H'00 is set in EBR1 and
EBR2, all blocks are protected from erasing
and programming.
Emulation When the RAMS or RAM0 bit, but not both, is Disabled Disabled*3Enabled
protect*2set in the wait-state control register (WSCR),
all blocks are protected from programming and
erasing.
Notes: 1. Three modes: program-verify, erase-verify, and prewrite-verify.
2. Except in RAM areas overlapped onto flash memory.
3. All blocks are erase-disabled. It is not possible to specify individual blocks.
456
Hardware Protection: Suspends or disables the programming and erasing of flash memory, and
resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2).
Details of hardware protection are as follows.
Function
Protection Description Program Erase Verify*1
Programing When 12 V is not applied to the FVPP pin, Disabled Disabled*2Disabled
voltage (VPP) FLMCR, EBR1, and EBR2 are initialized,
protect disabling programming and erasing. To obtain
this protection, VPP should not exceed VCC.*3
Reset and When a reset occurs (including a watchdog Disabled Disabled*2Disabled
standby timer reset) or standby mode is entered,
protect FLMCR, EBR1, and EBR2 are initialized,
disabling programming and erasing. Note that
RES input does not ensure a reset unless the
RES pin is held low for at least 20 ms at
power-up (to enable the oscillator to settle),
or at least ten system clock cycles (10ø) during
operation.
Interrupt protect To prevent damage to the flash memory, if Disabled Disabled*2Enabled
interrupt input occurs while flash memory is being
programmed or erased, programming or erasing
is aborted immediately. The settings in FLMCR,
EBR1, and EBR2 are retained. This type of
protection can be cleared only by a reset.
Notes: 1. Three modes: program-verify, erase-verify, and prewrite-verify.
2. All blocks are erase-disabled. It is not possible to specify individual blocks.
3. For details, see section 20.7, Flash Memory Programming and Erasing Precautions.
20.4.9 Interrupt Handling during Flash Memory Programming and Erasing
If an interrupt occurs*1 while flash memory is being programmed or erased (while the P or E bit of
FLMCR is set), the following operating states can occur.
• If an interrupt is generated during programming or erasing, programming or erasing is aborted to
protect the flash memory. Since memory cell values after a forced interrupt are indeterminate,
the system will not operate correctly after such an interrupt.
• Program runaway may result because the vector table could not be read correctly in interrupt
exception handling during programming or erasure*2.
For NMI interrupts while flash memory is being programmed or erased, these malfunction and
runaway problems can be prevented by using the RAM overlap function with the settings described
below.
1. Do not store the NMI interrupt-handling routine*3 in the flash memory area (neither H'0000 to
H'EF7F in mode 2 nor H'0000 to H'F77F in mode 3). Store it elsewhere (in RAM, for example).
2. Set the NMI interrupt vector in address H'F806 in RAM (corresponding to H'0006 in flash
memory).
3. After the above settings, set both the RAMS and RAM0 bits to 1 in WSCR.*4
Due to the setting of step 3, if an interrupt signal is input while 12 V is applied to the FVPP pin, the
RAM overlap function is enabled and part of the RAM (H'F800 to H'F87F) is overlapped onto the
small-block area of flash memory (H'0000 to H'007F). As a result, when an interrupt is input, the
vector is read from RAM, not flash memory, so the interrupt is handled normally even if flash
memory is being programmed or erased. This can prevent malfunction and runaway.
Notes: 1. When the interrupt mask bit (I) of the condition control register (CCR) is set to 1, all
interrupts except NMI are masked. For details see (2) in section 2.2.2, Control
Registers.
2. The vector table might not be read correctly for one of the following reasons:
• If flash memory is read while it is being programmed or erased (while the P or E bit
of FLMCR is set), the correct value cannot be read.
• If no value has been written for the NMI entry in the vector table yet, NMI exception
handling will not be executed correctly.
3. This routine should be programmed so as to prevent microcontroller runaway.
4. For details on WSCR settings, see section 20.2.4, Wait-State Control Register.
Notes on Interrupt Handling in Boot Mode
In boot mode, the settings described above concerning NMI interrupts are carried out, and NMI
interrupt handling (but not other interrupt handling) is enabled while the boot program is executing.
Note the following points concerning the user program.
• If interrupt handling is required
— Load the NMI vector (H'F780) into address H'F806 in RAM (the 38th byte of the transferred
user program should be H'F780).
— The interrupt handling routine used by the boot program is stored in addresses H'F780 to
H'F78F in RAM. Make sure that the user program does not overwrite this area.
• If interrupt handling is not required
Since the RAMS and RAM0 bits remain set to 1 in WSCR, make sure that the user program
disables the RAM overlap by clearing the RAMS and RAM0 bits both to 0.
457
20.5 Flash Memory Emulation by RAM
Erasing and programming flash memory takes time, which can make it difficult to tune parameters
and other data in real time. If necessary, real-time updates of flash memory can be emulated by
overlapping the small-block flash-memory area with part of the RAM (H'F800 to H'F97F). This
RAM reassignment is performed using bits 7 and 6 of the wait-state control register (WSCR). See
figure 20-11.
After a flash memory area has been overlapped by RAM, the RAM area can be accessed from two
address areas: the overlapped flash memory area, and the original RAM area (H'F800 to H'F97F).
Table 20-11 indicates how to reassign RAM.
Wait-State Control Register (WSCR)*2
Table 20-11 RAM Area Selection
Bit 7 Bit 6
RAMS RAM0 RAM Area ROM Area
0 0 None —
0 1 H'F880 to H'F8FF H'0080 to H'00FF
1 0 H'F880 to H'F97F H'0080 to H'017F
1 1 H'F800 to H'F87F H'0000 to H'007F
Bit
Initial value*1
Read/Write
7
RAMS
0
R/W
6
RAM0
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
Notes: 1.
2.
WSCR is initialized by a reset and in hardware standby mode. It is not initialized in
software standby mode.
For details of WSCR settings, see section 20.2.4, Wait-State Control Register (WSCR).
458
Example of Emulation of Real-Time Flash-Memory Update
Figure 20-12 Example of RAM Overlap
H'007F
H'0080
H'00FF
H'0100
H'0000
H'F77F
H'F780
H'F880
H'F8FF
H'FF7F
Small-block
area (SB1)
Flash memory
address space
Overlapped
RAM
Overlapped RAM
On-chip
RAM area
459
Procedure
1. Overlap part of RAM (H'F880 to H'F8FF) onto the area requiring real-time update (SB1).
(Set WSCR bits 7 and 6 to 01.)
2. Perform real-time updates in the overlapping RAM.
3. After finalization of the update data, clear the RAM overlap (by clearing the RAMS and
RAM0 bits).
4. Read the data written in RAM addresses H'F880 to H'F8FF out externally, then program
the flash memory area, using this data as part of the program data.
Notes on Use of RAM Emulation Function
• Notes on Applying, Releasing, and Shutting Off the Programming Voltage (VPP)
Care is necessary to avoid errors in programming and erasing when applying, releasing, and
shutting off VPP, just as in the on-board programming modes. In particular, even if the
emulation function is being used, make sure that the watchdog timer is set when the P or E bit of
the flash memory control register (FLMCR) has been set, to prevent errors in programming and
erasing due to program runaway while VPP is applied.
For details see section 20.7, Flash Memory Programming and Erasing Precautions (5).
460
20.6 Flash Memory PROM Mode (H8/3437F)
20.6.1 PROM Mode Setting
The on-chip flash memory of the H8/3437F can be programmed and erased not only in the on-board
programming modes but also in PROM mode, using a general-purpose PROM programmer.
20.6.2 Socket Adapter and Memory Map
Programs can be written and verified by attaching a special 100-pin/32-pin socket adapter to the
PROM programmer. Table 20-12 gives ordering information for the socket adapter. Figure 20-13
shows a memory map in PROM mode. Figure 20-14 shows the socket adapter pin interconnections.
Table 20-12 Socket Adapter
Microcontroller Package Socket Adapter
HD64F3437F16 100-pin QFP HS3434ESHF1H
HD64F3437TF16 100-pin TQFP HS3434ESNF1H
Figure 20-13 Memory Map in PROM Mode
H8/3437F H'0000
H'F77F
H'0000
H'F77F
On-chip ROM area
MCU mode PROM mode
1 output
H'1FFFF
461
Figure 20-14 Wiring of Socket Adapter
H8/3437F
Pin Name
FP-100B, TFP-100B
8
7
18
19
22
82
83
84
85
86
87
88
89
79
78
77
76
75
74
73
72
67
66
65
64
63
62
61
60
24, 25, 29,
32, 16
5, 6, 23,35
36, 37
4, 9, 59
46
15, 70, 71, 92
1
2, 3
Other pins
1
26
2
3
31
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
32
16
HN28F101 (32 Pins)
Pin No.
Pin Name
VPP
FA9
FA16
FA15
WE
FO0
FO1
FO2
FO3
FO4
FO5
FO6
FO7
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
OE
FA10
FA11
FA12
FA13
FA14
CE
VCC
VSS
Socket Adapter Pin No.
STBY/FVPP
NMI
P95
P94
P93
P30
P31
P32
P33
P34
P35
P36
P37
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P91, P90, P63,
P64, P97
MD1, MD0, P92, P67
AVref, AVCC
VCCB, VCC
AVSS
VSS
RES
XTAL, EXTAL
NC (OPEN)
Power-on
reset circuit
Oscillator circuit
Legend
VPP:
FO7 to FO0:
FA16 to FA0:
OE:
CE:
WE:
Programming power supply
Data input/output
Address input
Output enable
Chip enable
Write enable
462
20.6.3 Operation in PROM Mode
The program/erase/verify specifications in PROM mode are the same as for the standard HN28F101
flash memory. However, since the H8/3437F does not support product name recognition mode, the
programmer cannot be automatically set with the device name. Table 20-13 indicates how to select
the various operating modes.
Table 20-13 Operating Mode Selection in PROM Mode
Pins
Mode FVPP VCC CE OE WE D7to D0A16 to A0
Read Read VCC VCC L L H Data output Address input
Output VCC VCC L H H High impedance
disable
Standby VCC VCC H X X High impedance
Command Read VPP VCC L L H Data output
write Output VPP VCC L H H High impedance
disable
Standby VPP VCC H X X High impedance
Write VPP VCC L H L Data input
Note: *Be sure to set the FVPP pin to VCC in these states. If it is set to 0 V, hardware standby mode
will be entered, even when in PROM mode, resulting in incorrect operation.
Legend
L: Low level
H: High level
VPP:V
PP level
VCC:V
CC level
X: Don’t care
VH: 11.5 V ≤VH ≤12.5 V
463
Table 20-14 PROM Mode Commands
1st Cycle 2nd Cycle
Command Cycles Mode Address Data Mode Address Data
Memory read 1 Write X H'00 Read RA Dout
Erase setup/erase 2 Write X H'20 Write X H'20
Erase-verify 2 Write EA H'A0 Read X EVD
Auto-erase setup/ 2 Write X H'30 Write X H'30
auto-erase
Program setup/ 2 Write X H'40 Write PA PD
program
Program-verify 2 Write X H'C0 Read X PVD
Reset 2 Write X H'FF Write X H'FF
PA: Program address
EA: Erase-verify address
RA: Read address
PD: Program data
PVD: Program-verify output data
EVD: Erase-verify output data
464
High-Speed, High-Reliability Programming: Unused areas of the H8/3437F flash memory
contain H'FF data (initial value). The H8/3437F flash memory uses a high-speed, high-reliability
programming procedure. This procedure provides enhanced programming speed without subjecting
the device to voltage stress and without sacrificing the reliability of programmed data. Figure 20-15
shows the basic high-speed, high-reliability programming flowchart. Tables 20-15 and 20-16 list the
electrical characteristics during programming.
Figure 20-15 High-Speed, High-Reliability Programming
Start
Set VPP = 12.0 V ±0.6 V
Address = 0
n = 0
Program command
Program setup command
n + 1 → n
Wait (25 µs)
Program-verify command
Wait (6 µs)
Address + 1 → address
Verification?
Last address?
Set VPP = VCC
End Fail
n = 20?
No go
No
Yes
Go
Yes
No
465
High-Speed, High-Reliability Erasing: The H8/3437F flash memory uses a high-speed, high-
reliability erasing procedure. This procedure provides enhanced erasing speed without subjecting
the device to voltage stress and without sacrificing data reliability . Figure 20-16 shows the basic
high-speed, high-reliability erasing flowchart. Tables 20-15 and 20-16 list the electrical
characteristics during erasing.
Figure 20-16 High-Speed, High-Reliability Erasing
Start
Program all bits to 0*
Address = 0
n = 0
Wait (10 ms)
Erase setup/erase command
n + 1 → n
Erase-verify command
Wait (6 µs)
Address + 1 → address
Verification?
Last address?
End Fail
n = 3000?
No go
No
Yes
Go
Yes
No
Follow the high-speed, high-reliability programming flowchart in programming all bits. If some bits
are already programmed to 0, program only the bits that have not yet been programmed.
Note: *
466
Table 20-15 DC Characteristics in PROM Mode
(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta= 25°C ±5°C)
Item Symbol Min Typ Max Unit Test Conditions
Input high FO7to FO0, VIH 2.2 — VCC + 0.3 V
voltage FA16 to FA0,
OE, CE, WE
Input low FO7to FO0, VIL –0.3 — 0.8 V
voltage FA16 to FA0,
OE, CE, WE
Output high FO7to FO0VOH 2.4 — — V IOH = –200 µA
voltage
Output low FO7to FO0VOL — — 0.45 V IOL = 1.6 mA
voltage
Input leakage FO7to FO0, | ILI | — — 2 µA Vin = 0 to VCC
current FA16 to FA0,
OE, CE, WE
VCC current Read ICC —4080 mA
Program ICC —4080 mA
Erase ICC —4080 mA
FVPP current Read IPP — — 10 µA VPP = 2.7 V to
5.5 V
—1020 mAV
PP = 12.6 V
Program IPP —2040 mAV
PP = 12.6 V
Erase IPP —2040 mAV
PP = 12.6 V
467
Table 20-16 AC Characteristics in PROM Mode
(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta= 25°C ±5°C)
Item Symbol Min Typ Max Unit Test Conditions
Command write cycle tCWC 120 — — ns Figure 20-17
Address setup time tAS 0 ——nsFigure 20-18*
Address hold time tAH 60——nsFigure 20-19
Data setup time tDS 50——ns
Data hold time tDH 10——ns
CE setup time tCES 0 ——ns
CE hold time tCEH 0 ——ns
V
PP setup time tVPS 100 — — ns
VPP hold time tVPH 100 — — ns
WE programming pulse width tWEP 70——ns
WE programming pulse high time tWEH 40——ns
OE setup time before command write tOEWS 0 ——ns
OE setup time before verify tOERS 6 ——µs
Verify access time tVA — — 500 ns
OE setup time before status polling tOEPS 120 — — ns
Status polling access time tSPA — — 120 ns
Program wait time tPPW 25——ns
Erase wait time tET 9—11ms
Output disable time tDF 0 — 40 ns
Total auto-erase time tAET 0.5 — 30 s
Note: CE, OE, and WE should be high during transitions of VPP from 5 V to 12 V and from 12 V to
5V.
*Input pulse level: 0.45 V to 2.4 V
Input rise time and fall time ≤10 ns
Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output
468
Figure 20-17 Auto-Erase Timing
Figure 20-18 High-Speed, High-Reliability Programming Timing
tVPH
tVPS
tCEH
tCES
tOEWS tWEP tCEH
tCES
tCWC
tWEP
tDS tDH tDS tDH
tAS tAH
tPPW
tCES
tWEH
tCEH
tWEP tOERS
tDH
tDS
tVA tDF
Command
input
Command
input
Data
input
Command
input
Command
input
Valid data
output
Data
input
Program setup Program Program-verify
Valid address
Address
5.0 V
12 V
5.0 V
VCC
VPP
CE
OE
WE
I/O7
I/O0 to I/O6
Note: Program-verify data output values may be intermediate between 1 and 0 before programming has been completed.
Valid data
output
Auto-erase setup Auto-erase and status polling
Address
Command
input
Status polling
Command
input
Command
input Command
input
5.0 V
12 V
5.0 V
VCC
VPP
CE
OE
WE
I/O7
I/O0 to I/O6
tVPS tVPH
tCEH tCES
tCES
tOEWS tWEP tCEH
tCES
tCWC
tWEP
tOEPS
tAET
tWEH
tDS tDH tDS tDH tSPA tDF
469
Figure 20-19 Erase Timing
Address
5.0 V
12 V
5.0 V
VCC
VPP
CE
OE
WE
I/O0 to I/O7
Erase setup Erase Erase-verify
Valid address
Command
input Command
input Command
input
Valid data
output
tVPS tVPH
tAS tAH
tOEWS tCWC
tCES tWEP
tCEH
tDH
tDS
tWEH
tDS tDH tDS tDH
tVA
tDF
tCES tWEP
tCEH tCES
tET tWEP
tCEH
tOERS
Note: Erase-verify data output values may be intermediate between 1 and 0 before erasing has been completed.
470
20.7 Flash Memory Programming and Erasing Precautions
Read these precautions before using PROM mode, on-board programming mode, or flash memory
emulation by RAM.
(1) Program with the specified voltages and timing.
The rated programming voltage (VPP) of the flash memory is 12.0 V.
If the PROM programmer is set to Hitachi HN28F101 specifications, VPP will be 12.0 V. Applying
voltages in excess of the rating can permanently damage the device. Take particular care to ensure
that the PROM programmer peak overshoot does not exceed the rated limit of 13 V.
(2) Before programming, check that the chip is correctly mounted in the PROM
programmer. Overcurrent damage to the device can result if the index marks on the PROM
programmer socket, socket adapter, and chip are not correctly aligned.
(3) Don’t touch the socket adapter or chip while programming. Touching either of these can
cause contact faults and write errors.
(4) Set H'FF as the PROM programmer buffer data for addresses H'F780 to H'1FFFF. The
H8/3437F PROM size is 60 kbytes. Addresses H'F780 to H'1FFFF always read H'FF, so if
H'FF is not specified as programmer data, a verify error will occur.
(5) Notes on applying, releasing, and shutting off the programming voltage (VPP)
Note: In this section, the application, release, and shutting-off of VPP are defined as follows.
Application: A rise in voltage from VCC to 12 V ± 0.6 V.
Release: A drop in voltage from 12 V ± 0.6 V to VCC.
Shut-off: No applied voltage (floating).
• Apply the programming voltage (VPP) after the rise of VCC, and release VPP before shutting off
VCC.
To prevent unintended programming or erasing of flash memory, in these power-on and power-
off timings, the application, release, and shutting-off of VPP must take place when the
microcontroller is in a stable operating condition as defined below.
Stable operating condition
— The VCC voltage must be stabilized within the rated voltage range (VCC = 2.7 V to 5.5 V)
If VPP is applied, released, or shut off while the microcontroller’s VCC voltage is not within
the rated voltage range (VCC = 2.7 to 5.5 V), since microcontroller operation is unstable, the
flash memory may be programmed or erased by mistake. This can occur even if VCC = 0 V.
471
To prevent changes in the VCC power supply when VPP is applied, be sure that the power
supply is adequately decoupled with inserting bypass capacitors.
— Clock oscillation must be stabilized (the oscillation settling time must have elapsed), and
oscillation must not be stopped
When turning on VCC power, hold the RES pin low during the oscillation settling time
(tOSC1 = 20 ms), and do not apply VPP until after this time.
— The microcontroller must be in the reset state, or in a state in which a reset has ended
normally (reset has been released) and flash memory is not being accessed
Apply or release VPP either in the reset state, or when the CPU is not accessing flash
memory (when a program in on-chip RAM or external memory is executing). Flash memory
cannot be read normally at the instant when VPP is applied or released. Do not read flash
memory while VPP is being applied or released.
For a reset during operation, apply or release VPP only after the RES pin has been held low
for at least ten system clock cycles (10ø).
— The P and E bits must be cleared in the flash memory control register (FLMCR)
When applying or releasing VPP, make sure that the P or E bit is not set by mistake.
— No program runaway
When VPP is applied, program execution must be supervised, e.g. by the watchdog timer.
These power-on and power-off timing requirements should also be satisfied in the event of a
power failure and in recovery from a power failure. If these requirements are not satisfied,
overprogramming or overerasing may occur due to program runaway etc., which could cause
memory cells to malfunction.
• The VPP flag is set and cleared by a threshold decision on the voltage applied to the FVPP pin.
The threshold level is between approximately VCC + 2 V to 11.4 V.
When this flag is set, it becomes possible to write to the flash memory control register (FLMCR)
and the erase block registers (EBR1 and EBR2), even though the VPP voltage may not yet have
reached the programming voltage range of 12.0 ± 0.6 V.
Do not actually program or erase the flash memory until VPP has reached the programming
voltage range.
The programming voltage range for programming and erasing flash memory is 12.0 ± 0.6 V
(11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range.
When not programming or erasing the flash memory, ensure that the VPP voltage does not
472
exceed the VCC voltage. This will prevent unintended programming and erasing.
• In this chip, the same pin is used for STBY and FVPP. When this pin is driven low, a transition
is made to hardware standby mode. This happens not only in the normal operating modes
(modes 1, 2, and 3), but also when programming the flash memory with a PROM programmer.
When programming with a PROM programmer, therefore, use a programmer which sets this pin
to the VCC level when not programming (FVPP=12 V).
Note: Here, VPP application, release, and cutoff are defined as follows:
Application: Raising the voltage from VCC to 12±0.6 V.
Release: Dropping the voltage from 12±0.6 V to VCC.
Cutoff: Halting voltage application (setting the floating state).
Figure 20-20 VPP Power-On and Power-Off Timing
tOSC1
2.7 to 5.5 V
12 ± 0.6 V
VCC + 2 V to 11.4 V
VCCV
12 ± 0.6 V
VCCV
0 µs min
0 µs min
0 µs min
0 to VCCV
0 to VCCV
Min 10ø
(when RES is low)
ø
VCC
VPP
VPP
RES
Boot mode
User program
mode
Timing at which boot
program branches
to RAM area
Periods during which the VPP flag is being set or
cleared and flash memory must not be accessed
473
(6) Do not apply 12 V to the FVPP pin during normal operation.
To prevent accidental programming or erasing due to microcontroller program runaway etc.,
apply 12 V to the VPP pin only when the flash memory is programmed or erased, or when flash
memory is emulated by RAM. Overprogramming or overerasing due to program runaway can
cause memory cells to malfunction. Avoid system configurations in which 12 V is always
applied to the FVPP pin.
While 12 V is applied, the watchdog timer should be running and enabled to halt runaway
program execution, so that program runaway will not lead to overprogramming or overerasing.
(7) Design a current margin into the programming voltage (VPP) power supply. Ensure that
VPP will not depart from 12.0 ±0.6 V (11.4 V to 12.6 V) during programming or erasing.
Programming and erasing may become impossible outside this range.
(8) Ensure that peak overshoot does not exceed the rated value at the FVPP and MD1pins.
Connect decoupling capacitors as close to the FVPP and MD1pins as possible.
Also connect decoupling capacitors to the MD1pin in the same way when boot mode is used.
Figure 20-21 VPP Power Supply Circuit Design (Example)
(9) Use the recommended algorithms for programming and erasing flash memory. These
algorithms are designed to program and erase without subjecting the device to voltage stress
and without sacrificing the reliability of programmed data.
Before setting the program (P) or erase (E) bit in the flash memory control register (FLMCR),
set the watchdog timer to ensure that the P or E bit does not remain set for more than the
specified time.
0.01 µF1.0 µF
12 V MD1
0.01 µF1.0 µF
12 V FVPP
H8/3437F
474
475
(10)For details on interrupt handling while flash memory is being programmed or erased, see the
notes on NMI interrupt handling in section 20.4.9, Interrupt Handling during Flash Memory
Programming and Erasing.
(11)Cautions on Accessing Flash Memory Control Registers
(a) Flash memory control register access state in each operating mode
The H8/3437F has flash memory control registers located at addresses H'FF80 (FLMCR),
H'FF82 (EBR1), and H'FF83 (EBR2). These registers can only be accessed when 12 V is
applied to the flash memory program power supply pin, FVPP.
Table 20-17 shows the area accessed for the above addresses in each mode, when 12 V is
and is not applied to FVPP.
Table 20-17 Area Accessed in Each Mode with 12V Applied and Not Applied to FVpp
Mode 1 Mode 2 Mode 3
12 V applied Reserved area Flash memory control Flash memory control
to FVPP (always H'FF) register (initial value H'80) register (initial value H'80)
12 V not applied External address External address space Reserved area
to FVPP space (always H'FF)
(b) When a flash memory control register is accessed in mode 2 (expanded mode with on-chip
ROM enabled)
When a flash memory control register is accessed in mode 2, it can be read or written to if
12 V is being applied to FVPP, but if not, external address space will be accessed. It is
therefore essential to confirm that 12 V is being applied to the FVPP pin before accessing
these registers.
(c) To check for 12 V application/non-application in mode 3 (single-chip mode)
When address H'FF80 is accessed in mode 3, if 12 V is being applied to FVPP, FLMCR is
read/written to, and its initial value after reset is H'80. When 12 V is not being applied to
FVPP, FLMCR is a reserved area that cannot be modified and always reads H'FF. Since bit
7 (corresponding to the VPP bit) is set to 1 at this time regardless of whether 12 V is applied
to FVPP, application or release of 12 V to FVpp cannot be determined simply from the 0 or
1 status of this bit. A byte data comparison is necessary to check whether 12V is being
applied. The relevant coding is shown below.
LABEL1: MOV.B @H’FF80, R1L
CMP.B #H’FF, R1L
BEQ LABEL1
Sample program for detection of 12 V application to FVpp (mode 3)
Table 20-18 DC Characteristics of Flash Memory
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, AVREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, VPP = 12.0 ± 0.6 V, Ta= –20°C to +75°C (regular specifications),
Ta= –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
High-voltage FVPP, MD1VHVCC + 2 — 11.4 V
(12 V)
threshold
level*
FVPP current During read IPP — — 10 µA VPP = 2.7 to 5.5 V
—1020mAV
PP = 12.6 V
During — 20 40 mA
programming
During — 20 40 mA
erasure
Note: *The listed voltages describe the threshold level at which high-voltage application is
recognized. In boot mode and while flash memory is being programmed or erased, the
applied voltage should be 12.0 V ± 0.6 V.
476
Table 20-19 AC Characteristics of Flash Memory
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, AVREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, VPP = 12.0 ± 0.6 V, Ta= –20°C to +75°C (regular specifications),
Ta= –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
Programming time*1,*2tP— 50 1000 µs
Erase time*1,*3tE— 1 30 s
Number of writing/erasing count
NWEC — — 100 Times
Verify setup time 1*1tVS1 4——µs
Verify setup time 2*1tVS2 2——µs
Flash memory read setup tFRS 50 — — µs VCC ≥4.5 V
time*4100 — — VCC < 4.5 V
Notes: 1. Set the times following the programming/erasing algorithm shown in section 20.
2. The programming time is the time during which a byte is programmed or the P bit in the
flash memory control register (FLMCR) is set. It does not include the program-verify time.
3. The erase time is the time during which all 60-kbyte blocks are erased or the E bit in the
flash memory control register (FLMCR) is set . It does not include the prewrite time
before erasure or erase-verify time.
4. After power-on when using an external colck source, after return from standby mode, or
after switching the programming voltage (VPP) from 12 V to VCC, make sure that this
read setup time has elapsed before reading flash memory.
When VPP is released, the flash memory read setup time is defined as the period from
when the FVPP pin has reached VCC + 2 V until flash memory can be read.
477
Section 21 Power-Down State
21.1 Overview
The H8/3437 Series has a power-down state that greatly reduces power consumption by stopping
some or all of the chip functions. The power-down state includes three modes:
(1) Sleep mode
(2) Software standby mode
(3) Hardware standby mode
Table 21-1 lists the conditions for entering and leaving the power-down modes. It also indicates the
status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 21-1 Power-Down State
Entering CPU Sup. I/O Exiting
Mode Procedure Clock CPU Reg’s. Mod. RAM Ports Methods
Sleep Execute Run Halt Held Run Held Held • Interrupt
mode SLEEP • RES
instruction • STBY
Software Set SSBY bit Halt Halt Held Halt Held Held • NMI
standby in SYSCR to and • IRQ0–IRQ2
mode 1, then initial- IRQ6(incl.
execute ized KEYIN0–
SLEEP KEYIN15)
instruction • RES
•STBY
Hardware Set STBY Halt Halt Not Halt Held High • STBY and
standby pin to low held and impe- RES
mode level initialized dance
state
Notes: 1. SYSCR: System control register
2. SSBY: Software standby bit
479
21.1.1 System Control Register (SYSCR)
Four of the eight bits in the system control register (SYSCR) control the power-down state. These
are bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0). See table 21-2.
Table 21-2 System Control Register
Name Abbreviation R/W Initial Value Address
System control register SYSCR R/W H'09 H'FFC4
Bit 7—Software Standby (SSBY): This bit enables or disables the transition to software standby
mode.
On recovery from the software standby mode by an external interrupt, SSBY remains set to 1. To
clear this bit, software must write a 0.
Bit 7
SSBY Description
0 The SLEEP instruction causes a transition to sleep mode. (Initial value)
1 The SLEEP instruction causes a transition to software standby mode.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
480
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time
when the chip recovers from software standby mode by an external interrupt. During the selected
time, the clock oscillator runs but the CPU and on-chip supporting modules remain in standby. Set
bits STS2 to STS0 according to the clock frequency to obtain a settling time of at least 8 ms. See
table 21-3.
ZTAT and Mask ROM Versions
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Settling time = 8,192 states (Initial value)
0 0 1 Settling time = 16,384 states
0 1 0 Settling time = 32,768 states
0 1 1 Settling time = 65,536 states
1 0 — Settling time = 131,072 states
1 1 — Unused
F-ZTAT Version
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Settling time = 8,192 states (Initial value)
0 0 1 Settling time = 16,384 states
0 1 0 Settling time = 32,768 states
0 1 1 Settling time = 65,536 states
1 0 0 Settling time = 131,072 states
1 0 1 Settling time = 1,024 states
1 1 — Unused
Note: When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted.
If a period exceeding øp/1,024 (e.g. øp/2,048) is specified when selecting the 8-bit timer,
PWM timer, or watchdog timer clock, the counter in the timer will not count up normally when
1,024 states is specified for the settling time. To avoid this problem, set the STS value just
before the transition to software standby mode (before executing the SLEEP instruction), and
re-set the value of STS2 to STS0 to a value from 000 to 100 directly after software standby
mode is cleared by an interrupt.
481
21.2 Sleep Mode
21.2.1 Transition to Sleep Mode
When the SSBY bit in the system control register is cleared to 0, execution of the SLEEP
instruction causes a transition from the program execution state to sleep mode. After executing the
SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The
on-chip supporting modules continue to operate normally.
21.2.2 Exit from Sleep Mode
The chip exits sleep mode when it receives an internal or external interrupt request, or a low input at
the RES or STBY pin.
1. Exit by Interrupt: An interrupt releases sleep mode and starts the CPU’s interrupt-handling
sequence.
If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable
bit in the module’s control register, the interrupt cannot be requested, so it cannot wake the chip up.
Similarly, the CPU cannot be awakened by an interrupt other than NMI if the I (interrupt mask) bit
is set when the SLEEP instruction is executed.
2. Exit by RES Pin: When the RES pin goes low, the chip exits from sleep mode to the reset state.
3. Exit by STBY Pin: When the STBY pin goes low, the chip exits from sleep mode to hardware
standby mode.
482
21.3 Software Standby Mode
21.3.1 Transition to Software Standby Mode
To enter software standby mode, set the standby bit (SSBY) in the system control register (SYSCR)
to 1, then execute the SLEEP instruction.
In software standby mode, the system clock stops and chip functions halt, including both CPU
functions and the functions of the on-chip supporting modules. Power consumption is reduced to an
extremely low level. The on-chip supporting modules and their registers are reset to their initial
states, but as long as a minimum necessary voltage supply is maintained, the contents of the CPU
registers and on-chip RAM remain unchanged.
21.3.2 Exit from Software Standby Mode
The chip can be brought out of software standby mode by an RES input, STBY input, or external
interrupt input at the NMI pin, IRQ0to IRQ2pins, or IRQ6pin (including KEYIN0to KEYIN15).
1. Exit by Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, or IRQ6interrupt request signal is input,
the clock oscillator begins operating. After the waiting time set in bits STS2 to STS0 of SYSCR, a
stable clock is supplied to the entire chip, software standby mode is released, and interrupt
exception-handling begins. IRQ3, IRQ4, IRQ5, and IRQ7interrupts should be disabled before the
transition to software standby (clear IRQ3E, IRQ4E, IRQ5E, and IRQ7E to 0).
2. Exit by RES Pin: When the RES input goes low, the clock oscillator begins operating. When
RES is brought to the high level (after allowing time for the clock oscillator to settle), the CPU
starts reset exception handling. Be sure to hold RES low long enough for clock oscillation to
stabilize.
3. Exit by STBY Pin: When the STBY input goes low, the chip exits from software standby mode
to hardware standby mode.
483
21.3.3 Clock Settling Time for Exit from Software Standby Mode
Set bits STS2 to STS0 in SYSCR as follows:
• Crystal oscillator
Set STS2 to STS0 for a settling time of at least 8 ms. Table 21-3 lists the settling times selected
by these bits at several clock frequencies.
• External clock
The STS bits can be set to any value. When 1,024 states (STS2 to STS0 = 101) is selected, the
following points should be noted.
If a period exceeding øp/1,024 (e.g. øp/2,048) is specified when selecting the 8-bit timer, PWM
timer, or watchdog timer clock, the counter in the timer will not count up normally when 1,024
states is specified for the settling time. To avoid this problem, set the STS value just before the
transition to software standby mode (before executing the SLEEP instruction), and re-set the
value of STS2 to STS0 to a value from 000 to 100 directly after software standby mode is
cleared by an interrupt.
Table 21-3 Times Set by Standby Timer Select Bits (Unit: ms)
Settling
Time System Clock Frequency (MHz)
STS2 STS1 STS0 (States) 16 12 10 8 6 4 2 1 0.5
0 0 0 8,192 0.51 0.65 0.8 1.0 1.3 2.0 4.1 8.2 16.4
0 0 1 16,384 1.0 1.3 1.6 2.0 2.7 4.1 8.2 16.4 32.8
0 1 0 32,768 2.0 2.7 3.3 4.1 5.5 8.2 16.4 32.8 65.5
0 1 1 65,536 4.1 5.5 6.6 8.2 10.9 16.4 32.8 65.5 131.1
1 0 0/—*131,072 8.2 10.9 13.1 16.4 21.8 32.8 65.5 131.1 262.1
Notes: 1. All times are in milliseconds.
2. Recommended values are printed in boldface.
*F-ZTAT version/ZTAT and mask-ROM versions
484
21.3.4 Sample Application of Software Standby Mode
In this example the chip enters the software standby mode when NMI goes low and exits when NMI
goes high, as shown in figure 21-1.
The NMI edge bit (NMIEG) in the system control register is originally cleared to 0, selecting the
falling edge. When NMI goes low, the NMI interrupt handling routine sets NMIEG to 1, sets SSBY
to 1 (selecting the rising edge), then executes the SLEEP instruction. The chip enters software
standby mode. It recovers from software standby mode on the next rising edge of NMI.
Figure 21-1 NMI Timing in Software Standby Mode
21.3.5 Application Note
(1) The I/O ports retain their current states in software standby mode. If a port is in the high output
state, the current dissipation caused by the output current is not reduced.
ø
NMI
NMIEG
SSBY
NMI interrupt
handler
NMIEG = 1
SSBY = 1
Software standby
mode (power-
down state)
Settling time
SLEEP
NMI interrupt
handler
Clock
oscillator
485
(2) For H8/3434F lots up to week code “5M*”, current dissipation is not reduced below the
specification value when the SLEEP instruction is executed in the ROM space after the SSBY
bit in SYSCR is set and the mode is changed to software standby mode.
This is because operation of the sense amplifier in the flash memory is not completely halted
when the SLEEP instruction is executed in the ROM space and the mode is changed to software
standby mode. There is a continuous Vcc current of approximately 100 µA to 200 µA per bit,
and approximately 2 mA to 4 mA in total (when VCC = 5.0 V and Ta = 25°C).
Remedial measures for this problem are described below.
(a) Preliminary remedy
Current dissipation is reduced normally if the SLEEP instruction is executed in the RAM
space. Please change the software as shown below.
(b) Permanent remedy
A permanent remedy will be implemented in lots with week code "6A1" onward by
modifying the internal logic circuitry.
Note: The current responsible for this phenomenon also flows when the mode is changed to
SLEEP mode. In order to reduce current dissipation, therefore, please use the preliminary
remedy for the SLEEP instruction when changing the mode to SLEEP mode.
; Sets the SSBY bit
; Executes the SLEEP instruction
BSET
SLEEP
•
•
•
#7, @SYSCR:8
•
•
•
: Sets the SSBY bit
: Writes the SLEEP code H'0180
; to the RAM
; Writes the RTS code H'5470
; to the RAM
; Subroutine branch
*Registers and RAM addresses
are arbitrary.
BSET
MOV.W
MOV.W
MOV.W
MOV.W
JSR
•
•
•
#7, @SYSCR:8
#H'0180, R0
R0, @H'FF00
#H'5470, R0
R0, @H'FF02
@H'FF00
•
•
•
Replace the underlined part
(SLEEP instruction)
with the code shown below.
486
21.4 Hardware Standby Mode
21.4.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes
low.
Hardware standby mode reduces power consumption drastically by halting the CPU, stopping all
the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance state.
The registers of the on-chip supporting modules are reset to their initial values. Only the on-chip
RAM is held unchanged, provided the minimum necessary voltage supply is maintained.
Notes: 1. The RAME bit in the system control register should be cleared to 0 before the STBY pin
goes low.
2. Do not change the inputs at the mode pins (MD1, MD0) during hardware standby mode.
Be particularly careful not to let both mode pins go low in hardware standby mode, since
that places the chip in PROM mode and increases current dissipation.
21.4.2 Recovery from Hardware Standby Mode
Recovery from the hardware standby mode requires inputs at both the STBY and RES pins. When
the STBY pin goes high, the clock oscillator begins running. The RES pin should be low at this time
and should be held low long enough for the clock to stabilize. When the RES pin changes from low
to high, the reset sequence is executed and the chip returns to the program execution state.
487
21.4.3 Timing Relationships
Figure 21-2 shows the timing relationships in hardware standby mode.
In the sequence shown, first RES goes low, then STBY goes low, at which point the chip enters
hardware standby mode. To recover, first STBY goes high, then after the clock settling time, RES
goes high.
Figure 21-2 Hardware Standby Mode Timing
RES
STBY
Clock pulse
generator
Clock settling
time
Restart
488
Section 22 Electrical Specifications
22.1 Absolute Maximum Ratings
Table 22-1 lists the absolute maximum ratings.
Table 22-1 Absolute Maximum Ratings
Item Symbol Rating Unit
Supply voltage VCC –0.3 to +7.0 V
I/O buffer supply voltage VCCB –0.3 to +7.0 V
Flash memory programming FVPP –0.3 to +13.0 V
voltage
Programming voltage VPP –0.3 to +13.5 V
Input voltage Pins other than Vin –0.3 to VCC + 0.3 V
Ports 7, MD1, P86,
P97, PA7to PA4
P86, P97, Vin –0.3 to VCCB + 0.3 V
PA7to PA4
Port 7 Vin –0.3 to AVCC + 0.3 V
MD1Vin F-ZTAT version: –0.3 to +13.0 V
Other versions: –0.3 to VCC + 0.3
Reference supply voltage AVref –0.3 to AVCC + 0.3 V
Analog supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC + 0.3 V
Operating temperature Topr Regular specifications: –20 to +75 ˚C
Wide-range specifications: –40 to +85 ˚C
Storage temperature Tstg –55 to +125 ˚C
Caution: Exceeding the absolute maximum ratings shown in table 22-1 can permanently destroy
the chip.*
Note: *FVPP must not exceed 13 V and VPP must not exceed 13.5 V, including allowances for
peak overshoot. For the F-ZTAT version, MD1must not exceed 13 V, including an
allowance for peak overshoot.
489
22.2 Electrical Characteristics
22.2.1 DC Characteristics
Table 22-2 lists the DC characteristics of the 5-V version. Table 22-3 lists the DC characteristics of
4-V version. Table 22-4 lists the DC characteristics of the 3 V version. Table 22-5 gives the
allowable current output values of the 5-V and 4-V versions. Table 22-6 gives the allowable current
output values of the 3-V version. Bus drive characteristics common to 5-V, 4-V and 3-V versions
are listed in table 22-7.
Table 22-2 DC Characteristics (5-V Version)
Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC = 5.0 V ±10%*1, AVref = 4.5 V to
AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C
to +85˚C (wide-range specifications)
Test
Item Symbol Min Typ Max Unit Conditions
Schmitt P67to P60*4, (1)*7VT–1.0 — — V
trigger KEYIN15 to VT+——V
CC ×0.7
input KEYIN8,VCCB ×0.7
voltage IRQ2to IRQ0*5,
IRQ7to IRQ3VT+– VT–0.4 — —
Input high RES, STBY, (2) VIH VCC – 0.7 — VCC + 0.3 V
voltage MD1, MD0,
EXTAL, NMI
PA7to PA0*7VCC ×0.7 — VCC + 0.3
SCL, SDA VCCB ×0.7 VCCB + 0.3
P77to P702.0 — AVCC + 0.3
All input pins other 2.0 — VCC + 0.3
than (1) and (2) VCCB + 0.3
above*7
Input low RES, STBY, (3) VIL –0.3 — 0.5 V
voltage MD1, MD0
PA7to PA0–0.3 — 1.0
SCL, SDA
All input pins other –0.3 — 0.8
than (1) and (3)
above
Output All output pins VOH VCC – 0.5 — — V IOH = –200 µA
high (except RESO)*6,*7VCCB – 0.5
voltage 3.5 — — IOH = –1.0 mA
490
Table 22-2 DC Characteristics (5-V Version) (cont)
Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC = 5.0 V ±10%*1, AVref = 4.5 V to
AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C
to +85˚C (wide-range specifications)
Test
Item Symbol Min Typ Max Unit Conditions
Output All output pins VOL — — 0.4 V IOL = 1.6 mA
low (except RESO)*6
voltage P17to P10, — — 1.0 IOL = 10.0 mA
P27to P20
RESO — — 0.4 IOL = 2.6 mA
Input RES, STBY | Iin | — — 10.0 µA Vin = 0.5 V to
leakage NMI, MD1, MD0— — 1.0 VCC – 0.5 V
current P77to P70— — 1.0 Vin = 0.5 V to
AVCC – 0.5 V
Leakage Ports 1 to 6, 8, 9, | ITSI | — — 1.0 µA Vin = 0.5 V to
current in A, B, RESO*7VCC – 0.5 V,
three-state Vin = 0.5 V to
(off state) VCCB – 0.5 V
Input Ports 1 to 3 –IP30 — 250 µA Vin = 0 V
pull-up
MOS Ports 6, A, B 60 — 500
current
Input STBY (F-ZTAT (4) Cin — — 120 pF Vin = 0 V,
capaci- version) f = 1 MHz,
tance RES, STBY ——60 Ta = 25°C
(except F-ZTAT
version)
NMI, MD1——50
PA7to PA4, — — 20
P97, P86
All input pins other — — 15
than (4)
Current Normal operation ICC — 27 45 mA f = 12 MHz
dissipa- — 36 60 f = 16 MHz
tion*2Sleep mode — 18 30 f = 12 MHz
— 24 40 f = 16 MHz
Standby modes*3— 0.01 5.0 µA Ta ≤50°C
— — 20.0 50°C < Ta
491
Table 22-2 DC Characteristics (5-V Version) (cont)
Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC = 5.0 V ±10%*1, AVref = 4.5 V to
AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C
to +85˚C (wide-range specifications)
Test
Item Symbol Min Typ Max Unit Conditions
Analog During A/D AICC — 1.2 2.0 mA
supply conversion
current During A/D and D/A — 1.2 2.0
conversion
A/D and D/A — 0.01 5.0 µA AVCC = 2.0 V
conversion idle to 5.5 V
Reference During A/D AIref — 0.3 0.6 mA
supply conversion
current During A/D and D/A — 1.3 3.0
conversion
A/D and D/A — 0.01 5.0 µA AVref = 2.0 V
conversion idle to 5.5 V
Analog supply voltage*1AVCC 4.5 — 5.5 V During
operation
2.0 — 5.5 While idle or
when not in
use
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Even when the A/D and D/A converters are not used, connect AVCC to power supply VCC
and keep the applied voltage between 2.0 V and 5.5 V. At this time, make sure AVref ≤
AVCC.
2. Current dissipation values assume that VIH min = VCC – 0.5 V, V CCB – 0.5 V, VIL max = 0.5 V,
all output pins are in the no-load state, and all input pull-up transistors are off.
3. For these values it is assumed that VRAM ≤VCC < 4.5 V and VIH min = VCC ×0.9,
VCCB×0.9, VIL max = 0.3 V.
4. P67to P60include supporting module inputs multiplexed with them.
5. IRQ2includes ADTRG multiplexed with it.
6. Applies when IICS = IICE = 0. The output low level is determined separately when the
bus drive function is selected.
7. The characteristics of PA7to PA4, KEYIN15 to KEYIN12, P97/WAIT, SDA, and
P86/IRQ5/SCK1, SCL depend on VCCB; the characteristics of all other pins depend on
VCC.
492
Table 22-3 DC Characteristics (4-V Version)
Conditions: VCC = 4.0 V to 5.5 V, AVCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V*1, AVref = 4.0
V to AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C (regular specifications), Ta =
–40˚C to +85˚C (wide-range specifications)
Test
Item Symbol Min Typ Max Unit Conditions
Schmitt P67to P60*4, (1)*7VT–1.0 — — V VCC = 4.5 V to
trigger KEYIN15 to, VT+——V
CC ×0.7 5.5 V, VCCB =
input KEYIN8,VCCB ×0.7 4.5 V to 5.5 V
voltage IRQ2to IRQ0*5,VT+– VT–0.4 — —
IRQ7to IRQ3VT–0.8 — — VCC = 4.0 V to
VT+——V
CC ×0.7 4.5 V, VCCB =
VCCB ×0.7 4.0 V to 4.5 V
VT+– VT–0.3 — —
Input high RES, STBY, (2) VIH VCC – 0.7 — VCC + 0.3 V
voltage MD1, MD0,
EXTAL, NMI
PA7to PA0*7VCC ×0.7 — VCC + 0.3
SCL, SDA VCC B ×0.7 VCCB + 0.3
P77to P702.0 — AVCC + 0.3
All input pins other 2.0 — VCC + 0.3
than (1) and (2) VCCB + 0.3
above*7
Input low RES, STBY, (3) VIL –0.3 — 0.5 V
voltage MD1, MD0
PA7to PA0*7–0.3 — 1.0 VCC = 4.5 V to
SCL, SDA 5.5 V, VCCB =
4.5 V to 5.5 V
–0.3 — 0.8 VCC = 4.0 V to
4.5 V, VCCB =
4.0 V to 4.5 V
All input pins other –0.3 — 0.8 VCC = 4.5 V to
than (1) and (3) 5.5 V, VCCB =
above*74.5 V to 5.5 V
–0.3 — 0.6 VCC = 4.0 V to
4.5 V, VCCB =
4.0 V to 4.5 V
493
Table 22-3 DC Characteristics (4-V Version) (cont)
Conditions: VCC = 4.0 V to 5.5 V, AVCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V*1, AVref = 4.0
V to AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C (regular specifications), Ta =
–40˚C to +85˚C (wide-range specifications)
Test
Item Symbol Min Typ Max Unit Conditions
Output All output pins VOH VCC – 0.5 — — V IOH = –200 µA
high (except RESO)*6,*7VCCB – 0.5
voltage 3.5 — — IOH = –1.0 mA,
VCC = 4.5 V to
5.5 V, VCCB =
4.5 V to 5.5 V
2.8 — — IOH = –1.0 mA,
VCC = 4.0 V to
4.5 V, VCCB =
4.0 V to 4.5 V
Output All output pins VOL — — 0.4 V IOL = 1.6 mA
low (except RESO)*6
voltage P17to P10, — — 1.0 IOL = 10.0 mA
P27to P20
RESO — — 0.4 IOL = 2.6 mA
Input RES, STBY | Iin | — — 10.0 µA Vin = 0.5 V to
leakage NMI, MD1, MD0— — 1.0 VCC – 0.5 V
current P77to P70— — 1.0 Vin = 0.5 V to
AVCC – 0.5 V
Leakage Ports 1 to 6, 8, 9, | ITSI | — — 1.0 µA Vin = 0.5 V to
current in A, B, RESO*7VCC – 0.5 V,
three-state Vin = 0.5 V to
(off state) VCCB – 0.5 V
Input Ports 1 to 3 –IP30 — 250 µA Vin = 0 V,
pull-up Ports 6, A, B*760 — 500 VCC = 4.5 V to
MOS 5.5 V, VCCB =
current 4.5 V to 5.5 V
Ports 1 to 3 20 — 200 Vin = 0 V,
Ports 6, A, B*740 — 400 VCC = 4.0 V to
4.5 V, VCCB =
4.0 V to 4.5 V
494
Table 22-3 DC Characteristics (4-V Version) (cont)
Conditions: VCC = 4.0 V to 5.5 V, AVCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V*1, AVref = 4.0
V to AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C (regular specifications), Ta =
–40˚C to +85˚C (wide-range specifications)
Test
Item Symbol Min Typ Max Unit Conditions
Input STBY (F-ZTAT (4) Cin — — 120 pF Vin = 0 V,
capaci- version) f = 1 MHz,
tance RES, STBY ——60 Ta = 25°C
(except F-ZTAT
version)
NMI, MD1——50
PA7to PA4, — — 20
P97,P86
All input pins other — — 15
than (4) above
Current Normal operation ICC — 27 45 mA f = 12 MHz
dissipa- — 36 60 f = 16 MHz,
tion*2VCC = 4.5 V to
5.5 V
Sleep mode — 18 30 f = 12 MHz
— 24 40 f = 16 MHz
VCC = 4.5 V to
5.5 V
Standby modes*3— 0.01 5.0 µA Ta ≤50°C
— — 20.0 50°C < Ta
Analog During A/D AICC — 1.2 2.0 mA
supply conversion
current During A/D and D/A — 1.2 2.0
conversion
A/D and D/A — 0.01 5.0 µA AVCC = 2.0 V
conversion idle to 5.5 V
Reference During A/D AIref — 0.3 0.6 mA
supply conversion
current During A/D and D/A — 1.3 3.0
conversion
A/D and D/A — 0.01 5.0 µA AVref = 2.0 V
conversion idle to 5.5 V
495
Table 22-3 DC Characteristics (4-V Version) (cont)
Conditions: VCC = 4.0 V to 5.5 V, AVCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V*1, AVref = 4.0
V to AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C (regular specifications), Ta =
–40˚C to +85˚C (wide-range specifications)
Test
Item Symbol Min Typ Max Unit Conditions
Analog supply voltage*1AVCC 4.0 — 5.5 V During
operation
2.0 — 5.5 While idle or
when not in
use
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Even when the A/D and D/A converters are not used, connect AVCC to power supply VCC
and keep the applied voltage between 2.0 V and 5.5 V. At this time, make sure AVref ≤
AVCC.
2. Current dissipation values assume that VIH min = VCC – 0.5 V, VCCB – 0.5 V, VIL max =
0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off.
3. For these values it is assumed that VRAM ≤VCC < 4.0 V and VIH min = VCC ×0.9, VCCB ×
0.9, VIL max = 0.3 V.
4. P67to P60include supporting module inputs multiplexed with them.
5. IRQ2includes ADTRG multiplexed with it.
6. Applies when IICS = IICE = 0. The output low level is determined separately when the
bus drive function is selected.
7. The characteristics of PA7to PA4, KEYIN15 to KEYIN12, P97/WAIT, SDA, and
P86/IRQ5/SCK1, SCL depend on VCCB; the characteristics of all other pins depend on
VCC.
496
Table 22-4 DC Characteristics (3-V Version)
Conditions: VCC = 2.7 V to 5.5 V, AVCCB = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V*1,
AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C
Test
Item Symbol Min Typ Max Unit Conditions
Schmitt P67to P60*4, (1)*7VT–VCC ×0.15 — — V
trigger KEYIN15 to, VCCB ×0.15
input KEYIN8,VT+——V
CC ×0.7
voltage IRQ2to IRQ0*5,VCCB ×0.7
IRQ7to IRQ3VT+– VT–0.2 — —
Input high RES, STBY, (2) VIH VCC ×0.9 — VCC + 0.3 V
voltage MD1, MD0,
EXTAL, NMI
PA7to PA0*7VCC ×0.7 — VCC + 0.3
SCL, SDA VCC B ×0.7 VCCB + 0.3
P77to P70VCC ×0.7 — AVCC + 0.3
All input pins other VCC ×0.7 — VCC + 0.3
than (1) and (2) VCC B ×0.7 VCCB + 0.3
above*7
Input low RES, STBY, (3) VIL –0.3 — VCC ×0.1 V
voltage*4MD1, MD0
PA7to PA0*7–0.3 — VCC ×0.15
SCL, SDA VCCB ×0.15
All input pins other –0.3 — VCC ×0.15
than (1) and (3) VCCB ×0.15
above*7
Output All output pins VOH VCC – 0.5 — — V IOH = –200 µA
high (except RESO)*6,*7VCCB – 0.5
voltage VCC – 1.0 — — IOH = –1 mA,
VCCB – 1.0
Output All output pins VOL — — 0.4 V IOL = 0.8 mA
low (except RESO)*6
voltage P17to P10, — — 0.4 IOL = 1.6 mA
P27to P20
RESO — — 0.4 IOL = 1.6 mA
Input RES, STBY | Iin | — — 10.0 µA Vin = 0.5 V to
leakage NMI, MD1, MD0— — 1.0 VCC – 0.5 V
current P77to P70— — 1.0 Vin = 0.5 V to
AVCC – 0.5 V
497
498
Table 22-4 DC Characteristics (3-V Version) (cont)
Conditions: VCC = 2.7 V to 5.5 V, AVCCB = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V*1,
AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C
Test
Item Symbol Min Typ Max Unit Conditions
Leakage Ports 1 to 6, 8, 9, | ITSI | — — 1.0 µA Vin = 0.5 V to
current in A, B, RESO*7VCC – 0.5 V,
three-state Vin = 0.5 V to
(off state) VCCB – 0.5 V
Input Ports 1 to 3 –IP3 — 120 µA Vin = 0 V,
pull-up Ports 6, A, B*730 — 250 VCC = 2.7 V to
MOS 3.6 V, VCCB =
current 2.7 V to 3.6 V
Input STBY (F-ZTAT (4) Cin — — 120 pF Vin = 0 V,
capaci- version) f = 1 MHz,
tance RES, STBY ——60 Ta = 25°C
(except F-ZTAT
version)
NMI, MD1——50
PA7to PA4, — — 20
P97,P86
All input pins other — — 15
than (4) above
Current Normal operation ICC — 7 — mA f = 6 MHz,
dissipa- VCC = 2.7 V to
tion*23.6 V
— 12 22 f = 10 MHz,
VCC = 2.7 V to
3.6 V
— 25 — f = 10 MHz,
VCC = 4.0 V to
5.5 V
Sleep mode — 5 — f = 6 MHz,
VCC = 2.7 V to
3.6 V
— 9 16 f = 10 MHz,
VCC = 2.7 V to
3.6 V
— 18 — f = 10 MHz,
VCC = 4.0 V to
5.5 V
Standby modes*3— 0.01 5.0 µA Ta ≤50°C
— — 20.0 50°C < Ta
499
Table 22-4 DC Characteristics (3-V Version) (cont)
Conditions: VCC = 2.7 V to 5.5 V, AVCCB = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V*1,
AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C
Test
Item Symbol Min Typ Max Unit Conditions
Analog During A/D AICC — 1.2 2.0 mA
supply conversion
current During A/D and D/A — 1.2 2.0
conversion
A/D and D/A — 0.01 5.0 µA AVCC = 2.0 V
conversion idle to 5.5 V
Reference During A/D AIref — 0.3 0.6 mA
supply conversion
current During A/D and D/A — 1.3 3.0
conversion
A/D and D/A — 0.01 5.0 µA AVref = 2.0 V
conversion idle to 5.5 V
Analog supply voltage*1AVCC 2.7 — 5.5 V During
operation
2.0 — 5.5 While idle or
when not in
use
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Even when the A/D and D/A converters are not used, connect AVCC to power supply VCC
and keep the applied voltage between 2.0 V and 5.5 V. At this time, make sure AVref ≤
AVCC.
2. Current dissipation values assume that VIH min = VCC – 0.5 V, VCCB – 0.5 V, VIL max =
0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off.
3. For these values it is assumed that VRAM ≤VCC < 2.7 V and VIH min = VCC ×0.9, VCCB ×
0.9, VIL max = 0.3 V.
4. P67to P60include supporting module inputs multiplexed with them.
5. IRQ2includes ADTRG multiplexed with it.
6. Applies when IICS = IICE = 0. The output low level is determined separately when the
bus drive function is selected.
7. The characteristics of PA7to PA4, KEYIN15 to KEYIN12, P97/WAIT, SDA, and
P86/IRQ5/SCK1, SCL depend on VCCB; the characteristics of all other pins depend on
VCC.
500
Table 22-5 Allowable Output Current Values (5-V and 4-V Versions)
Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V
to AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C (regular specifications), Ta =
–40˚C to +85˚C (wide-range specifications)
Item Symbol Min Typ Max Unit
Allowable output low SCL, SDA, PA4to PA7IOL — — 20 mA
current (per pin) (bus drive selection)
Ports 1 and 2 — — 10
RESO ——3
Other output pins — — 2
Allowable output low Ports 1 and 2, total ΣIOL — — 80 mA
current (total) Total of all output — — 120
Allowable output high All output pins –IOH ——2 mA
current (per pin)
Allowable output high Total of all output Σ–IOH — — 40 mA
current (total)
Table 22-6 Allowable Output Current Values (3-V Version)
Conditions: VCC = 2.7 V to 5.5 V, VCCB = 2.7 to 5.5 V, AVCC = 2.7 V to 5.5 V, AVref = 2.7 V to
AVCC, VSS = AVSS = 0 V, Ta = –20˚C to +75˚C
Item Symbol Min Typ Max Unit
Allowable output low SCL, SDA, PA4to PA7IOL — — 10 mA
current (per pin) (bus drive selection)
Ports 1 and 2 — — 2
RESO ——1
Other output pins — — 1
Allowable output low Ports 1 and 2, total ΣIOL — — 40 mA
current (total) Total of all output — — 60
Allowable output high All output pins –IOH ——2 mA
current (per pin)
Allowable output high Total of all output Σ–IOH — — 30 mA
current (total)
Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current
values in tables 22-5 and 22-6. In particular, when driving a darlington transistor pair or LED
directly, be sure to insert a current-limiting resistor in the output path. See figures 22-1 and
22-2.
501
Figure 22-1 Example of Circuit for Driving a Darlington Transistor (5-V Version)
Figure 22-2 Example of Circuit for Driving an LED (5-V Version)
Table 22-7 Bus Drive Characteristics
Conditions: VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20˚C to +75°C
Item Symbol Min Typ Max Unit Test Conditions
Output low SCL, SDA VOL — — 0.5 V VCCB = 5 V ±10%
level voltage PA4to PA7IOL = 16 mA
(bus drive — — 0.5 VCCB = 2.7 V to 5.5 V
selection) IOL = 8 mA
H8/3437
Ports 1 or 2
LED
600Ω
VCC
H8/3437
Port 2 kΩ
Darlington
transistor
502
22.2.2 AC Characteristics
The AC characteristics are listed in four tables. Bus timing parameters are given in table 22-8,
control signal timing parameters in table 22-9, timing parameters of the on-chip supporting modules
in table 22-10, I2C bus timing parameters in table 22-11, and external clock output stabilization
delay time in table 22-12.
Table 22-8 Bus Timing
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20 to +75˚C (regular specifications), Ta = –40 to +85˚C
(wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20 to +75˚C (regular specifications), Ta = –40 to +85˚C
(wide-range specifications)
Condition C: VCC = 2.7 V to 5.5 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20 to +75˚C
Condition C Condition B Condition A
10 MHz 12 MHz 16 MHz Test
Item Symbol Min Max Min Max Min Max Unit Conditions
Clock cycle time tcyc 100 500 83.3 500 62.5 500 ns Fig. 22-4
Clock pulse width low tCL 30 – 30 – 20 – ns
Clock pulse width high tCH 30 – 30 – 20 – ns
Clock rise time tCr –20 –10 –10ns
Clock fall time tCf –20 –10 –10ns
Address delay time tAD –50 –35 –30 ns
Address hold time tAH 20 – 15 – 10 – ns
Address strobe delay time tASD –50 –35 –30 ns
Write strobe delay time tWSD –50 –35 –30ns
Strobe delay time tSD –50 –35 –30ns
Write strobe pulse width*1tWSW 110 – 90 – 60 – ns
Address setup time 1*1tAS1 15 – 10 – 10 – ns
Address setup time 2*1tAS2 65 – 50 – 40 – ns
Read data setup time tRDS 35 – 20 – 20 – ns
Read data hold time*1tRDH 0– 0– 0– ns
Read data access time*1tACC – 170 – 160 – 110 ns
Write data delay time tWDD – 80/75*2– 65/60*2–60ns
Write data setup time tWDS 0/5*2– 0/5*2– 0/5*2–ns
Write data hold time tWDH 20 – 20 – 20 – ns
Wait setup time tWTS 40 – 35 – 30 – ns Fig. 22-5
Wait hold time tWTH 10 – 10 – 10 – ns
Notes: *1Values at maximum operating frequency
*2H8/3437 F-ZTAT version/other products
503
Table 22-9 Control Signal Timing
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C to
+85˚C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5V, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C to
+85˚C (wide-range specifications)
Condition C: VCC = 2.7 V to 5.5 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C
Condition C Condition B Condition A
10 MHz 12 MHz 16 MHz Test
Item Symbol Min Max Min Max Min Max Unit Conditions
RES setup time tRESS 300 – 200 – 200 – ns Fig. 22-6
RES pulse width tRESW 10 – 10 – 10 – tcyc
RESO output delay time tRESD — 200 — 120 — 100 ns Fig. 22-22
RESO output pulse width tRESOW 132 — 132 — 132 — tcyc
NMI setup time tNMIS 300 – 150 – 150 – ns Fig. 22-7
(NMI, IRQ0to IRQ7)
NMI hold time tNMIH 10 – 10 – 10 – ns
(NMI, IRQ0to IRQ7)
Interrupt pulse width tNMIW 300 – 200 – 200 – ns
for recovery from soft-
ware standby mode
(NMI, IRQ0to IRQ2, IRQ6)
Crystal oscillator settling tOSC1 20 – 20 – 20 – ms Fig. 22-8
time (reset)
Crystal oscillator settling tOSC2 8 – 8 – 8 – ms Fig. 22-9
time (software standby)
• Measurement Conditions for AC Characteristics
Figure 22-3 Measurement Conditions for A/C Characteristics
CRH
5 V
RL
LSI
output pin C =
Input/output timing measurement levels
Low: 0.8 V
High: 2.0 V
RL =
RH =
90 pF: Ports 1–4, 6, 9, A, B
30 pF: Ports 5, 8
2.4 kΩ
12 kΩ
504
Table 22-10 Timing Conditions of On-Chip Supporting Modules
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C to
+85˚C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5V, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C to
+85˚C (wide-range specifications)
Condition C: VCC = 2.7 V to 5.5 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C
Condition C Condition B Condition A
10 MHz 12 MHz 16 MHz Test
Item Symbol Min Max Min Max Min Max Unit Conditions
FRT Timer output tFTOD – 150 – 100 – 100 ns Fig. 22-10
delay time
Timer input tFTIS 80 – 50 – 50 – ns
setup time
Timer clock input tFTCS 80 – 50 – 50 – ns Fig. 22-11
setup time
Timer clock pulse tFTCWH 1.5 – 1.5 – 1.5 – tcyc
width tFTCWL
TMR Timer output tTMOD – 150 – 100 – 100 ns Fig. 22-12
delay time
Timer reset input tTMRS 80 – 50 – 50 – ns Fig. 22-14
setup time
Timer clock input tTMCS 80 – 50 – 50 – ns Fig. 22-13
setup time
Timer clock pulse tTMCWH 1.5 – 1.5 – 1.5 – tcyc
width (single edge)
Timer clock pulse tTMCWL 2.5 – 2.5 – 2.5 – tcyc
width (both edges)
PWM Timer output tPWOD – 150 – 100 – 100 ns Fig. 22-15
delay time
SCI Input clock (Async) tScyc 4– 4– 4– t
cyc Fig. 22-16
cycle (Sync) tScyc 6– 6– 6– t
cyc
Transmit data tTXD – 200 – 100 – 100 ns
delay time (Sync)
Receive data tRXS 150 – 100 – 100 – ns
setup time (Sync)
Receive data tRXH 150 – 100 – 100 – ns
hold time (Sync)
Input clock pulse tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc Fig. 22-17
width
505
Table 22-10 Timing Conditions of On-Chip Supporting Modules (cont)
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C to
+85˚C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5V, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C to
+85˚C (wide-range specifications)
Condition C: VCC = 2.7 V to 5.5 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C
Condition C Condition B Condition A
10 MHz 12 MHz 16 MHz Test
Item Symbol Min Max Min Max Min Max Unit Conditions
Ports Output data tPWD – 150 – 100 – 100 ns Fig. 22-18
delay time
Input data setup tPRS 80 – 50 – 50 – ns
time
Input data hold tPRH 80 – 50 – 50 – ns
time
HIF CS/HA0setup time tHAR 10 — 10 — 10 — ns Fig. 22-19
read CS/HA0hold time tHRA 10 — 10 — 10 — ns
cycle IOR pulse width tHRPW 220 — 120 — 120 — ns
HDB delay time tHRD — 200 — 100 — 100 ns
HDB hold time tHRF 040 025 025 ns
HIRQ delay time tHIRQ — 200 — 120 — 120 ns
HIF CS/HA0setup time tHAW 10 — 10 — 10 — ns Fig. 22-20
write CS/HA0hold time tHWA 10 — 10 — 10 — ns
cycle IOW pulse width tHWPW 100 — 60 — 60 — ns
HDB High-speed tHDW 50 — 30 — 30 — ns
setup GATE A20
time not used
High-speed 85 — 55 — 45 —
GATE A20
used
HDB hold time tHWD 25 — 15 — 15 — ns
GA20 delay time tHGA — 180 — 90 — 90 ns
Table 22-11 I2C Bus Timing
Conditions: VCC = 2.7 V to 5.5 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20°C to +75°C
Item Symbol Min Typ Max Unit Test Conditions Note
SCL clock cycle tSCL 12 tcyc — — ns Fig. 22-21
time
SCL clock high tSCLH 3 tcyc —— ns
pulse width
SCL clock low tSCLL 5 tcyc —— ns
pulse width
SCL and SDA tSr — — 1000 ns Normal mode
rise time 100 kbits/s (max)
20 + 0.1Cb— 300 High-speed mode
400 kbits/s (max)
SCL and SDA tSf — — 300 ns Normal mode
fall time 100 kbits/s (max)
20 + 0.1Cb— 300 High-speed mode
400 kbits/s (max)
SDA bus-free tBUF 7 tcyc – 300 — — ns
time
SCL start tSTAH 3 tcyc —— ns
condition hold
time
SCL resend start tSTAS 3 tcyc —— ns
condition setup
time
SDA stop tSTOS 3 tcyc —— ns
condition setup
time
SDA data tSDAS 1 tcyc + 10 — — ns
setup time
SDA data hold tSDAH 0——ns
time
SDA load Cb— — 400 pF
capacitance
Table 22-12 External Clock Output Stabilization Delay Time
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = –40°C to +85°C
Item Symbol Min Max Unit Notes
External clock output stabilization tDEXT*500 — µs Figure 22-23
delay time
Note: *tDEXT includes a 10 tcyc RES pulse width (tRESW).
506
22.2.3 A/D Converter Characteristics
Table 22-13 lists the characteristics of the on-chip A/D converter.
Table 22-13 A/D Converter Characteristics
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVref = 4.5 V to
AVCC, VSS = AVSS = 0 V, ø = 2.0 MHz to maximum operating frequency, Ta = –20 to
+75˚C (regular specifications), Ta = –40 to +85˚C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V
to AVCC, VSS = AVSS = 0 V, ø = 2.0 MHz to maximum operating frequency, Ta =
–20 to +75˚C (regular specifications), Ta = –40 to +85˚C (wide-range specifications)
Condition C: VCC = 2.7 V to 5.5 V, VCCB = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, AVref = 2.7 V
to AVCC, VSS = AVSS = 0 V, ø = 2.0 MHz to maximum operating frequency, Ta =
–20 to +75˚C
Condition C Condition B Condition A
10 MHz 12 MHz 16 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 Bits
Conversion — — 13.4 — — 11.2 — — 8.4 µs
(single mode)*
Analog input — — 20 — — 20 — — 20 pF
capacitance
Allowable signal — — 5 — — 10 — — 10 kΩ
source impedance
Nonlinearity error — — ±6.0 — — ±3.0 — — ±3.0 LSB
Offset error — — ±4.0 — — ±3.5 — — ±3.5 LSB
Full-scale error — — ±4.0 — — ±3.5 — — ±3.5 LSB
Quantizing error — — ±0.5 — — ±0.5 — — ±0.5 LSB
Absolute accuracy — — ±8.0 — — ±4.0 — — ±4.0 LSB
Note: *Values at maximum operating frequency
507
22.2.4 D/A Converter Characteristics
Table 22-14 lists the characteristics of the on-chip D/A converter.
Table 22-14 D/A Converter Characteristics
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVref = 4.5 V to
AVCC, VSS = AVSS = 0 V, ø = 2.0 MHz to maximum operating frequency, Ta = –20 to
+75˚C (regular specifications), Ta = –40 to +85˚C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V
to AVCC, VSS = AVSS = 0 V, ø = 2.0 MHz to maximum operating frequency, Ta =
–20 to +75˚C (regular specifications), Ta = –40 to +85˚C (wide-range specifications)
Condition C: VCC = 2.7 V to 5.5 V, VCCB = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, AVref = 2.7 V
to AVCC, VSS = AVSS = 0 V, ø = 2.0 MHz to maximum operating frequency, Ta =
–20 to +75˚C
Condition C Condition B Condition A
10 MHz 12MHz 16 MHz Test
Item Min Typ Max Min Typ Max Min Typ Max Unit Conditions
Resolution 888888888Bits
Conversion — — 10.0 — — 10.0 — — 10.0 µs 30 pF load
time capacitance
(settling time)
Absolute — ±2.0 ±3.0 — ±1.0 ±1.5 — ±1.0 ±1.5 LSB 2 MΩload
accuracy resistance
— — ±2.0 — — ±1.0 — — ±1.0 LSB 4 MΩload
resistance
508
22.3 MCU Operational Timing
This section provides the following timing charts:
22.3.1 Bus Timing Figures 22-4 to 22-5
22.3.2 Control Signal Timing Figures 22-6 to 22-9
22.3.3 16-Bit Free-Running Timer Timing Figures 22-10 to 22-11
22.3.4 8-Bit Timer Timing Figures 22-12 to 22-14
22.3.5 PWM Timer Timing Figure 22-15
22.3.6 SCI Timing Figures 22-16 to 22-17
22.3.7 I/O Port Timing Figure 22-18
22.3.8 Host Interface Timing Figures 22-19 and 22-20
22.3.9 I2C Bus Timing Figure 22-21
22.3.10 Reset Output Timing Figure 22-22
22.3.11 External Clock Output Timing Figure 22-23
22.3.1 Bus Timing
(1) Basic Bus Cycle (without Wait States) in Expanded Modes
Figure 22-4 Basic Bus Cycle (without Wait States) in Expanded Modes
T2
T1
tcyc
T3
tCH tCL
tAD tCr
tASD
tACC tRDS
tWSD
tAS2
tWDD tWDS tWDH
tAH
tWSW
tRDH
tAH
tSD
ø
A15 to A0
WR
D7 to D0
(read)
D7 to D0
(write)
AS, RD
tCf
tASI
tSD
509
(2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes
Figure 22-5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes
ø
AS, RD
WR
WAIT
D7 to D0
(read)
A15 to A0
D7 to D0
(write)
T1T2TWT3
tWTS tWTH tWTS tWTH
510
22.3.2 Control Signal Timing
(1) Reset Input Timing
Figure 22-6 Reset Input Timing
(2) Interrupt Input Timing
Figure 22-7 Interrupt Input Timing
ø
IRQL (level)
NMI
IRQi
tNMIS tNMIH
tNMIS
NMI
IRQE (edge)
tNMIW
Note: i = 0 to 7; IRQE: IRQi when edge-sensed; IRQL: IRQi when level-sensed
ø
RES
tRESS tRESS
tRESW
511
(3) Clock Settling Timing
Figure 22-8 Clock Settling Timing
(4) Clock Settling Timing for Recovery from Software Standby Mode
Figure 22-9 Clock Settling Timing for Recovery from Software Standby Mode
ø
NMI
IRQi
(i = 0, 1, 2, 6) tOSC2
ø
VCC
RES
STBY tOSC1 tOSC1
512
22.3.3 16-Bit Free-Running Timer Timing
(1) Free-Running Timer Input/Output Timing
Figure 22-10 Free-Running Timer Input/Output Timing
(2) External Clock Input Timing for Free-Running Timer
Figure 22-11 External Clock Input Timing for Free-Running Timer
ø
FTCI
tFTCS
tFTCWL tFTCWH
ø
Compare-match
FTIA, FTIB,
FTIC, FTID
FTOA , FTOB
Free-running
timer counter tFTOD
tFTIS
513
22.3.4 8-Bit Timer Timing
(1) 8-Bit Timer Output Timing
Figure 22-12 8-Bit Timer Output Timing
(2) 8-Bit Timer Clock Input Timing
Figure 22-13 8-Bit Timer Clock Input Timing
(3) 8-Bit Timer Reset Input Timing
Figure 22-14 8-Bit Timer Reset Input Timing
NH'00
ø
Timer
counter
tTMRS
TMRI0,
TMRI1
ø
tTMCS tTMCS
tTMCWL tTMCWH
TMCI0,
TMCI1
ø
Timer
counter Compare-match
TMO0,
TMO1
tTMOD
514
22.3.5 Pulse Width Modulation Timer Timing
Figure 22-15 PWM Timer Output Timing
Compare-match
tPWOD
ø
Timer
counter
PW0, PW1
515
22.3.6 Serial Communication Interface Timing
(1) SCI Input/Output Timing
Figure 22-16 SCI Input/Output Timing (Synchronous Mode)
(2) SCI Input Clock Timing
Figure 22-17 SCI Input Clock Timing
tSCKW
tScyc
SCK0, SCK1
tScyc
tTXD
tRXS tRXH
Serial clock
(SCK0,
SCK1)
Transmit
data
(TxD0,
TxD1)
Receive
data
(RxD0,
RxD1)
516
22.3.7 I/O Port Timing
Figure 22-18 I/O Port Input/Output Timing
Note: * Except P96 and P77 to P70
Port read/write cycle
tPRS tPRH
tPWD
Port 1 to
port 9 (input)
Port A, B
ø
Port 1* to
port 9 (output)
Port A, B
T1T2T3
517
22.3.8 Host Interface Timing
(1) Host Interface Read Timing
Figure 22-19 Host Interface Read Timing
(2) Host Interface Write Timing
Figure 22-20 Host Interface Write Timing
CS/HA0
HA0
IOW
HDB7 to HDB0
GA20
tHAW tHWPW tHWA
tHWD
tHGA
tHDW
CS/HA0
HA0
IOR
HDB7 to HDB0
HIRQi*
(i = 1, 11, 12)
Note: * Rising edge timing is the same as in port 4 output timing. Refer to figure 22-18.
tHAR tHRPW tHRA
tHRF
tHRD
tHIRQ
Valid data
518
22.3.9 I2C Bus Timing (Option)
Figure 22-21 I2C Bus Interface I/O Timing
22.3.10 Reset Output Timing
Figure 22-22 Reset Output Timing
ø
RESO
tRESD tRESD
tRESOW
SDA VIL
VIH
tBUF
P*S*
tSTAH tSCLH
tSr
tSCLL
tSCL
tSf
tSDAH
Sr*
tSDAS
tSTAS tSP tSTOS
Note: *Conditions S, P, and Sr are defined as follows:
S:
P:
Sr:
Start condition
Stop condition
Resend “start” condition
SCL
P*
519
22.3.11 External Clock Output Timing
Figure 22-23 External Clock Output Stabilization Delay Time
VCC
STBY
EXTAL
ø (internal or
external)
RES
tDEXT*
Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW).
2.7 V
VIH
520
Appendix A CPU Instruction Set
A.1 Instruction Set List
Operation Notation
Rd8/16 General register (destination) (8 or 16 bits)
Rs8/16 General register (source) (8 or 16 bits)
Rn8/16 General register (8 or 16 bits)
CCR Condition code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#xx:3/8/16 Immediate data (3, 8, or 16 bits)
d:8/16 Displacement (8 or 16 bits)
@aa:8/16 Absolute address (8 or 16 bits)
+ Addition
– Subtraction
×Multiplication
÷ Division
∧Logical AND
∨Logical OR
⊕Exclusive logical OR
→Move
—NOT (logical complement)
Condition Code Notation
↕ Modified according to the instruction result
*Undetermined (unpredictable)
0 Always cleared to 0
— Not affected by the instruction result
521
Table A-1 Instruction Set
Mnemonic Operation Condition Code
IHNZVC
MOV.B #xx:8, Rd B #xx:8 →Rd8 2 — — ↕↕0—2
MOV.B Rs, Rd B Rs8 →Rd8 2 — — ↕↕0—2
MOV.B @Rs, Rd B @Rs16 →Rd8 2 — — ↕↕0—4
MOV.B @(d:16, Rs), Rd B @(d:16, Rs16)→Rd8 4 — — ↕↕0—6
MOV.B @Rs+, Rd B @Rs16 →Rd8 2 — — ↕↕0—6
Rs16+1 →Rs16
MOV.B @aa:8, Rd B @aa:8 →Rd8 2 — — ↕↕0—4
MOV.B @aa:16, Rd B @aa:16 →Rd8 4 — — ↕↕0—6
MOV.B Rs, @Rd B Rs8 →@Rd16 2 — — ↕↕0—4
MOV.B Rs, @(d:16, Rd) B Rs8 →@(d:16, Rd16) 4 — — ↕↕0—6
MOV.B Rs, @–Rd B Rd16–1 →Rd16 2 — — ↕↕0—6
Rs8 →@Rd16
MOV.B Rs, @aa:8 B Rs8 →@aa:8 2 — — ↕↕0—4
MOV.B Rs, @aa:16 B Rs8 →@aa:16 4 — — ↕↕0—6
MOV.W #xx:16, Rd W #xx:16 →Rd16 4 — — ↕↕0—4
MOV.W Rs, Rd W Rs16 →Rd16 2 — — ↕↕0—2
MOV.W @Rs, Rd W @Rs16 →Rd16 2 — — ↕↕0—4
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) →Rd16 4 — — ↕↕0—6
MOV.W @Rs+, Rd W @Rs16 →Rd16 2 — — ↕↕0—6
Rs16+2 →Rs16
MOV.W @aa:16, Rd W @aa:16 →Rd16 4 — — ↕↕0—6
MOV.W Rs, @Rd W Rs16 →@Rd16 2 — — ↕↕0—4
MOV.W Rs, @(d:16, Rd) W Rs16 →@(d:16, Rd16) 4 — — ↕↕0—6
MOV.W Rs, @–Rd W Rd16–2 →Rd16 2 — — ↕↕0—6
Rs16 →@Rd16
MOV.W Rs, @aa:16 W Rs16 →@aa:16 4 — — ↕↕0—6
POP Rd W @SP →Rd16 2 — — ↕↕0—6
SP+2 →SP
PUSH Rs W SP–2 →SP 2 — — ↕↕0—6
Rs16 →@SP
522
#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied
No. of States
Addressing Mode/
Instruction Length
Operand Size
Table A-1 Instruction Set (cont)
Mnemonic Operation Condition Code
IHNZVC
MOVFPE @aa:16, Rd B Not supported
MOVTPE Rs, @aa:16 B Not supported
EEPMOV — if R4L≠0 then 4 ——————(4)
Repeat @R5 →@R6
R5+1 →R5
R6+1 →R6
R4L–1 →R4L
Until R4L=0
else next
ADD.B #xx:8, Rd B Rd8+#xx:8 →Rd8 2 — ↕↕↕↕↕2
ADD.B Rs, Rd B Rd8+Rs8 →Rd8 2 — ↕↕↕↕↕2
ADD.W Rs, Rd W Rd16+Rs16 →Rd16 2 — (1) ↕↕↕↕2
ADDX.B #xx:8, Rd B Rd8+#xx:8 +C →Rd8 2 — ↕↕(2) ↕↕2
ADDX.B Rs, Rd B Rd8+Rs8 +C →Rd8 2 — ↕↕(2) ↕↕2
ADDS.W #1, Rd W Rd16+1 →Rd16 2 —————— 2
ADDS.W #2, Rd W Rd16+2 →Rd16 2 —————— 2
INC.B Rd B Rd8+1 →Rd8 2 — — ↕↕↕—2
DAA.B Rd B
Rd8 decimal adjust →Rd8
2—*↕↕*(3) 2
SUB.B Rs, Rd B Rd8–Rs8 →Rd8 2 — ↕↕↕↕↕2
SUB.W Rs, Rd W Rd16–Rs16 →Rd16 2 — (1) ↕↕↕↕2
SUBX.B #xx:8, Rd B Rd8–#xx:8 –C →Rd8 2 — ↕↕(2) ↕↕2
SUBX.B Rs, Rd B Rd8–Rs8 –C →Rd8 2 — ↕↕(2) ↕↕2
SUBS.W #1, Rd W Rd16–1 →Rd16 2 —————— 2
SUBS.W #2, Rd W Rd16–2 →Rd16 2 —————— 2
DEC.B Rd B Rd8–1 →Rd8 2 — — ↕↕↕—2
DAS.B Rd B
Rd8 decimal adjust →Rd8
2—*↕↕*—2
NEG.B Rd B 0–Rd8 →Rd8 2 — ↕↕↕↕↕2
CMP.B #xx:8, Rd B Rd8–#xx:8 2 — ↕↕↕↕↕2
CMP.B Rs, Rd B Rd8–Rs8 2 — ↕↕↕↕↕2
CMP.W Rs, Rd W Rd16–Rs16 2 — (1) ↕↕↕↕2
523
#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied
No. of States
Addressing Mode/
Instruction Length
Operand Size
Table A-1 Instruction Set (cont)
Mnemonic Operation Condition Code
IHNZVC
MULXU.B Rs, Rd B Rd8 ×Rs8 →Rd16 2 ——————14
DIVXU.B Rs, Rd B Rd16÷Rs8 →Rd16 2 — — (6) (7) — — 14
(RdH: remainder,
RdL: quotient)
AND.B #xx:8, Rd B Rd8∧#xx:8 →Rd8 2 — — ↕↕0—2
AND.B Rs, Rd B Rd8∧Rs8 →Rd8 2 — — ↕↕0—2
OR.B #xx:8, Rd B Rd8∨#xx:8 →Rd8 2 — — ↕↕0—2
OR.B Rs, Rd B Rd8∨Rs8 →Rd8 2 — — ↕↕0—2
XOR.B #xx:8, Rd B Rd8⊕#xx:8 →Rd8 2 — — ↕↕0—2
XOR.B Rs, Rd B Rd8⊕Rs8 →Rd8 2 — — ↕↕0—2
NOT.B Rd B Rd8 →Rd8 2 — — ↕↕0—2
SHAL.B Rd B 2 — — ↕↕↕↕2
SHAR.B Rd B 2 — — ↕↕0↕2
SHLL.B Rd B 2 — — ↕↕0↕2
SHLR.B Rd B 2 — — 0 ↕0↕2
ROTXL.B Rd B 2 — — ↕↕0↕2
ROTXR.B Rd B 2 — — ↕↕0↕2
524
b7b0
0C
C
b7b0
b7b0
0C
b7b0
0C
C
b
7
b
0
C
b
7
b
0
#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied
No. of States
Addressing Mode/
Instruction Length
Operand Size
Table A-1 Instruction Set (cont)
Mnemonic Operation Condition Code
IHNZVC
ROTL.B Rd B 2 — — ↕↕0↕2
ROTR.B Rd B 2 — — ↕↕0↕2
BSET #xx:3, Rd B (#xx:3 of Rd8) ←1 2 —————— 2
BSET #xx:3, @Rd B (#xx:3 of @Rd16) ←1 4 —————— 8
BSET #xx:3, @aa:8 B (#xx:3 of @aa:8) ←1 4 —————— 8
BSET Rn, Rd B (Rn8 of Rd8) ←1 2 —————— 2
BSET Rn, @Rd B (Rn8 of @Rd16) ←1 4 —————— 8
BSET Rn, @aa:8 B (Rn8 of @aa:8) ←1 4 —————— 8
BCLR #xx:3, Rd B (#xx:3 of Rd8) ←0 2 —————— 2
BCLR #xx:3, @Rd B (#xx:3 of @Rd16) ←0 4 —————— 8
BCLR #xx:3, @aa:8 B (#xx:3 of @aa:8) ←0 4 —————— 8
BCLR Rn, Rd B (Rn8 of Rd8) ←0 2 —————— 2
BCLR Rn, @Rd B (Rn8 of @Rd16) ←0 4 —————— 8
BCLR Rn, @aa:8 B (Rn8 of @aa:8) ←0 4 —————— 8
BNOT #xx:3, Rd B (#xx:3 of Rd8) ←2 —————— 2
(#xx:3 of Rd8)
BNOT #xx:3, @Rd B (#xx:3 of @Rd16) ←4 —————— 8
(#xx:3 of @Rd16)
BNOT #xx:3, @aa:8 B (#xx:3 of @aa:8) ←4 —————— 8
(#xx:3 of @aa:8)
BNOT Rn, Rd B (Rn8 of Rd8) ←2 —————— 2
(Rn8 of Rd8)
BNOT Rn, @Rd B (Rn8 of @Rd16) ←4 —————— 8
(Rn8 of @Rd16)
BNOT Rn, @aa:8 B (Rn8 of @aa:8) ←4 —————— 8
(Rn8 of @aa:8)
525
#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied
No. of States
Addressing Mode/
Instruction Length
Operand Size
C
b7b0
C
b7b0
Table A-1 Instruction Set (cont)
Mnemonic Operation Condition Code
IHNZVC
BTST #xx:3, Rd B (#xx:3 of Rd8) →Z 2 ——— ↕—— 2
BTST #xx:3, @Rd B (#xx:3 of @Rd16) →Z 4 ——— ↕—— 6
BTST #xx:3, @aa:8 B (#xx:3 of @aa:8) →Z 4 ——— ↕—— 6
BTST Rn, Rd B (Rn8 of Rd8) →Z 2 ——— ↕—— 2
BTST Rn, @Rd B (Rn8 of @Rd16) →Z 4 ——— ↕—— 6
BTST Rn, @aa:8 B (Rn8 of @aa:8) →Z 4 ——— ↕—— 6
BLD #xx:3, Rd B (#xx:3 of Rd8) →C 2 ————— ↕2
BLD #xx:3, @Rd B (#xx:3 of @Rd16) →C 4 ————— ↕6
BLD #xx:3, @aa:8 B (#xx:3 of @aa:8) →C 4 ————— ↕6
BILD #xx:3, Rd B (#xx:3 of Rd8) →C 2 ————— ↕2
BILD #xx:3, @Rd B (#xx:3 of @Rd16) →C 4 ————— ↕6
BILD #xx:3, @aa:8 B (#xx:3 of @aa:8) →C 4 ————— ↕6
BST #xx:3, Rd B C →(#xx:3 of Rd8) 2 —————— 2
BST #xx:3, @Rd B C →(#xx:3 of @Rd16) 4 —————— 8
BST #xx:3, @aa:8 B C →(#xx:3 of @aa:8) 4 —————— 8
BIST #xx:3, Rd B C→(#xx:3 of Rd8) 2 —————— 2
BIST #xx:3, @Rd B C→(#xx:3 of @Rd16) 4 —————— 8
BIST #xx:3, @aa:8 B C→(#xx:3 of @aa:8) 4 —————— 8
BAND #xx:3, Rd B C∧(#xx:3 of Rd8) →C 2 ————— ↕2
BAND #xx:3, @Rd B C∧(#xx:3 of @Rd16) →C 4 ————— ↕6
BAND #xx:3, @aa:8 B C∧(#xx:3 of @aa:8) →C 4 ————— ↕6
BIAND #xx:3, Rd B C∧(#xx:3 of Rd8) →C 2 ————— ↕2
BIAND #xx:3, @Rd B C∧(#xx:3 of @Rd16) →C 4 ————— ↕6
BIAND #xx:3, @aa:8 B C∧(#xx:3 of @aa:8) →C 4 ————— ↕6
BOR #xx:3, Rd B C∨(#xx:3 of Rd8) →C 2 ————— ↕2
BOR #xx:3, @Rd B C∨(#xx:3 of @Rd16) →C 4 ————— ↕6
BOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) →C 4 ————— ↕6
BIOR #xx:3, Rd B C∨(#xx:3 of Rd8) →C 2 ————— ↕2
BIOR #xx:3, @Rd B C∨(#xx:3 of @Rd16) →C 4 ————— ↕6
526
#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied
No. of States
Addressing Mode/
Instruction Length
Operand Size
Table A-1 Instruction Set (cont)
Mnemonic Operation Condition Code
IHNZVC
BIOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) →C 4 ————— ↕6
BXOR #xx:3, Rd B C⊕(#xx:3 of Rd8) →C 2 ————— ↕2
BXOR #xx:3, @Rd B C⊕(#xx:3 of @Rd16) →C 4 ————— ↕6
BXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) →C 4 ————— ↕6
BIXOR #xx:3, Rd B C⊕(#xx:3 of Rd8) →C 2 ————— ↕2
BIXOR #xx:3, @Rd B C⊕(#xx:3 of @Rd16) →C 4 ————— ↕6
BIXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) →C 4 ————— ↕6
BRA d:8 (BT d:8) — PC ←PC+d:8 2 —————— 4
BRN d:8 (BF d:8) — PC ←PC+2 2 —————— 4
BHI d:8 — C ∨Z = 0 2 ——————4
BLS d:8 — C ∨Z = 1 2 —————— 4
BCC d:8 (BHS d:8) — C = 0 2 —————— 4
BCS d:8 (BLO d:8) — C = 1 2 —————— 4
BNE d:8 — Z = 0 2 —————— 4
BEQ d:8 — Z = 1 2 —————— 4
BVC d:8 — V = 0 2 —————— 4
BVS d:8 — V = 1 2 —————— 4
BPL d:8 — N = 0 2 —————— 4
BMI d:8 — N = 1 2 —————— 4
BGE d:8 — N⊕V = 0 2 —————— 4
BLT d:8 — N⊕V = 1 2 ——————4
BGT d:8 —
Z ∨(N⊕V) = 0
2 —————— 4
BLE d:8 —
Z ∨(N⊕V) = 1
2 —————— 4
JMP @Rn — PC ←Rn16 2 —————— 4
JMP @aa:16 — PC ←aa:16 4 —————— 6
JMP @@aa:8 — PC ←@aa:8 2 —————— 8
BSR d:8 — SP–2 →SP 2 —————— 6
PC →@SP
PC ←PC+d:8
527
#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied
No. of States
Addressing Mode/
Instruction Length
Condition Code
Operand Size
If
condition
is true
then
PC ←
PC+d:8
else next;
Branching
Condition
Table A-1 Instruction Set (cont)
Mnemonic Operation I H N Z V C
JSR @Rn — SP–2 →SP 2 —————— 6
PC →@SP
PC ←Rn16
JSR @aa:16 — SP–2 →SP 4 —————— 8
PC →@SP
PC ←aa:16
JSR @@aa:8 — SP–2 →SP 2 —————— 8
PC →@SP
PC ←@aa:8
RTS — PC ←@SP 2 —————— 8
SP+2 →SP
RTE — CCR ←@SP 2 ↕↕↕↕↕↕10
SP+2 →SP
PC ←@SP
SP+2 →SP
SLEEP — Transit to sleep mode. 2 —————— 2
LDC #xx:8, CCR B #xx:8 →CCR 2 ↕↕↕↕↕↕2
LDC Rs, CCR B Rs8 →CCR 2 ↕↕↕↕↕↕2
STC CCR, Rd B CCR →Rd8 2 —————— 2
ANDC #xx:8, CCR B CCR∧#xx:8 →CCR 2 ↕↕↕↕↕↕2
ORC #xx:8, CCR B CCR∨#xx:8 →CCR 2 ↕↕↕↕↕↕2
XORC #xx:8, CCR B CCR⊕#xx:8 →CCR 2 ↕↕↕↕↕↕2
NOP — PC ←PC+2 2 —————— 2
Notes: The number of states is the number of states required for execution when the instruction and its
operands are located in on-chip memory.
(1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0.
(4) The number of states required for execution is 4n+8 (n = value of R4L).
(5) These instructions are not supported by the H8/3437 Series.
(6) Set to 1 if the divisor is negative; otherwise cleared to 0.
(7) Set to 1 if the divisor is 0; otherwise cleared to 0.
528
#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied
No. of States
Addressing Mode/
Instruction Length (bytes)
Condition Code
Operand Size
A.2 Operation Code Map
Table A-2 is a map of the operation codes contained in the first byte of the instruction code (bits 15
to 8 of the first instruction word).
Some pairs of instructions have identical first bytes. These instructions are differentiated by the first
bit of the second byte (bit 7 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
529
Table A-2 Operation Code Map
"#
"#
High Low 0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
BRA*2
MULXU
BSET
SHLL
SHAL
SLEEP
BRN*2
DIVXU
BNOT
SHLR
SHAR
STC
BHI
BCLR
ROTXL
ROTL
LDC
BLS
BTS
ROTXR
ROTR
ORC
OR
BCC*2
RTS
XORC
XOR
BCS*2
BSR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
ANDC
AND
BNE
RTE
LDC
BEQ
NOT
NEG
BLD
BILD
BST
BIST
ADD
SUB
BVC BVS
MOV
INC
DEC
BPL
JMP
ADDS
SUBS
BMI
EEPMOV
MOV
CMP
BGE BLT
ADDX
SUBX
BGT
JSR
DAA
DAS
BLE
MOV
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
MOV*1
#
Notes: 1.
2.
Bit manipulation instructions
The MOVFPE and MOVTPE instructions are identical to MOV instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word).
The PUSH and POP instructions are identical in machine language to MOV instructions.
The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively.
530
A.3 Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution.
Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates
the number of cycles of each type occurring in each instruction. The total number of states required
for execution of an instruction can be calculated from these two tables as follows:
Execution states = I ×SI+ J ×SJ+ K ×SK+ L ×SL+ M ×SM+ N ×SN
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state inserted
in external memory access.
1. BSET #0, @FFC7
From table A-4: I = L = 2, J = K = M = N= 0
From table A-3: SI= 8, SL= 3
Number of states required for execution: 2 ×8 + 2 ×3 =22
2. JSR @@30
From table A-4: I = 2, J = K = 1, L = M = N = 0
From table A-3: SI= SJ= SK= 8
Number of states required for execution: 2 ×8 + 1 ×8 + 1 ×8 = 32
Table A-3. Number of States Taken by Each Cycle in Instruction Execution
Execution Status Access location
(Instruction Cycle) On-Chip Memory On-Chip Reg. Field External Memory
Instruction fetch SI2 6 6 + 2m
Branch address read SJ
Stack operation SK
Byte data access SL3 3 + m
Word data access SM6 6 + 2m
Internal operation SN11 1
Notes: m: Number of wait states inserted in access to external device.
531
Table A-4 Number of Cycles in Each Instruction
Instruction Branch Stack Byte Data Word Data Internal
Fetch Addr. Read Operation Access Access Operation
Instruction Mnemonic I J K L M N
ADD ADD.B #xx:8, Rd 1
ADD.B Rs, Rd 1
ADD.W Rs, Rd 1
ADDS ADDS.W #1/2, Rd 1
ADDX ADDX.B #xx:8, Rd 1
ADDX.B Rs, Rd 1
AND AND.B #xx:8, Rd 1
AND.B Rs, Rd 1
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd 1
BAND #xx:3, @Rd 2 1
BAND #xx:3, @aa:8 2 1
Bcc BRA d:8 (BT d:8) 2
BRN d:8 (BF d:8) 2
BHI d:8 2
BLS d:8 2
BCC d:8 (BHS d:8) 2
BCS d:8 (BLO d:8) 2
BNE d:8 2
BEQ d:8 2
BVC d:8 2
BVS d:8 2
BPL d:8 2
BMI d:8 2
BGE d:8 2
BLT d:8 2
BGT d:8 2
BLE d:8 2
BCLR BCLR #xx:3, Rd 1
BCLR #xx:3, @Rd 2 2
BCLR #xx:3, @aa:8 2 2
BCLR Rn, Rd 1
BCLR Rn, @Rd 2 2
BCLR Rn, @aa:8 2 2
Note: All values left blank are zero.
532
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Branch Stack Byte Data Word Data Internal
Fetch Addr. Read Operation Access Access Operation
Instruction Mnemonic I J K L M N
BIAND BIAND #xx:3, Rd 1
BIAND #xx:3, @Rd 2 1
BIAND #xx:3, @aa:8 2 1
BILD BILD #xx:3, Rd 1
BILD #xx:3, @Rd 2 1
BILD #xx:3, @aa:8 2 1
BIOR BIOR #xx:3, Rd 1
BIOR #xx:3, @Rd 2 1
BIOR #xx:3, @aa:8 2 1
BIST BIST #xx:3, Rd 1
BIST #xx:3, @Rd 2 2
BIST #xx:3, @aa:8 2 2
BIXOR BIXOR #xx:3, Rd 1
BIXOR #xx:3, @Rd 2 1
BIXOR #xx:3, @aa:8 2 1
BLD BLD #xx:3, Rd 1
BLD #xx:3, @Rd 2 1
BLD #xx:3, @aa:8 2 1
BNOT BNOT #xx:3, Rd 1
BNOT #xx:3, @Rd 2 2
BNOT #xx:3, @aa:8 2 2
BNOT Rn, Rd 1
BNOT Rn, @Rd 2 2
BNOT Rn, @aa:8 2 2
BOR BOR #xx:3, Rd 1
BOR #xx:3, @Rd 2 1
BOR #xx:3, @aa:8 2 1
BSET BSET #xx:3, Rd 1
BSET #xx:3, @Rd 2 2
BSET #xx:3, @aa:8 2 2
BSET Rn, Rd 1
BSET Rn, @Rd 2 2
BSET Rn, @aa:8 2 2
Note: All values left blank are zero.
533
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Branch Stack Byte Data Word Data Internal
Fetch Addr. Read Operation Access Access Operation
Instruction Mnemonic I J K L M N
BSR BSR d:8 2 1
BST BST #xx:3, Rd 1
BST #xx:3, @Rd 2 2
BST #xx:3, @aa:8 2 2
BTST BTST #xx:3, Rd 1
BTST #xx:3, @Rd 2 1
BTST #xx:3, @aa:8 2 1
BTST Rn, Rd 1
BTST Rn, @Rd 2 1
BTST Rn, @aa:8 2 1
BXOR BXOR #xx:3, Rd 1
BXOR #xx:3, @Rd 2 1
BXOR #xx:3, @aa:8 2 1
CMP CMP.B #xx:8, Rd 1
CMP.B Rs, Rd 1
CMP.W Rs, Rd 1
DAA DAA.B Rd 1
DAS DAS.B Rd 1
DEC DEC.B Rd 1
DIVXU DIVXU.B Rs, Rd 1 12
EEPMOV EEPMOV 2 2n+2*1
INC INC.B Rd 1
JMP JMP @Rn 2
JMP @aa:16 2 2
JMP @@aa:8 2 1 2
JSR JSR @Rn 2 1
JSR @aa:16 2 1 2
JSR @@aa:8 2 1 1
LDC LDC #xx:8, CCR 1
LDC Rs, CCR 1
MOV MOV.B #xx:8, Rd 1
MOV.B Rs, Rd 1
MOV.B @Rs, Rd 1 1
MOV.B @(d:16,Rs), Rd 2 1
Notes: All values left blank are zero.
*n: Initial value in R4L. Source and destination are accessed n + 1 times each.
534
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Branch Stack Byte Data Word Data Internal
Fetch Addr. Read Operation Access Access Operation
Instruction Mnemonic I J K L M N
MOV MOV.B @Rs+, Rd 1 1 2
MOV.B @aa:8, Rd 1 1
MOV.B @aa:16, Rd 2 1
MOV.B Rs, @Rd 1 1
MOV.B Rs, @(d:16, Rd) 2 1
MOV.B Rs, @–Rd 1 1 2
MOV.B Rs, @aa:8 1 1
MOV.B Rs, @aa:16 2 1
MOV.W #xx:16, Rd 2
MOV.W Rs, Rd 1
MOV.W @Rs, Rd 1 1
MOV.W @(d:16, Rs), Rd 2 1
MOV.W @Rs+, Rd 1 1 2
MOV.W @aa:16, Rd 2 1
MOV.W Rs, @Rd 1 1
MOV.W Rs, @(d:16, Rd) 2 1
MOV.W Rs, @–Rd 1 1 2
MOV.W Rs, @aa:16 2 1
MOVFPE MOVFPE @aa:16, Rd Not supported
MOVTPE MOVTPE.Rs, @aa:16 Not supported
MULXU MULXU.Rs, Rd 1 12
NEG NEG.B Rd 1
NOP NOP 1
NOT NOT.B Rd 1
OR OR.B #xx:8, Rd 1
OR.B Rs, Rd 1
ORC ORC #xx:8, CCR 1
POP POP Rd 1 1 2
PUSH PUSH Rd 1 1 2
ROTL ROTL.B Rd 1
ROTR ROTR.B Rd 1
ROTXL ROTXL.B Rd 1
ROTXR ROTXR.B Rd 1
RTE RTE 2 2 2
RTS RTS 2 1 2
Note: All values left blank are zero.
535
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Branch Stack Byte Data Word Data Internal
Fetch Addr. Read Operation Access Access Operation
Instruction Mnemonic I J K L M N
SHAL SHAL.B Rd 1
SHAR SHAR.B Rd 1
SHLL SHLL.B Rd 1
SHLR SHLR.B Rd 1
SLEEP SLEEP 1
STC STC CCR, Rd 1
SUB SUB.B Rs, Rd 1
SUB.W Rs, Rd 1
SUBS SUBS.W #1/2, Rd 1
SUBX SUBX.B #xx:8, Rd 1
SUBX.B Rs, Rd 1
XOR XOR.B #xx:8, Rd 1
XOR.B Rs, Rd 1
XORC XORC #xx:8, CCR 1
Note: All values left blank are zero.
536
Appendix B Internal I/O Register
B.1 Addresses
Addr.
(Last Register Bit Names
Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'80 FLMCR VPP ———EVPVE P
H'81 —————————
H'82 EBR1 LB7/—*LB6/—*LB5/—*LB4/—*LB3 LB2 LB1 LB0
H'83 EBR2 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
H'84
H'85
H'86
H'87
H'88 SMR C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI1
H'89 BRR
H'8A SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'8B TDR
H'8C SSR TDRE RDRF ORER FER PER TEND MPB MPBT
H'8D RDR
H'8E
H'8F
H'90 TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — FRT
H'91 TCSR ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
H'92 FRCH
H'93 FRCL
H'94 OCRAH
OCRBH
H'95 OCRAL
OCRBL
H'96 TCR IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
H'97 TOCR — — — OCRS OEA OEB OLVLA OLVLB
H'98 ICRAH
H'99 ICRAL
H'9A ICRBH
H'9B ICRBL
H'9C ICRCH
H'9D ICRCL
H'9E ICRDH
H'9F ICRDL
Notes: *H8/3437F /H8/3434F (Continued on next page)
FRT: Free-running timer
SCI1: Serial communication interface 1
537
Flash
memory or
external
addresses
(in expand-
ed modes)
(Continued from previous page)
Addr.
(Last Register Bit Names
Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'A0 TCR OE OS — — — CKS2 CKS1 CKS0 PWM0
H'A1 DTR
H'A2 TCNT
H'A3 —————————
H'A4 TCR OE OS — — — CKS2 CKS1 CKS0 PWM1
H'A5 DTR
H'A6 TCNT
H'A7 —————————
H'A8 TCSR/ OVF WT/IT TME — RST/NMI CKS2 CKS1 CKS0 WDT
TCNT
H'A9 TCNT
H'AA PAODR PA7PA6PA5PA4PA3PA2PA1PA0Port A
H'AB PAPIN/ PA7/PA
6
/PA
5
/PA
4
/PA
3
/PA
2
/PA
1
/PA
0
/
PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
H'AC P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Port 1
H'AD P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2
H'AE P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Port 3
H'AF ——————————
H'B0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1
H'B1 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2
H'B2 P1DR P17P16P15P14P13P12P11P10Port 1
H'B3 P2DR P27P26P25P24P23P22P21P20Port 2
H'B4 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3
H'B5 P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4
H'B6 P3DR P37P36P35P34P33P32P31P30Port 3
H'B7 P4DR P47P46P45P44P43P42P41P40Port 4
H'B8 P5DDR —————P5
2
DDR P51DDR P50DDR Port 5
H'B9 P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6
H'BA P5DR —————P5
2P51P50Port 5
H'BB P6DR P67P66P65P64P63P62P61P60Port 6
Notes: PWM0: Pulse-width modulation timer channel 0 (Continued on next page)
PWM1: Pulse-width modulation timer channel 1
WDT: Watchdog timer
538
(Continued from preceding page)
Addr.
(Last Register Bit Names
Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'BC PBODR PB7PB6PB5PB4PB3PB2PB1PB0Port B
H'BD P8DDR/ —/PB7P86DDR/ P85DDR/ P84DDR/ P83DDR/ P82DDR/ P81DDR/ P80DDR/ Port 8/
PBPIN PB6PB5PB4PB3PB2PB1PB0Port B
H'BE P7PIN/ P77/P7
6
/P7
5
/P7
4
/P7
3
/P7
2
/P7
1
/P7
0
/ Port 7/
PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Port B
H'BF P8DR — P86P85P84P83P82P81P80Port 8
H'C0 P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9
H'C1 P9DR P97P96P95P94P93P92P91P90
H'C2 WSCR RAMS RAM0 CKDBL — WMS1 WMS0 WC1 WC0
H'C3 STCR IICS IICD IICX IICE STAC MPE ICKS1 ICKS0
H'C4 SYSCR SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME
H'C5 MDCR ——————MDS1 MDS0
H'C6 ISCR IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
H'C7 IER IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
H'C8 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR0
H'C9 TCSR CMFB CMFA OVF — OS3 OS2 OS1 OS0
H'CA TCORA
H'CB TCORB
H'CC TCNT
H'CD —————————
H'CE —————————
H'CF —————————
H'D0 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR1
H'D1 TCSR CMFB CMFA OVF — OS3 OS2 OS1 OS0
H'D2 TCORA
H'D3 TCORB
H'D4 TCNT
H'D5 —————————
H'D6 —————————
H'D7 —————————
Notes: TMR0: 8-bit timer channel 0 (Continued on next page)
TMR1: 8-bit timer channel 1
539
(Continued from preceding page)
Addr.
(Last Register Bit Names
Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'D8 SMR C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI0
ICCR ICE IEIC MST TRS ACK CKS2 CKS1 CKS0 and I2C
H'D9 BRR
ICSR BBSY IRIC SCP — AL AAS ADZ ACKB
H'DA SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'DB TDR
H'DC SSR TDRE RDRF ORER FER PER TEND MPB MPBT
H'DD RDR
H'DE —————————
ICDR ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0
H'DF —————————
ICMR/ MLS/ WAIT/ —/ —/ —/ BC2/ BC1/ BC0/
SAR SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
H'E0 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D
H'E1 ADDRAL AD1 AD0 ——————
H'E2 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E3 ADDRBL AD1 AD0 ——————
H'E4 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E5 ADDRCL AD1 AD0 ——————
H'E6 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E7 ADDRDL AD1 AD0 ——————
H'E8 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0
H'E9 ADCR TRGE ———————
H'EA —————————
H'EB —————————
H'EC ——————————
H'ED —————————
H'EE —————————
H'EF —————————
Notes: A/D: Analog-to-digital converter (Continued on next page)
SCI0: Serial communication interface 0
I2C: I2C bus interface
540
(Continued from preceding page)
Addr.
(Last Register Bit Names
Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'F0 HICR —————IBFIE2 IBFIE1 FGA20E HIF
H'F1 KMIMR KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0
H'F2 KMPCR KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR
H'F3 KMIMRA KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8
H'F4 IDR1 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 HIF1
H'F5 ODR1 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
H'F6 STR1 DBU DBU DBU DBU C/DDBU IBF OBF
H'F7 —————————
H'F8 DADR0 D/A
H'F9 DADR1
H'FA DACR DAOE1 DAOE0 DAE —————
H'FB —————————
H'FC IDR2 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 HIF2
H'FD ODR2 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
H'FE STR2 DBU DBU DBU DBU C/DDBU IBF OBF
H'FF —————————
Note: HIF: Host interface
541
B.2 Function
TIER—Timer Interrupt Enable Register H'FF90 FRT
Bit No.
Initial value
Type of access permitted
R
W
R/W
Abbreviation
of register
name
Register name Address onto which
register is mapped
Name of
on-chip
supporting
module
Bit names
(abbreviations).
Bits marked “—”
are reserved.
Full name
of bit
Description
of bit function
Read only
Write only
Read or write
Bit
Initial value
Read/Write
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
R/W
3
OCIAE
0
R/W
0
—
1
—
2
OCIBE
0
R/W
1
OVIE
0
R/W
Overflow Interrupt Enable
0
1Overflow interrupt request is disabled.
Overflow interrupt request is enabled.
Output Compare Interrupt B Enable
0
1Output compare interrupt request B is disabled.
Output compare interrupt request B is enabled.
Output Compare Interrupt A Enable
0
1Output compare interrupt request A is disabled.
Output compare interrupt request A is enabled.
Input Capture Interrupt D Enable
0
1Input capture interrupt request D is disabled.
Input capture interrupt request D is enabled.
542
FLMCR—Flash Memory Control Register H'FF80 Flash memory
Bit
Initial value
Read/Write
7
VPP
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
EV
0
R/W
0
P
0
R/W
2
PV
0
R/W
1
E
0
R/W
Program Mode
0
1
Exit from program mode
Transition to program mode
Erase Mode
0
1Exit from erase mode
Transition to erase mode
Programming Power
0
112 V is not applied to FVPP
12 V is applied to FVPP
Program-Verify Mode
0
1Exit from program-verify mode
Transition to program-verify mode
Erase-Verify Mode
0
1Exit from erase-verify mode
Transition to erase-verify mode
543
EBR1—Erase Block Register 1 H'FF82 Flash memory
EBR2—Erase Block Register 2 H'FF83 Flash memory
Bit
Initial value
Read/Write
7
SB7
0
R/W
6
SB6
0
R/W
5
SB5
0
R/W
4
SB4
0
R/W
3
SB3
0
R/W
0
SB0
0
R/W
2
SB2
0
R/W
1
SB1
0
R/W
Small Block 7 to 0
0
1Corresponding block (SB7 to SB0) is not selected
Corresponding block (SB7 to SB0) is selected
Bit
Initial value
Read/Write
H8/3434 F-ZTAT
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
LB3
0
R/W
0
LB0
0
R/W
2
LB2
0
R/W
1
LB1
0
R/W
Large Block 3 to 0
0
1Corresponding block (LB3 to LB0) is not selected
Corresponding block (LB3 to LB0) is selected
Bit
Initial value
Read/Write
H8/3437 F-ZTAT
7
LB7
0
R/W
6
LB6
0
R/W
5
LB5
0
R/W
4
LB4
0
R/W
3
LB3
0
R/W
0
LB0
0
R/W
2
LB2
0
R/W
1
LB1
0
R/W
Large Block 7 to 0
0
1
Corresponding block (LB7 to LB0) is not selected
(Initial value)
Corresponding block (LB7 to LB0) is selected
544
SMR—Serial Mode Register H'FF88 SCI1
Bit
Initial value
Read/Write
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Clock Select
0
0
1
1
0
1
0
1
ø clock
øP/4 clock
øP/16 clock
øP/64 clock
Multiprocessor Mode
0
1Multiprocessor function disabled
Multiprocessor format selected
Stop Bit Length
0
1One stop bit
Two stop bits
Parity Mode
0
1Even parity
Odd parity
Parity Enable
0Transmit:
Receive:
Character Length
0
18-bit data length
7-bit data length
Communication Mode
0
1Asynchronous
Synchronous
Transmit:
Receive:
1
No parity bit added.
Parity bit not checked.
Parity bit added.
Parity bit checked.
545
546
BRR—Bit Rate Register H'FF89 SCI1
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Constant that determines the bit rate
SCR—Serial Control Register H'FF8A SCI1
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Clock Enable 0
0
1Asynchronous serial clock not output
Asynchronous serial clock output at SCK pin
Clock Enable 1
0
1Internal clock
External clock
Transmit End Interrupt Enable
0
1TSR-empty interrupt request is disabled.
TSR-empty interrupt request is enabled.
Multiprocessor Interrupt Enable
0
1Multiprocessor receive interrupt function is disabled.
Multiprocessor receive interrupt function is enabled.
Receive Enable
0
1Receive disabled
Receive enabled
Transmit Enable
0
1Transmit disabled
Transmit enabled
Receive Interrupt Enable
0
1Receive interrupt and receive error interrupt requests are disabled.
Receive interrupt and receive error interrupt requests are enabled.
Transmit Interrupt Enable
0
1TDR-empty interrupt request is disabled.
TDR-empty interrupt request is enabled.
547
TDR—Transmit Data Register H'FF8B SCI1
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Transmit data
548
SSR—Serial Status Register H'FF8C SCI1
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
ORER
0
R/(W)
4
FER
0
R/(W)
3
PER
0
R/(W)
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Multiprocessor Bit Transfer
0
1Multiprocessor bit = 0 in transmit data.
Multiprocessor bit = 1 in transmit data.
Multiprocessor Bit
Transmit End
0
1Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set to 1 when TE = 0, or when TDRE = 1 at the end of
character transmission.
Parity Error
0
1Cleared by reading PER = 1, then writing 0 in PER.
Set when a parity error occurs (parity of receive data
does not match parity selected by O/E bit in SMR).
Framing Error
0
1Cleared by reading FER = 1, then writing 0 in FER.
Set when a framing error occurs (stop bit is 0).
Overrun Error
0
1Cleared by reading ORER = 1, then writing 0 in ORER.
Set when an overrun error occurs (next data is completely
received while RDRF bit is set to 1).
Receive Data Register Full
0
1Cleared by reading RDRF = 1, then writing 0 in RDRF.
Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0
1Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = 0.
*****
Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits.
0
1Multiprocessor bit = 0 in receive data.
Multiprocessor bit = 1 in receive data.
549
RDR—Receive Data Register H'FF8D SCI1
Bit
Initial value
Read/Write
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Receive data
550
TIER—Timer Interrupt Enable Register H'FF90 FRT
Bit
Initial value
Read/Write
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
R/W
3
OCIAE
0
R/W
0
—
1
—
2
OCIBE
0
R/W
1
OVIE
0
R/W
Overflow Interrupt Enable
0
1Overflow interrupt request is disabled.
Overflow interrupt request is enabled.
Output Compare Interrupt B Enable
0
1Output compare interrupt request B is disabled.
Output compare interrupt request B is enabled.
Output Compare Interrupt A Enable
0
1Output compare interrupt request A is disabled.
Output compare interrupt request A is enabled.
Input Capture Interrupt D Enable
0
1Input capture interrupt request D is disabled.
Input capture interrupt request D is enabled.
Input Capture Interrupt C Enable
0
1Input capture interrupt request C is disabled.
Input capture interrupt request C is enabled.
Input Capture Interrupt B Enable
0
1Input capture interrupt request B is disabled.
Input capture interrupt request B is enabled.
Input Capture Interrupt A Enable
0
1Input capture interrupt request A is disabled.
Input capture interrupt request A is enabled.
551
TCSR—Timer Control/Status Register H'FF91 FRT
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)
6
ICFB
0
R/(W)
5
ICFC
0
R/(W)
4
ICFD
0
R/(W)
3
OCFA
0
R/(W)
0
CCLRA
0
R/W
2
OCFB
0
R/(W)
1
OVF
0
R/(W)
Counter Clear A
0
1FRC count is not cleared.
FRC count is cleared by compare-match A.
Timer Overflow Flag
Output Compare Flag B
0
1Cleared by reading OCFB = 1, then writing 0 in OCFB.
Set when FRC = OCRB.
Output Compare Flag A
0
1Cleared by reading OCFA = 1, then writing 0 in OCFA.
Set when FRC = OCRA.
Input Capture Flag D
0
1Cleared by reading ICFD = 1, then writing 0 in ICFD.
Set when FTID input signal is received.
Input Capture Flag C
0
1Cleared by reading ICFC = 1, then writing 0 in ICFC.
Set when FTIC input signal is received.
Input Capture Flag B
0
1Cleared by reading ICFB = 1, then writing 0 in ICFB.
Set when FTIB input causes FRC to be copied to ICRB.
Input Capture Flag A
0
1Cleared by reading ICFA = 1, then writing 0 in ICFA.
Set when FTIA input causes FRC to be copied to ICRA.
*****
Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits.
0
1Cleared by reading OVF = 1, then writing 0 in OVF.
Set when FRC changes from H'FFFF to H'0000.
**
552
FRC (H and L)—Free-Running Counter H'FF92, H'FF93 FRT
OCRA (H and L)—Output Compare Register A H'FF94, H'FF95 FRT
OCRB (H and L)—Output Compare Register B H'FF94, H'FF95 FRT
Continually compared with FRC → OCFB is set when OCRB = FRC.
Bit
Initial value
Read/Write
15
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
7
1
R/W
1
1
R/W
4
1
R/W
2
1
R/W
14
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
6
1
R/W
5
1
R/W
3
1
R/W
0
1
R/W
Continually compared with FRC → OCFA is set when OCRA = FRC.
Bit
Initial value
Read/Write
15
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
7
1
R/W
1
1
R/W
4
1
R/W
2
1
R/W
14
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
6
1
R/W
5
1
R/W
3
1
R/W
0
1
R/W
Bit
Initial value
Read/Write
15
0
R/W
12
0
R/W
10
0
R/W
8
0
R/W
7
0
R/W
1
0
R/W
4
0
R/W
2
0
R/W
Count value
14
0
R/W
13
0
R/W
11
0
R/W
9
0
R/W
6
0
R/W
5
0
R/W
3
0
R/W
0
0
R/W
553
TCR—Timer Control Register H'FF96 FRT
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
Clock Select
0
0
1
1
0
1
0
1
Internal clock source: øP/2
Internal clock source: øP/8
Internal clock source: øP/32
External clock source: counted on rising edge
Buffer Enable B
0
1ICRD is used for input capture D.
ICRD is buffer register for input capture B.
Buffer Enable A
0
1ICRC is used for input capture C.
ICRC is buffer register for input capture A.
Input Edge Select D
0
1Falling edge of FTID is valid.
Rising edge of FTID is valid.
Input Edge Select C
Input Edge Select B
0
1Falling edge of FTIB is valid.
Rising edge of FTIB is valid.
Input Edge Select A
0
1Falling edge of FTIA is valid.
Rising edge of FTIA is valid.
0
1Falling edge of FTIC is valid.
Rising edge of FTIC is valid.
554
TOCR—Timer Output Compare Control Register H'FF97 FRT
ICRA (H and L)—Input Capture Register A H'FF98, H'FF99 FRT
Contains FRC count captured on FTIA input.
Bit
Initial value
Read/Write
15
0
R
12
0
R
10
0
R
8
0
R
7
0
R
1
0
R
4
0
R
2
0
R
14
0
R
13
0
R
11
0
R
9
0
R
6
0
R
5
0
R
3
0
R
0
0
R
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
OCRS
0
R/W
3
OEA
0
R/W
0
OLVLB
0
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
Output Level B
0
1Compare-match B causes 0 output.
Compare-match B causes 1 output.
Output Level A
0
1Compare-match A causes 0 output.
Compare-match A causes 1 output.
Output Enable B
0
1Output compare B output is disabled.
Output compare B output is enabled.
Output Enable A
Output Compare Register Select
0
1The CPU can access OCRA.
The CPU can access OCRB.
0
1Output compare A output is disabled.
Output compare A output is enabled.
555
ICRB (H and L)—Input Capture Register B H'FF9A, H'FF9B FRT
ICRC (H and L)—Input Capture Register C H'FF9C, H'FF9D FRT
ICRD (H and L)—Input Capture Register D H'FF9E, H'FF9F FRT
Contains FRC count captured on FTID input, or old ICRB value in buffer mode.
Bit
Initial value
Read/Write
15
0
R
12
0
R
10
0
R
8
0
R
7
0
R
1
0
R
4
0
R
2
0
R
14
0
R
13
0
R
11
0
R
9
0
R
6
0
R
5
0
R
3
0
R
0
0
R
Contains FRC count captured on FTIC input, or old ICRA value in buffer mode.
Bit
Initial value
Read/Write
15
0
R
12
0
R
10
0
R
8
0
R
7
0
R
1
0
R
4
0
R
2
0
R
14
0
R
13
0
R
11
0
R
9
0
R
6
0
R
5
0
R
3
0
R
0
0
R
Contains FRC count captured on FTIB input.
Bit
Initial value
Read/Write
15
0
R
12
0
R
10
0
R
8
0
R
7
0
R
1
0
R
4
0
R
2
0
R
14
0
R
13
0
R
11
0
R
9
0
R
6
0
R
5
0
R
3
0
R
0
0
R
556
TCR—Timer Control Register H'FFA0 PWM0
DTR—Duty Register H'FFA1 PWM0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Pulse duty cycle
Bit
Initial value
Read/Write
7
OE
0
R/W
6
OS
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select (Values when øP = 10 MHz)
0
1
øP/2
øP/8
øP/32
øP/128
øP/256
øP/1024
øP/2048
øP/4096
Output Enable
0
1PWM output disabled; TCNT cleared to H'00 and stops.
PWM output enabled; TCNT runs.
0
1
0
1
0
1
0
1
0
1
0
1
Resolution
Internal
clock freq. PWM
period PWM
frequency
200 ns
800 ns
3.2 µs
12.8 µs
25.6 µs
102.4 µs
204.8 µs
409.6 µs
50 µs
200 µs
800 µs
3.2 ms
6.4 ms
25.6 ms
51.2 ms
102.4 ms
20 kHz
5 kHz
1.25 kHz
312.5 Hz
156.3 Hz
39.1 Hz
19.5 Hz
9.8 Hz
Output Select
0
1Positive logic
Negative logic
557
TCNT—Timer Counter H'FFA2 PWM0
TCR—Timer Control Register H'FFA4 PWM1
DTR—Duty Register H'FFA5 PWM1
TCNT—Timer Counter H'FFA6 PWM1
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Note: Bit functions are the same as for PWM0.
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Note: Bit functions are the same as for PWM0.
Bit
Initial value
Read/Write
7
OE
0
R/W
6
OS
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Note: Bit functions are the same as for PWM0.
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Count value (runs from H'00 to H'F9, then repeats from H'00)
558
TCSR—Timer Control/Status Register H'FFA8 WDT
Bit
Initial value
Read/Write
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select 2 to 0
0
1
Timer Enable
0
1
Timer disabled: TCNT is initialized to H’00 and
stopped
Timer enabled: TCNT runs; CPU interrupts can be
requested
Timer Mode Select
0
1Interval timer mode (OVF interrupt request) (initial value)
Watchdog timer mode (generates reset or NMI signal)
Overflow Flag
0
1Cleared by reading OVF = 1, then writing 0 in OVF (initial value)
Set when TCNT changes from H'FF to H'00
Note: * Only 0 can be written, to clear the flag.
0
1
0
1
øP/2
øP/32
øP/64
øP/128
øP/256
øP/512
øP/2048
øP/4096
0
1
0
1
0
1
0
1
Reset or NMI
0
1Functions as NMI (initial value)
Functions as reset
(initial value)
559
TCNT—Timer Counter H'FFA9 (read), WDT
H'FFA8 (write)
P1PCR—Port 1 Input Pull-Up Control Register H'FFAC Port 1
P2PCR—Port 2 Input Pull-Up Control Register H'FFAD Port 2
Bit
Initial value
Read/Write
7
P27PCR
0
R/W
6
P26PCR
0
R/W
5
P25PCR
0
R/W
4
P24PCR
0
R/W
3
P23PCR
0
R/W
0
P20PCR
0
R/W
2
P22PCR
0
R/W
1
P21PCR
0
R/W
Port 2 Input Pull-Up Control
0
1Input pull-up transistor is off.
Input pull-up transistor is on.
Bit
Initial value
Read/Write
7
P17PCR
0
R/W
6
P16PCR
0
R/W
5
P15PCR
0
R/W
4
P14PCR
0
R/W
3
P13PCR
0
R/W
0
P10PCR
0
R/W
2
P12PCR
0
R/W
1
P11PCR
0
R/W
Port 1 Input Pull-Up Control
0
1Input pull-up transistor is off.
Input pull-up transistor is on.
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Count value
560
P3PCR—Port 3 Input Pull-Up Control Register H'FFAE Port 3
P1DDR—Port 1 Data Direction Register H'FFB0 Port 1
P1DR—Port 1 Data Register H'FFB2 Port 1
Bit
Initial value
Read/Write
7
P17
0
R/W
6
P16
0
R/W
5
P15
0
R/W
4
P14
0
R/W
3
P13
0
R/W
0
P10
0
R/W
2
P12
0
R/W
1
P11
0
R/W
Bit
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
7
P17DDR
1
—
0
W
6
P16DDR
1
—
0
W
5
P15DDR
1
—
0
W
4
P14DDR
1
—
0
W
3
P13DDR
1
—
0
W
0
P10DDR
1
—
0
W
2
P12DDR
1
—
0
W
1
P11DDR
1
—
0
W
Port 1 Input/Output Control
0
1Input port
Output port
Bit
Initial value
Read/Write
7
P37PCR
0
R/W
6
P36PCR
0
R/W
5
P35PCR
0
R/W
4
P34PCR
0
R/W
3
P33PCR
0
R/W
0
P30PCR
0
R/W
2
P32PCR
0
R/W
1
P31PCR
0
R/W
Port 3 Input Pull-Up Control
0
1Input pull-up transistor is off.
Input pull-up transistor is on.
561
P2DDR—Port 2 Data Direction Register H'FFB1 Port 2
P2DR—Port 2 Data Register H'FFB3 Port 2
P3DDR—Port 3 Data Direction Register H'FFB4 Port 3
Bit
Initial value
Read/Write
7
P37DDR
0
W
6
P36DDR
0
W
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
0
P30DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
Port 3 Input/Output Control
0
1Input port
Output port
Bit
Initial value
Read/Write
7
P27
0
R/W
6
P26
0
R/W
5
P25
0
R/W
4
P24
0
R/W
3
P23
0
R/W
0
P20
0
R/W
2
P22
0
R/W
1
P21
0
R/W
Bit
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
7
P27DDR
1
—
0
W
6
P26DDR
1
—
0
W
5
P25DDR
1
—
0
W
4
P24DDR
1
—
0
W
3
P23DDR
1
—
0
W
0
P20DDR
1
—
0
W
2
P22DDR
1
—
0
W
1
P21DDR
1
—
0
W
Port 2 Input/Output Control
0
1Input port
Output port
562
P3DR—Port 3 Data Register H'FFB6 Port 3
P4DDR—Port 4 Data Direction Register H'FFB5 Port 4
P4DR—Port 4 Data Register H'FFB7 Port 4
P5DDR—Port 5 Data Direction Register H'FFB8 Port 5
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
P50DDR
0
W
2
P52DDR
0
W
1
P51DDR
0
W
Port 5 Input/Output Control
0
1Input port
Output port
Bit
Initial value
Read/Write
7
P47
0
R/W
6
P46
0
R/W
5
P45
0
R/W
4
P44
0
R/W
3
P43
0
R/W
0
P40
0
R/W
2
P42
0
R/W
1
P41
0
R/W
Bit
Initial value
Read/Write
7
P47DDR
0
W
6
P46DDR
0
W
5
P45DDR
0
W
4
P44DDR
0
W
3
P43DDR
0
W
0
P40DDR
0
W
2
P42DDR
0
W
1
P41DDR
0
W
Port 4 Input/Output Control
0
1Input port
Output port
Bit
Initial value
Read/Write
7
P37
0
R/W
6
P36
0
R/W
5
P35
0
R/W
4
P34
0
R/W
3
P33
0
R/W
0
P30
0
R/W
2
P32
0
R/W
1
P31
0
R/W
563
P5DR—Port 5 Data Register H'FFBA Port 5
P6DDR—Port 6 Data Direction Register H'FFB9 Port 6
P6DR—Port 6 Data Register H'FFBB Port 6
P7PIN—Port 7 Input Data Register H'FFBE Port 7
Bit
Initial value
Read/Write
7
P77
*
R
6
P76
*
R
5
P75
*
R
4
P74
*
R
3
P73
*
R
0
P70
*
R
2
P72
*
R
1
P71
*
R
Note: Depends on the levels of pins P77 to P70.
*
Bit
Initial value
Read/Write
7
P67
0
R/W
6
P66
0
R/W
5
P65
0
R/W
4
P64
0
R/W
3
P63
0
R/W
0
P60
0
R/W
2
P62
0
R/W
1
P61
0
R/W
Bit
Initial value
Read/Write
7
P67DDR
0
W
6
P66DDR
0
W
5
P65DDR
0
W
4
P64DDR
0
W
3
P63DDR
0
W
0
P60DDR
0
W
2
P62DDR
0
W
1
P61DDR
0
W
Port 6 Input/Output Control
0
1Input port
Output port
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
P50
0
R/W
2
P52
0
R/W
1
P51
0
R/W
564
565
P8DDR—Port 8 Data Direction Register H'FFBD Port 8
P8DR—Port 8 Data Register H'FFBF Port 8
P9DDR—Port 9 Data Direction Register H'FFC0 Port 9
Bit
Modes 1 and 2
Initial value
Read/Write
Mode 3
Initial value
Read/Write
7
P97DDR
0
W
0
W
6
P96DDR
1
—
0
W
5
P95DDR
0
W
0
W
4
P94DDR
0
W
0
W
3
P93DDR
0
W
0
W
0
P90DDR
0
W
0
W
2
P92DDR
0
W
0
W
1
P91DDR
0
W
0
W
Port 9 Input/Output Control
0
1Input port
Output port
Bit
Initial value
Read/Write
7
—
1
—
6
P86
0
R/W
5
P85
0
R/W
4
P84
0
R/W
3
P83
0
R/W
0
P80
0
R/W
2
P82
0
R/W
1
P81
0
R/W
Bit
Initial value
Read/Write
7
—
1
—
6
P86DDR
0
W
5
P85DDR
0
W
4
P84DDR
0
W
3
P83DDR
0
W
0
P80DDR
0
W
2
P82DDR
0
W
1
P81DDR
0
W
Port 8 Input/Output Control
0
1Input port
Output port
P9DR—Port 9 Data Register H'FFC1 Port 9
PADDR—Port A Data Direction Register H'AB Port A
PAPIN—Port A Input Data Register H'AB Port A
PAODR—Port A Output Data Register H'AA Port A
Bit
Initial value
Read/Write
7
PA7
0
R/W
6
PA6
0
R/W
5
PA5
0
R/W
4
PA4
0
R/W
3
PA3
0
R/W
0
PA0
0
R/W
2
PA2
0
R/W
1
PA1
0
R/W
Port A Output Data/Input Pull-Up Control
0
1
During output
0 output
1 output
During input
Input pull-up transistor off
Input pull-up transistor on
Bit
Initial value
Read/Write
7
PA7
—*
R
6
PA6
—*
R
5
PA5
—*
R
4
PA4
—*
R
3
PA3
—*
R
0
PA0
—*
R
2
PA2
—*
R
1
PA1
—*
R
Note: * Depends on the levels of pins PA7 to PA0.
Bit
Initial value
Read/Write
7
PA7DDR
0
W
6
PA6DDR
0
W
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
0
PA0DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
Port A Input/Output Control
0
1Input port
Output port
Bit
Initial value
Read/Write
7
P97
0
R/W
6
P96
*
R
5
P95
0
R/W
4
P94
0
R/W
3
P93
0
R/W
0
P90
0
R/W
2
P92
0
R/W
1
P91
0
R/W
Note: Depends on the level of pin P96.
*
566
PBDDR—Port B Data Direction Register H'BE Port B
PBPIN—Port B Input Data Register H'BD Port B
PBODR—Port B Output Data Register H'BC Port B
Bit
Initial value
Read/Write
7
PB7
0
R/W
6
PB6
0
R/W
5
PB5
0
R/W
4
PB4
0
R/W
3
PB3
0
R/W
0
PB0
0
R/W
2
PB2
0
R/W
1
PB1
0
R/W
Port B Output Data/Input Pull-Up Control
0
1
During output
0 output
1 output
During input
Input pull-up transistor off
Input pull-up transistor on
Bit
Initial value
Read/Write
7
PB7
—*
R
6
PB6
—*
R
5
PB5
—*
R
4
PB4
—*
R
3
PB3
—*
R
0
PB0
—*
R
2
PB2
—*
R
1
PB1
—*
R
Note: * Depends on the levels of pins PB7 to PB0.
Bit
Initial value
Read/Write
7
PB7DDR
0
W
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
0
PB0DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
Port B Input/Output Control
0
1Input port
Output port
567
WSCR—Wait-State Control Register H'FFC2 System control
Bit
Initial value
Read/Write
7
RAMS
0
R/W
6
RAM0
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
Wait Count
0
0
1
1
0
1
0
1
No wait states inserted by wait-state controller (initial value)
1 state inserted
2 states inserted
3 states inserted
Wait Mode Select
Clock Double
RAM Select and RAM Area Select
0
1Supporting module clock frequency is not divided (øP = ø) (initial value)
Supporting module clock frequency is divided by two (øP = ø/2)
0
0
1
1
0
1
0
1
Programmable wait mode
No wait states inserted by wait-state controller
Pin wait mode
Pin auto-wait mode
None
H'FC80 to H'FCFF
H'FC80 to H'FD7F
H'FC00 to H'FC7F
RAM Area ROM AreaRAMS, RAM0 —
H'0080 to H'00FF
H'0080 to H'017F
H'0000 to H'007F
0
0
1
1
0
1
0
1
(initial value)
H8/3434 F-ZTAT
H8/3437 F-ZTAT
None
H'F880 to H'F8FF
H'F880 to H'F97F
H'F800 to H'F87F
RAM Area ROM AreaRAMS, RAM0 —
H'0080 to H'00FF
H'0080 to H'017F
H'0000 to H'007F
0
0
1
1
0
1
0
1
568
STCR—Serial/Timer Control Register H'FFC3 System Control
Bit
Initial value
Read/Write
7
IICS
0
R/W
6
IICD
0
R/W
5
IICX
0
R/W
4
IICE
0
R/W
3
STAC
0
R/W
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
Internal Clock Source Select
See TCR under TMR0 and TMR1.
Multiprocessor Enable
0
1Multiprocessor communication function is disabled.
Multiprocessor communication function is enabled.
Slave Mode Control Input Switch
0
1CS2 and IOW are enabled
ECS2 and EIOW are enabled
I2C Master Enable
0
1I2C bus interface data registers and control registers are disabled (initial value)
I2C bus interface data registers and control registers are enabled
I2C Transfer Rate Select
I2C Extra Buffer Reserve
I2C Extra Buffer Select
0
1PA7 to PA4 are normal input/output pins
PA7 to PA4 are selected for bus drive
IICX CKS2*CKS1*CKS0*Clock Transfer Rate
Notes: øP = ø.
* CKS2 to CKS0 are bits 2 to 0 of the I2C bus control register in the I2C bus interface.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
øP/28
øP/40
øP/48
øP/64
øP/80
øP/100
øP/112
øP/128
øP/56
øP/80
øP/96
øP/128
øP/160
øP/200
øP/224
øP/256
143 kHz
100 kHz
83.3 kHz
62.5 kHz
50.0 kHz
40.0 kHz
35.7 kHz
31.3 kHz
71.4 kHz
50.0 kHz
41.7 kHz
31.3 kHz
25.0 kHz
20.0 kHz
17.9 kHz
15.6 kHz
øP = 4 MHz øP = 5 MHz øP = 8 MHz
øP = 10 MHz øP = 16 MHz
179 kHz
125 kHz
104 kHz
78.1 kHz
62.5 kHz
50.0 kHz
44.6 kHz
39.1 kHz
89.3 kHz
62.5 kHz
52.1 kHz
39.1 kHz
31.3 kHz
25.0 kHz
22.3 kHz
19.5 kHz
286 kHz
200 kHz
167 kHz
125 kHz
100 kHz
80.0 kHz
71.4 kHz
62.5 kHz
143 kHz
100 kHz
83.3 kHz
62.5 kHz
50.0 kHz
40.0 kHz
35.7 kHz
31.3 kHz
357 kHz
250 kHz
208 kHz
156 kHz
125 kHz
100 kHz
89.3 kHz
78.1 kHz
179 kHz
125 kHz
104 kHz
78.1 kHz
62.5 kHz
50.0 kHz
44.6 kHz
39.1 kHz
571 kHz
400 kHz
333 kHz
250 kHz
200 kHz
160 kHz
143 kHz
125 kHz
286 kHz
200 kHz
167 kHz
125 kHz
100 kHz
80.0 kHz
71.4 kHz
62.5 kHz
569
SYSCR—System Control Register H'FFC4 System Control
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
RAM Enable
0
1On-chip RAM is disabled.
On-chip RAM is enabled. (initial value)
Standby Timer Select 2 to 0 (ZTAT and Mask ROM Versions)
0
0
0
0
1
1
Clock settling time = 8,192 states (initial value)
Clock settling time = 16,384 states
Clock settling time = 32,768 states
Clock settling time = 65,536 states
Clock settling time = 131,072 states
Unused
Software Standby
0
1SLEEP instruction causes transition to sleep mode. (initial value)
SLEEP instruction causes transition to software standby mode.
0
0
1
1
0
1
0
1
0
1
—
—
Host Interface Enable
0
1Host interface is prohibited (initial value)
Host interface is allowed (slave mode)
NMI Edge
0
1Falling edge of NMI is detected.
Rising edge of NMI is detected.
External Reset
0
1Reset was caused by watchdog timer overflow
Reset was caused by external reset signal (initial value)
Standby Timer Select 2 to 0 (F-ZTAT Version)
0
0
0
0
1
1
1
Settling time = 8,192 states (initial value)
Settling time = 16,384 states
Settling time = 32,768 states
Settling time = 65,536 states
Settling time = 131,072 states
Settling time = 1,024 states
Unused
0
0
1
1
0
0
1
0
1
0
1
0
1
—
570
MDCR—Mode Control Register H'FFC5 System Control
ISCR—IRQ Sense Control Register H'FFC6 System Control
IER—IRQ Enable Register H'FFC7 System Control
Bit
Initial value
Read/Write
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
IRQ0 to IRQ7 Enable
0
1IRQ0 to IRQ7 are disabled.
IRQ0 to IRQ7 are enabled.
Bit
Initial value
Read/Write
7
IRQ7SC
0
R/W
6
IRQ6SC
0
R/W
5
IRQ5SC
0
R/W
4
IRQ4SC
0
R/W
3
IRQ3SC
0
R/W
0
IRQ0SC
0
R/W
2
IRQ2SC
0
R/W
1
IRQ1SC
0
R/W
IRQ0 to IRQ7 Sense Control
0
1IRQ0 to IRQ7 are level-sensed (active low).
IRQ0 to IRQ7 are edge-sensed (falling edge).
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
0
—
3
—
0
—
0
MDS0
*
R
2
—
1
—
1
MDS1
*
R
Mode Select Bits
Value at mode pins.
Note: Determined by inputs at pins MD1 and MD0.
*
571
572
TCR—Timer Control Register H'FFC8 TMR0
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select
CKS2
0
0
0
0
0
0
0
1
1
1
1
Timer stopped
øP/8 internal clock, falling edge
øP/2 internal clock, falling edge
øP/64 internal clock, falling edge
øP/32 internal clock, falling edge
øP/1024 internal clock, falling edge
øP/256 internal clock, falling edge
Timer stopped
External clock, rising edge
External clock, falling edge
External clock, rising and falling edges
Counter Clear
0
0
1
1
Counter is not cleared.
Cleared by compare-match A.
Cleared by compare-match B.
Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
Compare-Match Interrupt Enable A
0
1Compare-match A interrupt request is disabled.
Compare-match A interrupt request is enabled.
Compare-Match Interrupt Enable B
0
1Compare-match B interrupt request is disabled.
Compare-match B interrupt request is enabled.
0
1Overflow interrupt request is disabled.
Overflow interrupt request is enabled.
0
1
0
1
CKS1
0
0
0
1
1
1
1
0
0
1
1
CKS0
0
1
1
0
0
1
1
0
1
0
1
ICKS1
—
—
—
—
—
—
—
—
—
—
—
ICKS0
—
0
1
0
1
0
1
—
—
—
—
TCR STCR Description
573
TCSR—Timer Control/Status Register H'FFC9 TMR0
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)
6
CMFA
0
R/(W)
5
OVF
0
R/(W)
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Output Select
0
0
1
1
No change on compare-match A.
Output 0 on compare-match A.
Output 1 on compare-match A.
Invert (toggle) output on compare-match A.
Output Select
0
0
1
1
No change on compare-match B.
Output 0 on compare-match B.
Output 1 on compare-match B.
Invert (toggle) output on compare-match B.
Timer Overflow Flag
0
1Cleared by reading OVF = 1, then writing 0 in OVF.
Set when TCNT changes from H'FF to H'00.
Compare-Match Flag A
0
1Cleared by reading CMFA = 1, then writing 0 in CMFA.
Set when TCNT = TCORA.
Compare-Match Flag B
0
1Cleared by reading CMFB = 1, then writing 0 in CMFB.
Set when TCNT = TCORB.
Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
When all four bits (OS3 to OS0) are cleared to 0, output is disabled.
Notes: 1.
2.
*1*1*1
*2*2*2*2
0
1
0
1
0
1
0
1
574
TCORA—Time Constant Register A H'FFCA TMR0
TCORB—Time Constant Register B H'FFCB TMR0
TCNT—Timer Counter H'FFCC TMR0
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Count value
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
The CMFB bit is set to 1 when TCORB = TCNT.
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
The CMFA bit is set to 1 when TCORA = TCNT.
TCR—Timer Control Register H'FFD0 TMR1
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select
CKS2
0
0
0
0
0
0
0
1
1
1
1
Timer stopped
øP/8 internal clock, falling edge
øP/2 internal clock, falling edge
øP/64 internal clock, falling edge
øP/128 internal clock, falling edge
øP/1024 internal clock, falling edge
øP/2048 internal clock, falling edge
Timer stopped
External clock, rising edge
External clock, falling edge
External clock, rising and falling edges
Counter Clear
0
0
1
1
Counter is not cleared.
Cleared by compare-match A.
Cleared by compare-match B.
Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
Compare-Match Interrupt Enable A
0
1Compare-match A interrupt request is disabled.
Compare-match A interrupt request is enabled.
Compare-Match Interrupt Enable B
0
1Compare-match B interrupt request is disabled.
Compare-match B interrupt request is enabled.
0
1Overflow interrupt request is disabled.
Overflow interrupt request is enabled.
0
1
0
1
CKS1
0
0
0
1
1
1
1
0
0
1
1
CKS0
0
1
1
0
0
1
1
0
1
0
1
ICKS1
—
0
1
0
1
0
1
—
—
—
—
ICKS0
—
—
—
—
—
—
—
—
—
—
—
TCR STCR Description
575
TCSR—Timer Control/Status Register H'FFD1 TMR1
TCORA—Time Constant Register A H'FFD2 TMR1
TCORB—Time Constant Register B H'FFD3 TMR1
TCNT—Timer Counter H'FFD4 TMR1
Bit
Initial value
Read/Write
Note: Bit functions are the same as for TMR0.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
Note: Bit functions are the same as for TMR0.
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
Note: Bit functions are the same as for TMR0.
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)
6
CMFA
0
R/(W)
5
OVF
0
R/(W)
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
*1*1*1
*2*2*2*2
Bit functions are the same as for TMR0.
1. Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
2. When all four bits (OS3 to OS0) are cleared to 0, output is disabled.
Notes:
576
SMR—Serial Mode Register H'FFD8 SCI0
Bit
Initial value
Read/Write
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Clock Select
0
0
1
1
0
1
0
1
ø clock
øP/4 clock
øP/16 clock
øP/64 clock
Multiprocessor Mode
0
1Multiprocessor function disabled
Multiprocessor format selected
Stop Bit Length
0
1One stop bit
Two stop bits
Parity Mode
0
1Even parity
Odd parity
Parity Enable
0Transmit:
Receive:
Character Length
0
18-bit data length
7-bit data length
Communication Mode
0
1Asynchronous
Synchronous
Transmit:
Receive:
1
No parity bit added.
Parity bit not checked.
Parity bit added.
Parity bit checked.
Note: Bit functions are the same as for SCI1.
577
ICCR—I2C Bus Control Register H'FFD8 I2C
Bit
Initial value
Read/Write
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACK
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Transfer Clock Select
Acknowledgement Mode Select
0
1Acknowledgement mode
Serial mode
Master/Slave Select and Transmit/Receive Select
0
1
Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
0
1
0
1
I2C Bus Interface Interrupt Enable
0
1Interrupts disabled
Interrupts enabled
I2C Bus Interface Enable
0
1
Interface module disabled, with pins SCL and SDA operating as ports
Interface module enabled for transfer operations, with pins SCL and SDA capable of bus drive
IICX*CKS2 CKS1 CKS0 Clock Transfer Rate
Note: When øP = ø.
* IICX is bit 5 of the serial timer control register (STCR).
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
øP/28
øP/40
øP/48
øP/64
øP/80
øP/100
øP/112
øP/128
øP/56
øP/80
øP/96
øP/128
øP/160
øP/200
øP/224
øP/256
143 kHz
100 kHz
83.3 kHz
62.5 kHz
50.0 kHz
40.0 kHz
35.7 kHz
31.3 kHz
71.4 kHz
50.0 kHz
41.7 kHz
31.3 kHz
25.0 kHz
20.0 kHz
17.9 kHz
15.6 kHz
øP = 4 MHz øP = 5 MHz øP = 8 MHz
øP = 10 MHz øP = 16 MHz
179 kHz
125 kHz
104 kHz
78.1 kHz
62.5 kHz
50.0 kHz
44.6 kHz
39.1 kHz
89.3 kHz
62.5 kHz
52.1 kHz
39.1 kHz
31.3 kHz
25.0 kHz
22.3 kHz
19.5 kHz
286 kHz
200 kHz
167 kHz
125 kHz
100 kHz
80.0 kHz
71.4 kHz
62.5 kHz
143 kHz
100 kHz
83.3 kHz
62.5 kHz
50.0 kHz
40.0 kHz
35.7 kHz
31.3 kHz
357 kHz
250 kHz
208 kHz
156 kHz
125 kHz
100 kHz
89.3 kHz
78.1 kHz
179 kHz
125 kHz
104 kHz
78.1 kHz
62.5 kHz
50.0 kHz
44.6 kHz
39.1 kHz
571 kHz
400 kHz
333 kHz
250 kHz
200 kHz
160 kHz
143 kHz
125 kHz
286 kHz
200 kHz
167 kHz
125 kHz
100 kHz
80.0 kHz
71.4 kHz
62.5 kHz
578
ICSR—I2C Bus Status Register H'FFD9 I2C
Bit
Initial value
Read/Write
7
BBSY
0
R/W
6
IRIC
0
R/(W)*
5
SCP
1
W
4
—
1
—
3
AL
0
R/(W)*
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
Acknowledge Bit
0
1
Receive mode: 0 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has acknowledged the data
Receive mode: 1 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has not acknowledged the data
General Call Address Recognition Flag
0
1
General call address not recognized
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading ADZ = 1, then writing 0
General call address recognized
Set when the general call address is detected in slave receive mode
Slave Address Recognition Flag
0
1
Slave address or general call address not recognized (Initial value)
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading AAS = 1, then writing 0
Slave address or general call address recognized
Set when the slave address or general call address is detected in slave receive mode
Arbitration Lost Flag
0
1
Bus arbitration won
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading AL = 1, then writing 0
Arbitration lost
Set if the internal SDA and bus line disagree at the rise of SCL in master transmit mode
Set if the internal SCL is high at the fall of SCL in master transmit mode
Start Condition/Stop Condition Prohibit
0
1Writing 0 issues a start or stop condition, in combination with BBSY
Reading always results in 1
Writing is ignored
I2C Bus Interface Interrupt Request Flag
0
1
Waiting for transfer, or transfer in progress
Cleared by reading IRIC = 1, then writing 0
Interrupt requested
Set to 1 at the following times:
Master mode
• End of data transfer
• Bus arbitration lost
Slave mode (when FS = 0)
• When the slave address is matched, and whenever a data transfer ends at timing of
a retransmit start condition after address matching or a stop condition is detected
• When a general call address is detected, and whenever a data transfer ends at timing
of a retransmit start condition after address detection or a stop condition is detected
Slave mode (when FS = 1)
• End of data transfer
Bus Busy
0
1
Bus is free
Cleared by detection
of a stop condition
Bus is busy
Set by detection
of a start condition
Note: * Only 0 can be written, to clear the flag.
579
BRR—Bit Rate Register H'FFD9 SCI0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Constant that determines the bit rate
Note: Bit functions are the same as for SCI1.
580
SCR—Serial Control Register H'FFDA SCI0
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Clock Enable 0
0
1Asynchronous serial clock not output
Asynchronous serial clock output at SCK pin
Clock Enable 1
0
1Internal clock
External clock
Transmit End Interrupt Enable
0
1TSR-empty interrupt request is disabled.
TSR-empty interrupt request is enabled.
Multiprocessor Interrupt Enable
0
1Multiprocessor receive interrupt function is disabled.
Multiprocessor receive interrupt function is enabled.
Receive Enable
0
1Receive disabled
Receive enabled
Transmit Enable
0
1Transmit disabled
Transmit enabled
Receive Interrupt Enable
0
1Receive-end interrupt and receive-error interrupt requests are disabled.
Receive-end interrupt and receive-error interrupt requests are enabled.
Transmit Interrupt Enable
0
1TDR-empty interrupt request is disabled.
TDR-empty interrupt request is enabled.
Note: Bit functions are the same as for SCI1.
581
TDR—Transmit Data Register H'FFDB SCI0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Transmit data
Note: Bit functions are the same as for SCI1.
582
SSR—Serial Status Register H'FFDC SCI0
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
ORER
0
R/(W)
4
FER
0
R/(W)
3
PER
0
R/(W)
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Multiprocessor Bit Transfer
0
1Multiprocessor bit = 0 in transmit data.
Multiprocessor bit = 1 in transmit data.
Multiprocessor Bit
Transmit End
0
1Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set to 1 when TE = 0, or when TDRE = 1 at the end of
character transmission.
Parity Error
0
1Cleared by reading PER = 1, then writing 0 in PER.
Set when a parity error occurs (parity of receive data
does not match parity selected by O/E bit in SMR).
Framing Error
0
1Cleared by reading FER = 1, then writing 0 in FER.
Set when a framing error occurs (stop bit is 0).
Overrun Error
0
1Cleared by reading ORER = 1, then writing 0 in ORER.
Set when an overrun error occurs (next data is completely
received while RDRF bit is set to 1).
Receive Data Register Full
0
1Cleared by reading RDRF = 1, then writing 0 in RDRF.
Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0
1Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = 0.
*****
0
1
Multiprocessor bit = 0 in receive data.
Multiprocessor bit = 1 in receive data.
Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits.
Bit functions are the same as for SCI1.
Note: *
583
RDR—Receive Data Register H'FFDD SCI0
ICDR—I2C Bus Data Register H'FFDE I2C
SAR—Slave Address Register H'FFDF I2C
Bit
Initial value
Read/Write
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Slave address
Format Select
0
1Addressing format, slave address recognized
Non-addressing format
Bit
Initial value
Read/Write
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
0
ICDR0
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
Transmit/receive data
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI1.
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Receive data
584
585
ICMR—I2C Bus Mode Register H'FFDF I2C
Bit
Initial value
Read/Write
7
MLS
0
R/W
6
WAIT
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
Bit Counter
BC0 Serial Mode
8
1
2
3
4
5
6
7
Wait Insertion Bit
0
1Data and acknowledge transferred consecutively
Wait inserted between data and acknowledge
BC1BC2
0
1
0
1
0
1
Bits/Frame
0
1
0
1
0
1
0
1
Acknowledgement Mode
9
2
3
4
5
6
7
8
MSB-First/LSB-First
0
1MSB-first
LSB-first
ADDRA (H and L)—A/D Data Register A H'FFE0, H'FFE1 A/D
ADDRB (H and L)—A/D Data Register B H'FFE2, H'FFE3 A/D
ADDRC (H and L)—A/D Data Register C H'FFE4, H'FFE5 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
A/D Conversion Data
10-bit data giving an A/D conversion result
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRCH ADDRCL
Reserved Bits
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
A/D Conversion Data
10-bit data giving an A/D conversion result
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRBH ADDRBL
Reserved Bits
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
A/D Conversion Data
10-bit data giving an A/D conversion result
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRAH ADDRAL
Reserved Bits
586
ADDRD (H and L)—A/D Data Register D H'FFE6, H'FFE7 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
A/D Conversion Data
10-bit data giving an A/D conversion result
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRDH ADDRDL
Reserved Bits
587
588
ADCSR—A/D Control/Status Register H'FFE8 A/D
Bit
Initial value
Read/Write
7
ADF
0
R/(W)
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
Channel Select
Clock Select
0
1Conversion time = 266 states (max)
Conversion time = 134 states (max)
*
Note: * Only 0 can be written, to clear the flag.
CH2
0
1
CH1
0
1
0
1
CH0
0
1
0
1
0
1
0
1
Single Mode
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Scan Mode
AN0
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
AN4, AN5
AN4 to AN6
AN4 to AN7
Scan Mode
0
1Single mode
Scan mode
A/D Start
0
1A/D conversion is halted.
A/D Interrupt Enable
0
1The A/D interrupt request (ADI) is disabled.
The A/D interrupt request (ADI) is enabled.
A/D End Flag
0
1Cleared from 1 to 0 when CPU reads ADF = 1, then writes 0 in ADF.
Set to 1 at the following times:
1. Single mode: at the completion of A/D conversion
2. Scan mode: when all selected channels have been converted.
Single mode:
One A/D conversion is performed, then this bit is automatically cleared to 0.
Scan mode:
A/C conversion starts and continues cyclically on all selected channels until 0 is
written in this bit.
1.
2.
Note: When øP = ø
ADCR—A/D Control Register H'FFE9 A/D
HICR—Host Interface Control Register H'FFF0 HIF
Bit
Initial value
Host Read/Write
Slave Read/Write
7
—
1
—
—
6
—
1
—
—
5
—
1
—
—
4
—
1
—
—
3
—
1
—
—
0
FGA20E
0
—
R/W
2
IBFIE2
0
—
R/W
1
IBFIE1
0
—
R/W
Fast Gate A20 Enable
0
1Fast A20 gate function disabled
Fast A20 gate function enabled
Input Buffer Full Interrupt Enable 1
0
1IDR1 input buffer full interrupt disabled
IDR1 input buffer full interrupt enabled
Input Buffer Full Interrupt Enable 2
0
1IDR2 input buffer full interrupt disabled
IDR2 input buffer full interrupt enabled
Trigger Enable
0
1
ADTRG is disabled.
ADTRG is enabled. A/D conversion can be started by external trigger,
or by software.
Bit
Initial value
Read/Write
7
TRGE
0
R/W
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
589
KMIMR—Keyboard Matrix Interrupt Mask Register H'FFF1 HIF
KMPCR—Port 6 Input Pull-Up Control Register H'FFF2 HIF (port 6)
KMIMRA—Keyboard Matrix Interrupt Mask Register A H'FFF3 HIF
Bit
Initial value
Read/Write
7
KMIMR15
1
R/W
6
KMIMR14
1
R/W
5
KMIMR13
1
R/W
4
KMIMR12
1
R/W
3
KMIMR11
1
R/W
0
KMIMR8
1
R/W
2
KMIMR10
1
R/W
1
KMIMR9
1
R/W
Keyboard Matrix Interrupt Mask
0
1Key-sense input interrupt request enabled
Key-sense input interrupt request disabled (initial value)
Bit
Initial value
Read/Write
7
KM7PCR
0
R/W
6
KM6PCR
0
R/W
5
KM5PCR
0
R/W
4
KM4PCR
0
R/W
3
KM3PCR
0
R/W
0
KM0PCR
0
R/W
2
KM2PCR
0
R/W
1
KM1PCR
0
R/W
Port 6 Input Pull-Up Control
0
1Input pull-up transistor is off. (initial value)
Input pull-up transistor is on.
Bit
Initial value
Read/Write
7
KMIMR7
1
R/W
6
KMIMR6
0
R/W
5
KMIMR5
1
R/W
4
KMIMR4
1
R/W
3
KMIMR3
1
R/W
0
KMIMR0
1
R/W
2
KMIMR2
1
R/W
1
KMIMR1
1
R/W
Keyboard Matrix Interrupt Mask
0
1Key-sense input interrupt request enabled
Key-sense input interrupt request disabled (initial value)*
Note: * Initial value of KMIMR6 is 0.
590
IDR1—Input Data Register 1 H'FFF4 HIF
ODR1—Output Data Register 1 H'FFF5 HIF
Bit
Initial value
Host Read/Write
Slave Read/Write
7
ODR7
—
R
R/W
6
ODR6
—
R
R/W
5
ODR5
—
R
R/W
4
ODR4
—
R
R/W
3
ODR3
—
R
R/W
0
ODR0
—
R
R/W
2
ODR2
—
R
R/W
1
ODR1
—
R
R/W
Output data (data output to host processor)
Bit
Initial value
Host Read/Write
Slave Read/Write
7
IDR7
—
W
R
6
IDR6
—
W
R
5
IDR5
—
W
R
4
IDR4
—
W
R
3
IDR3
—
W
R
0
IDR0
—
W
R
2
IDR2
—
W
R
1
IDR1
—
W
R
Input data (command or data input from host processor)
591
STR1—Status Register 1 H'FFF6 HIF
Bit
Initial value
Host Read/Write
Slave Read/Write
7
DBU
0
R
R/W
6
DBU
0
R
R/W
5
DBU
0
R
R/W
4
DBU
0
R
R/W
3
C/D
0
R
R
0
OBF
0
R
R
2
DBU
0
R
R/W
1
IBF
0
R
R
Output Buffer Full
0
1Host has read ODR1
Slave has written to ODR1
Input Buffer Full
0
1Slave has read IDR1
Host has written to IDR1
Defined By User
Command/Data
0
1IDR1 contains data
IDR1 contains a command
Defined By User
592
DADR0—D/A Data Register 0 H'FFF8 D/A
DADR1—D/A Data Register 1 H'FFF9 D/A
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Data to be converted
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Data to be converted
593
DACR—D/A Control Register H'FFFA D/A
Bit
Initial value
Read/Write
7
DAOE1
0
R/W
6
DAOE0
0
R/W
5
DAE
0
R/W
4
1
—
3
1
—
0
1
—
2
1
—
1
1
—
D/A Enable
DAOE1
D/A Output Enable 0
0
1Analog output at DA0 disabled
Analog conversion in channel 0 and output at DA0 enabled
Description
0
1
DAOE0 DAE
Bit 7 Bit 6 Bit 5
Channels 0 and 1 disabled
Channel 0 enabled, channel 1 disabled
Channels 0 and 1 enabled
Channel 0 disabled, channel 1 enabled
Channels 0 and 1 enabled
Channels 0 and 1 enabled
0
1
0
1
—
0
1
0
1
—
D/A Output Enable 1
0
1Analog output at DA1 disabled
Analog conversion in channel 1 and output at DA1 enabled
594
IDR2—Input Data Register 2 H'FFFC HIF
ODR2—Output Data Register 2 H'FFFD HIF
Bit
Initial value
Host Read/Write
Slave Read/Write
7
ODR7
—
R
R/W
6
ODR6
—
R
R/W
5
ODR5
—
R
R/W
4
ODR4
—
R
R/W
3
ODR3
—
R
R/W
0
ODR0
—
R
R/W
2
ODR2
—
R
R/W
1
ODR1
—
R
R/W
Output data (data output to host processor)
Bit
Initial value
Host Read/Write
Slave Read/Write
7
IDR7
—
W
R
6
IDR6
—
W
R
5
IDR5
—
W
R
4
IDR4
—
W
R
3
IDR3
—
W
R
0
IDR0
—
W
R
2
IDR2
—
W
R
1
IDR1
—
W
R
Input data (command or data input from host processor)
595
STR2—Status Register 2 H'FFFE HIF
Bit
Initial value
Host Read/Write
Slave Read/Write
7
DBU
0
R
R/W
6
DBU
0
R
R/W
5
DBU
0
R
R/W
4
DBU
0
R
R/W
3
C/D
0
R
R
0
OBF
0
R
R
2
DBU
0
R
R/W
1
IBF
0
R
R
Output Buffer Full
0
1Host has read ODR2
Slave has written to ODR2
Input Buffer Full
0
1Slave has read IDR2
Host has written to IDR2
Defined By User
Command/Data
0
1IDR2 contains data
IDR2 contains a command
Defined By User
596
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagram
Figure C-1 Port 1 Block Diagram
WP1P:
WP1D:
WP1:
RP1P:
RP1:
n = 0 to 7
Note: * Set priority
Write to P1PCR
Write to P1DDR
Write to port 1
Read P1PCR
Read port 1
Reset
R
QD
C
P1nPCR
WP1P
ResetMode 1
RS
QD
C
P1nDDR
P1n
WP1D
Reset
R
QD
C
P1nDR
WP1
RP1
*
RP1P
Hardware standby
Mode 3
Modes 1 or 2
Internal data bus
Internal address bus (lower)
597
C.2 Port 2 Block Diagram
Figure C-2 Port 2 Block Diagram
WP2P:
WP2D:
WP2:
RP2P:
RP2:
n = 0 to 7
Note: * Set priority
Write to P2PCR
Write to P2DDR
Write to port 2
Read P2PCR
Read port 2
Reset
R
QD
C
P2nPCR
WP2P
ResetMode 1
RS
QD
C
P2nDDR
P2n
WP2D
Reset
R
QD
C
P2nDR
WP2
RP2
*
RP2P
Hardware standby
Mode 3
Modes 1 or 2
Internal data bus
Internal address bus (upper)
598
C.3 Port 3 Block Diagram
Figure C-3 Port 3 Block Diagram
WP3P:
WP3D:
WP3:
RP3P:
RP3:
n = 0 to 7
Write to P3PCR
Write to P3DDR
Write to port 3
Read P3PCR
Read port 3
Reset
R
QD
C
P3nPCR
WP3P
P3n
External address
write
RP3P
Mode 3
Modes 1 or 2
R
QD
C
P3nDDR
WP3D
Reset
RD
C
P3nDR
Reset
WP3
HIE Mode 3
Q
Internal data bus
Host interface data bus
External address
read
RP3
CS
IOW
CS
IOR
599
C.4 Port 4 Block Diagrams
Figure C-4 (a) Port 4 Block Diagram (Pins P40, P42)
WP4D:
WP4:
RP4:
n = 0, 2
Write to P4DDR
Write to port 4
Read port 4
Reset
R
QD
C
P4nDDR
WP4D
Reset
R
QD
C
P4nDR
WP4
P4n
RP4
8-bit timer
Counter clock input
Counter reset input
Internal data bus
600
Figure C-4 (b) Port 4 Block Diagram (Pins P41, P46, P47)
WP4D:
WP4:
RP4:
n = 1, 6, 7
Reset
8-bit timer output
Write to P4DDR
Write to port 4
Read port 4
Output enable
8-bit timer
R
QD
C
P4nDR
WP4
Reset
R
QD
C
P4nDDR
WP4D
P4n
RP4
Internal data bus
PWM timer output
601
Figure C-4 (c) Port 4 Block Diagram (Pins P43, P45)
WP4D:
WP4:
RP4:
n = 3, 5
Note: * Refer to table 14.4.
Write to P4DDR
Write to port 4*
Read port 4
Reset
R
QD
C
P4nDDR
WP4D
Reset
R
QD
C
P4nDR
WP4
P4n
RP4
8-bit timer
Counter clock input
Counter reset input
Internal data bus
Reset RESOBF2,
RESOBF1
(reset HIRQ11
and HIRQ12,
respectively)
HIF
602
Figure C-4 (d) Port 4 Block Diagram (Pin P44)
WP4D:
WP4:
RP4:
Write to P4DDR
Write to port 4*
Read port 4
Output enable
8-bit timer output
8-bit timer
PWM timer
R
QD
C
P44DR
WP4
Reset
R
QD
C
P44DDR
WP4D
P44
RP4
Internal data bus
Reset
HIF
RESOBF1
(reset HIRQ1)
Note: * Refer to table 14.4.
603
C.5 Port 5 Block Diagrams
Figure C-5 (a) Port 5 Block Diagram (Pin P50)
WP5D:
WP5:
RP5:
Reset
Serial transmit
data
Write to P5DDR
Write to port 5
Read port 5
Output enable
SCI
R
QD
C
P50DR
WP5
Reset
R
QD
C
P50DDR
WP5D
P50
RP5
Internal data bus
604
Figure C-5 (b) Port 5 Block Diagram (Pin P51)
WP5D:
WP5:
RP5:
Reset
Serial receive
data
Write to P5DDR
Write to port 5
Read port 5
Input enable
SCI
R
QD
C
P51DR
WP5
Reset
R
QD
C
P51DDR
WP5D
P51
RP5
Internal data bus
605
Figure C-5 (c) Port 5 Block Diagram (Pin P52)
WP5D:
WP5:
RP5:
Reset
Clock output
Write to P5DDR
Write to port 5
Read port 5
Clock output
enable
SCI
R
QD
C
P52DR
WP5
Reset
R
QD
C
P52DDR
WP5D
P52
RP5
Clock input
Clock input
enable
Internal data bus
606
C.6 Port 6 Block Diagrams
Figure C-6 (a) Port 6 Block Diagram (Pins P60, P62, P63, P64, P65)
WP6D:
WP6:
RP6:
RP6P:
WP6P:
n = 0, 2, 3, 4, 5
Write to P6DDR
Write to port 6
Read port 6
Read KMPCR
Write to KMPCR
Reset
R
QD
C
P6nDDR
WP6D
Reset
R
QD
C
P6nDR
WP6
P6n
RP6
Free-running timer
Input capture input
Counter clock input
Internal data bus
Reset
WP6P
RP6P
Hardware standby
R
QD
C
KMnPCR
Key-sense interrupt
input
KMIMRn
607
Figure C-6 (b) Port 6 Block Diagram (Pin P61)
WP6D:
WP6:
RP6:
RP6P:
WP6P:
Reset
Output compare
output
Write to P6DDR
Write to port 6
Read port 6
Read KMPCR
Write to KMPCR
Output enable
Free-running timer
R
QD
C
P61DR
WP6
Reset
R
QD
C
P61DDR
WP6D
P61
RP6
Internal data bus
Key-sense interrupt
input
KMIMR1
Reset
WP6P
RP6P
Hardware standby
R
QD
C
KM1PCR
608
Figure C-6 (c) Port 6 Block Diagram (Pin P66)
Reset
WP6P
RP6P
Hardware standby
R
QD
C
KM6PCR
WP6D:
WP6:
RP6:
RP6P:
WP6P:
Reset
Output compare
output
Write to P6DDR
Write to port 6
Read port 6
Read KMPCR
Write to KMPCR
Output enable
Free-running timer
IRQ enable register
R
QD
C
P66DR
WP6
Reset
R
QD
C
P66DDR
WP6D
P66
RP6
IRQ6 enable
IRQ6 input
Internal data bus
KMIMR6
Other key-sense
interrupt inputs
609
Figure C-6 (d) Port 6 Block Diagram (Pin P67)
Reset
WP6P
RP6P
Hardware standby
R
QD
C
KM7PCR
Reset
R
QD
C
P67DDR
WP6D
Reset
R
QD
C
P67DR
WP6
P67
RP6
WP6D:
WP6:
RP6:
RP6P:
WP6P:
Write to P6DDR
Write to port 6
Read port 6
Read KMPCR
Write to KMPCR
IRQ enable register
IRQ7 enable
IRQ7 input
Internal data bus
KMIMR7
Key-sense interrupt
input
610
C.7 Port 7 Block Diagrams
Figure C-7 (a) Port 7 Block Diagram (Pins P70to P75)
Figure C-7 (b) Port 7 Block Diagram (Pins P76and P77)
P7n
RP7:
n = 6, 7Read port 7
A/D converter
D/A converter
Analog input
Output enable
Internal data bus
RP7
Analog output
P7n
RP7:
n = 0 to 5
Read port 7
A/D converter
Analog input
Internal data bus
RP7
611
C.8 Port 8 Block Diagrams
Figure C-8 (a) Port 8 Block Diagram (Pin P80)
WP8D:
WP8:
RP8:
Write to P8DDR
Write to port 8
Read port 8
Reset
R
QD
C
P80DDR
WP8D
Reset
R
QD
C
P80DR
WP8
P80
RP8
Internal data bus
HIF
HA0
HIE
612
Figure C-8 (b) Port 8 Block Diagram (Pin P81)
WP8D:
WP8:
RP8:
Reset
FGA20
Write to P8DDR
Write to port 8
Read port 8
FGA20E
HIF
R
QD
C
P81DR
WP8
Reset
R
QD
C
P81DDR
WP8D
P81
RP8
Internal data bus
613
Figure C-8 (c) Port 8 Block Diagram (Pins P82, P83)
WP8D:
WP8:
RP8:
n = 2, 3
Reset
Write to P8DDR
Write to port 8
Read port 8
R
QD
C
P8nDR
WP8
Reset
R
QD
C
P8nDDR
WP8D
P8n
RP8
Internal data bus
HIE
HIF
Input (CS1, IOR)
614
Figure C-8 (d) Port 8 Block Diagram (Pin P84)
WP8D:
WP8:
RP8:
Reset
Write to P8DDR
Write to port 8
Read port 8
R
QD
C
P84DR
WP8
Reset
R
QD
C
P84DDR
WP8D
RP8
Internal data bus
IRQ enable register
IRQ3 enable
HIF
IOW
IRQ3 input
HIE STAC
Output enable
Serial transmit data
P84
SCI
615
Figure C-8 (e) Port 8 Block Diagram (Pin P85)
P85
Reset
Internal data bus
WP8D:
WP8:
RP8:
Write to P9DDR
Write to port 8
Read port 8
R
QD
C
P85DDR
WP8D
Reset
R
QD
C
P85DR
WP8
RP8
HIF
HIE
STAC
CS2 input
IRQ4 input
IRQ enable register
IRQ4 enable
SCI
Input enable
Serial receive
data
616
Figure C-8 (f) Port 8 Block Diagram (Pin P86)
Reset
Internal data bus
WP8D:
WP8:
RP8:
Write to P8DDR
Write to port 8
Read port 8
R
QD
C
P86DDR
WP8D
Reset
R
QD
C
P86DR
WP8
RP8
IRQ5 enable
IRQ enable register
IRQ5 input
Note: For a block diagram when the SCL pin function is selected, see section 13,
I2C Bus Interface.
SCI
P86
Clock input enable
Clock output enable
Clock output
Clock input
617
C.9 Port 9 Block Diagrams
Figure C-9 (a) Port 9 Block Diagram (Pin P90)
P90
Reset
Internal data bus
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
R
QD
C
P90DDR
WP9D
Reset
R
QD
C
P90DR
WP9
RP9
IRQ2 input
IRQ2 enable
IRQ enable register
External trigger
input
A/D converter
ECS2 input
HIE
STAC
HIF
618
Figure C-9 (b) Port 9 Block Diagram (Pin P91)
P91
Reset
Internal data bus
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
R
QD
C
P91DDR
WP9D
Reset
R
QD
C
P91DR
WP9
RP9
IRQ1 enable
IRQ enable register
IRQ1 input
HIE
STAC
HIF
EIOW input
619
Figure C-9 (c) Port 9 Block Diagram (Pin P92)
P92
Reset
Internal data bus
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
R
QD
C
P92DDR
WP9D
Reset
R
QD
C
P92DR
WP9
RP9
IRQ0 enable
IRQ enable register
IRQ0 input
620
Figure C-9 (d) Port 9 Block Diagram (Pins P93, P94, P95)
P9n
Reset
Internal data bus
WP9D:
WP9:
RP9:
n = 3, 4, 5
Write to P9DDR
Write to port 9
Read port 9
R
QD
C
P9nDDR
WP9D
Reset
R
QD
C
P9nDR
WP9
RP9
Hardware standby Modes 1 or 2
Mode 3
Modes 1 or 2 RD output
WR output
AS output
621
Figure C-9 (e) Port 9 Block Diagram (Pin P96)
P96
Reset
Internal data bus
WP9D:
WP9:
RP9:
Note: * Set priority
Write to P9DDR
Write to port 9
Read port 9
RS
QD
C
P96DDR
WP9D
RP9
ø
Hardware standby Modes 1 or 2
*
622
Figure C-9 (f) Port 9 Block Diagram (Pin P97)
P97
Modes 1 or 2 Reset
Internal data bus
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
R
QD
C
P97DDR
WP9D
Reset
R
QD
C
P97DR
WP9
RP9
WAIT input
Note: For a block diagram when the SDA pin function is selected, see section 13, I2C Bus Interface.
Wait input enable
623
C.10 Port A Block Diagram
Figure C-10 Port A Block Diagram (Pins PA0to PA7)
WPAD:
WPA:
RPA:
n = 0 to 7
Write to PADDR
Write to port A
Read port A
Reset
R
QD
C
PAnDDR
WPAD
Reset
R
QD
C
PAnODR
WPA
PAn
RPA
Internal data bus
Key-sense interrupt
input
KMIMRn+8
Note: For a block diagram when pins PA7 to PA4 are used as bus buffer input/output pins, see section 13,
I2C Bus Interface.
IICS
624
625
C.11 Port B Block Diagram
Figure C-11 Port B Block Diagram
WPBD:
WPB:
RPB:
n = 0 to 7
Write to PBDDR
Write to port B
Read port B
PBn
R
QD
C
PBnDDR
WPBD
Reset
RD
C
PBnODR
Reset
WPB
HIE Modes 1 or 2
Q
Internal data bus
Host interface data bus
RPB
CS
IOW
CS
IOW
Appendix D Pin States
D.1 Port States in Each Mode
Table D-1 Port States
Hardware Software Sleep Normal
Pin Name Mode Reset Standby Standby Mode Operation
P17to P101 Low 3-state Low Prev. state A7to A0
A7to A02 3-state Low if (Addr. Addr. output
DDR = 1, output pins: or input port
prev. state last address
if DDR = 0 accessed)
3 Prev. state I/O port
P27to P201 Low 3-state Low Prev. state A15 to A8
A15 to A82 3-state Low if (Addr. Addr. output
DDR = 1, output pins: or input port
prev. state last address
if DDR = 0 accessed)
3 Prev. state I/O port
P37to P301 3-state 3-state 3-state 3-state D7to D0
D7to D02
3 Prev. state Prev. state I/O port
P47to P401 3-state 3-state Prev. state*Prev. state I/O port
2
3
P52to P501 3-state 3-state Prev. state*Prev. state I/O port
2
3
Notes: 1. 3-state: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS
pull-up on if DDR = 0, PCR = 1). Output ports hold their previous output level.
3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may also
be used by the on-chip supporting modules.
See section 7, I/O Ports, for further information.
*On-chip supporting modules are initialized, so these pins revert to I/O ports according to
the DDR and DR bits.
626
627
Table D-1 Port States (cont)
Hardware Software Sleep Normal
Pin Name Mode Reset Standby Standby Mode Operation
P67to P601 3-state 3-state Prev. state*Prev. state I/O port
2
3
P77to P701 3-state 3-state 3-state 3-state Input port
2
3
P86to P801 3-state 3-state Prev. state*Prev. state I/O port
2
3
P97/WAIT 1 3-state 3-state 3-state/ 3-state/ WAIT/
2Prev. state*Prev. state I/O port
3 Prev. state*Prev. state I/O port
P96/ø 1 Clock 3-state High Clock Clock
2output output output
3 3-state High if Clock output Clock output
DDR = 1, if DDR = 1, if DDR = 1,
3-state if 3-state if input port if
DDR = 0 DDR = 0 DDR = 0
P95to P93, 1 High 3-state High High AS, WR, RD
AS, WR, RD 2
3 3-state Prev. state Prev. state I/O port
P92to P901 3-state 3-state Prev. state Prev. state I/O port
2
3
Notes: 1. 3-state: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS
pull-up on if DDR = 0, PCR = 1). Output ports hold their previous output level.
3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may also
be used by the on-chip supporting modules.
See section 7, I/O Ports, for further information.
*On-chip supporting modules are initialized, so these pins revert to I/O ports according to
the DDR and DR bits.
Table D-1 Port States (cont)
Hardware Software Sleep Normal
Pin Name Mode Reset Standby Standby Mode Operation
PA7to PA01 3-state 3-state Prev. state*Prev. state I/O port
2
3
PB7to PB01 3-state 3-state Prev. state*Prev. state I/O port
2
3
Notes: 1. 3-state: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS
pull-up on if DDR = 0, PCR = 1). Output ports hold their previous output level.
3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may also
be used by the on-chip supporting modules.
See section 7, I/O Ports, for further information.
*On-chip supporting modules are initialized, so these pins revert to I/O ports according to
the DDR and DR bits.
628
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents when the RAME bit in SYSCR is set to 1, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown below. RES must remain low
until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
(2) When the RAME bit in SYSCR is cleared to 0 or when it is not necessary to retain RAM
contents, RES does not have to be driven low as in (1).
Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
RES
t ≥ 100 ns tOSC
STBY
RES
t1 ≥ 10 tcyc t2 ≥ 0 ns
629
630
Appendix F Option Lists
HD6433437, HD6433436, HD6433434 Option List
Please check off the appropriate applications and
enter the necessary information.
1 ROM Size
■■HD6433434: 32-kbyte
■■HD6433436: 48-kbyte
■■HD6433437: 60-kbyte
2 System Oscillator
■■Ceramic oscillator f = MHz
■■External clock f = MHz
3 Power Supply Voltage/Maximum Operating Frequency
■■VCC = 4.5 V to 5.5 V (16 MHz max.)
■■VCC = 4.0 V to 5.5 V (12 MHz max.)
■■VCC = 2.7 V to 5.5 V (10 MHz max.)
Notes: 1. Please select the power supply voltage/operating frequency version according to the
power supply voltage used.
Example: For use at VCC = 4.5 V to 5.5 V/f = 10 MHz,
select VCC = 4.5 V to 5.5 V (16 MHz max.).
2. The power supply voltage and maximum operating frequency of the selected version
should also be entered on the Single-Chip Microcomputer Ordering Specifications Sheet.
Continued on the following page.
Date of order
Customer
Department
Name
ROM code name
LSI number
(Hitachi entry)
Continued from the preceding page.
631
4I
2
C Bus Option
■■I2C bus used
■■I2C bus not used
Notes: 1. The “I2C bus used” option includes all cases where data transfer is performed via the SCL
and SDA pins using the on-chip I2C bus interface function (hardware module). If the I2C
bus interface function (hardware module) is used, various bus interfaces with different bus
specifications and names are also included in “I2C bus used”. The case in which only the
bus drive function of pins PA7 to PA4 in port A is used is not included.
2. When “I2C bus not used” is selected, values cannot be set in registers relating to the I2C
bus interface (ICCR, ICSR, ICDR, ICMR). These register always read H'FF. With
emulators, and ZTAT and F-ZTAT versions, the “I2C bus used” option is selected. If the
“I2C bus not used” option is selected, it is essential to ensure that I2C bus interface related
registers are not accessed.
For the Microcomputer Family item in 1. Basic Specifications in the Single-Chip
Microcomputer Ordering Specifications Sheet*, please specify the appropriate item from the
table below according to the combination of items 1 and 4 above. If the “I2C bus used” option
is selected, please also specify this in Special Specifications (Product Specifications, Mark
Specifications, etc.) in 1. Basic Specifications.
*Please contact the relevant sales department for information on the Single-Chip
Microcomputer Ordering Specifications Sheet.
I2C
ROM Size I2C bus used I2C bus not used
32-kbyte HD6433434W HD6433434
48-kbyte HD6433436W HD6433436
60-kbyte HD6433437W HD6433437
ROM code name
LSI number
(Hitachi entry)
Appendix G Product Code Lineup
Table G-1 H8/3437 Series Product Code Lineup Package
Product Type Product Code Mark Code (Hitachi Package Code)
H8/3437 Flash F-ZTAT HD64F3437F16 HD64F3437F16 100-pin QFP (FP-100B)
memory version HD64F3437TF16 HD64F3437TF16 100-pin TQFP (TFP-100B)
version
PROM ZTAT HD6473437F16 HD6473437F16 100-pin QFP (FP-100B)
version version HD6473437TF16 HD6473437TF16 100-pin TQFP (TFP-100B)
Mask With I2C HD6433437WF HD6433437W(***)F 100-pin QFP (FP-100B)
ROM interface HD6433437WTF HD6433437W(***)TF 100-pin TQFP (TFP-100B)
version Without I2C HD6433437F HD6433437(***)F 100-pin QFP (FP-100B)
interface HD6433437TF HD6433437(***)TF 100-pin TQFP (TFP-100B)
H8/3436 Mask With I2C HD6433436WF HD6433436W(***)F 100-pin QFP (FP-100B)
ROM interface HD6433436WTF HD6433436W(***)TF 100-pin TQFP (TFP-100B)
version Without I2C HD6433436F HD6433436(***)F 100-pin QFP (FP-100B)
interface HD6433436TF HD6433436(***)TF 100-pin TQFP (TFP-100B)
H8/3434 Flash F-ZTAT HD64F3434F16 HD64F3434F16 100-pin QFP (FP-100B)
memory version HD64F3434TF16 HD64F3434TF16 100-pin TQFP (TFP-100B)
version
PROM ZTAT HD6473434F16 HD6473434F16 100-pin QFP (FP-100B)
version version HD6473434TF16 HD6473434TF16 100-pin TQFP (TFP-100B)
Mask With I2C HD6433434WF HD6433434W(***)F 100-pin QFP (FP-100B)
ROM interface HD6433434WTF HD6433434W(***)TF 100-pin TQFP (TFP-100B)
version Without I2C HD6433434F HD6433434(***)F 100-pin QFP (FP-100B)
interface HD6433434TF HD6433434(***)TF 100-pin TQFP (TFP-100B)
Note: (***) in mask ROM versions is the ROM code.
The I2C interface is an option. Please note the following points when using this optional function.
(1) Notify your Hitachi sales representative that you will be using an optional function.
(2) With mask ROM versions, optional functions can be used if the product code includes the letter
W (e.g. HD6433437WF, HD6433434WTF).
(3) The product code is the same for ZTAT versions, but please be sure to notify Hitachi if you are
going to use this optional function.
632
Appendix H Package Dimensions
Figure H-1 shows the dimensions of the FP-100B package. Figure H-2 shows the dimensions of the
TFP-100B package.
Unit: mm
Figure H-1 Package Dimensions (FP-100B)
0.10
16.0 ± 0.3
1.0
0.5 ± 0.2
16.0 ± 0.3
3.05 Max
75 51
50
26
125
76
100
14
0 – 8°
0.5
0.08 M
0.22 ± 0.05
2.70
0.17 ± 0.05
0.12+0.13
–0.12
1.0
0.20 ± 0.04
0.15 ± 0.04
633
Unit: mm
Figure H-2 Package Dimensions (TFP-100B)
16.0 ± 0.2
14
0.08
0.10 0.5 ± 0.1
16.0 ± 0.2
0.5
0.10 ± 0.10
1.20 Max
0.17 ± 0.05
0 – 8°
75 51
125
76
100 26
50
M
0.22 ± 0.05
1.0
1.00
1.00
0.20 ± 0.04
0.15 ± 0.04
634
H8/3437 Series, H8/3434 F-ZTAT™ H8/3437 F-ZTAT™
Hardware Manual
Publication Date: 1st Edition, September 1994
4th Edition, December 1996
Published by: Semiconductor and IC Div.
Hitachi, Ltd.
Edited by: Technical Documentation Center
Hitachi Microcomputer System Ltd.
Copyright © Hitachi, Ltd., 1994. All rights reserved. Printed in Japan.
