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FEATURES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVCC
AGND
CLKIN
SEL
OE
GND
1Y1
VCC
GND
1Y2
VCC
GND
1Y3
VCC
AVCC
AGND
FBIN
TEST
CLR
VCC
2Y1
GND
VCC
2Y2
GND
VCC
2Y3
GND
DB PACKAGE
(TOP VIEW)
DESCRIPTION
CDC2536
SCAS377E – APRIL 1994 – REVISED JULY 2004
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
•Low Output Skew for Clock-Distribution andClock-Generation Applications•Operates at 3.3-V V
CC•Distributes One Clock Input to Six Outputs•One Select Input Configures Three Outputs toOperate at One-Half or Double the InputFrequency
•No External RC Network Required•On-Chip Series Damping Resistors•External Feedback Pin (FBIN) Is Used toSynchronize the Outputs to the Clock Input•Application for Synchronous DRAM,High-Speed Microprocessor•TTL-Compatible Inputs and Outputs•Outputs Drive 50-ΩParallel-TerminatedTransmission Lines•State-of-the-Art EPIC-IIB™ BiCMOS DesignSignificantly Reduces Power Dissipation•Distributed V
CC
and Ground Pins ReduceSwitching Noise•Packaged in Plastic 28-Pin ShrinkSmall-Outline Package
The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) toprecisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It isspecifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536operates at 3.3-V V
CC
and is designed to drive a 50-W transmission line. The CDC2536 also provides on-chipseries-damping resistors, eliminating the need for external termination components.
The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization betweenCLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) inputconfigures three Y outputs to operate at one-half or double the CLKIN frequency, depending on which pin is fedback to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the dutycycle at the input clock.
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypassthe PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC2536 does not require external RC networks. The loop filter forthe PLL is included on-chip, minimizing component count, board space, and cost.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.EPIC-IIBis a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DETAILED DESCRIPTION OF OUTPUT CONFIGURATIONS
Output Configuration A
Output Configuration B
CDC2536
SCAS377E – APRIL 1994 – REVISED JULY 2004
Because it is based on PLL circuitry, the CDC2536 requires a stabilization time to achieve phase lock of thefeedback signal to the reference signal. This stabilization time is required following power up and application of afixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or feedbacksignals. Such changes occur upon change of SEL, enabling the PLL via TEST, and upon enable of all outputsvia OE.
The CDC2536 is characterized for operation from 0°C to 70°C.
The voltage-controlled oscillator (VCO) used in the CDC2536 has a frequency range of 100 MHz to 200 MHz,twice the operating frequency of the CDC2536 outputs. The output of the VCO is divided by two and by four toprovide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. SELdetermines which of the two signals is buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that thefrequency of the output matches that of CLKIN. In the case that a VCO/2 output is wired to FBIN, the VCO mustoperate at twice the CLKIN frequency resulting in device outputs that operate at either the same or one-half theCLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at the same or twice the CLKINfrequency.
Output configuration A is valid when any output configured as a 1×frequency output in Table 1 is fed back toFBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputsconfigured as 1/2×outputs operate at half the CLKIN frequency, while outputs configured as 1×outputs operateat the same frequency as CLKIN.
Table 1. Output Configuration A
INPUT OUTPUTS
1/2×1×SEL
FREQUENCY FREQUENCY
L None AllH 1Yn 2Yn
Output configuration B is valid when any output configured as a 1×frequency output in Table 2 is fed back toFBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputsconfigured as 1×outputs operate at the CLKIN frequency, while outputs configured as 2×outputs operate atdouble the frequency of CLKIN.
Table 2. Output Configuration B
INPUT OUTPUTS
1×2×SEL
FREQUENCY FREQUENCY
H 1Yn 2YnL All None
2
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FUNCTIONAL BLOCK DIAGRAM






2Y3
2Y2
2Y1
1Y3
1Y2
1Y1






Phase-Lock Loop
CLR
CLKIN
TEST
SEL
FBIN
OE
2
2
5
24
26
3
25
4
7
10
13
22
19
16
CDC2536
SCAS377E – APRIL 1994 – REVISED JULY 2004
3
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ABSOLUTE MAXIMUM RATINGS
CDC2536
SCAS377E – APRIL 1994 – REVISED JULY 2004
FUNCTIONAL BLOCK DIAGRAM (continued)
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
Clock input. CLKIN provides the clock signal to be distributed by the CDC2536 clock-driver circuit. CLKINprovides the reference signal to the integrated PLL that generates the clock output signals. CLKIN mustCLKIN 3 I have a fixed frequency and fixed phase for the phase-lock loop to obtain phase lock. Once the circuit ispowered up and a valid CLKIN signal is applied, a stabilization time is required for the PLL to phase lockthe feedback signal to its reference signal.CLR 24 I CLR is used for testing purposes only. Connect CLR to GND for normal operation.Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one ofFBIN 26 I the six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks toobtain zero phase delay between the FBIN and differential CLKIN inputs.Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OEis high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directlyOE 5 I from an output, placing the outputs in the high-impedance state interrupts the feedback loop; therefore,when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is requiredbefore the PLL obtains phase lock.Output configuration select. SEL selects the output configuration for each output bank (e.g. 1×, 1/2×, orSEL 4 I
2×).(see Tables 1 and 2).TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputsTEST 25 I operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypassesthe PLL circuitry. TEST should be grounded for normal operation.These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. Therelationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle1Y1-1Y3 7, 10, 13 O of the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal. Each outputhas an internal series resistor to dampen transmission-line effects and improve the signal integrity at theload.
These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequencyand the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty2Y1-2Y3 22, 19, 16 O cycle of the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal. Eachoutput has an internal series resistor to dampen transmission-line effects and improve the signal integrity atthe load.
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage range, V
CC
-0.5 V to 4.6 VInput voltage range, V
I
(see
(2)
) -0.5 V to 7 VVoltage range applied to any output in the high state or power-off state, V
O
(see
(2)
) -0.5 V to 5.5 VCurrent into any output in the low state, I
O
24 mAInput clamp current, I
IK
(V
I
< 0) -20 mAOutput clamp current, I
OK
(V
O
< 0) -50 mAMaximum power dissipation at T
A
= 55°C (in still air) (see
(3)
) 0.68 WStorage temperature range, T
stg
-65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3) The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils. Formore information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology DataBook, literature number SCBD002B.
4
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RECOMMENDED OPERATING CONDITIONS (SEE
(1)
)
ELECTRICAL CHARACTERISTICS
TIMING REQUIREMENTS
CDC2536
SCAS377E – APRIL 1994 – REVISED JULY 2004
MIN MAX UNIT
V
CC
Supply voltage 3 3.6 VV
IH
High-level input voltage 2 VV
IL
Low-level input voltage 0.8 VV
I
Input voltage 0 5.5 VI
OH
High-level output current 12 mAI
OL
Low-level output current 12 mAT
A
Operating free-air temperature 0 70 °C
(1) Unused inputs must be held high or low to prevent them from floating.
over recommended operating free-air temperature range, T
A
= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
IK
V
CC
= 3 V, I
I
= -18 mA 1.2 VV
CC
-V
CC
= MIN to MAX
(1)
, I
OH
= -100 µA
0.2V
OH
VV
CC
= 3 V, I
OH
= -12 mA 2V
CC
= 3 V, I
OL
= 100 µA 0.2V
OL
VV
CC
= 3 V, I
OL
= 12 mA 0.8V
CC
= 0 or MAX
(1)
, V
I
= 3.6 V ±10I
I
µAV
CC
= 3.6 V, V
I
= V
CC
or GND ±1I
OZH
V
CC
= 3.6 V, V
O
= 3 V 10 µAI
OZL
V
CC
= 3.6 V, V
O
= 0 10 µAOutputs high 2I
CC
V
CC
= 3.6 V, I
O
= 0, V
I
= V
CC
or GND Outputs low 2 mAOutputs disabled 2C
i
V
I
= V
CC
or GND 6 pFC
o
V
O
= V
CC
or GND 9 pF
(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
over recommended ranges of supply voltage and operating free-air temperature
MIN MAX UNIT
When VCO is operating at four times the CLKIN frequency 25 50f
clock
Clock frequency MHzWhen VCO is operating at double the CLKIN frequency 50 100Duty cycle, CLKIN 40% 60%After SEL 50After OE↓50Stabilization time
(1)
µsAfter power up 50After CLKIN 50
(1) Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to beobtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications forpropagation delay and skew parameters given in the switching characteristics table are not applicable.
5
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SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
CDC2536
SCAS377E – APRIL 1994 – REVISED JULY 2004
over recommended ranges of supply voltage and operating free-air temperature, C
L
= 15 pF (see
(1)
and Figure 1 , Figure 2and Figure 3 )
FROM TOPARAMETER MIN MAX UNIT(INPUT) (OUTPUT)
f
max
100 MHzDuty cycle Y 45% 55%t
phase error
(2)
CLKIN↑Y↑500 +500 pst
jitter (RMS)
CLKIN↑Y↑200 pst
sk(o)
(2)
0.5 nst
sk(pr)
(2)
1 nst
r
1.4 nst
f
1.4 ns
(1) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.(2) The propagation delay, t
phase error
, is dependent on the feedback path from any output to FBIN. The t
phase error
, t
sk(o)
, and t
sk(pr)specfications are only valid for equal loading of all outputs.
A. NOTES: . C
L
includes probe and jig capacitance.B. All input pulses are supplied by generators having the following characteristics: PRR≤100 MHz, Z
O
= 50 Ω, t
r
≤2.5 ns,t
f
≤2.5 ns.C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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tphase error 1
CLKIN
Outputs
Operating
at 1/2 CLKIN
Frequency
Outputs
Operating
at CLKIN
Frequency
tphase error 2
tphase error 3
tphase error 4
tphase error 5
tphase error 6
tphase error 7
tphase error 8
tphase error 9
CDC2536
SCAS377E – APRIL 1994 – REVISED JULY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
A. NOTES: . Output skew, t
sk(o)
, is calculated as the greater of:•The difference between the fastest and slowest of t
phase error n
(n = 1, 2, . . . 6)•The difference between the fastest and slowest of t
phase error n
(n = 7, 8, 9)B. Process skew, t
sk(pr)
, is calculated as the greater of:•The difference between the maximum and minimum t
phase error n
(n = 1, 2, . . . 6) across multiple devices underidentical operating conditions•The difference between the maximum and minimum t
phase error n
(n = 7, 8, 9) across multiple devices underidentical operating conditions
Figure 2. Waveforms for Calculations of t
sk(o)
and t
sk(pr)
7
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tphase error 10
tphase error 11
tphase error 12
tphase error 15
CLKIN
Outputs
Operating
at CLKIN
Frequency
Outputs
Operating
at 2X CLKIN
Frequency
tphase error 13
tphase error 14
CDC2536
SCAS377E – APRIL 1994 – REVISED JULY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
A. NOTES: . Output skew, t
sk(o)
, is calculated as the greater of:•The difference between the fastest and slowest of t
phase error n
(n = 10, 11, . . . 15)B. Process skew, t
sk(pr)
, is calculated as the greater of:•The difference between the maximum and minimum t
phase error n
(n = 10, 11, . . . 15) across multiple devicesunder identical operating conditions.
Figure 3. Waveforms for Calculation of t
sk(o)
and t
sk(pr)
8
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CDC2536DB ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDC2536DBG4 ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDC2536DBR ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDC2536DBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDC2536DL OBSOLETE SSOP DL 28 TBD Call TI Call TI
CDC2536DLR OBSOLETE SSOP DL 28 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Nov-2005
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CDC2536DBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDC2536DBR SSOP DB 28 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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