Vishay Siliconix
Si7115DN
Document Number: 73864
S11-1908-Rev. C, 26-Sep-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P-Channel 150 V (D-S) MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• Low Thermal Resistance PowerPAK®
Package with Small Size and Low 1 mm
Profile
•100 % R
g and UIS Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Active Clamp in Intermediate DC/DC Power Supplies
• H-Bridge High Side Switch for Lighting Application
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. See solder profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Based on TC = 25 °C.
PRODUCT SUMMARY
VDS (V) RDS(on) ()I
D (A) Qg (Typ.)
- 150
0.295 at VGS = - 10 V - 8.9e
23.2 nC
0.315 at VGS = - 6 V - 8.6e
Ordering Information:
Si7115DN-T1-E3 (Lead (Pb)-free)
Si7115DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
1
2
3
4
5
6
7
8
S
S
S
G
D
D
D
D
3.30 mm 3.30 mm
PowerPAK 1212-8
Bottom View
S
G
D
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter Symbol Limit Unit
Drain-Source Voltage VDS - 150 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
ID
- 8.9
A
TC = 70 °C - 7.1
TA = 25 °C - 2.3a, b
TA = 70 °C - 1.9a, b
Pulsed Drain Current IDM - 15
Continuous Source-Drain Diode Current TC = 25 °C IS
- 13
TA = 25 °C - 3a, b
Avalanche Current
L = 0.1 mH IAS 15
Single-Pulse Avalanche Energy EAS 11.25 mJ
Maximum Power Dissipation
TC = 25 °C
PD
52
W
TC = 70 °C 33
TA = 25 °C 3.7a, b
TA = 70 °C 2.4a, b
Operating Junction and Storage Temperature Range TJ, Tstg - 50 to 150 °C
Soldering Recommendations (Peak Temperature)c, d 260
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Document Number: 73864
S11-1908-Rev. C, 26-Sep-11
Vishay Siliconix
Si7115DN
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. Maximum under steady state conditions is 81 °C/W.
Notes:
a. Pulse test; pulse width 300 µs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolut e Maximum Ratings” may cause permanent damage to t he device. These are stress rating s only, and functional opera tion
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambienta, b t 10 s RthJA 26 33 °C/W
Maximum Junction-to-Case (Drain) Steady State RthJC 1.9 2.4
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 150 V
VDS Temperature Coefficient VDS/TJID = - 250 µA - 165 mV/°C
VGS(th) Temperature Coefficient VGS(th)/TJ- 6.6
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 2 - 4 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 150 V, VGS = 0 V - 1 µA
VDS = - 150 V, VGS = 0 V, TJ = 55 °C - 10
On-State Drain CurrentaID(on) VDS - 5 V, VGS = - 10 V - 8 A
Drain-Source On-State ResistanceaRDS(on)
VGS = - 10 V, ID = - 4 A 0.245 0.295
VGS = - 6 V, ID = - 3 A 0.260 0.315
Forward Transconductanceagfs VDS = - 15 V, ID = 4 A 12 S
Dynamicb
Input Capacitance Ciss
VDS = - 50 V, VGS = 0 V, f = 1 MHz
1190
pFOutput Capacitance Coss 61
Reverse Transfer Capacitance Crss 42
Total Gate Charge Qg VDS = - 75 V, VGS = - 10 V, ID = - 3 A 27.5 42
nC
VDS = - 75 V, VGS = - 6 V, ID = - 3 A
23.2 35
Gate-Source Charge Qgs 5.4
Gate-Drain Charge Qgd 8.4
Gate Resistance Rgf = 1 MHz 1.3 6.1 9.2
Tur n - O n D e l ay Time td(on)
VDD = - 75 V, RL = 25
ID - 3 A, VGEN = - 6 V, Rg = 1
20 30
ns
Rise Time tr95 145
Turn-Off DelayTime td(off) 38 60
Fall Time tf34 51
Tur n - O n D e l ay T im e td(on)
VDD = - 75 V, RL = 25
ID - 3 A, VGEN = - 10 V, Rg = 1
11 18
Rise Time tr28 42
Turn-Off DelayTime td(off) 52 78
Fall Time tf35 53
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISTC = 25 °C - 13 A
Pulse Diode Forward CurrentaISM - 15
Body Diode Voltage VSD IS = - 3 A - 0.8 - 1.2 V
Body Diode Reverse Recovery Time trr
IF = - 4 A, dI/dt = 100 A/µs, TJ = 25 °C
65 90 ns
Body Diode Reverse Recovery Charge Qrr 180 270 nC
Reverse Recovery Fall Time ta45 ns
Reverse Recovery Rise Time tb20
Document Number: 73864
S11-1908-Rev. C, 26-Sep-11
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3
Vishay Siliconix
Si7115DN
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
0
4
8
12
16
20
0246810
V
GS
= 10 thru 6 V
4 V
V
DS
- Drain-to-Source Voltage (V)
)A( tnerruC niarD -I
D
5 V
0.1
0.2
0.3
0.4
0.5
0.6
04812 16 20
V
GS
= 10 V
ID - Drain Current (A)
V
GS
= 6 V
R)no(SD (Ω) ecnatsis
e
R-nO
-
0
2
4
6
8
10
0 6 12 1824 30
I
D
= 3 A
)V( e
g
atl
o
V ecruoS-ot-etaG
-
Qg - Total Gate Charge (nC)
VSG
V
DS
= 100 V
V
DS
= 250 V
V
DS
= 75 V
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0.0
0.4
0.8
1.2
1.6
2
.
0
0123456
25 °C
T
C
= 125 °C
- 55 °C
VGS - Gate-to-Source Voltage (V)
)A( tnerruC niarD -I D
C
rss
0
340
680
1020
1360
1700
020406080 100
C
oss
C
iss
VDS - Drain-to-Source Voltage (V)
)Fp( ecnati
c
a
pa
C
-
C
0.4
0.7
1.0
1.3
1.6
1.9
2
.
2
- 50 - 25 0 25 50 75 100 125 150
V
GS
= 10 V
TJ- Junction Temperature (°C)
R)
n
o
(
SD ecnats
is
e
R
-
n
O
- )dezilam
r
oN(
V
GS
= 6 V
I
D
= 4 A
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Document Number: 73864
S11-1908-Rev. C, 26-Sep-11
Vishay Siliconix
Si7115DN
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
Threshold Voltage
0.1
10
100
VSD
)A( tnerruC ecruoS -IS
1.2 1.5 0.00 0.3 0.6 0.9
- Source-to-Drain Voltage (V)
25 °C
TJ = 150 °C
1
- 0.5
- 0.2
0.1
0.4
0.7
1.0
- 50 - 25 0 25 50 75 100 125 150
TJ - Temperature (°C)
V)ht(
S
G)
V(
I
D
= 250 µA
I
D
= 5 mA
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
0.0
0.4
0.8
1.2
1.6
2
.
0
012345678910
V
GS
- Gate-to-Source Voltage (V)
R
)no(SD
(Ω) ecnatsiseR-nO ecruoS-ot-niarD -
25 °C
125 °C
0
30
50
10
20
)W
(
rewo
P
Time (s)
40
10 1 0.1 100 0.01
Safe Operating Area, Junction-to-Ambient
1 m
s
s
10 m
10 m
s
s
100 m
100 m
s
s
dc
dc
1
1
s
s
10
10
s
s
100
100
1
1
0.0
0.01 1 10
100
100
0.01
0.01
10
10
)
)
A
A
(
(
t
t
n
n
e
e
r
r
r
r
u
u
C
C
n
n
i
i
a
a
r
r
D
D
–
–
I
I
D
D
0.1
0.1
0.1
0.1
V
V
D
S
S
– Drain-to-Source
– Drain-to-Source V
oltage (V
oltage (V
)
)
*V
*V
G
S
S
minimum
minimum
V
V
G
S
S
at which
at which
r
r
DS(on
DS(on
)
)
is
is
specified
specified
T
T
A
A
= 25 °C
= 25 °C
Sin
Sing
le
le Puls
e
e
*Limited by
*Limited by
r
r
DS(on
DS(on
)
)
100
1
110100
0.01
10
)
A( t
ne
rru
C
n
i
ar
D
-
I
D
0.1
V
DS
- Drain-to-Source Voltage (V)
* V
GS
minimum V
GS
at which R
DS(on)
is specified
0.1 1000
T
A
= 25 °C
Single Pulse
Limited by R
DS(on)
1 ms
10 ms
100 ms
1 s
10 s
DC
*
Si7115DN
Document Number: 73864
S11-1908-Rev. C, 26-Sep-11
www.vishay.com
5
Vishay Siliconix
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases
where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.
Current Derating*
0
2
4
6
8
10
0 255075100125150
ID)A( tnerruC niarD -
TC - Case Temperature (°C)
Power, Junction-to-Case
0
13
26
39
52
6
5
0 25 50 75 100 125 150
TC - Case Temperature (°C)
)
W
(
r
e
w
o
P
Power, Junction-to-Ambient
0.0
0.4
0.8
1.2
1.6
2.0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power (W)
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6
Document Number: 73864
S11-1908-Rev. C, 26-Sep-11
Vishay Siliconix
Si7115DN
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73864.
Normalized Thermal Transient Impedance, Junction-to-Ambient
10
-3
10
-2
10
-1
100
Square Wave Pulse Duration (s)
10 1000
1
0.1
0.01
tneisnarT evitceffE dezilamroN
ecnadepmI lamrehT
1
10
-4
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 65 °C
3. T
JM
– T = P
DM
Z
thJA
(t)
t
1
t
2
4. Surface Mounted
Notes:
t
1 t
2
P
DM
Normalized Thermal Transient Impedance, Junction-to-Foot
10
-3
10
-2
10
-1
10 1
-4
1
0.1
0.01
Square Wave Pulse Duration (s)
tneisnar
T
ev
i
t
cef
fE
d
e
zi
l
am
r
oN
ecnadepmI
l
amrehT
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Package Information
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Revison: 09-Jan-17 1Document Number: 71656
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PowerPAK® 1212-8, (Single / Dual)
DIM. MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044
A1 0.00 - 0.05 0.000 - 0.002
b 0.23 0.30 0.41 0.009 0.012 0.016
c 0.23 0.28 0.33 0.009 0.011 0.013
D 3.20 3.30 3.40 0.126 0.130 0.134
D1 2.95 3.05 3.15 0.116 0.120 0.124
D2 1.98 2.11 2.24 0.078 0.083 0.088
D3 0.48 - 0.89 0.019 - 0.035
D4 0.47 typ. 0.0185 typ
D5 2.3 typ. 0.090 typ
E 3.20 3.30 3.40 0.126 0.130 0.134
E1 2.95 3.05 3.15 0.116 0.120 0.124
E2 1.47 1.60 1.73 0.058 0.063 0.068
E3 1.75 1.85 1.98 0.069 0.073 0.078
E4 0.034 typ. 0.013 typ.
e 0.65 BSC 0.026 BSC
K 0.86 typ. 0.034 typ.
K1 0.35 - - 0.014 - -
H 0.30 0.41 0.51 0.012 0.016 0.020
L 0.30 0.43 0.56 0.012 0.017 0.022
L1 0.06 0.13 0.20 0.002 0.005 0.008
0° - 12° 0° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M 0.125 typ. 0.005 typ.
ECN: S16-2667-Rev. M, 09-Jan-17
DWG: 5882
Notes
1. Inch will govern
2 Dimensions exclusive of mold gate burrs
3. Dimensions exclusive of mold ash and cutting burrs
Backside view of single pad
Backside view of dual pad
Detail Z D1
D2
D1
E1
c
A
54
18
D2
4
3
H
2
1
θ
θ
e
b
θ
θ
E2 L
b
D3(2x)
4
3
2
1
A1
Z
K
K1
W
M
D4
E3
E4
D5
KH
E4
E2 L
D2 D4
E3
D5
L1
2
2
D
E
H
Vishay Siliconix
AN822
Document Number 71681
03-Mar-06
www.vishay.com
1
PowerPAK® 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi-
ous that degradation of a high performance die by the
package is undesirable.
PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a deriva-
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
The PowerPAK 1212-8 has a footprint area compara-
ble to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger pack-
ages are typically required solely for thermal consider-
ation, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 single in the index of this
document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.
Figure 1. PowerPAK 1212 Devices
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2
Document Number 71681
03-Mar-06
Vishay Siliconix
AN822
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
Ramp-Up Rate + 6 °C /Second Maximum
Temperature at 155 ± 15 °C 120 Seconds Maximum
Temperature Above 180 °C 70 - 180 Seconds
Maximum Temperature 240 + 5/- 0 °C
Time at Maximum Temperature
20 - 40 Seconds
Ramp-Down Rate
+ 6 °C/Second Maximum
Figure 2. Solder Reflow Temperature Profile
Figure 3. Solder Reflow Temperatures and Time Durations
210 - 220 °C
3 °C/s (max) 4 ° C/s (max)
10 s (max)
183 °C
50 s (max)
Reflow Zone
60 s (min)
Pre-Heating Zone
3° C/s (max)
140 - 170 °C
Maximum peak temperature at 240 °C is allowed.
Vishay Siliconix
AN822
Document Number 71681
03-Mar-06
www.vishay.com
3
THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the tempera-
ture of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4)
.
Suppose each device is dissipating 2 W. Using the junc-
tion-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the Pow-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Spreading Copper
Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
nal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many appli-
cations. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No signif-
icant effect was observed.
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package SO-8 TSSOP-8 TSOP-8 PPAK 1212 PPAK SO-8
Configuration Single Dual Single Dual Single Dual Single Dual Single Dual
Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90 2.4 5.5 1.8 5.5
Figure 4. Temperature of Devices on a PC Board
2.4 °C/W
49.8 °C
PowerPAK 1212
20 °C/W
85 °C
Standard SO-8
PC Board at 45 °C
52 °C/W
149 °C
Standard TSSOP-8
40 °C/W
125 °C
TSOP-6
www.vishay.com
4
Document Number 71681
03-Mar-06
Vishay Siliconix
AN822
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal perfor-
mance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attrac-
tive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOS-
FET die in the standard TSSOP-8 or SO-8 packages.
Figure 5. Spreading Copper - Si7401DN
45
55
65
75
85
95
105
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
R
AJht
(°C/W)
Spreading Copper (sq. in.)
100 %
50 %
0 %
Figure 6. Spreading Copper - Junction-to-Ambient Performance
R
AJ
(°C/W)
ht
50
60
70
80
90
100
110
120
130
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Spreading Copper (sq. in.)
100 %
0 %
50 %
Application Note 826
Vishay Siliconix
Document Number: 72597 www.vishay.com
Revision: 21-Jan-08 7
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single
0.088
(2.235)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.152
(3.860)
0.094
(2.390)
0.039
(0.990)
0.068
(1.725)
0.010
(0.255)
0.016
(0.405)
0.026
(0.660)
0.025
(0.635)
0.030
(0.760)
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Revision: 08-Feb-17 1Document Number: 91000
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