RFP12N10L Data Sheet April 2005 12A, 100V, 0.200 Ohm, Logic Level, N-Channel Power MOSFET Features * 12A, 100V These are N-Channel enhancement mode silicon gate power field effect transistors specifically designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching and solenoid drivers. This performance is accomplished through a special gate oxide design which provides full rated conduction at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. * rDS(ON) = 0.200 * Design Optimized for 5V Gate Drives * Can be Driven Directly from QMOS, NMOS, TTL Circuits * Compatible with Automotive Drive Requirements * SOA is Power-Dissipation Limited * Nanosecond Switching Speeds Formerly developmental type TA09526. * Linear Transfer Characteristics Ordering Information * High Input Impedance PART NUMBER RFP12N10L PACKAGE TO-220AB BRAND F12N10L NOTE: When ordering, include the entire part number. * Majority Carrier Device * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards Symbol D G S Packaging JEDEC TO-220AB DRAIN (TAB) (c)2005 Fairchild Semiconductor Corporation SOURCE DRAIN GATE RFP12N10L Rev. B1 RFP12N10L Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFP12N10L UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 100 V Drain to Gate Voltage (RGS = 1M) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 12 A Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 30 A Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS 10 V Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 60 W 0.48 W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC Above TC = 25oC, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 100 - - V Drain to Source Breakdown Voltage BVDSS ID = 250A, VGS = 0V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250A (Figure 7) 1 - 2 V VDS = 80V - - 1 A - - 50 A VGS = 10V, VDS = 0V - - 100 nA ID = 12A, VGS = 5V (Figures 5, 6) - - 0.200 VGS = 0V, VDS = 25V, f = 1MHz (Figure 8) - - 900 pF Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IDSS IGSS rDS(ON) TC = 125oC VGS = 0V Input Capacitance CISS Output Capacitance COSS - - 325 pF Reverse-Transfer Capacitance CRSS - - 170 pF Turn-On Delay Time td(ON) - 15 50 ns - 70 150 ns td(OFF) - 100 130 ns tf - 80 150 ns 2.083 oC/W Rise Time tr Turn-Off Delay Time Fall Time Thermal Resistance Junction to Case R JC ID = 6A, VDD = 50V, RG = 6.25, VGS = 5V (Figures 9, 10, 11) TO-220 Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time VSD trr TEST CONDITIONS MIN TYP MAX UNITS ISD = 6A - - 1.4 V ISD = 4A, dISD/dt = 50A/s - 150 - ns NOTES: 2. Pulsed: pulse duration = 80s max, duty cycle = 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. (c)2005 Fairchild Semiconductor Corporation RFP12N10L Rev. B1 RFP12N10L Typical Performance Curves Unless Otherwise Specified 100 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 ID(MAX) CONTINUOUS 10 DC OPERATION 1 60W 0.2 0 0 50 100 0.1 1 150 TC, CASE TEMPERATURE (oC) 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE VG S 30 ID(ON), ON-STATE DRAIN CURRENT (A) 20 PULSE DURATION = 80s DUTY CYCLE 0.5% TC = 25oC V = 10 5V 20 4V 10 3V 2V 0 VDS = 10V PULSE DURATION = 80s DUTY CYCLE 0.5% 15 25oC 10 125oC 5 125oC 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) -40oC 5 0 1 -40oC 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 3. SATURATION CHARACTERISTICS FIGURE 4. TRANSFER CHARACTERISTICS 2.0 0.3 125oC 0.2 NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE () 1000 FIGURE 2. FORWARD BIAS OPERATING AREA 40 ID, DRAIN CURRENT (A) TC = 25oC TJ = MAX RATED OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 25oC -40oC 0.1 VGS = 5V PULSE DURATION = 80s DUTY CYCLE 0.5% 0 0 5 10 15 20 ID, DRAIN CURRENT (A) 25 30 FIGURE 5. DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENT (c)2005 Fairchild Semiconductor Corporation VGS = 5V, ID = 12A PULSE DURATION = 80s DUTY CYCLE 0.5% 1.5 1.0 0.5 0 -50 0 50 100 TJ, JUNCTION TEMPERATURE (oC) 150 FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE RFP12N10L Rev. B1 RFP12N10L Typical Performance Curves NORMALIZED GATE THRESHOLD VOLTAGE (V) 1.2 800 VDS = VGS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD ID = 250A C, CAPACITANCE (pF) 1.3 Unless Otherwise Specified (Continued) 1.1 1.0 0.9 0.8 600 CISS 400 COSS 200 0.7 CRSS 0.6 0 50 100 0 150 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE DRAIN TO SOURCE VOLTAGE (V) 100 FIGURE 8. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 BVDSS RL = 8.33 IG (REF) = 0.56mA VGS = 5V 8 GATE VDD = BVDSS SOURCE V = BVDSS VOLTAGE DD 6 75 50 4 0.75BVDSS 0.50BVDSS 0.25BVDSS DRAIN SOURCE VOLTAGE 25 2 0 0 20 50 IG (REF) IG (ACT) GATE TO SOURCE VOLTAGE (V) 0.5 -50 80 t, TIME (s) IG (REF) IG (ACT) NOTE: Refer to Fairchild Applications Notes AN7254 and AN7260 FIGURE 9. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + - VDD 10% 0 10% DUT 90% RGS VGS VGS 0 FIGURE 10. SWITCHING TIME TEST CIRCUIT (c)2005 Fairchild Semiconductor Corporation 10% 50% 50% PULSE WIDTH FIGURE 11. RESISTIVE SWITCHING WAVEFORMS RFP12N10L Rev. B1 RFP12N10L Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD DUT IG(REF) VGS = 5V VGS - VGS = 1V 0 Qg(TH) IG(REF) 0 FIGURE 12. GATE CHARGE TEST CIRCUIT (c)2005 Fairchild Semiconductor Corporation FIGURE 13. GATE CHARGE WAVEFORMS RFP12N10L Rev. B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FAST ActiveArrayTM FASTrTM BottomlessTM FPSTM CoolFETTM FRFETTM CROSSVOLTTM GlobalOptoisolatorTM DOMETM GTOTM EcoSPARKTM HiSeCTM E2CMOSTM I2CTM EnSignaTM i-LoTM FACTTM ImpliedDisconnectTM FACT Quiet SeriesTM IntelliMAXTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM Across the board. Around the world.TM OPTOLOGIC OPTOPLANARTM The Power Franchise PACMANTM Programmable Active DroopTM POPTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET UniFETTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I15