©2005 Fairchild Semiconductor Corporation RFP12N10L Rev. B1
RFP12N10L
12A, 100V, 0.200 Ohm, Logic Level,
N-Channel P ower MOSFET
These are N-Channel enhancement mode silicon gate
power field effect transistors specifically designed for use
with logic level (5V) driving sources in applications such as
prog r am ma ble controlle rs , automotiv e switching and
solenoid drivers. This performance is accomplished through
a special gate oxide design which provides full rated
conduction at gate biases in the 3V to 5V range, thereby
facilitating true on-of f po w er co ntrol directly from logic circuit
supply voltages.
Formerly developmental type TA09526.
Features
• 12A, 100 V
•r
DS(ON) = 0.200Ω
• Design Optimized for 5V Gate Drives
• Can be Driven Directly from QMOS, NMOS,
TTL Circ uits
• Compatible with Automotive Drive Requirements
• SOA is Power-Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Majority Carrier Device
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards
Symbol
Packaging
JEDEC TO-220AB
Ordering Information
PART NUMBER PACKAGE BRAND
RFP12N10L TO-220AB F12N10L
NOT E: When ordering, include the entire part number.
D
G
S
SOURCE
DRAIN
GATE
DRAIN
(TAB)
Data Sheet April 2005
©2005 Fairchild Semiconductor Corporation RFP12N10L Rev. B1
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFP12N10L UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 100 V
Drain to Gate Voltage (RGS = 1MΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V DGR 100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID12 A
Pul s e d D rai n C u r re n t (No te 3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 30 A
Gate to Sou rc e Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±10 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD60 W
Abo ve TC = 25oC, Derate Linearly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.48 W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
P ackage Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: St resses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a stress on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V 100 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 7) 1 - 2 V
Zero Gate Voltage Drain Current IDSS VDS = 80V - - 1 µA
VGS = 0V TC = 125oC- - 50 µA
Gate to Source Leakage Current IGSS VGS = 10V, VDS = 0V - - 100 nA
Drain to Source On Resistance (Note 2) rDS(ON) I
D = 12A, VGS = 5V (Figures 5, 6) - - 0.200 Ω
Input Capacitance CISS VGS = 0V, VDS = 25V, f = 1 MH z
(Figure 8) - - 900 pF
Output Capacitance COSS - - 325 pF
Reverse-Transfer Capacit ance CRSS - - 170 pF
Turn-On Delay Time td(ON) ID = 6A, VDD = 50V, RG = 6.25Ω,
VGS = 5V
(Figures 9, 10, 11)
-1550ns
Rise Time tr- 70 150 ns
Turn-Off Delay Time td(OFF) - 100 130 ns
Fall Ti me tf- 80 150 ns
Thermal Resistance Junction to Case RθJC TO-220 2.083 oC/W
Sour ce to Drain Diode Specificat ions
PARAMETER SYMBOL T EST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2) VSD ISD = 6A - - 1.4 V
Diode Reverse Recovery Time trr ISD = 4A, dISD/dt = 50A/µs - 150 - ns
NOTES:
2. Pulsed: pulse duration = 80µs max, duty cycle = 2%.
3. Repetitive rating: pulse width lim ited by max imum junction temperature.
RFP12N10L
©2005 Fairchild Semiconductor Corporation RFP12N10L Rev. B1
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED PO WER DISSIPA TION vs CASE
TEMPERATURE FIGURE 2. FORWARD BIAS OPERATING AREA
FIGURE 3. SATURATION CHARACTERISTICS FIGURE 4. TRANSFER CHARACTERISTICS
FIGURE 5. DRAIN TO SOURCE ON RESISTANCE vs DRAIN
CURRENT FIGURE 6. NORMALIZED DRAIN T O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
0 50 100 150
0
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.2
0.4
0.6
0.8
1.0
1.2 100
10
1
10001 10 100
OPERATION IN THIS
REGION IS LIMITED
BY rDS(ON)
0.1
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TC = 25oC
DC OPERATION
60W
ID(MAX) CONTINUOUS
TJ = MAX RATED
40
30
20
0
10
12 3405
V
GS
= 10V
PULSE DURATION = 80µs
DUTY CYCLE ≤ 0.5%
TC = 25oC
5V
4V
3V
2V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
20
15
10
0
5
12340
VDS = 10V
5
25oC
125oC
-40oC
PULSE DURATION = 80µs
DUTY CYCLE ≤ 0.5%
-40oC
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
125oC
rDS(ON), DRAIN TO SOURCE ON
ID, DRAIN CURRENT (A)
0.3
0.2
0.1
00 5 10 15 20 25 30
RESISTANCE (Ω)
-40oC
25oC
VGS = 5V
PULSE DURATION = 80µs
DUTY CYCLE ≤ 0.5%
125oC
2.0
1.5
1.0
0
0.5
0 50 100 150-50 TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
VGS = 5V, ID = 12A
PULSE DURATION = 80µs
DUTY CYCLE ≤ 0.5%
RFP12N10L
©2005 Fairchild Semiconductor Corporation RFP12N10L Rev. B1
FIGURE 7. NORMALIZED GATE THRESHOLD V OLTA GE vs
JUNCTION TEMPERATURE FIGURE 8. CAPACITANCE vs DRAIN TO S OURCE VOLTAGE
NOT E : Refer to Fairchild Applications Notes AN7254 and AN7260
FIGURE 9. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GAT E CURRENT
Test Circuits and Waveforms
FIGURE 10. SWITCHING TIME TEST CIRCUIT FIGURE 11. RESISTIVE SWITCHING WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
1.3
1.1
1.0
0.9
0.8
0.7
0.6
0.5 0 50 100 150-50
VDS = VGS
ID = 250µA
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE (V)
1.2
800
600
400
200
001020304050
CISS
COSS
CRSS
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
0.75BVDSS
0.50BVDSS
0.25BVDSS
DRAIN SOURCE
VOLTAGE
GATE
SOURCE
VOLTAGE
RL = 8.33Ω
IG (REF) = 0.56mA
VGS = 5V
VDD = BVDSS
VDD = BVDSS
BVDSS
IG (REF)
IG (ACT)
20 80 IG (REF)
IG (ACT)
t, TIME (µs)
GATE TO SOURCE VOLTAGE (V)
DRAIN TO SOURCE VOLTAGE (V)
100
75
50
25
0
10
8
6
4
0
2
VGS
RL
RGS DUT
+
-VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RFP12N10L
©2005 Fairchild Semiconductor Corporation RFP12N10L Rev. B1
FIGURE 12. GATE CHARGE TEST CIRCUIT FIGURE 13. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10V
VDS
VGS
IG(REF)
0
0
RFP12N10L
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS P ATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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In Design
First Production
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